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8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB
25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
87ecb68b
PB
30#include "hw.h"
31#include "fdc.h"
b47b3525 32#include "qemu-error.h"
87ecb68b
PB
33#include "qemu-timer.h"
34#include "isa.h"
f64ab228 35#include "sysbus.h"
e8133762 36#include "qdev-addr.h"
2446333c 37#include "blockdev.h"
1ca4d09a 38#include "sysemu.h"
cced7a13 39#include "qemu-log.h"
8977f3c1
FB
40
41/********************************************************/
42/* debug Floppy devices */
43//#define DEBUG_FLOPPY
44
45#ifdef DEBUG_FLOPPY
001faf32
BS
46#define FLOPPY_DPRINTF(fmt, ...) \
47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
8977f3c1 48#else
001faf32 49#define FLOPPY_DPRINTF(fmt, ...)
8977f3c1
FB
50#endif
51
8977f3c1
FB
52/********************************************************/
53/* Floppy drive emulation */
54
cefec4f5
BS
55#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
8977f3c1 58/* Will always be a fixed parameter for us */
f2d81b33
BS
59#define FD_SECTOR_LEN 512
60#define FD_SECTOR_SC 2 /* Sector size code */
61#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1 62
844f65d6
HP
63typedef struct FDCtrl FDCtrl;
64
8977f3c1 65/* Floppy disk drive emulation */
5c02c033 66typedef enum FDiskFlags {
baca51fa 67 FDISK_DBL_SIDES = 0x01,
5c02c033 68} FDiskFlags;
baca51fa 69
5c02c033 70typedef struct FDrive {
844f65d6 71 FDCtrl *fdctrl;
8977f3c1
FB
72 BlockDriverState *bs;
73 /* Drive status */
5c02c033 74 FDriveType drive;
8977f3c1 75 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB
76 /* Position */
77 uint8_t head;
78 uint8_t track;
79 uint8_t sect;
8977f3c1 80 /* Media */
5c02c033 81 FDiskFlags flags;
8977f3c1
FB
82 uint8_t last_sect; /* Nb sector per track */
83 uint8_t max_track; /* Nb of tracks */
baca51fa 84 uint16_t bps; /* Bytes per sector */
8977f3c1 85 uint8_t ro; /* Is read-only */
7d905f71 86 uint8_t media_changed; /* Is media changed */
844f65d6 87 uint8_t media_rate; /* Data rate of medium */
5c02c033 88} FDrive;
8977f3c1 89
5c02c033 90static void fd_init(FDrive *drv)
8977f3c1
FB
91{
92 /* Drive */
b939777c 93 drv->drive = FDRIVE_DRV_NONE;
8977f3c1 94 drv->perpendicular = 0;
8977f3c1 95 /* Disk */
baca51fa 96 drv->last_sect = 0;
8977f3c1
FB
97 drv->max_track = 0;
98}
99
08388273
HP
100#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
101
7859cb98 102static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 103 uint8_t last_sect, uint8_t num_sides)
8977f3c1 104{
08388273 105 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB
106}
107
108/* Returns current position, in sectors, for given drive */
5c02c033 109static int fd_sector(FDrive *drv)
8977f3c1 110{
08388273
HP
111 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
112 NUM_SIDES(drv));
8977f3c1
FB
113}
114
77370520
BS
115/* Seek to a new position:
116 * returns 0 if already on right track
117 * returns 1 if track changed
118 * returns 2 if track is invalid
119 * returns 3 if sector is invalid
120 * returns 4 if seek is disabled
121 */
5c02c033
BS
122static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
123 int enable_seek)
8977f3c1
FB
124{
125 uint32_t sector;
baca51fa
FB
126 int ret;
127
128 if (track > drv->max_track ||
4f431960 129 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB
130 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
131 head, track, sect, 1,
132 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
133 drv->max_track, drv->last_sect);
8977f3c1
FB
134 return 2;
135 }
136 if (sect > drv->last_sect) {
ed5fd2cc
FB
137 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
138 head, track, sect, 1,
139 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
140 drv->max_track, drv->last_sect);
8977f3c1
FB
141 return 3;
142 }
08388273 143 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 144 ret = 0;
8977f3c1
FB
145 if (sector != fd_sector(drv)) {
146#if 0
147 if (!enable_seek) {
cced7a13
BS
148 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
149 " (max=%d %02x %02x)\n",
150 head, track, sect, 1, drv->max_track,
151 drv->last_sect);
8977f3c1
FB
152 return 4;
153 }
154#endif
155 drv->head = head;
4f431960
JM
156 if (drv->track != track)
157 ret = 1;
8977f3c1
FB
158 drv->track = track;
159 drv->sect = sect;
8977f3c1
FB
160 }
161
c52acf60
PH
162 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) {
163 ret = 2;
164 }
165
baca51fa 166 return ret;
8977f3c1
FB
167}
168
169/* Set drive back to track 0 */
5c02c033 170static void fd_recalibrate(FDrive *drv)
8977f3c1
FB
171{
172 FLOPPY_DPRINTF("recalibrate\n");
173 drv->head = 0;
174 drv->track = 0;
175 drv->sect = 1;
8977f3c1
FB
176}
177
178/* Revalidate a disk drive after a disk change */
5c02c033 179static void fd_revalidate(FDrive *drv)
8977f3c1 180{
baca51fa 181 int nb_heads, max_track, last_sect, ro;
5bbdbb46 182 FDriveType drive;
f8d3d128 183 FDriveRate rate;
8977f3c1
FB
184
185 FLOPPY_DPRINTF("revalidate\n");
cfb08fba 186 if (drv->bs != NULL) {
4f431960 187 ro = bdrv_is_read_only(drv->bs);
5bbdbb46 188 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
f8d3d128 189 &last_sect, drv->drive, &drive, &rate);
cfb08fba
PH
190 if (!bdrv_is_inserted(drv->bs)) {
191 FLOPPY_DPRINTF("No disk in drive\n");
192 } else if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
193 FLOPPY_DPRINTF("User defined disk (%d %d %d)\n",
ed5fd2cc 194 nb_heads - 1, max_track, last_sect);
4f431960 195 } else {
5bbdbb46
BS
196 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
197 max_track, last_sect, ro ? "ro" : "rw");
4f431960
JM
198 }
199 if (nb_heads == 1) {
200 drv->flags &= ~FDISK_DBL_SIDES;
201 } else {
202 drv->flags |= FDISK_DBL_SIDES;
203 }
204 drv->max_track = max_track;
205 drv->last_sect = last_sect;
206 drv->ro = ro;
5bbdbb46 207 drv->drive = drive;
844f65d6 208 drv->media_rate = rate;
8977f3c1 209 } else {
cfb08fba 210 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 211 drv->last_sect = 0;
4f431960
JM
212 drv->max_track = 0;
213 drv->flags &= ~FDISK_DBL_SIDES;
8977f3c1 214 }
caed8802
FB
215}
216
8977f3c1 217/********************************************************/
4b19ec0c 218/* Intel 82078 floppy disk controller emulation */
8977f3c1 219
5c02c033
BS
220static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
221static void fdctrl_reset_fifo(FDCtrl *fdctrl);
85571bc7 222static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 223 int dma_pos, int dma_len);
5c02c033 224static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
a2df5fa3 225static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS
226
227static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
228static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
229static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
230static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
231static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
232static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
233static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
234static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
235static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
236static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
237static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 238static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 239
8977f3c1
FB
240enum {
241 FD_DIR_WRITE = 0,
242 FD_DIR_READ = 1,
243 FD_DIR_SCANE = 2,
244 FD_DIR_SCANL = 3,
245 FD_DIR_SCANH = 4,
246};
247
248enum {
b9b3d225
BS
249 FD_STATE_MULTI = 0x01, /* multi track flag */
250 FD_STATE_FORMAT = 0x02, /* format flag */
251 FD_STATE_SEEK = 0x04, /* seek flag */
8977f3c1
FB
252};
253
9fea808a 254enum {
8c6a4d77
BS
255 FD_REG_SRA = 0x00,
256 FD_REG_SRB = 0x01,
9fea808a
BS
257 FD_REG_DOR = 0x02,
258 FD_REG_TDR = 0x03,
259 FD_REG_MSR = 0x04,
260 FD_REG_DSR = 0x04,
261 FD_REG_FIFO = 0x05,
262 FD_REG_DIR = 0x07,
a758f8f4 263 FD_REG_CCR = 0x07,
9fea808a
BS
264};
265
266enum {
65cef780 267 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS
268 FD_CMD_SPECIFY = 0x03,
269 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS
270 FD_CMD_WRITE = 0x05,
271 FD_CMD_READ = 0x06,
9fea808a
BS
272 FD_CMD_RECALIBRATE = 0x07,
273 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS
274 FD_CMD_WRITE_DELETED = 0x09,
275 FD_CMD_READ_ID = 0x0a,
276 FD_CMD_READ_DELETED = 0x0c,
277 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS
278 FD_CMD_DUMPREG = 0x0e,
279 FD_CMD_SEEK = 0x0f,
280 FD_CMD_VERSION = 0x10,
65cef780 281 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS
282 FD_CMD_PERPENDICULAR_MODE = 0x12,
283 FD_CMD_CONFIGURE = 0x13,
65cef780
BS
284 FD_CMD_LOCK = 0x14,
285 FD_CMD_VERIFY = 0x16,
9fea808a
BS
286 FD_CMD_POWERDOWN_MODE = 0x17,
287 FD_CMD_PART_ID = 0x18,
65cef780
BS
288 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
289 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 290 FD_CMD_SAVE = 0x2e,
9fea808a 291 FD_CMD_OPTION = 0x33,
bb350a5e 292 FD_CMD_RESTORE = 0x4e,
9fea808a
BS
293 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
294 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS
295 FD_CMD_FORMAT_AND_WRITE = 0xcd,
296 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
297};
298
299enum {
300 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
301 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
302 FD_CONFIG_POLL = 0x10, /* Poll enabled */
303 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
304 FD_CONFIG_EIS = 0x40, /* No implied seeks */
305};
306
307enum {
308 FD_SR0_EQPMT = 0x10,
309 FD_SR0_SEEK = 0x20,
310 FD_SR0_ABNTERM = 0x40,
311 FD_SR0_INVCMD = 0x80,
312 FD_SR0_RDYCHG = 0xc0,
313};
314
77370520 315enum {
844f65d6 316 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 317 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS
318 FD_SR1_EC = 0x80, /* End of cylinder */
319};
320
321enum {
322 FD_SR2_SNS = 0x04, /* Scan not satisfied */
323 FD_SR2_SEH = 0x08, /* Scan equal hit */
324};
325
8c6a4d77
BS
326enum {
327 FD_SRA_DIR = 0x01,
328 FD_SRA_nWP = 0x02,
329 FD_SRA_nINDX = 0x04,
330 FD_SRA_HDSEL = 0x08,
331 FD_SRA_nTRK0 = 0x10,
332 FD_SRA_STEP = 0x20,
333 FD_SRA_nDRV2 = 0x40,
334 FD_SRA_INTPEND = 0x80,
335};
336
337enum {
338 FD_SRB_MTR0 = 0x01,
339 FD_SRB_MTR1 = 0x02,
340 FD_SRB_WGATE = 0x04,
341 FD_SRB_RDATA = 0x08,
342 FD_SRB_WDATA = 0x10,
343 FD_SRB_DR0 = 0x20,
344};
345
9fea808a 346enum {
78ae820c
BS
347#if MAX_FD == 4
348 FD_DOR_SELMASK = 0x03,
349#else
9fea808a 350 FD_DOR_SELMASK = 0x01,
78ae820c 351#endif
9fea808a
BS
352 FD_DOR_nRESET = 0x04,
353 FD_DOR_DMAEN = 0x08,
354 FD_DOR_MOTEN0 = 0x10,
355 FD_DOR_MOTEN1 = 0x20,
356 FD_DOR_MOTEN2 = 0x40,
357 FD_DOR_MOTEN3 = 0x80,
358};
359
360enum {
78ae820c 361#if MAX_FD == 4
9fea808a 362 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS
363#else
364 FD_TDR_BOOTSEL = 0x04,
365#endif
9fea808a
BS
366};
367
368enum {
369 FD_DSR_DRATEMASK= 0x03,
370 FD_DSR_PWRDOWN = 0x40,
371 FD_DSR_SWRESET = 0x80,
372};
373
374enum {
375 FD_MSR_DRV0BUSY = 0x01,
376 FD_MSR_DRV1BUSY = 0x02,
377 FD_MSR_DRV2BUSY = 0x04,
378 FD_MSR_DRV3BUSY = 0x08,
379 FD_MSR_CMDBUSY = 0x10,
380 FD_MSR_NONDMA = 0x20,
381 FD_MSR_DIO = 0x40,
382 FD_MSR_RQM = 0x80,
383};
384
385enum {
386 FD_DIR_DSKCHG = 0x80,
387};
388
8977f3c1
FB
389#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
390#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
baca51fa 391#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 392
5c02c033 393struct FDCtrl {
dc6c1b37 394 MemoryRegion iomem;
d537cf6c 395 qemu_irq irq;
4b19ec0c 396 /* Controller state */
ed5fd2cc 397 QEMUTimer *result_timer;
242cca4f
BS
398 int dma_chann;
399 /* Controller's identification */
400 uint8_t version;
401 /* HW */
8c6a4d77
BS
402 uint8_t sra;
403 uint8_t srb;
368df94d 404 uint8_t dor;
d7a6c270 405 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 406 uint8_t tdr;
b9b3d225 407 uint8_t dsr;
368df94d 408 uint8_t msr;
8977f3c1 409 uint8_t cur_drv;
77370520
BS
410 uint8_t status0;
411 uint8_t status1;
412 uint8_t status2;
8977f3c1 413 /* Command FIFO */
33f00271 414 uint8_t *fifo;
d7a6c270 415 int32_t fifo_size;
8977f3c1
FB
416 uint32_t data_pos;
417 uint32_t data_len;
418 uint8_t data_state;
419 uint8_t data_dir;
890fa6be 420 uint8_t eot; /* last wanted sector */
8977f3c1 421 /* States kept only to be returned back */
8977f3c1
FB
422 /* precompensation */
423 uint8_t precomp_trk;
424 uint8_t config;
425 uint8_t lock;
426 /* Power down config (also with status regB access mode */
427 uint8_t pwrd;
428 /* Floppy drives */
d7a6c270 429 uint8_t num_floppies;
242cca4f
BS
430 /* Sun4m quirks? */
431 int sun4m;
5c02c033 432 FDrive drives[MAX_FD];
f2d81b33 433 int reset_sensei;
09c6d585 434 uint32_t check_media_rate;
242cca4f
BS
435 /* Timers state */
436 uint8_t timer0;
437 uint8_t timer1;
baca51fa
FB
438};
439
5c02c033 440typedef struct FDCtrlSysBus {
8baf73ad 441 SysBusDevice busdev;
5c02c033
BS
442 struct FDCtrl state;
443} FDCtrlSysBus;
8baf73ad 444
5c02c033 445typedef struct FDCtrlISABus {
8baf73ad 446 ISADevice busdev;
c9ae703d
HP
447 uint32_t iobase;
448 uint32_t irq;
449 uint32_t dma;
5c02c033 450 struct FDCtrl state;
1ca4d09a
GN
451 int32_t bootindexA;
452 int32_t bootindexB;
5c02c033 453} FDCtrlISABus;
8baf73ad 454
baca51fa
FB
455static uint32_t fdctrl_read (void *opaque, uint32_t reg)
456{
5c02c033 457 FDCtrl *fdctrl = opaque;
baca51fa
FB
458 uint32_t retval;
459
a18e67f5 460 reg &= 7;
e64d7d59 461 switch (reg) {
8c6a4d77
BS
462 case FD_REG_SRA:
463 retval = fdctrl_read_statusA(fdctrl);
4f431960 464 break;
8c6a4d77 465 case FD_REG_SRB:
4f431960
JM
466 retval = fdctrl_read_statusB(fdctrl);
467 break;
9fea808a 468 case FD_REG_DOR:
4f431960
JM
469 retval = fdctrl_read_dor(fdctrl);
470 break;
9fea808a 471 case FD_REG_TDR:
baca51fa 472 retval = fdctrl_read_tape(fdctrl);
4f431960 473 break;
9fea808a 474 case FD_REG_MSR:
baca51fa 475 retval = fdctrl_read_main_status(fdctrl);
4f431960 476 break;
9fea808a 477 case FD_REG_FIFO:
baca51fa 478 retval = fdctrl_read_data(fdctrl);
4f431960 479 break;
9fea808a 480 case FD_REG_DIR:
baca51fa 481 retval = fdctrl_read_dir(fdctrl);
4f431960 482 break;
a541f297 483 default:
4f431960
JM
484 retval = (uint32_t)(-1);
485 break;
a541f297 486 }
ed5fd2cc 487 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
baca51fa
FB
488
489 return retval;
490}
491
492static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
493{
5c02c033 494 FDCtrl *fdctrl = opaque;
baca51fa 495
ed5fd2cc
FB
496 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
497
a18e67f5 498 reg &= 7;
e64d7d59 499 switch (reg) {
9fea808a 500 case FD_REG_DOR:
4f431960
JM
501 fdctrl_write_dor(fdctrl, value);
502 break;
9fea808a 503 case FD_REG_TDR:
baca51fa 504 fdctrl_write_tape(fdctrl, value);
4f431960 505 break;
9fea808a 506 case FD_REG_DSR:
baca51fa 507 fdctrl_write_rate(fdctrl, value);
4f431960 508 break;
9fea808a 509 case FD_REG_FIFO:
baca51fa 510 fdctrl_write_data(fdctrl, value);
4f431960 511 break;
a758f8f4
HP
512 case FD_REG_CCR:
513 fdctrl_write_ccr(fdctrl, value);
514 break;
a541f297 515 default:
4f431960 516 break;
a541f297 517 }
baca51fa
FB
518}
519
dc6c1b37
AK
520static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
521 unsigned ize)
62a46c61 522{
5dcb6b91 523 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB
524}
525
dc6c1b37
AK
526static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
527 uint64_t value, unsigned size)
62a46c61 528{
5dcb6b91 529 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB
530}
531
dc6c1b37
AK
532static const MemoryRegionOps fdctrl_mem_ops = {
533 .read = fdctrl_read_mem,
534 .write = fdctrl_write_mem,
535 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB
536};
537
dc6c1b37
AK
538static const MemoryRegionOps fdctrl_mem_strict_ops = {
539 .read = fdctrl_read_mem,
540 .write = fdctrl_write_mem,
541 .endianness = DEVICE_NATIVE_ENDIAN,
542 .valid = {
543 .min_access_size = 1,
544 .max_access_size = 1,
545 },
7c560456
BS
546};
547
7d905f71
JW
548static bool fdrive_media_changed_needed(void *opaque)
549{
550 FDrive *drive = opaque;
551
8e49ca46 552 return (drive->bs != NULL && drive->media_changed != 1);
7d905f71
JW
553}
554
555static const VMStateDescription vmstate_fdrive_media_changed = {
556 .name = "fdrive/media_changed",
557 .version_id = 1,
558 .minimum_version_id = 1,
559 .minimum_version_id_old = 1,
7d905f71
JW
560 .fields = (VMStateField[]) {
561 VMSTATE_UINT8(media_changed, FDrive),
562 VMSTATE_END_OF_LIST()
563 }
564};
565
844f65d6
HP
566static bool fdrive_media_rate_needed(void *opaque)
567{
568 FDrive *drive = opaque;
569
570 return drive->fdctrl->check_media_rate;
571}
572
573static const VMStateDescription vmstate_fdrive_media_rate = {
574 .name = "fdrive/media_rate",
575 .version_id = 1,
576 .minimum_version_id = 1,
577 .minimum_version_id_old = 1,
578 .fields = (VMStateField[]) {
579 VMSTATE_UINT8(media_rate, FDrive),
580 VMSTATE_END_OF_LIST()
581 }
582};
583
d7a6c270
JQ
584static const VMStateDescription vmstate_fdrive = {
585 .name = "fdrive",
586 .version_id = 1,
587 .minimum_version_id = 1,
588 .minimum_version_id_old = 1,
7d905f71 589 .fields = (VMStateField[]) {
5c02c033
BS
590 VMSTATE_UINT8(head, FDrive),
591 VMSTATE_UINT8(track, FDrive),
592 VMSTATE_UINT8(sect, FDrive),
d7a6c270 593 VMSTATE_END_OF_LIST()
7d905f71
JW
594 },
595 .subsections = (VMStateSubsection[]) {
596 {
597 .vmsd = &vmstate_fdrive_media_changed,
598 .needed = &fdrive_media_changed_needed,
844f65d6
HP
599 } , {
600 .vmsd = &vmstate_fdrive_media_rate,
601 .needed = &fdrive_media_rate_needed,
7d905f71
JW
602 } , {
603 /* empty */
604 }
d7a6c270
JQ
605 }
606};
3ccacc4a 607
d4bfa4d7 608static void fdc_pre_save(void *opaque)
3ccacc4a 609{
5c02c033 610 FDCtrl *s = opaque;
3ccacc4a 611
d7a6c270 612 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
3ccacc4a
BS
613}
614
e59fb374 615static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 616{
5c02c033 617 FDCtrl *s = opaque;
3ccacc4a 618
d7a6c270
JQ
619 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
620 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
3ccacc4a
BS
621 return 0;
622}
623
d7a6c270 624static const VMStateDescription vmstate_fdc = {
aef30c3c 625 .name = "fdc",
d7a6c270
JQ
626 .version_id = 2,
627 .minimum_version_id = 2,
628 .minimum_version_id_old = 2,
629 .pre_save = fdc_pre_save,
630 .post_load = fdc_post_load,
631 .fields = (VMStateField []) {
632 /* Controller State */
5c02c033
BS
633 VMSTATE_UINT8(sra, FDCtrl),
634 VMSTATE_UINT8(srb, FDCtrl),
635 VMSTATE_UINT8(dor_vmstate, FDCtrl),
636 VMSTATE_UINT8(tdr, FDCtrl),
637 VMSTATE_UINT8(dsr, FDCtrl),
638 VMSTATE_UINT8(msr, FDCtrl),
639 VMSTATE_UINT8(status0, FDCtrl),
640 VMSTATE_UINT8(status1, FDCtrl),
641 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 642 /* Command FIFO */
8ec68b06
BS
643 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
644 uint8_t),
5c02c033
BS
645 VMSTATE_UINT32(data_pos, FDCtrl),
646 VMSTATE_UINT32(data_len, FDCtrl),
647 VMSTATE_UINT8(data_state, FDCtrl),
648 VMSTATE_UINT8(data_dir, FDCtrl),
649 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 650 /* States kept only to be returned back */
5c02c033
BS
651 VMSTATE_UINT8(timer0, FDCtrl),
652 VMSTATE_UINT8(timer1, FDCtrl),
653 VMSTATE_UINT8(precomp_trk, FDCtrl),
654 VMSTATE_UINT8(config, FDCtrl),
655 VMSTATE_UINT8(lock, FDCtrl),
656 VMSTATE_UINT8(pwrd, FDCtrl),
657 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
658 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
659 vmstate_fdrive, FDrive),
d7a6c270 660 VMSTATE_END_OF_LIST()
78ae820c 661 }
d7a6c270 662};
3ccacc4a 663
2be37833 664static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 665{
5c02c033
BS
666 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
667 FDCtrl *s = &sys->state;
2be37833
BS
668
669 fdctrl_reset(s, 0);
670}
671
672static void fdctrl_external_reset_isa(DeviceState *d)
673{
5c02c033
BS
674 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
675 FDCtrl *s = &isa->state;
3ccacc4a
BS
676
677 fdctrl_reset(s, 0);
678}
679
2be17ebd
BS
680static void fdctrl_handle_tc(void *opaque, int irq, int level)
681{
5c02c033 682 //FDCtrl *s = opaque;
2be17ebd
BS
683
684 if (level) {
685 // XXX
686 FLOPPY_DPRINTF("TC pulsed\n");
687 }
688}
689
8977f3c1 690/* Change IRQ state */
5c02c033 691static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 692{
8c6a4d77
BS
693 if (!(fdctrl->sra & FD_SRA_INTPEND))
694 return;
ed5fd2cc 695 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 696 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 697 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB
698}
699
5c02c033 700static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
8977f3c1 701{
b9b3d225
BS
702 /* Sparc mutation */
703 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
704 /* XXX: not sure */
705 fdctrl->msr &= ~FD_MSR_CMDBUSY;
706 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
77370520 707 fdctrl->status0 = status0;
4f431960 708 return;
6f7e9aec 709 }
8c6a4d77 710 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 711 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 712 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 713 }
21fcf360
HP
714 if (status0 & FD_SR0_SEEK) {
715 FDrive *cur_drv;
716 /* A seek clears the disk change line (if a disk is inserted) */
717 cur_drv = get_cur_drv(fdctrl);
cfb08fba 718 if (cur_drv->bs != NULL && bdrv_is_inserted(cur_drv->bs)) {
21fcf360
HP
719 cur_drv->media_changed = 0;
720 }
721 }
722
f2d81b33 723 fdctrl->reset_sensei = 0;
77370520
BS
724 fdctrl->status0 = status0;
725 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB
726}
727
4b19ec0c 728/* Reset controller */
5c02c033 729static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB
730{
731 int i;
732
4b19ec0c 733 FLOPPY_DPRINTF("reset controller\n");
baca51fa 734 fdctrl_reset_irq(fdctrl);
4b19ec0c 735 /* Initialise controller */
8c6a4d77
BS
736 fdctrl->sra = 0;
737 fdctrl->srb = 0xc0;
738 if (!fdctrl->drives[1].bs)
739 fdctrl->sra |= FD_SRA_nDRV2;
baca51fa 740 fdctrl->cur_drv = 0;
1c346df2 741 fdctrl->dor = FD_DOR_nRESET;
368df94d 742 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 743 fdctrl->msr = FD_MSR_RQM;
8977f3c1 744 /* FIFO state */
baca51fa
FB
745 fdctrl->data_pos = 0;
746 fdctrl->data_len = 0;
b9b3d225 747 fdctrl->data_state = 0;
baca51fa 748 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 749 for (i = 0; i < MAX_FD; i++)
1c346df2 750 fd_recalibrate(&fdctrl->drives[i]);
baca51fa 751 fdctrl_reset_fifo(fdctrl);
77370520 752 if (do_irq) {
9fea808a 753 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
f2d81b33 754 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 755 }
baca51fa
FB
756}
757
5c02c033 758static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 759{
46d3233b 760 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB
761}
762
5c02c033 763static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 764{
46d3233b
BS
765 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
766 return &fdctrl->drives[1];
767 else
768 return &fdctrl->drives[0];
baca51fa
FB
769}
770
78ae820c 771#if MAX_FD == 4
5c02c033 772static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS
773{
774 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
775 return &fdctrl->drives[2];
776 else
777 return &fdctrl->drives[1];
778}
779
5c02c033 780static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS
781{
782 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
783 return &fdctrl->drives[3];
784 else
785 return &fdctrl->drives[2];
786}
787#endif
788
5c02c033 789static FDrive *get_cur_drv(FDCtrl *fdctrl)
baca51fa 790{
78ae820c
BS
791 switch (fdctrl->cur_drv) {
792 case 0: return drv0(fdctrl);
793 case 1: return drv1(fdctrl);
794#if MAX_FD == 4
795 case 2: return drv2(fdctrl);
796 case 3: return drv3(fdctrl);
797#endif
798 default: return NULL;
799 }
8977f3c1
FB
800}
801
8c6a4d77 802/* Status A register : 0x00 (read-only) */
5c02c033 803static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS
804{
805 uint32_t retval = fdctrl->sra;
806
807 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
808
809 return retval;
810}
811
8977f3c1 812/* Status B register : 0x01 (read-only) */
5c02c033 813static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 814{
8c6a4d77
BS
815 uint32_t retval = fdctrl->srb;
816
817 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
818
819 return retval;
8977f3c1
FB
820}
821
822/* Digital output register : 0x02 */
5c02c033 823static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 824{
1c346df2 825 uint32_t retval = fdctrl->dor;
8977f3c1 826
8977f3c1 827 /* Selected drive */
baca51fa 828 retval |= fdctrl->cur_drv;
8977f3c1
FB
829 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
830
831 return retval;
832}
833
5c02c033 834static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 835{
8977f3c1 836 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS
837
838 /* Motors */
839 if (value & FD_DOR_MOTEN0)
840 fdctrl->srb |= FD_SRB_MTR0;
841 else
842 fdctrl->srb &= ~FD_SRB_MTR0;
843 if (value & FD_DOR_MOTEN1)
844 fdctrl->srb |= FD_SRB_MTR1;
845 else
846 fdctrl->srb &= ~FD_SRB_MTR1;
847
848 /* Drive */
849 if (value & 1)
850 fdctrl->srb |= FD_SRB_DR0;
851 else
852 fdctrl->srb &= ~FD_SRB_DR0;
853
8977f3c1 854 /* Reset */
9fea808a 855 if (!(value & FD_DOR_nRESET)) {
1c346df2 856 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 857 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB
858 }
859 } else {
1c346df2 860 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 861 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 862 fdctrl_reset(fdctrl, 1);
b9b3d225 863 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB
864 }
865 }
866 /* Selected drive */
9fea808a 867 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS
868
869 fdctrl->dor = value;
8977f3c1
FB
870}
871
872/* Tape drive register : 0x03 */
5c02c033 873static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 874{
46d3233b 875 uint32_t retval = fdctrl->tdr;
8977f3c1 876
8977f3c1
FB
877 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
878
879 return retval;
880}
881
5c02c033 882static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 883{
8977f3c1 884 /* Reset mode */
1c346df2 885 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 886 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB
887 return;
888 }
889 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
890 /* Disk boot selection indicator */
46d3233b 891 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB
892 /* Tape indicators: never allow */
893}
894
895/* Main status register : 0x04 (read) */
5c02c033 896static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 897{
b9b3d225 898 uint32_t retval = fdctrl->msr;
8977f3c1 899
b9b3d225 900 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 901 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 902
82407d1a
AT
903 /* Sparc mutation */
904 if (fdctrl->sun4m) {
905 retval |= FD_MSR_DIO;
906 fdctrl_reset_irq(fdctrl);
907 };
908
8977f3c1
FB
909 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
910
911 return retval;
912}
913
914/* Data select rate register : 0x04 (write) */
5c02c033 915static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 916{
8977f3c1 917 /* Reset mode */
1c346df2 918 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM
919 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
920 return;
921 }
8977f3c1
FB
922 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
923 /* Reset: autoclear */
9fea808a 924 if (value & FD_DSR_SWRESET) {
1c346df2 925 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 926 fdctrl_reset(fdctrl, 1);
1c346df2 927 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 928 }
9fea808a 929 if (value & FD_DSR_PWRDOWN) {
baca51fa 930 fdctrl_reset(fdctrl, 1);
8977f3c1 931 }
b9b3d225 932 fdctrl->dsr = value;
8977f3c1
FB
933}
934
a758f8f4
HP
935/* Configuration control register: 0x07 (write) */
936static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
937{
938 /* Reset mode */
939 if (!(fdctrl->dor & FD_DOR_nRESET)) {
940 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
941 return;
942 }
943 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
944
945 /* Only the rate selection bits used in AT mode, and we
946 * store those in the DSR.
947 */
948 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
949 (value & FD_DSR_DRATEMASK);
950}
951
5c02c033 952static int fdctrl_media_changed(FDrive *drv)
ea185bbd 953{
21fcf360 954 return drv->media_changed;
ea185bbd
FB
955}
956
8977f3c1 957/* Digital input register : 0x07 (read-only) */
5c02c033 958static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 959{
8977f3c1
FB
960 uint32_t retval = 0;
961
a2df5fa3 962 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 963 retval |= FD_DIR_DSKCHG;
a2df5fa3 964 }
3c83eb4f 965 if (retval != 0) {
baca51fa 966 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 967 }
8977f3c1
FB
968
969 return retval;
970}
971
972/* FIFO state control */
5c02c033 973static void fdctrl_reset_fifo(FDCtrl *fdctrl)
8977f3c1 974{
baca51fa
FB
975 fdctrl->data_dir = FD_DIR_WRITE;
976 fdctrl->data_pos = 0;
b9b3d225 977 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
8977f3c1
FB
978}
979
980/* Set FIFO status for the host to read */
5c02c033 981static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
8977f3c1 982{
baca51fa
FB
983 fdctrl->data_dir = FD_DIR_READ;
984 fdctrl->data_len = fifo_len;
985 fdctrl->data_pos = 0;
b9b3d225 986 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1 987 if (do_irq)
baca51fa 988 fdctrl_raise_irq(fdctrl, 0x00);
8977f3c1
FB
989}
990
991/* Set an error: unimplemented/unknown command */
5c02c033 992static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 993{
cced7a13
BS
994 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
995 fdctrl->fifo[0]);
9fea808a 996 fdctrl->fifo[0] = FD_SR0_INVCMD;
baca51fa 997 fdctrl_set_fifo(fdctrl, 1, 0);
8977f3c1
FB
998}
999
746d6de7 1000/* Seek to next sector */
5c02c033 1001static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS
1002{
1003 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1004 cur_drv->head, cur_drv->track, cur_drv->sect,
1005 fd_sector(cur_drv));
1006 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1007 error in fact */
1008 if (cur_drv->sect >= cur_drv->last_sect ||
1009 cur_drv->sect == fdctrl->eot) {
1010 cur_drv->sect = 1;
1011 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1012 if (cur_drv->head == 0 &&
1013 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1014 cur_drv->head = 1;
1015 } else {
1016 cur_drv->head = 0;
1017 cur_drv->track++;
1018 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1019 return 0;
1020 }
1021 } else {
1022 cur_drv->track++;
1023 return 0;
1024 }
1025 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1026 cur_drv->head, cur_drv->track,
1027 cur_drv->sect, fd_sector(cur_drv));
1028 } else {
1029 cur_drv->sect++;
1030 }
1031 return 1;
1032}
1033
8977f3c1 1034/* Callback for transfer end (stop or abort) */
5c02c033
BS
1035static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1036 uint8_t status1, uint8_t status2)
8977f3c1 1037{
5c02c033 1038 FDrive *cur_drv;
8977f3c1 1039
baca51fa 1040 cur_drv = get_cur_drv(fdctrl);
8977f3c1
FB
1041 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1042 status0, status1, status2,
cefec4f5
BS
1043 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1044 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
baca51fa
FB
1045 fdctrl->fifo[1] = status1;
1046 fdctrl->fifo[2] = status2;
1047 fdctrl->fifo[3] = cur_drv->track;
1048 fdctrl->fifo[4] = cur_drv->head;
1049 fdctrl->fifo[5] = cur_drv->sect;
1050 fdctrl->fifo[6] = FD_SECTOR_SC;
1051 fdctrl->data_dir = FD_DIR_READ;
368df94d 1052 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
baca51fa 1053 DMA_release_DREQ(fdctrl->dma_chann);
ed5fd2cc 1054 }
b9b3d225 1055 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1056 fdctrl->msr &= ~FD_MSR_NONDMA;
baca51fa 1057 fdctrl_set_fifo(fdctrl, 7, 1);
8977f3c1
FB
1058}
1059
1060/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1061static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1062{
5c02c033 1063 FDrive *cur_drv;
8977f3c1 1064 uint8_t kh, kt, ks;
77370520 1065 int did_seek = 0;
8977f3c1 1066
cefec4f5 1067 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB
1068 cur_drv = get_cur_drv(fdctrl);
1069 kt = fdctrl->fifo[2];
1070 kh = fdctrl->fifo[3];
1071 ks = fdctrl->fifo[4];
4b19ec0c 1072 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1073 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP
1074 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1075 NUM_SIDES(cur_drv)));
77370520 1076 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB
1077 case 2:
1078 /* sect too big */
9fea808a 1079 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB
1080 fdctrl->fifo[3] = kt;
1081 fdctrl->fifo[4] = kh;
1082 fdctrl->fifo[5] = ks;
8977f3c1
FB
1083 return;
1084 case 3:
1085 /* track too big */
77370520 1086 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB
1087 fdctrl->fifo[3] = kt;
1088 fdctrl->fifo[4] = kh;
1089 fdctrl->fifo[5] = ks;
8977f3c1
FB
1090 return;
1091 case 4:
1092 /* No seek enabled */
9fea808a 1093 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB
1094 fdctrl->fifo[3] = kt;
1095 fdctrl->fifo[4] = kh;
1096 fdctrl->fifo[5] = ks;
8977f3c1
FB
1097 return;
1098 case 1:
1099 did_seek = 1;
1100 break;
1101 default:
1102 break;
1103 }
b9b3d225 1104
844f65d6
HP
1105 /* Check the data rate. If the programmed data rate does not match
1106 * the currently inserted medium, the operation has to fail. */
1107 if (fdctrl->check_media_rate &&
1108 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1109 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1110 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1111 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1112 fdctrl->fifo[3] = kt;
1113 fdctrl->fifo[4] = kh;
1114 fdctrl->fifo[5] = ks;
1115 return;
1116 }
1117
8977f3c1 1118 /* Set the FIFO state */
baca51fa
FB
1119 fdctrl->data_dir = direction;
1120 fdctrl->data_pos = 0;
b9b3d225 1121 fdctrl->msr |= FD_MSR_CMDBUSY;
baca51fa
FB
1122 if (fdctrl->fifo[0] & 0x80)
1123 fdctrl->data_state |= FD_STATE_MULTI;
1124 else
1125 fdctrl->data_state &= ~FD_STATE_MULTI;
8977f3c1 1126 if (did_seek)
baca51fa
FB
1127 fdctrl->data_state |= FD_STATE_SEEK;
1128 else
1129 fdctrl->data_state &= ~FD_STATE_SEEK;
1130 if (fdctrl->fifo[5] == 00) {
1131 fdctrl->data_len = fdctrl->fifo[8];
1132 } else {
4f431960 1133 int tmp;
3bcb80f1 1134 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1135 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1136 if (fdctrl->fifo[0] & 0x80)
771effeb 1137 tmp += fdctrl->fifo[6];
4f431960 1138 fdctrl->data_len *= tmp;
baca51fa 1139 }
890fa6be 1140 fdctrl->eot = fdctrl->fifo[6];
368df94d 1141 if (fdctrl->dor & FD_DOR_DMAEN) {
8977f3c1
FB
1142 int dma_mode;
1143 /* DMA transfer are enabled. Check if DMA channel is well programmed */
baca51fa 1144 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
8977f3c1 1145 dma_mode = (dma_mode >> 2) & 3;
baca51fa 1146 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
4f431960 1147 dma_mode, direction,
baca51fa 1148 (128 << fdctrl->fifo[5]) *
4f431960 1149 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
8977f3c1
FB
1150 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1151 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1152 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1153 (direction == FD_DIR_READ && dma_mode == 1)) {
1154 /* No access is allowed until DMA transfer has completed */
b9b3d225 1155 fdctrl->msr &= ~FD_MSR_RQM;
4b19ec0c 1156 /* Now, we just have to wait for the DMA controller to
8977f3c1
FB
1157 * recall us...
1158 */
baca51fa
FB
1159 DMA_hold_DREQ(fdctrl->dma_chann);
1160 DMA_schedule(fdctrl->dma_chann);
8977f3c1 1161 return;
baca51fa 1162 } else {
cced7a13
BS
1163 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1164 direction);
8977f3c1
FB
1165 }
1166 }
1167 FLOPPY_DPRINTF("start non-DMA transfer\n");
368df94d 1168 fdctrl->msr |= FD_MSR_NONDMA;
b9b3d225
BS
1169 if (direction != FD_DIR_WRITE)
1170 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1171 /* IO based transfer: calculate len */
baca51fa 1172 fdctrl_raise_irq(fdctrl, 0x00);
8977f3c1
FB
1173
1174 return;
1175}
1176
1177/* Prepare a transfer of deleted data */
5c02c033 1178static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1179{
cced7a13 1180 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1181
8977f3c1
FB
1182 /* We don't handle deleted data,
1183 * so we don't return *ANYTHING*
1184 */
9fea808a 1185 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB
1186}
1187
1188/* handlers for DMA transfers */
85571bc7
FB
1189static int fdctrl_transfer_handler (void *opaque, int nchan,
1190 int dma_pos, int dma_len)
8977f3c1 1191{
5c02c033
BS
1192 FDCtrl *fdctrl;
1193 FDrive *cur_drv;
baca51fa 1194 int len, start_pos, rel_pos;
8977f3c1
FB
1195 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1196
baca51fa 1197 fdctrl = opaque;
b9b3d225 1198 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB
1199 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1200 return 0;
1201 }
baca51fa
FB
1202 cur_drv = get_cur_drv(fdctrl);
1203 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1204 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1205 status2 = FD_SR2_SNS;
85571bc7
FB
1206 if (dma_len > fdctrl->data_len)
1207 dma_len = fdctrl->data_len;
890fa6be 1208 if (cur_drv->bs == NULL) {
4f431960 1209 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1210 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1211 else
9fea808a 1212 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1213 len = 0;
890fa6be
FB
1214 goto transfer_error;
1215 }
baca51fa 1216 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB
1217 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1218 len = dma_len - fdctrl->data_pos;
baca51fa
FB
1219 if (len + rel_pos > FD_SECTOR_LEN)
1220 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB
1221 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1222 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1223 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1224 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1225 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1226 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1227 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa
FB
1228 /* READ & SCAN commands and realign to a sector for WRITE */
1229 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
4f431960 1230 fdctrl->fifo, 1) < 0) {
8977f3c1
FB
1231 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1232 fd_sector(cur_drv));
1233 /* Sure, image size is too small... */
baca51fa 1234 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1235 }
890fa6be 1236 }
4f431960
JM
1237 switch (fdctrl->data_dir) {
1238 case FD_DIR_READ:
1239 /* READ commands */
85571bc7
FB
1240 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1241 fdctrl->data_pos, len);
4f431960
JM
1242 break;
1243 case FD_DIR_WRITE:
baca51fa 1244 /* WRITE commands */
8510854e
HP
1245 if (cur_drv->ro) {
1246 /* Handle readonly medium early, no need to do DMA, touch the
1247 * LED or attempt any writes. A real floppy doesn't attempt
1248 * to write to readonly media either. */
1249 fdctrl_stop_transfer(fdctrl,
1250 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1251 0x00);
1252 goto transfer_error;
1253 }
1254
85571bc7
FB
1255 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1256 fdctrl->data_pos, len);
baca51fa 1257 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
4f431960 1258 fdctrl->fifo, 1) < 0) {
cced7a13
BS
1259 FLOPPY_DPRINTF("error writing sector %d\n",
1260 fd_sector(cur_drv));
9fea808a 1261 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1262 goto transfer_error;
890fa6be 1263 }
4f431960
JM
1264 break;
1265 default:
1266 /* SCAN commands */
baca51fa 1267 {
4f431960 1268 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1269 int ret;
85571bc7 1270 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
baca51fa 1271 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1272 if (ret == 0) {
77370520 1273 status2 = FD_SR2_SEH;
8977f3c1
FB
1274 goto end_transfer;
1275 }
baca51fa
FB
1276 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1277 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB
1278 status2 = 0x00;
1279 goto end_transfer;
1280 }
1281 }
4f431960 1282 break;
8977f3c1 1283 }
4f431960
JM
1284 fdctrl->data_pos += len;
1285 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1286 if (rel_pos == 0) {
8977f3c1 1287 /* Seek to next sector */
746d6de7
BS
1288 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1289 break;
8977f3c1
FB
1290 }
1291 }
4f431960 1292 end_transfer:
baca51fa
FB
1293 len = fdctrl->data_pos - start_pos;
1294 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1295 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB
1296 if (fdctrl->data_dir == FD_DIR_SCANE ||
1297 fdctrl->data_dir == FD_DIR_SCANL ||
1298 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1299 status2 = FD_SR2_SEH;
baca51fa 1300 if (FD_DID_SEEK(fdctrl->data_state))
9fea808a 1301 status0 |= FD_SR0_SEEK;
baca51fa 1302 fdctrl->data_len -= len;
890fa6be 1303 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1304 transfer_error:
8977f3c1 1305
baca51fa 1306 return len;
8977f3c1
FB
1307}
1308
8977f3c1 1309/* Data register : 0x05 */
5c02c033 1310static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1311{
5c02c033 1312 FDrive *cur_drv;
8977f3c1 1313 uint32_t retval = 0;
746d6de7 1314 int pos;
8977f3c1 1315
baca51fa 1316 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS
1317 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1318 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1319 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB
1320 return 0;
1321 }
baca51fa 1322 pos = fdctrl->data_pos;
368df94d 1323 if (fdctrl->msr & FD_MSR_NONDMA) {
8977f3c1
FB
1324 pos %= FD_SECTOR_LEN;
1325 if (pos == 0) {
746d6de7
BS
1326 if (fdctrl->data_pos != 0)
1327 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1328 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1329 fd_sector(cur_drv));
1330 return 0;
1331 }
77370520
BS
1332 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1333 FLOPPY_DPRINTF("error getting sector %d\n",
1334 fd_sector(cur_drv));
1335 /* Sure, image size is too small... */
1336 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1337 }
8977f3c1
FB
1338 }
1339 }
baca51fa
FB
1340 retval = fdctrl->fifo[pos];
1341 if (++fdctrl->data_pos == fdctrl->data_len) {
1342 fdctrl->data_pos = 0;
890fa6be 1343 /* Switch from transfer mode to status mode
8977f3c1
FB
1344 * then from status mode to command mode
1345 */
368df94d 1346 if (fdctrl->msr & FD_MSR_NONDMA) {
9fea808a 1347 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
ed5fd2cc 1348 } else {
baca51fa 1349 fdctrl_reset_fifo(fdctrl);
ed5fd2cc
FB
1350 fdctrl_reset_irq(fdctrl);
1351 }
8977f3c1
FB
1352 }
1353 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1354
1355 return retval;
1356}
1357
5c02c033 1358static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1359{
5c02c033 1360 FDrive *cur_drv;
baca51fa 1361 uint8_t kh, kt, ks;
8977f3c1 1362
cefec4f5 1363 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB
1364 cur_drv = get_cur_drv(fdctrl);
1365 kt = fdctrl->fifo[6];
1366 kh = fdctrl->fifo[7];
1367 ks = fdctrl->fifo[8];
1368 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1369 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP
1370 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1371 NUM_SIDES(cur_drv)));
9fea808a 1372 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB
1373 case 2:
1374 /* sect too big */
9fea808a 1375 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB
1376 fdctrl->fifo[3] = kt;
1377 fdctrl->fifo[4] = kh;
1378 fdctrl->fifo[5] = ks;
1379 return;
1380 case 3:
1381 /* track too big */
77370520 1382 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB
1383 fdctrl->fifo[3] = kt;
1384 fdctrl->fifo[4] = kh;
1385 fdctrl->fifo[5] = ks;
1386 return;
1387 case 4:
1388 /* No seek enabled */
9fea808a 1389 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB
1390 fdctrl->fifo[3] = kt;
1391 fdctrl->fifo[4] = kh;
1392 fdctrl->fifo[5] = ks;
1393 return;
1394 case 1:
baca51fa
FB
1395 fdctrl->data_state |= FD_STATE_SEEK;
1396 break;
1397 default:
1398 break;
1399 }
1400 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1401 if (cur_drv->bs == NULL ||
1402 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
cced7a13 1403 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 1404 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1405 } else {
4f431960
JM
1406 if (cur_drv->sect == cur_drv->last_sect) {
1407 fdctrl->data_state &= ~FD_STATE_FORMAT;
1408 /* Last sector done */
1409 if (FD_DID_SEEK(fdctrl->data_state))
9fea808a 1410 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
4f431960
JM
1411 else
1412 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1413 } else {
1414 /* More to do */
1415 fdctrl->data_pos = 0;
1416 fdctrl->data_len = 4;
1417 }
baca51fa
FB
1418 }
1419}
1420
5c02c033 1421static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS
1422{
1423 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1424 fdctrl->fifo[0] = fdctrl->lock << 4;
a005186c 1425 fdctrl_set_fifo(fdctrl, 1, 0);
65cef780
BS
1426}
1427
5c02c033 1428static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 1429{
5c02c033 1430 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS
1431
1432 /* Drives position */
1433 fdctrl->fifo[0] = drv0(fdctrl)->track;
1434 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS
1435#if MAX_FD == 4
1436 fdctrl->fifo[2] = drv2(fdctrl)->track;
1437 fdctrl->fifo[3] = drv3(fdctrl)->track;
1438#else
65cef780
BS
1439 fdctrl->fifo[2] = 0;
1440 fdctrl->fifo[3] = 0;
78ae820c 1441#endif
65cef780
BS
1442 /* timers */
1443 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 1444 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS
1445 fdctrl->fifo[6] = cur_drv->last_sect;
1446 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1447 (cur_drv->perpendicular << 2);
1448 fdctrl->fifo[8] = fdctrl->config;
1449 fdctrl->fifo[9] = fdctrl->precomp_trk;
1450 fdctrl_set_fifo(fdctrl, 10, 0);
1451}
1452
5c02c033 1453static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS
1454{
1455 /* Controller's version */
1456 fdctrl->fifo[0] = fdctrl->version;
a005186c 1457 fdctrl_set_fifo(fdctrl, 1, 0);
65cef780
BS
1458}
1459
5c02c033 1460static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS
1461{
1462 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1463 fdctrl_set_fifo(fdctrl, 1, 0);
1464}
1465
5c02c033 1466static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 1467{
5c02c033 1468 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS
1469
1470 /* Drives position */
1471 drv0(fdctrl)->track = fdctrl->fifo[3];
1472 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS
1473#if MAX_FD == 4
1474 drv2(fdctrl)->track = fdctrl->fifo[5];
1475 drv3(fdctrl)->track = fdctrl->fifo[6];
1476#endif
65cef780
BS
1477 /* timers */
1478 fdctrl->timer0 = fdctrl->fifo[7];
1479 fdctrl->timer1 = fdctrl->fifo[8];
1480 cur_drv->last_sect = fdctrl->fifo[9];
1481 fdctrl->lock = fdctrl->fifo[10] >> 7;
1482 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1483 fdctrl->config = fdctrl->fifo[11];
1484 fdctrl->precomp_trk = fdctrl->fifo[12];
1485 fdctrl->pwrd = fdctrl->fifo[13];
1486 fdctrl_reset_fifo(fdctrl);
1487}
1488
5c02c033 1489static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 1490{
5c02c033 1491 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS
1492
1493 fdctrl->fifo[0] = 0;
1494 fdctrl->fifo[1] = 0;
1495 /* Drives position */
1496 fdctrl->fifo[2] = drv0(fdctrl)->track;
1497 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS
1498#if MAX_FD == 4
1499 fdctrl->fifo[4] = drv2(fdctrl)->track;
1500 fdctrl->fifo[5] = drv3(fdctrl)->track;
1501#else
65cef780
BS
1502 fdctrl->fifo[4] = 0;
1503 fdctrl->fifo[5] = 0;
78ae820c 1504#endif
65cef780
BS
1505 /* timers */
1506 fdctrl->fifo[6] = fdctrl->timer0;
1507 fdctrl->fifo[7] = fdctrl->timer1;
1508 fdctrl->fifo[8] = cur_drv->last_sect;
1509 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1510 (cur_drv->perpendicular << 2);
1511 fdctrl->fifo[10] = fdctrl->config;
1512 fdctrl->fifo[11] = fdctrl->precomp_trk;
1513 fdctrl->fifo[12] = fdctrl->pwrd;
1514 fdctrl->fifo[13] = 0;
1515 fdctrl->fifo[14] = 0;
a005186c 1516 fdctrl_set_fifo(fdctrl, 15, 0);
65cef780
BS
1517}
1518
5c02c033 1519static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 1520{
5c02c033 1521 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 1522
65cef780
BS
1523 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1524 qemu_mod_timer(fdctrl->result_timer,
74475455 1525 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
65cef780
BS
1526}
1527
5c02c033 1528static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 1529{
5c02c033 1530 FDrive *cur_drv;
65cef780 1531
cefec4f5 1532 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS
1533 cur_drv = get_cur_drv(fdctrl);
1534 fdctrl->data_state |= FD_STATE_FORMAT;
1535 if (fdctrl->fifo[0] & 0x80)
1536 fdctrl->data_state |= FD_STATE_MULTI;
1537 else
1538 fdctrl->data_state &= ~FD_STATE_MULTI;
1539 fdctrl->data_state &= ~FD_STATE_SEEK;
1540 cur_drv->bps =
1541 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1542#if 0
1543 cur_drv->last_sect =
1544 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1545 fdctrl->fifo[3] / 2;
1546#else
1547 cur_drv->last_sect = fdctrl->fifo[3];
1548#endif
1549 /* TODO: implement format using DMA expected by the Bochs BIOS
1550 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1551 * the sector with the specified fill byte
1552 */
1553 fdctrl->data_state &= ~FD_STATE_FORMAT;
1554 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1555}
1556
5c02c033 1557static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS
1558{
1559 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1560 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS
1561 if (fdctrl->fifo[2] & 1)
1562 fdctrl->dor &= ~FD_DOR_DMAEN;
1563 else
1564 fdctrl->dor |= FD_DOR_DMAEN;
65cef780
BS
1565 /* No result back */
1566 fdctrl_reset_fifo(fdctrl);
1567}
1568
5c02c033 1569static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 1570{
5c02c033 1571 FDrive *cur_drv;
65cef780 1572
cefec4f5 1573 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS
1574 cur_drv = get_cur_drv(fdctrl);
1575 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1576 /* 1 Byte status back */
1577 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1578 (cur_drv->track == 0 ? 0x10 : 0x00) |
1579 (cur_drv->head << 2) |
cefec4f5 1580 GET_CUR_DRV(fdctrl) |
65cef780
BS
1581 0x28;
1582 fdctrl_set_fifo(fdctrl, 1, 0);
1583}
1584
5c02c033 1585static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 1586{
5c02c033 1587 FDrive *cur_drv;
65cef780 1588
cefec4f5 1589 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS
1590 cur_drv = get_cur_drv(fdctrl);
1591 fd_recalibrate(cur_drv);
1592 fdctrl_reset_fifo(fdctrl);
1593 /* Raise Interrupt */
1594 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1595}
1596
5c02c033 1597static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 1598{
5c02c033 1599 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 1600
f2d81b33
BS
1601 if(fdctrl->reset_sensei > 0) {
1602 fdctrl->fifo[0] =
1603 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1604 fdctrl->reset_sensei--;
1605 } else {
1606 /* XXX: status0 handling is broken for read/write
1607 commands, so we do this hack. It should be suppressed
1608 ASAP */
1609 fdctrl->fifo[0] =
1610 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1611 }
1612
65cef780
BS
1613 fdctrl->fifo[1] = cur_drv->track;
1614 fdctrl_set_fifo(fdctrl, 2, 0);
1615 fdctrl_reset_irq(fdctrl);
77370520 1616 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS
1617}
1618
5c02c033 1619static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 1620{
5c02c033 1621 FDrive *cur_drv;
65cef780 1622
cefec4f5 1623 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 1624 cur_drv = get_cur_drv(fdctrl);
65cef780 1625 fdctrl_reset_fifo(fdctrl);
b072a3c8
HP
1626 /* The seek command just sends step pulses to the drive and doesn't care if
1627 * there is a medium inserted of if it's banging the head against the drive.
1628 */
65cef780 1629 if (fdctrl->fifo[2] > cur_drv->max_track) {
b072a3c8 1630 cur_drv->track = cur_drv->max_track;
65cef780
BS
1631 } else {
1632 cur_drv->track = fdctrl->fifo[2];
65cef780 1633 }
b072a3c8
HP
1634 /* Raise Interrupt */
1635 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
65cef780
BS
1636}
1637
5c02c033 1638static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 1639{
5c02c033 1640 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS
1641
1642 if (fdctrl->fifo[1] & 0x80)
1643 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1644 /* No result back */
1c346df2 1645 fdctrl_reset_fifo(fdctrl);
65cef780
BS
1646}
1647
5c02c033 1648static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS
1649{
1650 fdctrl->config = fdctrl->fifo[2];
1651 fdctrl->precomp_trk = fdctrl->fifo[3];
1652 /* No result back */
1653 fdctrl_reset_fifo(fdctrl);
1654}
1655
5c02c033 1656static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS
1657{
1658 fdctrl->pwrd = fdctrl->fifo[1];
1659 fdctrl->fifo[0] = fdctrl->fifo[1];
a005186c 1660 fdctrl_set_fifo(fdctrl, 1, 0);
65cef780
BS
1661}
1662
5c02c033 1663static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS
1664{
1665 /* No result back */
1666 fdctrl_reset_fifo(fdctrl);
1667}
1668
5c02c033 1669static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 1670{
5c02c033 1671 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS
1672
1673 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1674 /* Command parameters done */
1675 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1676 fdctrl->fifo[0] = fdctrl->fifo[1];
1677 fdctrl->fifo[2] = 0;
1678 fdctrl->fifo[3] = 0;
a005186c 1679 fdctrl_set_fifo(fdctrl, 4, 0);
65cef780
BS
1680 } else {
1681 fdctrl_reset_fifo(fdctrl);
1682 }
1683 } else if (fdctrl->data_len > 7) {
1684 /* ERROR */
1685 fdctrl->fifo[0] = 0x80 |
cefec4f5 1686 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
a005186c 1687 fdctrl_set_fifo(fdctrl, 1, 0);
65cef780
BS
1688 }
1689}
1690
5c02c033 1691static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 1692{
5c02c033 1693 FDrive *cur_drv;
65cef780 1694
cefec4f5 1695 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 1696 cur_drv = get_cur_drv(fdctrl);
65cef780
BS
1697 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1698 cur_drv->track = cur_drv->max_track - 1;
1699 } else {
1700 cur_drv->track += fdctrl->fifo[2];
1701 }
1702 fdctrl_reset_fifo(fdctrl);
77370520 1703 /* Raise Interrupt */
65cef780
BS
1704 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1705}
1706
5c02c033 1707static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 1708{
5c02c033 1709 FDrive *cur_drv;
65cef780 1710
cefec4f5 1711 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 1712 cur_drv = get_cur_drv(fdctrl);
65cef780
BS
1713 if (fdctrl->fifo[2] > cur_drv->track) {
1714 cur_drv->track = 0;
1715 } else {
1716 cur_drv->track -= fdctrl->fifo[2];
1717 }
1718 fdctrl_reset_fifo(fdctrl);
1719 /* Raise Interrupt */
1720 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1721}
1722
678803ab
BS
1723static const struct {
1724 uint8_t value;
1725 uint8_t mask;
1726 const char* name;
1727 int parameters;
5c02c033 1728 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab
BS
1729 int direction;
1730} handlers[] = {
1731 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1732 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1733 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1734 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1735 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1736 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1737 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1738 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1739 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1740 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1741 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1742 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1743 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1744 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1745 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1746 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1747 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1748 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1749 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1750 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1751 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1752 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1753 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1754 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1755 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1756 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1757 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1758 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1759 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1760 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1761 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1762 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1763};
1764/* Associate command to an index in the 'handlers' array */
1765static uint8_t command_to_handler[256];
1766
5c02c033 1767static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 1768{
5c02c033 1769 FDrive *cur_drv;
65cef780 1770 int pos;
baca51fa 1771
8977f3c1 1772 /* Reset mode */
1c346df2 1773 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1774 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB
1775 return;
1776 }
b9b3d225 1777 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1778 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB
1779 return;
1780 }
b9b3d225 1781 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1 1782 /* Is it write command time ? */
368df94d 1783 if (fdctrl->msr & FD_MSR_NONDMA) {
8977f3c1 1784 /* FIFO data write */
b3bc1540
BS
1785 pos = fdctrl->data_pos++;
1786 pos %= FD_SECTOR_LEN;
1787 fdctrl->fifo[pos] = value;
1788 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 1789 fdctrl->data_pos == fdctrl->data_len) {
77370520
BS
1790 cur_drv = get_cur_drv(fdctrl);
1791 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
cced7a13
BS
1792 FLOPPY_DPRINTF("error writing sector %d\n",
1793 fd_sector(cur_drv));
77370520
BS
1794 return;
1795 }
746d6de7
BS
1796 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1797 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1798 fd_sector(cur_drv));
1799 return;
1800 }
8977f3c1 1801 }
890fa6be 1802 /* Switch from transfer mode to status mode
8977f3c1
FB
1803 * then from status mode to command mode
1804 */
b9b3d225 1805 if (fdctrl->data_pos == fdctrl->data_len)
9fea808a 1806 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB
1807 return;
1808 }
baca51fa 1809 if (fdctrl->data_pos == 0) {
8977f3c1 1810 /* Command */
678803ab
BS
1811 pos = command_to_handler[value & 0xff];
1812 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1813 fdctrl->data_len = handlers[pos].parameters + 1;
1457a758 1814 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 1815 }
678803ab 1816
baca51fa 1817 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
77370520
BS
1818 fdctrl->fifo[fdctrl->data_pos++] = value;
1819 if (fdctrl->data_pos == fdctrl->data_len) {
8977f3c1
FB
1820 /* We now have all parameters
1821 * and will be able to treat the command
1822 */
4f431960
JM
1823 if (fdctrl->data_state & FD_STATE_FORMAT) {
1824 fdctrl_format_sector(fdctrl);
8977f3c1
FB
1825 return;
1826 }
65cef780 1827
678803ab
BS
1828 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1829 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1830 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
8977f3c1
FB
1831 }
1832}
ed5fd2cc
FB
1833
1834static void fdctrl_result_timer(void *opaque)
1835{
5c02c033
BS
1836 FDCtrl *fdctrl = opaque;
1837 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 1838
b7ffa3b1
TS
1839 /* Pretend we are spinning.
1840 * This is needed for Coherent, which uses READ ID to check for
1841 * sector interleaving.
1842 */
1843 if (cur_drv->last_sect != 0) {
1844 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1845 }
844f65d6
HP
1846 /* READ_ID can't automatically succeed! */
1847 if (fdctrl->check_media_rate &&
1848 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1849 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1850 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1851 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1852 } else {
1853 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1854 }
ed5fd2cc 1855}
678803ab 1856
7d4b4ba5 1857static void fdctrl_change_cb(void *opaque, bool load)
8e49ca46
MA
1858{
1859 FDrive *drive = opaque;
1860
1861 drive->media_changed = 1;
21fcf360 1862 fd_revalidate(drive);
8e49ca46
MA
1863}
1864
1865static const BlockDevOps fdctrl_block_ops = {
1866 .change_media_cb = fdctrl_change_cb,
1867};
1868
678803ab 1869/* Init functions */
b47b3525 1870static int fdctrl_connect_drives(FDCtrl *fdctrl)
678803ab 1871{
12a71a02 1872 unsigned int i;
7d0d6950 1873 FDrive *drive;
678803ab 1874
678803ab 1875 for (i = 0; i < MAX_FD; i++) {
7d0d6950 1876 drive = &fdctrl->drives[i];
844f65d6 1877 drive->fdctrl = fdctrl;
7d0d6950 1878
b47b3525
MA
1879 if (drive->bs) {
1880 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1881 error_report("fdc doesn't support drive option werror");
1882 return -1;
1883 }
1884 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1885 error_report("fdc doesn't support drive option rerror");
1886 return -1;
1887 }
1888 }
1889
7d0d6950 1890 fd_init(drive);
cfb08fba 1891 fdctrl_change_cb(drive, 0);
7d0d6950 1892 if (drive->bs) {
8e49ca46 1893 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
7d0d6950 1894 }
678803ab 1895 }
b47b3525 1896 return 0;
678803ab
BS
1897}
1898
dfc65f1f
MA
1899ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
1900{
1901 ISADevice *dev;
1902
1903 dev = isa_try_create(bus, "isa-fdc");
1904 if (!dev) {
1905 return NULL;
1906 }
1907
1908 if (fds[0]) {
1909 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv);
1910 }
1911 if (fds[1]) {
1912 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv);
1913 }
1914 qdev_init_nofail(&dev->qdev);
1915
1916 return dev;
1917}
1918
63ffb564
BS
1919void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1920 target_phys_addr_t mmio_base, DriveInfo **fds)
2091ba23 1921{
5c02c033 1922 FDCtrl *fdctrl;
2091ba23 1923 DeviceState *dev;
5c02c033 1924 FDCtrlSysBus *sys;
2091ba23
GH
1925
1926 dev = qdev_create(NULL, "sysbus-fdc");
5c02c033 1927 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
99244fa1
GH
1928 fdctrl = &sys->state;
1929 fdctrl->dma_chann = dma_chann; /* FIXME */
995bf0ca 1930 if (fds[0]) {
18846dee 1931 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
995bf0ca
GH
1932 }
1933 if (fds[1]) {
18846dee 1934 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
995bf0ca 1935 }
e23a1b33 1936 qdev_init_nofail(dev);
2091ba23
GH
1937 sysbus_connect_irq(&sys->busdev, 0, irq);
1938 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
678803ab
BS
1939}
1940
63ffb564
BS
1941void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1942 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 1943{
f64ab228 1944 DeviceState *dev;
5c02c033 1945 FDCtrlSysBus *sys;
678803ab 1946
12a71a02 1947 dev = qdev_create(NULL, "SUNW,fdtwo");
995bf0ca 1948 if (fds[0]) {
18846dee 1949 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
995bf0ca 1950 }
e23a1b33 1951 qdev_init_nofail(dev);
5c02c033 1952 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
8baf73ad
GH
1953 sysbus_connect_irq(&sys->busdev, 0, irq);
1954 sysbus_mmio_map(&sys->busdev, 0, io_base);
f64ab228 1955 *fdc_tc = qdev_get_gpio_in(dev, 0);
678803ab 1956}
f64ab228 1957
a64405d1 1958static int fdctrl_init_common(FDCtrl *fdctrl)
f64ab228 1959{
12a71a02
BS
1960 int i, j;
1961 static int command_tables_inited = 0;
f64ab228 1962
12a71a02
BS
1963 /* Fill 'command_to_handler' lookup table */
1964 if (!command_tables_inited) {
1965 command_tables_inited = 1;
1966 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1967 for (j = 0; j < sizeof(command_to_handler); j++) {
1968 if ((j & handlers[i].mask) == handlers[i].value) {
1969 command_to_handler[j] = i;
1970 }
1971 }
1972 }
1973 }
1974
1975 FLOPPY_DPRINTF("init controller\n");
1976 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
d7a6c270 1977 fdctrl->fifo_size = 512;
74475455 1978 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
12a71a02
BS
1979 fdctrl_result_timer, fdctrl);
1980
1981 fdctrl->version = 0x90; /* Intel 82078 controller */
1982 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 1983 fdctrl->num_floppies = MAX_FD;
12a71a02 1984
99244fa1
GH
1985 if (fdctrl->dma_chann != -1)
1986 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
b47b3525 1987 return fdctrl_connect_drives(fdctrl);
f64ab228
BS
1988}
1989
212ec7ba 1990static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 1991 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH
1992 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1993 PORTIO_END_OF_LIST(),
2f290a8c
RH
1994};
1995
81a322d4 1996static int isabus_fdc_init1(ISADevice *dev)
8baf73ad 1997{
5c02c033
BS
1998 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1999 FDCtrl *fdctrl = &isa->state;
2be37833 2000 int ret;
8baf73ad 2001
c9ae703d 2002 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc");
dee41d58 2003
c9ae703d
HP
2004 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq);
2005 fdctrl->dma_chann = isa->dma;
8baf73ad 2006
c9ae703d 2007 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2);
a64405d1 2008 ret = fdctrl_init_common(fdctrl);
2be37833 2009
1ca4d09a
GN
2010 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
2011 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
2012
2be37833 2013 return ret;
8baf73ad
GH
2014}
2015
81a322d4 2016static int sysbus_fdc_init1(SysBusDevice *dev)
12a71a02 2017{
5c02c033
BS
2018 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
2019 FDCtrl *fdctrl = &sys->state;
2be37833 2020 int ret;
12a71a02 2021
dc6c1b37 2022 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
750ecd44 2023 sysbus_init_mmio(dev, &fdctrl->iomem);
8baf73ad
GH
2024 sysbus_init_irq(dev, &fdctrl->irq);
2025 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
99244fa1 2026 fdctrl->dma_chann = -1;
8baf73ad 2027
dc6c1b37 2028 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
a64405d1 2029 ret = fdctrl_init_common(fdctrl);
2be37833
BS
2030
2031 return ret;
12a71a02
BS
2032}
2033
81a322d4 2034static int sun4m_fdc_init1(SysBusDevice *dev)
12a71a02 2035{
5c02c033 2036 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
12a71a02 2037
dc6c1b37
AK
2038 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2039 "fdctrl", 0x08);
750ecd44 2040 sysbus_init_mmio(dev, &fdctrl->iomem);
8baf73ad
GH
2041 sysbus_init_irq(dev, &fdctrl->irq);
2042 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2043
2044 fdctrl->sun4m = 1;
dc6c1b37 2045 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
a64405d1 2046 return fdctrl_init_common(fdctrl);
12a71a02 2047}
f64ab228 2048
34d4260e
KW
2049void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
2050{
2051 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2052 FDCtrl *fdctrl = &isa->state;
2053 int i;
2054
2055 for (i = 0; i < MAX_FD; i++) {
2056 bs[i] = fdctrl->drives[i].bs;
2057 }
2058}
2059
2060
a64405d1
JK
2061static const VMStateDescription vmstate_isa_fdc ={
2062 .name = "fdc",
2063 .version_id = 2,
2064 .minimum_version_id = 2,
2065 .fields = (VMStateField []) {
2066 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2067 VMSTATE_END_OF_LIST()
2068 }
2069};
2070
39bffca2 2071static Property isa_fdc_properties[] = {
c9ae703d
HP
2072 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2073 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2074 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
39bffca2
AL
2075 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2076 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2077 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2078 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
09c6d585
HP
2079 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2080 0, true),
39bffca2
AL
2081 DEFINE_PROP_END_OF_LIST(),
2082};
2083
8f04ee08
AL
2084static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2085{
39bffca2 2086 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08
AL
2087 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2088 ic->init = isabus_fdc_init1;
39bffca2
AL
2089 dc->fw_name = "fdc";
2090 dc->no_user = 1;
2091 dc->reset = fdctrl_external_reset_isa;
2092 dc->vmsd = &vmstate_isa_fdc;
2093 dc->props = isa_fdc_properties;
2094}
2095
2096static TypeInfo isa_fdc_info = {
2097 .name = "isa-fdc",
2098 .parent = TYPE_ISA_DEVICE,
2099 .instance_size = sizeof(FDCtrlISABus),
2100 .class_init = isabus_fdc_class_init1,
8baf73ad
GH
2101};
2102
a64405d1
JK
2103static const VMStateDescription vmstate_sysbus_fdc ={
2104 .name = "fdc",
2105 .version_id = 2,
2106 .minimum_version_id = 2,
2107 .fields = (VMStateField []) {
2108 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2109 VMSTATE_END_OF_LIST()
2110 }
2111};
2112
999e12bb
AL
2113static Property sysbus_fdc_properties[] = {
2114 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2115 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2116 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS
2117};
2118
999e12bb
AL
2119static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2120{
39bffca2 2121 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL
2122 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2123
2124 k->init = sysbus_fdc_init1;
39bffca2
AL
2125 dc->reset = fdctrl_external_reset_sysbus;
2126 dc->vmsd = &vmstate_sysbus_fdc;
2127 dc->props = sysbus_fdc_properties;
999e12bb
AL
2128}
2129
39bffca2
AL
2130static TypeInfo sysbus_fdc_info = {
2131 .name = "sysbus-fdc",
2132 .parent = TYPE_SYS_BUS_DEVICE,
2133 .instance_size = sizeof(FDCtrlSysBus),
2134 .class_init = sysbus_fdc_class_init,
999e12bb
AL
2135};
2136
2137static Property sun4m_fdc_properties[] = {
2138 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2139 DEFINE_PROP_END_OF_LIST(),
2140};
2141
2142static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2143{
39bffca2 2144 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL
2145 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2146
2147 k->init = sun4m_fdc_init1;
39bffca2
AL
2148 dc->reset = fdctrl_external_reset_sysbus;
2149 dc->vmsd = &vmstate_sysbus_fdc;
2150 dc->props = sun4m_fdc_properties;
999e12bb
AL
2151}
2152
39bffca2
AL
2153static TypeInfo sun4m_fdc_info = {
2154 .name = "SUNW,fdtwo",
2155 .parent = TYPE_SYS_BUS_DEVICE,
2156 .instance_size = sizeof(FDCtrlSysBus),
2157 .class_init = sun4m_fdc_class_init,
f64ab228
BS
2158};
2159
83f7d43a 2160static void fdc_register_types(void)
f64ab228 2161{
39bffca2
AL
2162 type_register_static(&isa_fdc_info);
2163 type_register_static(&sysbus_fdc_info);
2164 type_register_static(&sun4m_fdc_info);
f64ab228
BS
2165}
2166
83f7d43a 2167type_init(fdc_register_types)