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1/* NOR flash devices */
2typedef struct pflash_t pflash_t;
3
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4/* pflash_cfi01.c */
5pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
6 BlockDriverState *bs,
7 uint32_t sector_len, int nb_blocs, int width,
8 uint16_t id0, uint16_t id1,
9 uint16_t id2, uint16_t id3);
10
11/* pflash_cfi02.c */
12pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
cf6d9118 13 BlockDriverState *bs, uint32_t sector_len,
4fbd24ba 14 int nb_blocs, int nb_mappings, int width,
88eeee0a 15 uint16_t id0, uint16_t id1,
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16 uint16_t id2, uint16_t id3,
17 uint16_t unlock_addr0, uint16_t unlock_addr1);
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18
19/* nand.c */
20struct nand_flash_s;
21struct nand_flash_s *nand_init(int manf_id, int chip_id);
22void nand_done(struct nand_flash_s *s);
23void nand_setpins(struct nand_flash_s *s,
24 int cle, int ale, int ce, int wp, int gnd);
25void nand_getpins(struct nand_flash_s *s, int *rb);
26void nand_setio(struct nand_flash_s *s, uint8_t value);
27uint8_t nand_getio(struct nand_flash_s *s);
28
29#define NAND_MFR_TOSHIBA 0x98
30#define NAND_MFR_SAMSUNG 0xec
31#define NAND_MFR_FUJITSU 0x04
32#define NAND_MFR_NATIONAL 0x8f
33#define NAND_MFR_RENESAS 0x07
34#define NAND_MFR_STMICRO 0x20
35#define NAND_MFR_HYNIX 0xad
36#define NAND_MFR_MICRON 0x2c
37
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38/* onenand.c */
39void onenand_base_update(void *opaque, target_phys_addr_t new);
40void onenand_base_unmap(void *opaque);
41void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
c580d92b 42void *onenand_raw_otp(void *opaque);
7e7c5e4c 43
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44/* ecc.c */
45struct ecc_state_s {
46 uint8_t cp; /* Column parity */
47 uint16_t lp[2]; /* Line parity */
48 uint16_t count;
49};
50
51uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
52void ecc_reset(struct ecc_state_s *s);
53void ecc_put(QEMUFile *f, struct ecc_state_s *s);
54void ecc_get(QEMUFile *f, struct ecc_state_s *s);