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1fc3d392
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1/*
2 * QEMU G364 framebuffer Emulator.
3 *
97a3f6ff 4 * Copyright (c) 2007-2011 Herve Poussineau
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5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
fad6cb1a 16 * You should have received a copy of the GNU General Public License along
8167ee88 17 * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 */
19
20#include "hw.h"
21#include "console.h"
22#include "pixel_ops.h"
b213b370 23#include "trace.h"
97a3f6ff 24#include "sysbus.h"
0add30cf 25
1fc3d392 26typedef struct G364State {
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27 /* hardware */
28 uint8_t *vram;
97a3f6ff 29 uint32_t vram_size;
0add30cf 30 qemu_irq irq;
97a3f6ff
HP
31 MemoryRegion mem_vram;
32 MemoryRegion mem_ctrl;
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33 /* registers */
34 uint8_t color_palette[256][3];
35 uint8_t cursor_palette[3][3];
36 uint16_t cursor[512];
37 uint32_t cursor_position;
1fc3d392 38 uint32_t ctla;
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39 uint32_t top_of_screen;
40 uint32_t width, height; /* in pixels */
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41 /* display refresh support */
42 DisplayState *ds;
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43 int depth;
44 int blanked;
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45} G364State;
46
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HP
47#define REG_BOOT 0x000000
48#define REG_DISPLAY 0x000118
49#define REG_VDISPLAY 0x000150
50#define REG_CTLA 0x000300
51#define REG_TOP 0x000400
52#define REG_CURS_PAL 0x000508
53#define REG_CURS_POS 0x000638
54#define REG_CLR_PAL 0x000800
55#define REG_CURS_PAT 0x001000
56#define REG_RESET 0x100000
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57
58#define CTLA_FORCE_BLANK 0x00000400
59#define CTLA_NO_CURSOR 0x00800000
60
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61#define G364_PAGE_SIZE 4096
62
97a3f6ff 63static inline int check_dirty(G364State *s, ram_addr_t page)
0add30cf 64{
97a3f6ff 65 return memory_region_get_dirty(&s->mem_vram, page, DIRTY_MEMORY_VGA);
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66}
67
68static inline void reset_dirty(G364State *s,
c227f099 69 ram_addr_t page_min, ram_addr_t page_max)
0add30cf 70{
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71 memory_region_reset_dirty(&s->mem_vram,
72 page_min,
1213406b 73 page_max + G364_PAGE_SIZE - page_min - 1,
97a3f6ff 74 DIRTY_MEMORY_VGA);
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75}
76
77static void g364fb_draw_graphic8(G364State *s)
1fc3d392 78{
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79 int i, w;
80 uint8_t *vram;
81 uint8_t *data_display, *dd;
c227f099 82 ram_addr_t page, page_min, page_max;
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83 int x, y;
84 int xmin, xmax;
85 int ymin, ymax;
86 int xcursor, ycursor;
87 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
88
0e1f5a0c 89 switch (ds_get_bits_per_pixel(s->ds)) {
1fc3d392 90 case 8:
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91 rgb_to_pixel = rgb_to_pixel8;
92 w = 1;
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93 break;
94 case 15:
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95 rgb_to_pixel = rgb_to_pixel15;
96 w = 2;
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97 break;
98 case 16:
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99 rgb_to_pixel = rgb_to_pixel16;
100 w = 2;
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101 break;
102 case 32:
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103 rgb_to_pixel = rgb_to_pixel32;
104 w = 4;
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105 break;
106 default:
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107 hw_error("g364: unknown host depth %d",
108 ds_get_bits_per_pixel(s->ds));
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109 return;
110 }
111
97a3f6ff 112 page = 0;
c227f099 113 page_min = (ram_addr_t)-1;
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114 page_max = 0;
115
116 x = y = 0;
117 xmin = s->width;
118 xmax = 0;
119 ymin = s->height;
120 ymax = 0;
121
122 if (!(s->ctla & CTLA_NO_CURSOR)) {
123 xcursor = s->cursor_position >> 12;
124 ycursor = s->cursor_position & 0xfff;
125 } else {
126 xcursor = ycursor = -65;
127 }
128
129 vram = s->vram + s->top_of_screen;
130 /* XXX: out of range in vram? */
131 data_display = dd = ds_get_data(s->ds);
132 while (y < s->height) {
97a3f6ff 133 if (check_dirty(s, page)) {
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134 if (y < ymin)
135 ymin = ymax = y;
c227f099 136 if (page_min == (ram_addr_t)-1)
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137 page_min = page;
138 page_max = page;
139 if (x < xmin)
140 xmin = x;
1213406b 141 for (i = 0; i < G364_PAGE_SIZE; i++) {
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142 uint8_t index;
143 unsigned int color;
144 if (unlikely((y >= ycursor && y < ycursor + 64) &&
145 (x >= xcursor && x < xcursor + 64))) {
146 /* pointer area */
147 int xdiff = x - xcursor;
148 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
149 int op = (curs >> ((xdiff & 7) * 2)) & 3;
150 if (likely(op == 0)) {
151 /* transparent */
152 index = *vram;
153 color = (*rgb_to_pixel)(
154 s->color_palette[index][0],
155 s->color_palette[index][1],
156 s->color_palette[index][2]);
157 } else {
158 /* get cursor color */
159 index = op - 1;
160 color = (*rgb_to_pixel)(
161 s->cursor_palette[index][0],
162 s->cursor_palette[index][1],
163 s->cursor_palette[index][2]);
164 }
165 } else {
166 /* normal area */
167 index = *vram;
168 color = (*rgb_to_pixel)(
169 s->color_palette[index][0],
170 s->color_palette[index][1],
171 s->color_palette[index][2]);
172 }
173 memcpy(dd, &color, w);
174 dd += w;
175 x++;
176 vram++;
177 if (x == s->width) {
178 xmax = s->width - 1;
179 y++;
180 if (y == s->height) {
181 ymax = s->height - 1;
182 goto done;
183 }
184 data_display = dd = data_display + ds_get_linesize(s->ds);
185 xmin = 0;
186 x = 0;
187 }
188 }
189 if (x > xmax)
190 xmax = x;
191 if (y > ymax)
192 ymax = y;
193 } else {
194 int dy;
c227f099 195 if (page_min != (ram_addr_t)-1) {
0add30cf 196 reset_dirty(s, page_min, page_max);
c227f099 197 page_min = (ram_addr_t)-1;
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198 page_max = 0;
199 dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
200 xmin = s->width;
201 xmax = 0;
202 ymin = s->height;
203 ymax = 0;
204 }
1213406b 205 x += G364_PAGE_SIZE;
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206 dy = x / s->width;
207 x = x % s->width;
208 y += dy;
1213406b 209 vram += G364_PAGE_SIZE;
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210 data_display += dy * ds_get_linesize(s->ds);
211 dd = data_display + x * w;
212 }
1213406b 213 page += G364_PAGE_SIZE;
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214 }
215
216done:
c227f099 217 if (page_min != (ram_addr_t)-1) {
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218 dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
219 reset_dirty(s, page_min, page_max);
220 }
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221}
222
0add30cf 223static void g364fb_draw_blank(G364State *s)
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224{
225 int i, w;
226 uint8_t *d;
227
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228 if (s->blanked) {
229 /* Screen is already blank. No need to redraw it */
1fc3d392 230 return;
0add30cf 231 }
1fc3d392 232
0add30cf 233 w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
0e1f5a0c 234 d = ds_get_data(s->ds);
0add30cf 235 for (i = 0; i < s->height; i++) {
1fc3d392 236 memset(d, 0, w);
0e1f5a0c 237 d += ds_get_linesize(s->ds);
1fc3d392 238 }
221bb2d5 239
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240 dpy_update(s->ds, 0, 0, s->width, s->height);
241 s->blanked = 1;
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242}
243
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244static void g364fb_update_display(void *opaque)
245{
246 G364State *s = opaque;
1fc3d392 247
0add30cf 248 if (s->width == 0 || s->height == 0)
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249 return;
250
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251 if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
252 qemu_console_resize(s->ds, s->width, s->height);
221bb2d5 253 }
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254
255 if (s->ctla & CTLA_FORCE_BLANK) {
256 g364fb_draw_blank(s);
257 } else if (s->depth == 8) {
258 g364fb_draw_graphic8(s);
259 } else {
b213b370 260 error_report("g364: unknown guest depth %d", s->depth);
1fc3d392 261 }
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262
263 qemu_irq_raise(s->irq);
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264}
265
86178a57 266static inline void g364fb_invalidate_display(void *opaque)
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267{
268 G364State *s = opaque;
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269 int i;
270
271 s->blanked = 0;
1213406b 272 for (i = 0; i < s->vram_size; i += G364_PAGE_SIZE) {
97a3f6ff 273 memory_region_set_dirty(&s->mem_vram, i);
0add30cf 274 }
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275}
276
97a3f6ff 277static void g364fb_reset(G364State *s)
1fc3d392 278{
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279 qemu_irq_lower(s->irq);
280
281 memset(s->color_palette, 0, sizeof(s->color_palette));
282 memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
283 memset(s->cursor, 0, sizeof(s->cursor));
284 s->cursor_position = 0;
285 s->ctla = 0;
286 s->top_of_screen = 0;
287 s->width = s->height = 0;
288 memset(s->vram, 0, s->vram_size);
97a3f6ff 289 g364fb_invalidate_display(s);
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290}
291
292static void g364fb_screen_dump(void *opaque, const char *filename)
293{
294 G364State *s = opaque;
295 int y, x;
296 uint8_t index;
297 uint8_t *data_buffer;
298 FILE *f;
299
0add30cf 300 if (s->depth != 8) {
b213b370 301 error_report("g364: unknown guest depth %d", s->depth);
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302 return;
303 }
304
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305 f = fopen(filename, "wb");
306 if (!f)
307 return;
308
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309 if (s->ctla & CTLA_FORCE_BLANK) {
310 /* blank screen */
311 fprintf(f, "P4\n%d %d\n",
312 s->width, s->height);
313 for (y = 0; y < s->height; y++)
314 for (x = 0; x < s->width; x++)
315 fputc(0, f);
316 } else {
317 data_buffer = s->vram + s->top_of_screen;
318 fprintf(f, "P6\n%d %d\n%d\n",
319 s->width, s->height, 255);
320 for (y = 0; y < s->height; y++)
321 for (x = 0; x < s->width; x++, data_buffer++) {
322 index = *data_buffer;
323 fputc(s->color_palette[index][0], f);
324 fputc(s->color_palette[index][1], f);
325 fputc(s->color_palette[index][2], f);
1fc3d392 326 }
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327 }
328
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329 fclose(f);
330}
331
332/* called for accesses to io ports */
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HP
333static uint64_t g364fb_ctrl_read(void *opaque,
334 target_phys_addr_t addr,
335 unsigned int size)
1fc3d392 336{
0add30cf 337 G364State *s = opaque;
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338 uint32_t val;
339
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340 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
341 /* cursor pattern */
342 int idx = (addr - REG_CURS_PAT) >> 3;
343 val = s->cursor[idx];
344 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
345 /* cursor palette */
346 int idx = (addr - REG_CURS_PAL) >> 3;
347 val = ((uint32_t)s->cursor_palette[idx][0] << 16);
348 val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
349 val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
350 } else {
351 switch (addr) {
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352 case REG_DISPLAY:
353 val = s->width / 4;
354 break;
355 case REG_VDISPLAY:
356 val = s->height * 2;
357 break;
358 case REG_CTLA:
359 val = s->ctla;
360 break;
361 default:
362 {
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HP
363 error_report("g364: invalid read at [" TARGET_FMT_plx "]",
364 addr);
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365 val = 0;
366 break;
367 }
368 }
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369 }
370
b213b370 371 trace_g364fb_read(addr, val);
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372
373 return val;
374}
375
0add30cf 376static void g364fb_update_depth(G364State *s)
1fc3d392 377{
38972938 378 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
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379 s->depth = depths[(s->ctla & 0x00700000) >> 20];
380}
1fc3d392 381
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382static void g364_invalidate_cursor_position(G364State *s)
383{
384 int ymin, ymax, start, end, i;
1fc3d392 385
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386 /* invalidate only near the cursor */
387 ymin = s->cursor_position & 0xfff;
388 ymax = MIN(s->height, ymin + 64);
389 start = ymin * ds_get_linesize(s->ds);
390 end = (ymax + 1) * ds_get_linesize(s->ds);
1fc3d392 391
1213406b 392 for (i = start; i < end; i += G364_PAGE_SIZE) {
97a3f6ff 393 memory_region_set_dirty(&s->mem_vram, i);
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394 }
395}
396
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HP
397static void g364fb_ctrl_write(void *opaque,
398 target_phys_addr_t addr,
399 uint64_t val,
400 unsigned int size)
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401{
402 G364State *s = opaque;
403
b213b370 404 trace_g364fb_write(addr, val);
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405
406 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
1fc3d392 407 /* color palette */
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408 int idx = (addr - REG_CLR_PAL) >> 3;
409 s->color_palette[idx][0] = (val >> 16) & 0xff;
410 s->color_palette[idx][1] = (val >> 8) & 0xff;
411 s->color_palette[idx][2] = val & 0xff;
412 g364fb_invalidate_display(s);
413 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
414 /* cursor pattern */
415 int idx = (addr - REG_CURS_PAT) >> 3;
416 s->cursor[idx] = val;
417 g364fb_invalidate_display(s);
418 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
419 /* cursor palette */
420 int idx = (addr - REG_CURS_PAL) >> 3;
421 s->cursor_palette[idx][0] = (val >> 16) & 0xff;
422 s->cursor_palette[idx][1] = (val >> 8) & 0xff;
423 s->cursor_palette[idx][2] = val & 0xff;
424 g364fb_invalidate_display(s);
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425 } else {
426 switch (addr) {
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HP
427 case REG_BOOT: /* Boot timing */
428 case 0x00108: /* Line timing: half sync */
429 case 0x00110: /* Line timing: back porch */
430 case 0x00120: /* Line timing: short display */
431 case 0x00128: /* Frame timing: broad pulse */
432 case 0x00130: /* Frame timing: v sync */
433 case 0x00138: /* Frame timing: v preequalise */
434 case 0x00140: /* Frame timing: v postequalise */
435 case 0x00148: /* Frame timing: v blank */
436 case 0x00158: /* Line timing: line time */
437 case 0x00160: /* Frame store: line start */
438 case 0x00168: /* vram cycle: mem init */
439 case 0x00170: /* vram cycle: transfer delay */
440 case 0x00200: /* vram cycle: mask register */
441 /* ignore */
442 break;
443 case REG_TOP:
444 s->top_of_screen = val;
445 g364fb_invalidate_display(s);
446 break;
447 case REG_DISPLAY:
448 s->width = val * 4;
449 break;
450 case REG_VDISPLAY:
451 s->height = val / 2;
452 break;
453 case REG_CTLA:
454 s->ctla = val;
455 g364fb_update_depth(s);
456 g364fb_invalidate_display(s);
457 break;
458 case REG_CURS_POS:
459 g364_invalidate_cursor_position(s);
460 s->cursor_position = val;
461 g364_invalidate_cursor_position(s);
462 break;
463 case REG_RESET:
464 g364fb_reset(s);
465 break;
466 default:
467 error_report("g364: invalid write of 0x%" PRIx64
468 " at [" TARGET_FMT_plx "]", val, addr);
469 break;
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470 }
471 }
0add30cf 472 qemu_irq_lower(s->irq);
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473}
474
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HP
475static const MemoryRegionOps g364fb_ctrl_ops = {
476 .read = g364fb_ctrl_read,
477 .write = g364fb_ctrl_write,
478 .endianness = DEVICE_LITTLE_ENDIAN,
479 .impl.min_access_size = 4,
480 .impl.max_access_size = 4,
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481};
482
97a3f6ff 483static int g364fb_post_load(void *opaque, int version_id)
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484{
485 G364State *s = opaque;
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486
487 /* force refresh */
488 g364fb_update_depth(s);
489 g364fb_invalidate_display(s);
1fc3d392 490
0add30cf 491 return 0;
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492}
493
97a3f6ff
HP
494static const VMStateDescription vmstate_g364fb = {
495 .name = "g364fb",
496 .version_id = 1,
497 .minimum_version_id = 1,
498 .minimum_version_id_old = 1,
499 .post_load = g364fb_post_load,
500 .fields = (VMStateField[]) {
501 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
502 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
503 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
504 VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
505 VMSTATE_UINT32(cursor_position, G364State),
506 VMSTATE_UINT32(ctla, G364State),
507 VMSTATE_UINT32(top_of_screen, G364State),
508 VMSTATE_UINT32(width, G364State),
509 VMSTATE_UINT32(height, G364State),
510 VMSTATE_END_OF_LIST()
511 }
512};
1fc3d392 513
97a3f6ff 514static void g364fb_init(DeviceState *dev, G364State *s)
1fc3d392 515{
97a3f6ff 516 s->vram = g_malloc0(s->vram_size);
1fc3d392 517
3023f332
AL
518 s->ds = graphic_console_init(g364fb_update_display,
519 g364fb_invalidate_display,
520 g364fb_screen_dump, NULL, s);
1fc3d392 521
97a3f6ff
HP
522 memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
523 memory_region_init_ram_ptr(&s->mem_vram, dev, "vram",
524 s->vram_size, s->vram);
525 memory_region_set_coalescing(&s->mem_vram);
526}
527
528typedef struct {
529 SysBusDevice busdev;
530 G364State g364;
531} G364SysBusState;
1fc3d392 532
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533static int g364fb_sysbus_init(SysBusDevice *dev)
534{
535 G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
536
537 g364fb_init(&dev->qdev, s);
538 sysbus_init_irq(dev, &s->irq);
539 sysbus_init_mmio_region(dev, &s->mem_ctrl);
540 sysbus_init_mmio_region(dev, &s->mem_vram);
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541
542 return 0;
543}
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HP
544
545static void g364fb_sysbus_reset(DeviceState *d)
546{
547 G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
548 g364fb_reset(&s->g364);
549}
550
551static SysBusDeviceInfo g364fb_sysbus_info = {
552 .init = g364fb_sysbus_init,
553 .qdev.name = "sysbus-g364",
554 .qdev.desc = "G364 framebuffer",
555 .qdev.size = sizeof(G364SysBusState),
556 .qdev.vmsd = &vmstate_g364fb,
557 .qdev.reset = g364fb_sysbus_reset,
558 .qdev.props = (Property[]) {
559 DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
560 8 * 1024 * 1024),
561 DEFINE_PROP_END_OF_LIST(),
562 }
563};
564
565static void g364fb_register(void)
566{
567 sysbus_register_withprop(&g364fb_sysbus_info);
568}
569
570device_init(g364fb_register);