[qemu.git] / hw / g364fb.c

/*
 * QEMU G364 framebuffer Emulator.
 *
 * Copyright (c) 2007-2011 Herve Poussineau
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw.h"
#include "console.h"
#include "pixel_ops.h"
#include "trace.h"
#include "sysbus.h"

typedef struct G364State {
    /* hardware */
    uint8_t *vram;
    uint32_t vram_size;
    qemu_irq irq;
    MemoryRegion mem_vram;
    MemoryRegion mem_ctrl;
    /* registers */
    uint8_t color_palette[256][3];
    uint8_t cursor_palette[3][3];
    uint16_t cursor[512];
    uint32_t cursor_position;
    uint32_t ctla;
    uint32_t top_of_screen;
    uint32_t width, height; /* in pixels */
    /* display refresh support */
    DisplayState *ds;
    int depth;
    int blanked;
} G364State;

#define REG_BOOT     0x000000
#define REG_DISPLAY  0x000118
#define REG_VDISPLAY 0x000150
#define REG_CTLA     0x000300
#define REG_TOP      0x000400
#define REG_CURS_PAL 0x000508
#define REG_CURS_POS 0x000638
#define REG_CLR_PAL  0x000800
#define REG_CURS_PAT 0x001000
#define REG_RESET    0x100000

#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR   0x00800000

#define G364_PAGE_SIZE 4096

static inline int check_dirty(G364State *s, ram_addr_t page)
{
    return memory_region_get_dirty(&s->mem_vram, page, DIRTY_MEMORY_VGA);
}

static inline void reset_dirty(G364State *s,
                               ram_addr_t page_min, ram_addr_t page_max)
{
    memory_region_reset_dirty(&s->mem_vram,
                              page_min,
                              page_max + G364_PAGE_SIZE - page_min - 1,
                              DIRTY_MEMORY_VGA);
}

static void g364fb_draw_graphic8(G364State *s)
{
    int i, w;
    uint8_t *vram;
    uint8_t *data_display, *dd;
    ram_addr_t page, page_min, page_max;
    int x, y;
    int xmin, xmax;
    int ymin, ymax;
    int xcursor, ycursor;
    unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);

    switch (ds_get_bits_per_pixel(s->ds)) {
        case 8:
            rgb_to_pixel = rgb_to_pixel8;
            w = 1;
            break;
        case 15:
            rgb_to_pixel = rgb_to_pixel15;
            w = 2;
            break;
        case 16:
            rgb_to_pixel = rgb_to_pixel16;
            w = 2;
            break;
        case 32:
            rgb_to_pixel = rgb_to_pixel32;
            w = 4;
            break;
        default:
            hw_error("g364: unknown host depth %d",
                     ds_get_bits_per_pixel(s->ds));
            return;
    }

    page = 0;
    page_min = (ram_addr_t)-1;
    page_max = 0;

    x = y = 0;
    xmin = s->width;
    xmax = 0;
    ymin = s->height;
    ymax = 0;

    if (!(s->ctla & CTLA_NO_CURSOR)) {
        xcursor = s->cursor_position >> 12;
        ycursor = s->cursor_position & 0xfff;
    } else {
        xcursor = ycursor = -65;
    }

    vram = s->vram + s->top_of_screen;
    /* XXX: out of range in vram? */
    data_display = dd = ds_get_data(s->ds);
    while (y < s->height) {
        if (check_dirty(s, page)) {
            if (y < ymin)
                ymin = ymax = y;
            if (page_min == (ram_addr_t)-1)
                page_min = page;
            page_max = page;
            if (x < xmin)
                xmin = x;
            for (i = 0; i < G364_PAGE_SIZE; i++) {
                uint8_t index;
                unsigned int color;
                if (unlikely((y >= ycursor && y < ycursor + 64) &&
                    (x >= xcursor && x < xcursor + 64))) {
                    /* pointer area */
                    int xdiff = x - xcursor;
                    uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
                    int op = (curs >> ((xdiff & 7) * 2)) & 3;
                    if (likely(op == 0)) {
                        /* transparent */
                        index = *vram;
                        color = (*rgb_to_pixel)(
                            s->color_palette[index][0],
                            s->color_palette[index][1],
                            s->color_palette[index][2]);
                    } else {
                        /* get cursor color */
                        index = op - 1;
                        color = (*rgb_to_pixel)(
                            s->cursor_palette[index][0],
                            s->cursor_palette[index][1],
                            s->cursor_palette[index][2]);
                    }
                } else {
                    /* normal area */
                    index = *vram;
                    color = (*rgb_to_pixel)(
                        s->color_palette[index][0],
                        s->color_palette[index][1],
                        s->color_palette[index][2]);
                }
                memcpy(dd, &color, w);
                dd += w;
                x++;
                vram++;
                if (x == s->width) {
                    xmax = s->width - 1;
                    y++;
                    if (y == s->height) {
                        ymax = s->height - 1;
                        goto done;
                    }
                    data_display = dd = data_display + ds_get_linesize(s->ds);
                    xmin = 0;
                    x = 0;
                }
            }
            if (x > xmax)
                xmax = x;
            if (y > ymax)
                ymax = y;
        } else {
            int dy;
            if (page_min != (ram_addr_t)-1) {
                reset_dirty(s, page_min, page_max);
                page_min = (ram_addr_t)-1;
                page_max = 0;
                dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
                xmin = s->width;
                xmax = 0;
                ymin = s->height;
                ymax = 0;
            }
            x += G364_PAGE_SIZE;
            dy = x / s->width;
            x = x % s->width;
            y += dy;
            vram += G364_PAGE_SIZE;
            data_display += dy * ds_get_linesize(s->ds);
            dd = data_display + x * w;
        }
        page += G364_PAGE_SIZE;
    }

done:
    if (page_min != (ram_addr_t)-1) {
        dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
        reset_dirty(s, page_min, page_max);
    }
}

static void g364fb_draw_blank(G364State *s)
{
    int i, w;
    uint8_t *d;

    if (s->blanked) {
        /* Screen is already blank. No need to redraw it */
        return;
    }

    w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
    d = ds_get_data(s->ds);
    for (i = 0; i < s->height; i++) {
        memset(d, 0, w);
        d += ds_get_linesize(s->ds);
    }

    dpy_update(s->ds, 0, 0, s->width, s->height);
    s->blanked = 1;
}

static void g364fb_update_display(void *opaque)
{
    G364State *s = opaque;

    qemu_flush_coalesced_mmio_buffer();

    if (s->width == 0 || s->height == 0)
        return;

    if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
        qemu_console_resize(s->ds, s->width, s->height);
    }

    if (s->ctla & CTLA_FORCE_BLANK) {
        g364fb_draw_blank(s);
    } else if (s->depth == 8) {
        g364fb_draw_graphic8(s);
    } else {
        error_report("g364: unknown guest depth %d", s->depth);
    }

    qemu_irq_raise(s->irq);
}

static inline void g364fb_invalidate_display(void *opaque)
{
    G364State *s = opaque;

    s->blanked = 0;
    memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
}

static void g364fb_reset(G364State *s)
{
    qemu_irq_lower(s->irq);

    memset(s->color_palette, 0, sizeof(s->color_palette));
    memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
    memset(s->cursor, 0, sizeof(s->cursor));
    s->cursor_position = 0;
    s->ctla = 0;
    s->top_of_screen = 0;
    s->width = s->height = 0;
    memset(s->vram, 0, s->vram_size);
    g364fb_invalidate_display(s);
}

static void g364fb_screen_dump(void *opaque, const char *filename)
{
    G364State *s = opaque;
    int y, x;
    uint8_t index;
    uint8_t *data_buffer;
    FILE *f;

    qemu_flush_coalesced_mmio_buffer();

    if (s->depth != 8) {
        error_report("g364: unknown guest depth %d", s->depth);
        return;
    }

    f = fopen(filename, "wb");
    if (!f)
        return;

    if (s->ctla & CTLA_FORCE_BLANK) {
        /* blank screen */
        fprintf(f, "P4\n%d %d\n",
            s->width, s->height);
        for (y = 0; y < s->height; y++)
            for (x = 0; x < s->width; x++)
                fputc(0, f);
    } else {
        data_buffer = s->vram + s->top_of_screen;
        fprintf(f, "P6\n%d %d\n%d\n",
            s->width, s->height, 255);
        for (y = 0; y < s->height; y++)
            for (x = 0; x < s->width; x++, data_buffer++) {
                index = *data_buffer;
                fputc(s->color_palette[index][0], f);
                fputc(s->color_palette[index][1], f);
                fputc(s->color_palette[index][2], f);
        }
    }

    fclose(f);
}

/* called for accesses to io ports */
static uint64_t g364fb_ctrl_read(void *opaque,
                                 target_phys_addr_t addr,
                                 unsigned int size)
{
    G364State *s = opaque;
    uint32_t val;

    if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
        /* cursor pattern */
        int idx = (addr - REG_CURS_PAT) >> 3;
        val = s->cursor[idx];
    } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
        /* cursor palette */
        int idx = (addr - REG_CURS_PAL) >> 3;
        val = ((uint32_t)s->cursor_palette[idx][0] << 16);
        val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
        val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
    } else {
        switch (addr) {
            case REG_DISPLAY:
                val = s->width / 4;
                break;
            case REG_VDISPLAY:
                val = s->height * 2;
                break;
            case REG_CTLA:
                val = s->ctla;
                break;
            default:
            {
                error_report("g364: invalid read at [" TARGET_FMT_plx "]",
                             addr);
                val = 0;
                break;
            }
        }
    }

    trace_g364fb_read(addr, val);

    return val;
}

static void g364fb_update_depth(G364State *s)
{
    static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
    s->depth = depths[(s->ctla & 0x00700000) >> 20];
}

static void g364_invalidate_cursor_position(G364State *s)
{
    int ymin, ymax, start, end;

    /* invalidate only near the cursor */
    ymin = s->cursor_position & 0xfff;
    ymax = MIN(s->height, ymin + 64);
    start = ymin * ds_get_linesize(s->ds);
    end = (ymax + 1) * ds_get_linesize(s->ds);

    memory_region_set_dirty(&s->mem_vram, start, end - start);
}

static void g364fb_ctrl_write(void *opaque,
                              target_phys_addr_t addr,
                              uint64_t val,
                              unsigned int size)
{
    G364State *s = opaque;

    trace_g364fb_write(addr, val);

    if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
        /* color palette */
        int idx = (addr - REG_CLR_PAL) >> 3;
        s->color_palette[idx][0] = (val >> 16) & 0xff;
        s->color_palette[idx][1] = (val >> 8) & 0xff;
        s->color_palette[idx][2] = val & 0xff;
        g364fb_invalidate_display(s);
    } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
        /* cursor pattern */
        int idx = (addr - REG_CURS_PAT) >> 3;
        s->cursor[idx] = val;
        g364fb_invalidate_display(s);
    } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
        /* cursor palette */
        int idx = (addr - REG_CURS_PAL) >> 3;
        s->cursor_palette[idx][0] = (val >> 16) & 0xff;
        s->cursor_palette[idx][1] = (val >> 8) & 0xff;
        s->cursor_palette[idx][2] = val & 0xff;
        g364fb_invalidate_display(s);
    } else {
        switch (addr) {
        case REG_BOOT: /* Boot timing */
        case 0x00108: /* Line timing: half sync */
        case 0x00110: /* Line timing: back porch */
        case 0x00120: /* Line timing: short display */
        case 0x00128: /* Frame timing: broad pulse */
        case 0x00130: /* Frame timing: v sync */
        case 0x00138: /* Frame timing: v preequalise */
        case 0x00140: /* Frame timing: v postequalise */
        case 0x00148: /* Frame timing: v blank */
        case 0x00158: /* Line timing: line time */
        case 0x00160: /* Frame store: line start */
        case 0x00168: /* vram cycle: mem init */
        case 0x00170: /* vram cycle: transfer delay */
        case 0x00200: /* vram cycle: mask register */
            /* ignore */
            break;
        case REG_TOP:
            s->top_of_screen = val;
            g364fb_invalidate_display(s);
            break;
        case REG_DISPLAY:
            s->width = val * 4;
            break;
        case REG_VDISPLAY:
            s->height = val / 2;
            break;
        case REG_CTLA:
            s->ctla = val;
            g364fb_update_depth(s);
            g364fb_invalidate_display(s);
            break;
        case REG_CURS_POS:
            g364_invalidate_cursor_position(s);
            s->cursor_position = val;
            g364_invalidate_cursor_position(s);
            break;
        case REG_RESET:
            g364fb_reset(s);
            break;
        default:
            error_report("g364: invalid write of 0x%" PRIx64
                         " at [" TARGET_FMT_plx "]", val, addr);
            break;
        }
    }
    qemu_irq_lower(s->irq);
}

static const MemoryRegionOps g364fb_ctrl_ops = {
    .read = g364fb_ctrl_read,
    .write = g364fb_ctrl_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl.min_access_size = 4,
    .impl.max_access_size = 4,
};

static int g364fb_post_load(void *opaque, int version_id)
{
    G364State *s = opaque;

    /* force refresh */
    g364fb_update_depth(s);
    g364fb_invalidate_display(s);

    return 0;
}

static const VMStateDescription vmstate_g364fb = {
    .name = "g364fb",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = g364fb_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
        VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
        VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
        VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
        VMSTATE_UINT32(cursor_position, G364State),
        VMSTATE_UINT32(ctla, G364State),
        VMSTATE_UINT32(top_of_screen, G364State),
        VMSTATE_UINT32(width, G364State),
        VMSTATE_UINT32(height, G364State),
        VMSTATE_END_OF_LIST()
    }
};

static void g364fb_init(DeviceState *dev, G364State *s)
{
    s->vram = g_malloc0(s->vram_size);

    s->ds = graphic_console_init(g364fb_update_display,
                                 g364fb_invalidate_display,
                                 g364fb_screen_dump, NULL, s);

    memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
    memory_region_init_ram_ptr(&s->mem_vram, "vram",
                               s->vram_size, s->vram);
    vmstate_register_ram(&s->mem_vram, dev);
    memory_region_set_coalescing(&s->mem_vram);
}

typedef struct {
    SysBusDevice busdev;
    G364State g364;
} G364SysBusState;

static int g364fb_sysbus_init(SysBusDevice *dev)
{
    G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;

    g364fb_init(&dev->qdev, s);
    sysbus_init_irq(dev, &s->irq);
    sysbus_init_mmio(dev, &s->mem_ctrl);
    sysbus_init_mmio(dev, &s->mem_vram);

    return 0;
}

static void g364fb_sysbus_reset(DeviceState *d)
{
    G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
    g364fb_reset(&s->g364);
}

static Property g364fb_sysbus_properties[] = {
    DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
    8 * 1024 * 1024),
    DEFINE_PROP_END_OF_LIST(),
};

static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = g364fb_sysbus_init;
    dc->desc = "G364 framebuffer";
    dc->reset = g364fb_sysbus_reset;
    dc->vmsd = &vmstate_g364fb;
    dc->props = g364fb_sysbus_properties;
}

static TypeInfo g364fb_sysbus_info = {
    .name          = "sysbus-g364",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(G364SysBusState),
    .class_init    = g364fb_sysbus_class_init,
};

static void g364fb_register(void)
{
    type_register_static(&g364fb_sysbus_info);
}

device_init(g364fb_register);
Commit	Line	Data
1fc3d392 AJ	1	/*
	2	* QEMU G364 framebuffer Emulator.
	3	*
97a3f6ff	4	* Copyright (c) 2007-2011 Herve Poussineau
1fc3d392 AJ	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a	16	* You should have received a copy of the GNU General Public License along
8167ee88	17	* with this program; if not, see <http://www.gnu.org/licenses/>.
1fc3d392 AJ	18	*/
	19
	20	#include "hw.h"
	21	#include "console.h"
	22	#include "pixel_ops.h"
b213b370	23	#include "trace.h"
97a3f6ff	24	#include "sysbus.h"
0add30cf	25
1fc3d392	26	typedef struct G364State {
0add30cf AJ	27	/* hardware */
0add30cf AJ	28	uint8_t *vram;
97a3f6ff	29	uint32_t vram_size;
0add30cf	30	qemu_irq irq;
97a3f6ff HP	31	MemoryRegion mem_vram;
97a3f6ff HP	32	MemoryRegion mem_ctrl;
0add30cf AJ	33	/* registers */
	34	uint8_t color_palette[256][3];
	35	uint8_t cursor_palette[3][3];
	36	uint16_t cursor[512];
	37	uint32_t cursor_position;
1fc3d392	38	uint32_t ctla;
0add30cf AJ	39	uint32_t top_of_screen;
0add30cf AJ	40	uint32_t width, height; /* in pixels */
1fc3d392 AJ	41	/* display refresh support */
1fc3d392 AJ	42	DisplayState *ds;
0add30cf AJ	43	int depth;
0add30cf AJ	44	int blanked;
1fc3d392 AJ	45	} G364State;
1fc3d392 AJ	46
97a3f6ff HP	47	#define REG_BOOT 0x000000
	48	#define REG_DISPLAY 0x000118
	49	#define REG_VDISPLAY 0x000150
	50	#define REG_CTLA 0x000300
	51	#define REG_TOP 0x000400
	52	#define REG_CURS_PAL 0x000508
	53	#define REG_CURS_POS 0x000638
	54	#define REG_CLR_PAL 0x000800
	55	#define REG_CURS_PAT 0x001000
	56	#define REG_RESET 0x100000
0add30cf AJ	57
	58	#define CTLA_FORCE_BLANK 0x00000400
	59	#define CTLA_NO_CURSOR 0x00800000
	60
1213406b BS	61	#define G364_PAGE_SIZE 4096
1213406b BS	62
97a3f6ff	63	static inline int check_dirty(G364State *s, ram_addr_t page)
0add30cf	64	{
97a3f6ff	65	return memory_region_get_dirty(&s->mem_vram, page, DIRTY_MEMORY_VGA);
0add30cf AJ	66	}
	67
	68	static inline void reset_dirty(G364State *s,
c227f099	69	ram_addr_t page_min, ram_addr_t page_max)
0add30cf	70	{
97a3f6ff HP	71	memory_region_reset_dirty(&s->mem_vram,
97a3f6ff HP	72	page_min,
1213406b	73	page_max + G364_PAGE_SIZE - page_min - 1,
97a3f6ff	74	DIRTY_MEMORY_VGA);
0add30cf AJ	75	}
	76
	77	static void g364fb_draw_graphic8(G364State *s)
1fc3d392	78	{
0add30cf AJ	79	int i, w;
	80	uint8_t *vram;
	81	uint8_t data_display, dd;
c227f099	82	ram_addr_t page, page_min, page_max;
0add30cf AJ	83	int x, y;
	84	int xmin, xmax;
	85	int ymin, ymax;
	86	int xcursor, ycursor;
	87	unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
	88
0e1f5a0c	89	switch (ds_get_bits_per_pixel(s->ds)) {
1fc3d392	90	case 8:
0add30cf AJ	91	rgb_to_pixel = rgb_to_pixel8;
0add30cf AJ	92	w = 1;
1fc3d392 AJ	93	break;
1fc3d392 AJ	94	case 15:
0add30cf AJ	95	rgb_to_pixel = rgb_to_pixel15;
0add30cf AJ	96	w = 2;
1fc3d392 AJ	97	break;
1fc3d392 AJ	98	case 16:
0add30cf AJ	99	rgb_to_pixel = rgb_to_pixel16;
0add30cf AJ	100	w = 2;
1fc3d392 AJ	101	break;
1fc3d392 AJ	102	case 32:
0add30cf AJ	103	rgb_to_pixel = rgb_to_pixel32;
0add30cf AJ	104	w = 4;
1fc3d392 AJ	105	break;
1fc3d392 AJ	106	default:
b213b370 HP	107	hw_error("g364: unknown host depth %d",
b213b370 HP	108	ds_get_bits_per_pixel(s->ds));
1fc3d392 AJ	109	return;
	110	}
	111
97a3f6ff	112	page = 0;
c227f099	113	page_min = (ram_addr_t)-1;
0add30cf AJ	114	page_max = 0;
	115
	116	x = y = 0;
	117	xmin = s->width;
	118	xmax = 0;
	119	ymin = s->height;
	120	ymax = 0;
	121
	122	if (!(s->ctla & CTLA_NO_CURSOR)) {
	123	xcursor = s->cursor_position >> 12;
	124	ycursor = s->cursor_position & 0xfff;
	125	} else {
	126	xcursor = ycursor = -65;
	127	}
	128
	129	vram = s->vram + s->top_of_screen;
	130	/* XXX: out of range in vram? */
	131	data_display = dd = ds_get_data(s->ds);
	132	while (y < s->height) {
97a3f6ff	133	if (check_dirty(s, page)) {
0add30cf AJ	134	if (y < ymin)
0add30cf AJ	135	ymin = ymax = y;
c227f099	136	if (page_min == (ram_addr_t)-1)
0add30cf AJ	137	page_min = page;
	138	page_max = page;
	139	if (x < xmin)
	140	xmin = x;
1213406b	141	for (i = 0; i < G364_PAGE_SIZE; i++) {
0add30cf AJ	142	uint8_t index;
	143	unsigned int color;
	144	if (unlikely((y >= ycursor && y < ycursor + 64) &&
	145	(x >= xcursor && x < xcursor + 64))) {
	146	/* pointer area */
	147	int xdiff = x - xcursor;
	148	uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
	149	int op = (curs >> ((xdiff & 7) * 2)) & 3;
	150	if (likely(op == 0)) {
	151	/* transparent */
	152	index = *vram;
	153	color = (*rgb_to_pixel)(
	154	s->color_palette[index][0],
	155	s->color_palette[index][1],
	156	s->color_palette[index][2]);
	157	} else {
	158	/* get cursor color */
	159	index = op - 1;
	160	color = (*rgb_to_pixel)(
	161	s->cursor_palette[index][0],
	162	s->cursor_palette[index][1],
	163	s->cursor_palette[index][2]);
	164	}
	165	} else {
	166	/* normal area */
	167	index = *vram;
	168	color = (*rgb_to_pixel)(
	169	s->color_palette[index][0],
	170	s->color_palette[index][1],
	171	s->color_palette[index][2]);
	172	}
	173	memcpy(dd, &color, w);
	174	dd += w;
	175	x++;
	176	vram++;
	177	if (x == s->width) {
	178	xmax = s->width - 1;
	179	y++;
	180	if (y == s->height) {
	181	ymax = s->height - 1;
	182	goto done;
	183	}
	184	data_display = dd = data_display + ds_get_linesize(s->ds);
	185	xmin = 0;
	186	x = 0;
	187	}
	188	}
	189	if (x > xmax)
	190	xmax = x;
	191	if (y > ymax)
	192	ymax = y;
	193	} else {
	194	int dy;
c227f099	195	if (page_min != (ram_addr_t)-1) {
0add30cf	196	reset_dirty(s, page_min, page_max);
c227f099	197	page_min = (ram_addr_t)-1;
0add30cf AJ	198	page_max = 0;
	199	dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
	200	xmin = s->width;
	201	xmax = 0;
	202	ymin = s->height;
	203	ymax = 0;
	204	}
1213406b	205	x += G364_PAGE_SIZE;
0add30cf AJ	206	dy = x / s->width;
	207	x = x % s->width;
	208	y += dy;
1213406b	209	vram += G364_PAGE_SIZE;
0add30cf AJ	210	data_display += dy * ds_get_linesize(s->ds);
	211	dd = data_display + x * w;
	212	}
1213406b	213	page += G364_PAGE_SIZE;
0add30cf AJ	214	}
	215
	216	done:
c227f099	217	if (page_min != (ram_addr_t)-1) {
0add30cf AJ	218	dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
	219	reset_dirty(s, page_min, page_max);
	220	}
1fc3d392 AJ	221	}
1fc3d392 AJ	222
0add30cf	223	static void g364fb_draw_blank(G364State *s)
1fc3d392 AJ	224	{
	225	int i, w;
	226	uint8_t *d;
	227
0add30cf AJ	228	if (s->blanked) {
0add30cf AJ	229	/* Screen is already blank. No need to redraw it */
1fc3d392	230	return;
0add30cf	231	}
1fc3d392	232
0add30cf	233	w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
0e1f5a0c	234	d = ds_get_data(s->ds);
0add30cf	235	for (i = 0; i < s->height; i++) {
1fc3d392	236	memset(d, 0, w);
0e1f5a0c	237	d += ds_get_linesize(s->ds);
1fc3d392	238	}
221bb2d5	239
0add30cf AJ	240	dpy_update(s->ds, 0, 0, s->width, s->height);
0add30cf AJ	241	s->blanked = 1;
1fc3d392 AJ	242	}
1fc3d392 AJ	243
1fc3d392 AJ	244	static void g364fb_update_display(void *opaque)
	245	{
	246	G364State *s = opaque;
1fc3d392	247
e9a07334 JK	248	qemu_flush_coalesced_mmio_buffer();
e9a07334 JK	249
0add30cf	250	if (s->width == 0 \|\| s->height == 0)
221bb2d5 AJ	251	return;
221bb2d5 AJ	252
0add30cf AJ	253	if (s->width != ds_get_width(s->ds) \|\| s->height != ds_get_height(s->ds)) {
0add30cf AJ	254	qemu_console_resize(s->ds, s->width, s->height);
221bb2d5	255	}
0add30cf AJ	256
	257	if (s->ctla & CTLA_FORCE_BLANK) {
	258	g364fb_draw_blank(s);
	259	} else if (s->depth == 8) {
	260	g364fb_draw_graphic8(s);
	261	} else {
b213b370	262	error_report("g364: unknown guest depth %d", s->depth);
1fc3d392	263	}
0add30cf AJ	264
0add30cf AJ	265	qemu_irq_raise(s->irq);
1fc3d392 AJ	266	}
1fc3d392 AJ	267
86178a57	268	static inline void g364fb_invalidate_display(void *opaque)
1fc3d392 AJ	269	{
1fc3d392 AJ	270	G364State *s = opaque;
0add30cf AJ	271
0add30cf AJ	272	s->blanked = 0;
fd4aa979	273	memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
1fc3d392 AJ	274	}
1fc3d392 AJ	275
97a3f6ff	276	static void g364fb_reset(G364State *s)
1fc3d392	277	{
0add30cf AJ	278	qemu_irq_lower(s->irq);
	279
	280	memset(s->color_palette, 0, sizeof(s->color_palette));
	281	memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
	282	memset(s->cursor, 0, sizeof(s->cursor));
	283	s->cursor_position = 0;
	284	s->ctla = 0;
	285	s->top_of_screen = 0;
	286	s->width = s->height = 0;
	287	memset(s->vram, 0, s->vram_size);
97a3f6ff	288	g364fb_invalidate_display(s);
1fc3d392 AJ	289	}
	290
	291	static void g364fb_screen_dump(void opaque, const char filename)
	292	{
	293	G364State *s = opaque;
	294	int y, x;
	295	uint8_t index;
	296	uint8_t *data_buffer;
	297	FILE *f;
	298
e9a07334 JK	299	qemu_flush_coalesced_mmio_buffer();
e9a07334 JK	300
0add30cf	301	if (s->depth != 8) {
b213b370	302	error_report("g364: unknown guest depth %d", s->depth);
0add30cf AJ	303	return;
	304	}
	305
1fc3d392 AJ	306	f = fopen(filename, "wb");
	307	if (!f)
	308	return;
	309
0add30cf AJ	310	if (s->ctla & CTLA_FORCE_BLANK) {
	311	/* blank screen */
	312	fprintf(f, "P4\n%d %d\n",
	313	s->width, s->height);
	314	for (y = 0; y < s->height; y++)
	315	for (x = 0; x < s->width; x++)
	316	fputc(0, f);
	317	} else {
	318	data_buffer = s->vram + s->top_of_screen;
	319	fprintf(f, "P6\n%d %d\n%d\n",
	320	s->width, s->height, 255);
	321	for (y = 0; y < s->height; y++)
	322	for (x = 0; x < s->width; x++, data_buffer++) {
	323	index = *data_buffer;
	324	fputc(s->color_palette[index][0], f);
	325	fputc(s->color_palette[index][1], f);
	326	fputc(s->color_palette[index][2], f);
1fc3d392	327	}
0add30cf AJ	328	}
0add30cf AJ	329
1fc3d392 AJ	330	fclose(f);
	331	}
	332
	333	/* called for accesses to io ports */
97a3f6ff HP	334	static uint64_t g364fb_ctrl_read(void *opaque,
	335	target_phys_addr_t addr,
	336	unsigned int size)
1fc3d392	337	{
0add30cf	338	G364State *s = opaque;
1fc3d392 AJ	339	uint32_t val;
1fc3d392 AJ	340
0add30cf AJ	341	if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
	342	/* cursor pattern */
	343	int idx = (addr - REG_CURS_PAT) >> 3;
	344	val = s->cursor[idx];
	345	} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
	346	/* cursor palette */
	347	int idx = (addr - REG_CURS_PAL) >> 3;
	348	val = ((uint32_t)s->cursor_palette[idx][0] << 16);
	349	val \|= ((uint32_t)s->cursor_palette[idx][1] << 8);
	350	val \|= ((uint32_t)s->cursor_palette[idx][2] << 0);
	351	} else {
	352	switch (addr) {
0add30cf AJ	353	case REG_DISPLAY:
	354	val = s->width / 4;
	355	break;
	356	case REG_VDISPLAY:
	357	val = s->height * 2;
	358	break;
	359	case REG_CTLA:
	360	val = s->ctla;
	361	break;
	362	default:
	363	{
b213b370 HP	364	error_report("g364: invalid read at [" TARGET_FMT_plx "]",
b213b370 HP	365	addr);
0add30cf AJ	366	val = 0;
	367	break;
	368	}
	369	}
1fc3d392 AJ	370	}
1fc3d392 AJ	371
b213b370	372	trace_g364fb_read(addr, val);
1fc3d392 AJ	373
	374	return val;
	375	}
	376
0add30cf	377	static void g364fb_update_depth(G364State *s)
1fc3d392	378	{
38972938	379	static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
0add30cf AJ	380	s->depth = depths[(s->ctla & 0x00700000) >> 20];
0add30cf AJ	381	}
1fc3d392	382
0add30cf AJ	383	static void g364_invalidate_cursor_position(G364State *s)
0add30cf AJ	384	{
fd4aa979	385	int ymin, ymax, start, end;
1fc3d392	386
0add30cf AJ	387	/* invalidate only near the cursor */
	388	ymin = s->cursor_position & 0xfff;
	389	ymax = MIN(s->height, ymin + 64);
	390	start = ymin * ds_get_linesize(s->ds);
	391	end = (ymax + 1) * ds_get_linesize(s->ds);
1fc3d392	392
fd4aa979	393	memory_region_set_dirty(&s->mem_vram, start, end - start);
0add30cf AJ	394	}
0add30cf AJ	395
97a3f6ff HP	396	static void g364fb_ctrl_write(void *opaque,
	397	target_phys_addr_t addr,
	398	uint64_t val,
	399	unsigned int size)
0add30cf AJ	400	{
	401	G364State *s = opaque;
	402
b213b370	403	trace_g364fb_write(addr, val);
0add30cf AJ	404
0add30cf AJ	405	if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
1fc3d392	406	/* color palette */
0add30cf AJ	407	int idx = (addr - REG_CLR_PAL) >> 3;
	408	s->color_palette[idx][0] = (val >> 16) & 0xff;
	409	s->color_palette[idx][1] = (val >> 8) & 0xff;
	410	s->color_palette[idx][2] = val & 0xff;
	411	g364fb_invalidate_display(s);
	412	} else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
	413	/* cursor pattern */
	414	int idx = (addr - REG_CURS_PAT) >> 3;
	415	s->cursor[idx] = val;
	416	g364fb_invalidate_display(s);
	417	} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
	418	/* cursor palette */
	419	int idx = (addr - REG_CURS_PAL) >> 3;
	420	s->cursor_palette[idx][0] = (val >> 16) & 0xff;
	421	s->cursor_palette[idx][1] = (val >> 8) & 0xff;
	422	s->cursor_palette[idx][2] = val & 0xff;
	423	g364fb_invalidate_display(s);
1fc3d392 AJ	424	} else {
1fc3d392 AJ	425	switch (addr) {
97a3f6ff HP	426	case REG_BOOT: /* Boot timing */
	427	case 0x00108: /* Line timing: half sync */
	428	case 0x00110: /* Line timing: back porch */
	429	case 0x00120: /* Line timing: short display */
	430	case 0x00128: /* Frame timing: broad pulse */
	431	case 0x00130: /* Frame timing: v sync */
	432	case 0x00138: /* Frame timing: v preequalise */
	433	case 0x00140: /* Frame timing: v postequalise */
	434	case 0x00148: /* Frame timing: v blank */
	435	case 0x00158: /* Line timing: line time */
	436	case 0x00160: /* Frame store: line start */
	437	case 0x00168: /* vram cycle: mem init */
	438	case 0x00170: /* vram cycle: transfer delay */
	439	case 0x00200: /* vram cycle: mask register */
	440	/* ignore */
	441	break;
	442	case REG_TOP:
	443	s->top_of_screen = val;
	444	g364fb_invalidate_display(s);
	445	break;
	446	case REG_DISPLAY:
	447	s->width = val * 4;
	448	break;
	449	case REG_VDISPLAY:
	450	s->height = val / 2;
	451	break;
	452	case REG_CTLA:
	453	s->ctla = val;
	454	g364fb_update_depth(s);
	455	g364fb_invalidate_display(s);
	456	break;
	457	case REG_CURS_POS:
	458	g364_invalidate_cursor_position(s);
	459	s->cursor_position = val;
	460	g364_invalidate_cursor_position(s);
	461	break;
	462	case REG_RESET:
	463	g364fb_reset(s);
	464	break;
	465	default:
	466	error_report("g364: invalid write of 0x%" PRIx64
	467	" at [" TARGET_FMT_plx "]", val, addr);
	468	break;
1fc3d392 AJ	469	}
1fc3d392 AJ	470	}
0add30cf	471	qemu_irq_lower(s->irq);
1fc3d392 AJ	472	}
1fc3d392 AJ	473
97a3f6ff HP	474	static const MemoryRegionOps g364fb_ctrl_ops = {
	475	.read = g364fb_ctrl_read,
	476	.write = g364fb_ctrl_write,
	477	.endianness = DEVICE_LITTLE_ENDIAN,
	478	.impl.min_access_size = 4,
	479	.impl.max_access_size = 4,
1fc3d392 AJ	480	};
1fc3d392 AJ	481
97a3f6ff	482	static int g364fb_post_load(void *opaque, int version_id)
1fc3d392 AJ	483	{
1fc3d392 AJ	484	G364State *s = opaque;
0add30cf AJ	485
	486	/* force refresh */
	487	g364fb_update_depth(s);
	488	g364fb_invalidate_display(s);
1fc3d392	489
0add30cf	490	return 0;
1fc3d392 AJ	491	}
1fc3d392 AJ	492
97a3f6ff HP	493	static const VMStateDescription vmstate_g364fb = {
	494	.name = "g364fb",
	495	.version_id = 1,
	496	.minimum_version_id = 1,
	497	.minimum_version_id_old = 1,
	498	.post_load = g364fb_post_load,
	499	.fields = (VMStateField[]) {
	500	VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
	501	VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
	502	VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
	503	VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
	504	VMSTATE_UINT32(cursor_position, G364State),
	505	VMSTATE_UINT32(ctla, G364State),
	506	VMSTATE_UINT32(top_of_screen, G364State),
	507	VMSTATE_UINT32(width, G364State),
	508	VMSTATE_UINT32(height, G364State),
	509	VMSTATE_END_OF_LIST()
	510	}
	511	};
1fc3d392	512
97a3f6ff	513	static void g364fb_init(DeviceState dev, G364State s)
1fc3d392	514	{
97a3f6ff	515	s->vram = g_malloc0(s->vram_size);
1fc3d392	516
3023f332 AL	517	s->ds = graphic_console_init(g364fb_update_display,
	518	g364fb_invalidate_display,
	519	g364fb_screen_dump, NULL, s);
1fc3d392	520
97a3f6ff	521	memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
c5705a77	522	memory_region_init_ram_ptr(&s->mem_vram, "vram",
97a3f6ff	523	s->vram_size, s->vram);
c5705a77	524	vmstate_register_ram(&s->mem_vram, dev);
97a3f6ff HP	525	memory_region_set_coalescing(&s->mem_vram);
	526	}
	527
	528	typedef struct {
	529	SysBusDevice busdev;
	530	G364State g364;
	531	} G364SysBusState;
1fc3d392	532
97a3f6ff HP	533	static int g364fb_sysbus_init(SysBusDevice *dev)
	534	{
	535	G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
	536
	537	g364fb_init(&dev->qdev, s);
	538	sysbus_init_irq(dev, &s->irq);
750ecd44 AK	539	sysbus_init_mmio(dev, &s->mem_ctrl);
750ecd44 AK	540	sysbus_init_mmio(dev, &s->mem_vram);
1fc3d392 AJ	541
	542	return 0;
	543	}
97a3f6ff HP	544
	545	static void g364fb_sysbus_reset(DeviceState *d)
	546	{
	547	G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
	548	g364fb_reset(&s->g364);
	549	}
	550
999e12bb AL	551	static Property g364fb_sysbus_properties[] = {
	552	DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
	553	8 * 1024 * 1024),
	554	DEFINE_PROP_END_OF_LIST(),
	555	};
	556
	557	static void g364fb_sysbus_class_init(ObjectClass klass, void data)
	558	{
39bffca2	559	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	560	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	561
	562	k->init = g364fb_sysbus_init;
39bffca2 AL	563	dc->desc = "G364 framebuffer";
	564	dc->reset = g364fb_sysbus_reset;
	565	dc->vmsd = &vmstate_g364fb;
	566	dc->props = g364fb_sysbus_properties;
999e12bb AL	567	}
999e12bb AL	568
39bffca2 AL	569	static TypeInfo g364fb_sysbus_info = {
	570	.name = "sysbus-g364",
	571	.parent = TYPE_SYS_BUS_DEVICE,
	572	.instance_size = sizeof(G364SysBusState),
	573	.class_init = g364fb_sysbus_class_init,
97a3f6ff HP	574	};
	575
	576	static void g364fb_register(void)
	577	{
39bffca2	578	type_register_static(&g364fb_sysbus_info);
97a3f6ff HP	579	}
	580
	581	device_init(g364fb_register);