[qemu.git] / hw / g364fb.c

/*
 * QEMU G364 framebuffer Emulator.
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include "hw.h"
#include "mips.h"
#include "console.h"
#include "pixel_ops.h"

//#define DEBUG_G364

typedef struct G364State {
    unsigned int vram_size;
    uint8_t *vram_buffer;
    uint32_t ctla;
    uint8_t palette[256][3];
    /* display refresh support */
    DisplayState *ds;
    QEMUConsole *console;
    int graphic_mode;
    uint32_t scr_width, scr_height; /* in pixels */
} G364State;

/*
 * graphic modes
 */
#define BPP 8
#define PIXEL_WIDTH 8
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 15
#define PIXEL_WIDTH 16
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 16
#define PIXEL_WIDTH 16
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 32
#define PIXEL_WIDTH 32
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define REG_DISPLAYX 0x0918
#define REG_DISPLAYY 0x0940

#define CTLA_FORCE_BLANK 0x400

static void g364fb_draw_graphic(G364State *s, int full_update)
{
    switch (ds_get_bits_per_pixel(s->ds)) {
        case 8:
            g364fb_draw_graphic8(s, full_update);
            break;
        case 15:
            g364fb_draw_graphic15(s, full_update);
            break;
        case 16:
            g364fb_draw_graphic16(s, full_update);
            break;
        case 32:
            g364fb_draw_graphic32(s, full_update);
            break;
        default:
            printf("g364fb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
            return;
    }

    dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
}

static void g364fb_draw_blank(G364State *s, int full_update)
{
    int i, w;
    uint8_t *d;

    if (!full_update)
        return;

    w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
    d = ds_get_data(s->ds);
    for(i = 0; i < s->scr_height; i++) {
        memset(d, 0, w);
        d += ds_get_linesize(s->ds);
    }

    dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
}

#define GMODE_GRAPH 0
#define GMODE_BLANK 1

static void g364fb_update_display(void *opaque)
{
    G364State *s = opaque;
    int full_update, graphic_mode;

    if (s->scr_width == 0 || s->scr_height == 0)
        return;

    if (s->ctla & CTLA_FORCE_BLANK)
        graphic_mode = GMODE_BLANK;
    else
        graphic_mode = GMODE_GRAPH;
    full_update = 0;
    if (graphic_mode != s->graphic_mode) {
        s->graphic_mode = graphic_mode;
        full_update = 1;
    }
    if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
        qemu_console_resize(s->console, s->scr_width, s->scr_height);
        full_update = 1;
    }
    switch(graphic_mode) {
        case GMODE_GRAPH:
            g364fb_draw_graphic(s, full_update);
            break;
        case GMODE_BLANK:
        default:
            g364fb_draw_blank(s, full_update);
            break;
    }
}

/* force a full display refresh */
static void g364fb_invalidate_display(void *opaque)
{
    G364State *s = opaque;
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_reset(void *opaque)
{
    G364State *s = opaque;

    memset(s->palette, 0, sizeof(s->palette));
    s->scr_width = s->scr_height = 0;
    memset(s->vram_buffer, 0, s->vram_size);
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_screen_dump(void *opaque, const char *filename)
{
    G364State *s = opaque;
    int y, x;
    uint8_t index;
    uint8_t *data_buffer;
    FILE *f;

    f = fopen(filename, "wb");
    if (!f)
        return;

    data_buffer = s->vram_buffer;
    fprintf(f, "P6\n%d %d\n%d\n",
        s->scr_width, s->scr_height, 255);
    for(y = 0; y < s->scr_height; y++)
        for(x = 0; x < s->scr_width; x++, data_buffer++) {
            index = *data_buffer;
            fputc(s->palette[index][0], f);
            fputc(s->palette[index][1], f);
            fputc(s->palette[index][2], f);
        }
    fclose(f);
}

/* called for accesses to io ports */
static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
{
    //G364State *s = opaque;
    uint32_t val;

    addr &= 0xffff;

    switch (addr) {
        default:
#ifdef DEBUG_G364
            printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr);
#endif
            val = 0;
            break;
    }

#ifdef DEBUG_G364
    printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif

    return val;
}

static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_ctrl_readb(opaque, addr);
    v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
    return v;
}

static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_ctrl_readb(opaque, addr);
    v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
    v |= g364fb_ctrl_readb(opaque, addr + 2) << 16;
    v |= g364fb_ctrl_readb(opaque, addr + 3) << 24;
    return v;
}

static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    G364State *s = opaque;

    addr &= 0xffff;

#ifdef DEBUG_G364
    printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif

    if (addr < 0x0800) {
        /* color palette */
        int idx = addr >> 3;
        int c = addr & 7;
        if (c < 3)
            s->palette[idx][c] = (uint8_t)val;
    } else {
        switch (addr) {
            case REG_DISPLAYX:
                s->scr_width = (s->scr_width & 0xfffffc03) | (val << 2);
                break;
            case REG_DISPLAYX + 1:
                s->scr_width = (s->scr_width & 0xfffc03ff) | (val << 10);
                break;
            case REG_DISPLAYY:
                s->scr_height = (s->scr_height & 0xffffff80) | (val >> 1);
                break;
            case REG_DISPLAYY + 1:
                s->scr_height = (s->scr_height & 0xffff801f) | (val << 7);
                break;
            default:
#ifdef DEBUG_G364
                printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif
                break;
        }
    }
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_ctrl_writeb(opaque, addr, val & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}

static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_ctrl_writeb(opaque, addr, val & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}

static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
    g364fb_ctrl_readb,
    g364fb_ctrl_readw,
    g364fb_ctrl_readl,
};

static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
    g364fb_ctrl_writeb,
    g364fb_ctrl_writew,
    g364fb_ctrl_writel,
};

/* called for accesses to video ram */
static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
{
    G364State *s = opaque;

    return s->vram_buffer[addr];
}

static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_mem_readb(opaque, addr);
    v |= g364fb_mem_readb(opaque, addr + 1) << 8;
    return v;
}

static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_mem_readb(opaque, addr);
    v |= g364fb_mem_readb(opaque, addr + 1) << 8;
    v |= g364fb_mem_readb(opaque, addr + 2) << 16;
    v |= g364fb_mem_readb(opaque, addr + 3) << 24;
    return v;
}

static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    G364State *s = opaque;

    s->vram_buffer[addr] = val;
}

static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_mem_writeb(opaque, addr, val & 0xff);
    g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}

static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_mem_writeb(opaque, addr, val & 0xff);
    g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
    g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
    g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}

static CPUReadMemoryFunc *g364fb_mem_read[3] = {
    g364fb_mem_readb,
    g364fb_mem_readw,
    g364fb_mem_readl,
};

static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
    g364fb_mem_writeb,
    g364fb_mem_writew,
    g364fb_mem_writel,
};

int g364fb_mm_init(DisplayState *ds,
                   int vram_size, int it_shift,
                   target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
{
    G364State *s;
    int io_vram, io_ctrl;

    s = qemu_mallocz(sizeof(G364State));
    if (!s)
        return -1;

    s->vram_size = vram_size;
    s->vram_buffer = qemu_mallocz(s->vram_size);

    qemu_register_reset(g364fb_reset, s);
    g364fb_reset(s);

    s->ds = ds;

    s->console = graphic_console_init(ds, g364fb_update_display,
                                      g364fb_invalidate_display,
                                      g364fb_screen_dump, NULL, s);

    io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
    cpu_register_physical_memory(vram_base, vram_size, io_vram);

    io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
    cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);

    return 0;
}
Commit	Line	Data
1fc3d392 AJ	1	/*
	2	* QEMU G364 framebuffer Emulator.
	3	*
	4	* Copyright (c) 2007-2008 Hervé Poussineau
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include "hw.h"
cd5158ea	23	#include "mips.h"
1fc3d392 AJ	24	#include "console.h"
	25	#include "pixel_ops.h"
	26
	27	//#define DEBUG_G364
	28
	29	typedef struct G364State {
1fc3d392 AJ	30	unsigned int vram_size;
	31	uint8_t *vram_buffer;
	32	uint32_t ctla;
	33	uint8_t palette[256][3];
	34	/* display refresh support */
	35	DisplayState *ds;
c60e08d9	36	QEMUConsole *console;
1fc3d392 AJ	37	int graphic_mode;
1fc3d392 AJ	38	uint32_t scr_width, scr_height; /* in pixels */
1fc3d392 AJ	39	} G364State;
	40
	41	/*
	42	* graphic modes
	43	*/
	44	#define BPP 8
	45	#define PIXEL_WIDTH 8
	46	#include "g364fb_template.h"
	47	#undef BPP
	48	#undef PIXEL_WIDTH
	49
	50	#define BPP 15
	51	#define PIXEL_WIDTH 16
	52	#include "g364fb_template.h"
	53	#undef BPP
	54	#undef PIXEL_WIDTH
	55
	56	#define BPP 16
	57	#define PIXEL_WIDTH 16
	58	#include "g364fb_template.h"
	59	#undef BPP
	60	#undef PIXEL_WIDTH
	61
	62	#define BPP 32
	63	#define PIXEL_WIDTH 32
	64	#include "g364fb_template.h"
	65	#undef BPP
	66	#undef PIXEL_WIDTH
	67
	68	#define REG_DISPLAYX 0x0918
	69	#define REG_DISPLAYY 0x0940
	70
	71	#define CTLA_FORCE_BLANK 0x400
	72
	73	static void g364fb_draw_graphic(G364State *s, int full_update)
	74	{
0e1f5a0c	75	switch (ds_get_bits_per_pixel(s->ds)) {
1fc3d392 AJ	76	case 8:
	77	g364fb_draw_graphic8(s, full_update);
	78	break;
	79	case 15:
	80	g364fb_draw_graphic15(s, full_update);
	81	break;
	82	case 16:
	83	g364fb_draw_graphic16(s, full_update);
	84	break;
	85	case 32:
	86	g364fb_draw_graphic32(s, full_update);
	87	break;
	88	default:
0e1f5a0c	89	printf("g364fb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
1fc3d392 AJ	90	return;
	91	}
	92
221bb2d5	93	dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
1fc3d392 AJ	94	}
	95
	96	static void g364fb_draw_blank(G364State *s, int full_update)
	97	{
	98	int i, w;
	99	uint8_t *d;
	100
	101	if (!full_update)
	102	return;
1fc3d392	103
0e1f5a0c AL	104	w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
0e1f5a0c AL	105	d = ds_get_data(s->ds);
221bb2d5	106	for(i = 0; i < s->scr_height; i++) {
1fc3d392	107	memset(d, 0, w);
0e1f5a0c	108	d += ds_get_linesize(s->ds);
1fc3d392	109	}
221bb2d5 AJ	110
221bb2d5 AJ	111	dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
1fc3d392 AJ	112	}
	113
	114	#define GMODE_GRAPH 0
	115	#define GMODE_BLANK 1
	116
	117	static void g364fb_update_display(void *opaque)
	118	{
	119	G364State *s = opaque;
	120	int full_update, graphic_mode;
	121
221bb2d5 AJ	122	if (s->scr_width == 0 \|\| s->scr_height == 0)
	123	return;
	124
1fc3d392 AJ	125	if (s->ctla & CTLA_FORCE_BLANK)
	126	graphic_mode = GMODE_BLANK;
	127	else
	128	graphic_mode = GMODE_GRAPH;
	129	full_update = 0;
	130	if (graphic_mode != s->graphic_mode) {
	131	s->graphic_mode = graphic_mode;
	132	full_update = 1;
	133	}
0e1f5a0c	134	if (s->scr_width != ds_get_width(s->ds) \|\| s->scr_height != ds_get_height(s->ds)) {
221bb2d5 AJ	135	qemu_console_resize(s->console, s->scr_width, s->scr_height);
	136	full_update = 1;
	137	}
1fc3d392 AJ	138	switch(graphic_mode) {
	139	case GMODE_GRAPH:
	140	g364fb_draw_graphic(s, full_update);
	141	break;
	142	case GMODE_BLANK:
	143	default:
	144	g364fb_draw_blank(s, full_update);
	145	break;
	146	}
	147	}
	148
	149	/* force a full display refresh */
	150	static void g364fb_invalidate_display(void *opaque)
	151	{
	152	G364State *s = opaque;
	153	s->graphic_mode = -1; /* force full update */
	154	}
	155
	156	static void g364fb_reset(void *opaque)
	157	{
	158	G364State *s = opaque;
	159
	160	memset(s->palette, 0, sizeof(s->palette));
	161	s->scr_width = s->scr_height = 0;
1fc3d392 AJ	162	memset(s->vram_buffer, 0, s->vram_size);
	163	s->graphic_mode = -1; /* force full update */
	164	}
	165
	166	static void g364fb_screen_dump(void opaque, const char filename)
	167	{
	168	G364State *s = opaque;
	169	int y, x;
	170	uint8_t index;
	171	uint8_t *data_buffer;
	172	FILE *f;
	173
	174	f = fopen(filename, "wb");
	175	if (!f)
	176	return;
	177
	178	data_buffer = s->vram_buffer;
	179	fprintf(f, "P6\n%d %d\n%d\n",
	180	s->scr_width, s->scr_height, 255);
	181	for(y = 0; y < s->scr_height; y++)
	182	for(x = 0; x < s->scr_width; x++, data_buffer++) {
	183	index = *data_buffer;
	184	fputc(s->palette[index][0], f);
	185	fputc(s->palette[index][1], f);
	186	fputc(s->palette[index][2], f);
	187	}
	188	fclose(f);
	189	}
	190
	191	/* called for accesses to io ports */
	192	static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
	193	{
	194	//G364State *s = opaque;
	195	uint32_t val;
	196
	197	addr &= 0xffff;
	198
	199	switch (addr) {
	200	default:
	201	#ifdef DEBUG_G364
	202	printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr);
	203	#endif
	204	val = 0;
	205	break;
	206	}
	207
	208	#ifdef DEBUG_G364
	209	printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
	210	#endif
	211
	212	return val;
	213	}
	214
	215	static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
	216	{
	217	uint32_t v;
	218	v = g364fb_ctrl_readb(opaque, addr);
	219	v \|= g364fb_ctrl_readb(opaque, addr + 1) << 8;
	220	return v;
	221	}
	222
	223	static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
	224	{
	225	uint32_t v;
226	v = g364fb_ctrl_readb(opaque, addr);
227	v \|= g364fb_ctrl_readb(opaque, addr + 1) << 8;
228	v \|= g364fb_ctrl_readb(opaque, addr + 2) << 16;
229	v \|= g364fb_ctrl_readb(opaque, addr + 3) << 24;
230	return v;
231	}
232
233	static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
234	{
235	G364State *s = opaque;
236
237	addr &= 0xffff;
238
239	#ifdef DEBUG_G364
240	printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
241	#endif
242
243	if (addr < 0x0800) {
244	/* color palette */
245	int idx = addr >> 3;
246	int c = addr & 7;
247	if (c < 3)
248	s->palette[idx][c] = (uint8_t)val;
249	} else {
250	switch (addr) {
251	case REG_DISPLAYX:
252	s->scr_width = (s->scr_width & 0xfffffc03) \| (val << 2);
253	break;
254	case REG_DISPLAYX + 1:
255	s->scr_width = (s->scr_width & 0xfffc03ff) \| (val << 10);
256	break;
257	case REG_DISPLAYY:
258	s->scr_height = (s->scr_height & 0xffffff80) \| (val >> 1);
259	break;
260	case REG_DISPLAYY + 1:
261	s->scr_height = (s->scr_height & 0xffff801f) \| (val << 7);
262	break;
263	default:
264	#ifdef DEBUG_G364
265	printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
266	#endif
267	break;
268	}
269	}
c60e08d9	270	s->graphic_mode = -1; /* force full update */
1fc3d392 AJ	271	}
	272
	273	static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	274	{
	275	g364fb_ctrl_writeb(opaque, addr, val & 0xff);
	276	g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	277	}
	278
	279	static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	280	{
	281	g364fb_ctrl_writeb(opaque, addr, val & 0xff);
	282	g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	283	g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff);
	284	g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff);
	285	}
	286
	287	static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
	288	g364fb_ctrl_readb,
	289	g364fb_ctrl_readw,
	290	g364fb_ctrl_readl,
	291	};
	292
	293	static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
	294	g364fb_ctrl_writeb,
	295	g364fb_ctrl_writew,
	296	g364fb_ctrl_writel,
	297	};
	298
	299	/* called for accesses to video ram */
	300	static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
	301	{
	302	G364State *s = opaque;
1fc3d392	303
8da3ff18	304	return s->vram_buffer[addr];
1fc3d392 AJ	305	}
	306
	307	static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
	308	{
	309	uint32_t v;
	310	v = g364fb_mem_readb(opaque, addr);
	311	v \|= g364fb_mem_readb(opaque, addr + 1) << 8;
	312	return v;
	313	}
	314
	315	static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
	316	{
	317	uint32_t v;
	318	v = g364fb_mem_readb(opaque, addr);
	319	v \|= g364fb_mem_readb(opaque, addr + 1) << 8;
	320	v \|= g364fb_mem_readb(opaque, addr + 2) << 16;
	321	v \|= g364fb_mem_readb(opaque, addr + 3) << 24;
	322	return v;
	323	}
	324
	325	static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	326	{
	327	G364State *s = opaque;
1fc3d392	328
8da3ff18	329	s->vram_buffer[addr] = val;
1fc3d392 AJ	330	}
	331
	332	static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	333	{
	334	g364fb_mem_writeb(opaque, addr, val & 0xff);
	335	g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	336	}
	337
	338	static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	339	{
	340	g364fb_mem_writeb(opaque, addr, val & 0xff);
	341	g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	342	g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
	343	g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
	344	}
	345
	346	static CPUReadMemoryFunc *g364fb_mem_read[3] = {
	347	g364fb_mem_readb,
	348	g364fb_mem_readw,
	349	g364fb_mem_readl,
	350	};
	351
	352	static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
	353	g364fb_mem_writeb,
	354	g364fb_mem_writew,
	355	g364fb_mem_writel,
	356	};
	357
	358	int g364fb_mm_init(DisplayState *ds,
	359	int vram_size, int it_shift,
	360	target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
	361	{
	362	G364State *s;
	363	int io_vram, io_ctrl;
	364
	365	s = qemu_mallocz(sizeof(G364State));
	366	if (!s)
	367	return -1;
	368
	369	s->vram_size = vram_size;
	370	s->vram_buffer = qemu_mallocz(s->vram_size);
	371
	372	qemu_register_reset(g364fb_reset, s);
	373	g364fb_reset(s);
	374
	375	s->ds = ds;
1fc3d392	376
c60e08d9 PB	377	s->console = graphic_console_init(ds, g364fb_update_display,
	378	g364fb_invalidate_display,
	379	g364fb_screen_dump, NULL, s);
1fc3d392 AJ	380
1fc3d392 AJ	381	io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
8da3ff18	382	cpu_register_physical_memory(vram_base, vram_size, io_vram);
1fc3d392 AJ	383
	384	io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
	385	cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);
	386
	387	return 0;
	388	}