[qemu.git] / hw / g364fb.c

/*
 * QEMU G364 framebuffer Emulator.
 *
 * Copyright (c) 2007-2011 Herve Poussineau
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw/hw.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
#include "trace.h"
#include "hw/sysbus.h"

typedef struct G364State {
    /* hardware */
    uint8_t *vram;
    uint32_t vram_size;
    qemu_irq irq;
    MemoryRegion mem_vram;
    MemoryRegion mem_ctrl;
    /* registers */
    uint8_t color_palette[256][3];
    uint8_t cursor_palette[3][3];
    uint16_t cursor[512];
    uint32_t cursor_position;
    uint32_t ctla;
    uint32_t top_of_screen;
    uint32_t width, height; /* in pixels */
    /* display refresh support */
    QemuConsole *con;
    int depth;
    int blanked;
} G364State;

#define REG_BOOT     0x000000
#define REG_DISPLAY  0x000118
#define REG_VDISPLAY 0x000150
#define REG_CTLA     0x000300
#define REG_TOP      0x000400
#define REG_CURS_PAL 0x000508
#define REG_CURS_POS 0x000638
#define REG_CLR_PAL  0x000800
#define REG_CURS_PAT 0x001000
#define REG_RESET    0x100000

#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR   0x00800000

#define G364_PAGE_SIZE 4096

static inline int check_dirty(G364State *s, ram_addr_t page)
{
    return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE,
                                   DIRTY_MEMORY_VGA);
}

static inline void reset_dirty(G364State *s,
                               ram_addr_t page_min, ram_addr_t page_max)
{
    memory_region_reset_dirty(&s->mem_vram,
                              page_min,
                              page_max + G364_PAGE_SIZE - page_min - 1,
                              DIRTY_MEMORY_VGA);
}

static void g364fb_draw_graphic8(G364State *s)
{
    DisplaySurface *surface = qemu_console_surface(s->con);
    int i, w;
    uint8_t *vram;
    uint8_t *data_display, *dd;
    ram_addr_t page, page_min, page_max;
    int x, y;
    int xmin, xmax;
    int ymin, ymax;
    int xcursor, ycursor;
    unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);

    switch (surface_bits_per_pixel(surface)) {
        case 8:
            rgb_to_pixel = rgb_to_pixel8;
            w = 1;
            break;
        case 15:
            rgb_to_pixel = rgb_to_pixel15;
            w = 2;
            break;
        case 16:
            rgb_to_pixel = rgb_to_pixel16;
            w = 2;
            break;
        case 32:
            rgb_to_pixel = rgb_to_pixel32;
            w = 4;
            break;
        default:
            hw_error("g364: unknown host depth %d",
                     surface_bits_per_pixel(surface));
            return;
    }

    page = 0;
    page_min = (ram_addr_t)-1;
    page_max = 0;

    x = y = 0;
    xmin = s->width;
    xmax = 0;
    ymin = s->height;
    ymax = 0;

    if (!(s->ctla & CTLA_NO_CURSOR)) {
        xcursor = s->cursor_position >> 12;
        ycursor = s->cursor_position & 0xfff;
    } else {
        xcursor = ycursor = -65;
    }

    vram = s->vram + s->top_of_screen;
    /* XXX: out of range in vram? */
    data_display = dd = surface_data(surface);
    while (y < s->height) {
        if (check_dirty(s, page)) {
            if (y < ymin)
                ymin = ymax = y;
            if (page_min == (ram_addr_t)-1)
                page_min = page;
            page_max = page;
            if (x < xmin)
                xmin = x;
            for (i = 0; i < G364_PAGE_SIZE; i++) {
                uint8_t index;
                unsigned int color;
                if (unlikely((y >= ycursor && y < ycursor + 64) &&
                    (x >= xcursor && x < xcursor + 64))) {
                    /* pointer area */
                    int xdiff = x - xcursor;
                    uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
                    int op = (curs >> ((xdiff & 7) * 2)) & 3;
                    if (likely(op == 0)) {
                        /* transparent */
                        index = *vram;
                        color = (*rgb_to_pixel)(
                            s->color_palette[index][0],
                            s->color_palette[index][1],
                            s->color_palette[index][2]);
                    } else {
                        /* get cursor color */
                        index = op - 1;
                        color = (*rgb_to_pixel)(
                            s->cursor_palette[index][0],
                            s->cursor_palette[index][1],
                            s->cursor_palette[index][2]);
                    }
                } else {
                    /* normal area */
                    index = *vram;
                    color = (*rgb_to_pixel)(
                        s->color_palette[index][0],
                        s->color_palette[index][1],
                        s->color_palette[index][2]);
                }
                memcpy(dd, &color, w);
                dd += w;
                x++;
                vram++;
                if (x == s->width) {
                    xmax = s->width - 1;
                    y++;
                    if (y == s->height) {
                        ymax = s->height - 1;
                        goto done;
                    }
                    data_display = dd = data_display + surface_stride(surface);
                    xmin = 0;
                    x = 0;
                }
            }
            if (x > xmax)
                xmax = x;
            if (y > ymax)
                ymax = y;
        } else {
            int dy;
            if (page_min != (ram_addr_t)-1) {
                reset_dirty(s, page_min, page_max);
                page_min = (ram_addr_t)-1;
                page_max = 0;
                dpy_gfx_update(s->con, xmin, ymin,
                               xmax - xmin + 1, ymax - ymin + 1);
                xmin = s->width;
                xmax = 0;
                ymin = s->height;
                ymax = 0;
            }
            x += G364_PAGE_SIZE;
            dy = x / s->width;
            x = x % s->width;
            y += dy;
            vram += G364_PAGE_SIZE;
            data_display += dy * surface_stride(surface);
            dd = data_display + x * w;
        }
        page += G364_PAGE_SIZE;
    }

done:
    if (page_min != (ram_addr_t)-1) {
        dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
        reset_dirty(s, page_min, page_max);
    }
}

static void g364fb_draw_blank(G364State *s)
{
    DisplaySurface *surface = qemu_console_surface(s->con);
    int i, w;
    uint8_t *d;

    if (s->blanked) {
        /* Screen is already blank. No need to redraw it */
        return;
    }

    w = s->width * surface_bytes_per_pixel(surface);
    d = surface_data(surface);
    for (i = 0; i < s->height; i++) {
        memset(d, 0, w);
        d += surface_stride(surface);
    }

    dpy_gfx_update(s->con, 0, 0, s->width, s->height);
    s->blanked = 1;
}

static void g364fb_update_display(void *opaque)
{
    G364State *s = opaque;
    DisplaySurface *surface = qemu_console_surface(s->con);

    qemu_flush_coalesced_mmio_buffer();

    if (s->width == 0 || s->height == 0)
        return;

    if (s->width != surface_width(surface) ||
        s->height != surface_height(surface)) {
        qemu_console_resize(s->con, s->width, s->height);
    }

    if (s->ctla & CTLA_FORCE_BLANK) {
        g364fb_draw_blank(s);
    } else if (s->depth == 8) {
        g364fb_draw_graphic8(s);
    } else {
        error_report("g364: unknown guest depth %d", s->depth);
    }

    qemu_irq_raise(s->irq);
}

static inline void g364fb_invalidate_display(void *opaque)
{
    G364State *s = opaque;

    s->blanked = 0;
    memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
}

static void g364fb_reset(G364State *s)
{
    qemu_irq_lower(s->irq);

    memset(s->color_palette, 0, sizeof(s->color_palette));
    memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
    memset(s->cursor, 0, sizeof(s->cursor));
    s->cursor_position = 0;
    s->ctla = 0;
    s->top_of_screen = 0;
    s->width = s->height = 0;
    memset(s->vram, 0, s->vram_size);
    g364fb_invalidate_display(s);
}

static void g364fb_screen_dump(void *opaque, const char *filename, bool cswitch,
                               Error **errp)
{
    G364State *s = opaque;
    int ret, y, x;
    uint8_t index;
    uint8_t *data_buffer;
    FILE *f;

    qemu_flush_coalesced_mmio_buffer();

    if (s->depth != 8) {
        error_setg(errp, "g364: unknown guest depth %d", s->depth);
        return;
    }

    f = fopen(filename, "wb");
    if (!f) {
        error_setg(errp, "failed to open file '%s': %s", filename,
                   strerror(errno));
        return;
    }

    if (s->ctla & CTLA_FORCE_BLANK) {
        /* blank screen */
        ret = fprintf(f, "P4\n%d %d\n", s->width, s->height);
        if (ret < 0) {
            goto write_err;
        }
        for (y = 0; y < s->height; y++)
            for (x = 0; x < s->width; x++) {
                ret = fputc(0, f);
                if (ret == EOF) {
                    goto write_err;
                }
            }
    } else {
        data_buffer = s->vram + s->top_of_screen;
        ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
        if (ret < 0) {
            goto write_err;
        }
        for (y = 0; y < s->height; y++)
            for (x = 0; x < s->width; x++, data_buffer++) {
                index = *data_buffer;
                ret = fputc(s->color_palette[index][0], f);
                if (ret == EOF) {
                    goto write_err;
                }
                ret = fputc(s->color_palette[index][1], f);
                if (ret == EOF) {
                    goto write_err;
                }
                ret = fputc(s->color_palette[index][2], f);
                if (ret == EOF) {
                    goto write_err;
                }
        }
    }

out:
    fclose(f);
    return;

write_err:
    error_setg(errp, "failed to write to file '%s': %s", filename,
               strerror(errno));
    unlink(filename);
    goto out;
}

/* called for accesses to io ports */
static uint64_t g364fb_ctrl_read(void *opaque,
                                 hwaddr addr,
                                 unsigned int size)
{
    G364State *s = opaque;
    uint32_t val;

    if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
        /* cursor pattern */
        int idx = (addr - REG_CURS_PAT) >> 3;
        val = s->cursor[idx];
    } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
        /* cursor palette */
        int idx = (addr - REG_CURS_PAL) >> 3;
        val = ((uint32_t)s->cursor_palette[idx][0] << 16);
        val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
        val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
    } else {
        switch (addr) {
            case REG_DISPLAY:
                val = s->width / 4;
                break;
            case REG_VDISPLAY:
                val = s->height * 2;
                break;
            case REG_CTLA:
                val = s->ctla;
                break;
            default:
            {
                error_report("g364: invalid read at [" TARGET_FMT_plx "]",
                             addr);
                val = 0;
                break;
            }
        }
    }

    trace_g364fb_read(addr, val);

    return val;
}

static void g364fb_update_depth(G364State *s)
{
    static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
    s->depth = depths[(s->ctla & 0x00700000) >> 20];
}

static void g364_invalidate_cursor_position(G364State *s)
{
    DisplaySurface *surface = qemu_console_surface(s->con);
    int ymin, ymax, start, end;

    /* invalidate only near the cursor */
    ymin = s->cursor_position & 0xfff;
    ymax = MIN(s->height, ymin + 64);
    start = ymin * surface_stride(surface);
    end = (ymax + 1) * surface_stride(surface);

    memory_region_set_dirty(&s->mem_vram, start, end - start);
}

static void g364fb_ctrl_write(void *opaque,
                              hwaddr addr,
                              uint64_t val,
                              unsigned int size)
{
    G364State *s = opaque;

    trace_g364fb_write(addr, val);

    if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
        /* color palette */
        int idx = (addr - REG_CLR_PAL) >> 3;
        s->color_palette[idx][0] = (val >> 16) & 0xff;
        s->color_palette[idx][1] = (val >> 8) & 0xff;
        s->color_palette[idx][2] = val & 0xff;
        g364fb_invalidate_display(s);
    } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
        /* cursor pattern */
        int idx = (addr - REG_CURS_PAT) >> 3;
        s->cursor[idx] = val;
        g364fb_invalidate_display(s);
    } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
        /* cursor palette */
        int idx = (addr - REG_CURS_PAL) >> 3;
        s->cursor_palette[idx][0] = (val >> 16) & 0xff;
        s->cursor_palette[idx][1] = (val >> 8) & 0xff;
        s->cursor_palette[idx][2] = val & 0xff;
        g364fb_invalidate_display(s);
    } else {
        switch (addr) {
        case REG_BOOT: /* Boot timing */
        case 0x00108: /* Line timing: half sync */
        case 0x00110: /* Line timing: back porch */
        case 0x00120: /* Line timing: short display */
        case 0x00128: /* Frame timing: broad pulse */
        case 0x00130: /* Frame timing: v sync */
        case 0x00138: /* Frame timing: v preequalise */
        case 0x00140: /* Frame timing: v postequalise */
        case 0x00148: /* Frame timing: v blank */
        case 0x00158: /* Line timing: line time */
        case 0x00160: /* Frame store: line start */
        case 0x00168: /* vram cycle: mem init */
        case 0x00170: /* vram cycle: transfer delay */
        case 0x00200: /* vram cycle: mask register */
            /* ignore */
            break;
        case REG_TOP:
            s->top_of_screen = val;
            g364fb_invalidate_display(s);
            break;
        case REG_DISPLAY:
            s->width = val * 4;
            break;
        case REG_VDISPLAY:
            s->height = val / 2;
            break;
        case REG_CTLA:
            s->ctla = val;
            g364fb_update_depth(s);
            g364fb_invalidate_display(s);
            break;
        case REG_CURS_POS:
            g364_invalidate_cursor_position(s);
            s->cursor_position = val;
            g364_invalidate_cursor_position(s);
            break;
        case REG_RESET:
            g364fb_reset(s);
            break;
        default:
            error_report("g364: invalid write of 0x%" PRIx64
                         " at [" TARGET_FMT_plx "]", val, addr);
            break;
        }
    }
    qemu_irq_lower(s->irq);
}

static const MemoryRegionOps g364fb_ctrl_ops = {
    .read = g364fb_ctrl_read,
    .write = g364fb_ctrl_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl.min_access_size = 4,
    .impl.max_access_size = 4,
};

static int g364fb_post_load(void *opaque, int version_id)
{
    G364State *s = opaque;

    /* force refresh */
    g364fb_update_depth(s);
    g364fb_invalidate_display(s);

    return 0;
}

static const VMStateDescription vmstate_g364fb = {
    .name = "g364fb",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = g364fb_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
        VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
        VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
        VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
        VMSTATE_UINT32(cursor_position, G364State),
        VMSTATE_UINT32(ctla, G364State),
        VMSTATE_UINT32(top_of_screen, G364State),
        VMSTATE_UINT32(width, G364State),
        VMSTATE_UINT32(height, G364State),
        VMSTATE_END_OF_LIST()
    }
};

static void g364fb_init(DeviceState *dev, G364State *s)
{
    s->vram = g_malloc0(s->vram_size);

    s->con = graphic_console_init(g364fb_update_display,
                                  g364fb_invalidate_display,
                                  g364fb_screen_dump, NULL, s);

    memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
    memory_region_init_ram_ptr(&s->mem_vram, "vram",
                               s->vram_size, s->vram);
    vmstate_register_ram(&s->mem_vram, dev);
    memory_region_set_coalescing(&s->mem_vram);
}

typedef struct {
    SysBusDevice busdev;
    G364State g364;
} G364SysBusState;

static int g364fb_sysbus_init(SysBusDevice *dev)
{
    G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;

    g364fb_init(&dev->qdev, s);
    sysbus_init_irq(dev, &s->irq);
    sysbus_init_mmio(dev, &s->mem_ctrl);
    sysbus_init_mmio(dev, &s->mem_vram);

    return 0;
}

static void g364fb_sysbus_reset(DeviceState *d)
{
    G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
    g364fb_reset(&s->g364);
}

static Property g364fb_sysbus_properties[] = {
    DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
    8 * 1024 * 1024),
    DEFINE_PROP_END_OF_LIST(),
};

static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = g364fb_sysbus_init;
    dc->desc = "G364 framebuffer";
    dc->reset = g364fb_sysbus_reset;
    dc->vmsd = &vmstate_g364fb;
    dc->props = g364fb_sysbus_properties;
}

static const TypeInfo g364fb_sysbus_info = {
    .name          = "sysbus-g364",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(G364SysBusState),
    .class_init    = g364fb_sysbus_class_init,
};

static void g364fb_register_types(void)
{
    type_register_static(&g364fb_sysbus_info);
}

type_init(g364fb_register_types)
Commit	Line	Data
1fc3d392 AJ	1	/*
	2	* QEMU G364 framebuffer Emulator.
	3	*
97a3f6ff	4	* Copyright (c) 2007-2011 Herve Poussineau
1fc3d392 AJ	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a	16	* You should have received a copy of the GNU General Public License along
8167ee88	17	* with this program; if not, see <http://www.gnu.org/licenses/>.
1fc3d392 AJ	18	*/
1fc3d392 AJ	19
83c9f4ca	20	#include "hw/hw.h"
28ecbaee PB	21	#include "ui/console.h"
28ecbaee PB	22	#include "ui/pixel_ops.h"
b213b370	23	#include "trace.h"
83c9f4ca	24	#include "hw/sysbus.h"
0add30cf	25
1fc3d392	26	typedef struct G364State {
0add30cf AJ	27	/* hardware */
0add30cf AJ	28	uint8_t *vram;
97a3f6ff	29	uint32_t vram_size;
0add30cf	30	qemu_irq irq;
97a3f6ff HP	31	MemoryRegion mem_vram;
97a3f6ff HP	32	MemoryRegion mem_ctrl;
0add30cf AJ	33	/* registers */
	34	uint8_t color_palette[256][3];
	35	uint8_t cursor_palette[3][3];
	36	uint16_t cursor[512];
	37	uint32_t cursor_position;
1fc3d392	38	uint32_t ctla;
0add30cf AJ	39	uint32_t top_of_screen;
0add30cf AJ	40	uint32_t width, height; /* in pixels */
1fc3d392	41	/* display refresh support */
c78f7137	42	QemuConsole *con;
0add30cf AJ	43	int depth;
0add30cf AJ	44	int blanked;
1fc3d392 AJ	45	} G364State;
1fc3d392 AJ	46
97a3f6ff HP	47	#define REG_BOOT 0x000000
	48	#define REG_DISPLAY 0x000118
	49	#define REG_VDISPLAY 0x000150
	50	#define REG_CTLA 0x000300
	51	#define REG_TOP 0x000400
	52	#define REG_CURS_PAL 0x000508
	53	#define REG_CURS_POS 0x000638
	54	#define REG_CLR_PAL 0x000800
	55	#define REG_CURS_PAT 0x001000
	56	#define REG_RESET 0x100000
0add30cf AJ	57
	58	#define CTLA_FORCE_BLANK 0x00000400
	59	#define CTLA_NO_CURSOR 0x00800000
	60
1213406b BS	61	#define G364_PAGE_SIZE 4096
1213406b BS	62
97a3f6ff	63	static inline int check_dirty(G364State *s, ram_addr_t page)
0add30cf	64	{
cd7a45c9 BS	65	return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE,
cd7a45c9 BS	66	DIRTY_MEMORY_VGA);
0add30cf AJ	67	}
	68
	69	static inline void reset_dirty(G364State *s,
c227f099	70	ram_addr_t page_min, ram_addr_t page_max)
0add30cf	71	{
97a3f6ff HP	72	memory_region_reset_dirty(&s->mem_vram,
97a3f6ff HP	73	page_min,
1213406b	74	page_max + G364_PAGE_SIZE - page_min - 1,
97a3f6ff	75	DIRTY_MEMORY_VGA);
0add30cf AJ	76	}
	77
	78	static void g364fb_draw_graphic8(G364State *s)
1fc3d392	79	{
c78f7137	80	DisplaySurface *surface = qemu_console_surface(s->con);
0add30cf AJ	81	int i, w;
	82	uint8_t *vram;
	83	uint8_t data_display, dd;
c227f099	84	ram_addr_t page, page_min, page_max;
0add30cf AJ	85	int x, y;
	86	int xmin, xmax;
	87	int ymin, ymax;
	88	int xcursor, ycursor;
	89	unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
	90
c78f7137	91	switch (surface_bits_per_pixel(surface)) {
1fc3d392	92	case 8:
0add30cf AJ	93	rgb_to_pixel = rgb_to_pixel8;
0add30cf AJ	94	w = 1;
1fc3d392 AJ	95	break;
1fc3d392 AJ	96	case 15:
0add30cf AJ	97	rgb_to_pixel = rgb_to_pixel15;
0add30cf AJ	98	w = 2;
1fc3d392 AJ	99	break;
1fc3d392 AJ	100	case 16:
0add30cf AJ	101	rgb_to_pixel = rgb_to_pixel16;
0add30cf AJ	102	w = 2;
1fc3d392 AJ	103	break;
1fc3d392 AJ	104	case 32:
0add30cf AJ	105	rgb_to_pixel = rgb_to_pixel32;
0add30cf AJ	106	w = 4;
1fc3d392 AJ	107	break;
1fc3d392 AJ	108	default:
b213b370	109	hw_error("g364: unknown host depth %d",
c78f7137	110	surface_bits_per_pixel(surface));
1fc3d392 AJ	111	return;
	112	}
	113
97a3f6ff	114	page = 0;
c227f099	115	page_min = (ram_addr_t)-1;
0add30cf AJ	116	page_max = 0;
	117
	118	x = y = 0;
	119	xmin = s->width;
	120	xmax = 0;
	121	ymin = s->height;
	122	ymax = 0;
	123
	124	if (!(s->ctla & CTLA_NO_CURSOR)) {
	125	xcursor = s->cursor_position >> 12;
	126	ycursor = s->cursor_position & 0xfff;
	127	} else {
	128	xcursor = ycursor = -65;
	129	}
	130
	131	vram = s->vram + s->top_of_screen;
	132	/* XXX: out of range in vram? */
c78f7137	133	data_display = dd = surface_data(surface);
0add30cf	134	while (y < s->height) {
97a3f6ff	135	if (check_dirty(s, page)) {
0add30cf AJ	136	if (y < ymin)
0add30cf AJ	137	ymin = ymax = y;
c227f099	138	if (page_min == (ram_addr_t)-1)
0add30cf AJ	139	page_min = page;
	140	page_max = page;
	141	if (x < xmin)
	142	xmin = x;
1213406b	143	for (i = 0; i < G364_PAGE_SIZE; i++) {
0add30cf AJ	144	uint8_t index;
	145	unsigned int color;
	146	if (unlikely((y >= ycursor && y < ycursor + 64) &&
	147	(x >= xcursor && x < xcursor + 64))) {
	148	/* pointer area */
	149	int xdiff = x - xcursor;
	150	uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
	151	int op = (curs >> ((xdiff & 7) * 2)) & 3;
	152	if (likely(op == 0)) {
	153	/* transparent */
	154	index = *vram;
	155	color = (*rgb_to_pixel)(
	156	s->color_palette[index][0],
	157	s->color_palette[index][1],
	158	s->color_palette[index][2]);
	159	} else {
	160	/* get cursor color */
	161	index = op - 1;
	162	color = (*rgb_to_pixel)(
	163	s->cursor_palette[index][0],
	164	s->cursor_palette[index][1],
	165	s->cursor_palette[index][2]);
	166	}
	167	} else {
	168	/* normal area */
	169	index = *vram;
	170	color = (*rgb_to_pixel)(
	171	s->color_palette[index][0],
	172	s->color_palette[index][1],
	173	s->color_palette[index][2]);
	174	}
	175	memcpy(dd, &color, w);
	176	dd += w;
	177	x++;
	178	vram++;
	179	if (x == s->width) {
	180	xmax = s->width - 1;
	181	y++;
	182	if (y == s->height) {
	183	ymax = s->height - 1;
	184	goto done;
	185	}
c78f7137	186	data_display = dd = data_display + surface_stride(surface);
0add30cf AJ	187	xmin = 0;
	188	x = 0;
	189	}
	190	}
	191	if (x > xmax)
	192	xmax = x;
	193	if (y > ymax)
	194	ymax = y;
	195	} else {
	196	int dy;
c227f099	197	if (page_min != (ram_addr_t)-1) {
0add30cf	198	reset_dirty(s, page_min, page_max);
c227f099	199	page_min = (ram_addr_t)-1;
0add30cf	200	page_max = 0;
c78f7137	201	dpy_gfx_update(s->con, xmin, ymin,
a93a4a22	202	xmax - xmin + 1, ymax - ymin + 1);
0add30cf AJ	203	xmin = s->width;
	204	xmax = 0;
	205	ymin = s->height;
	206	ymax = 0;
	207	}
1213406b	208	x += G364_PAGE_SIZE;
0add30cf AJ	209	dy = x / s->width;
	210	x = x % s->width;
	211	y += dy;
1213406b	212	vram += G364_PAGE_SIZE;
c78f7137	213	data_display += dy * surface_stride(surface);
0add30cf AJ	214	dd = data_display + x * w;
0add30cf AJ	215	}
1213406b	216	page += G364_PAGE_SIZE;
0add30cf AJ	217	}
	218
	219	done:
c227f099	220	if (page_min != (ram_addr_t)-1) {
c78f7137	221	dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
0add30cf AJ	222	reset_dirty(s, page_min, page_max);
0add30cf AJ	223	}
1fc3d392 AJ	224	}
1fc3d392 AJ	225
0add30cf	226	static void g364fb_draw_blank(G364State *s)
1fc3d392	227	{
c78f7137	228	DisplaySurface *surface = qemu_console_surface(s->con);
1fc3d392 AJ	229	int i, w;
	230	uint8_t *d;
	231
0add30cf AJ	232	if (s->blanked) {
0add30cf AJ	233	/* Screen is already blank. No need to redraw it */
1fc3d392	234	return;
0add30cf	235	}
1fc3d392	236
c78f7137 GH	237	w = s->width * surface_bytes_per_pixel(surface);
c78f7137 GH	238	d = surface_data(surface);
0add30cf	239	for (i = 0; i < s->height; i++) {
1fc3d392	240	memset(d, 0, w);
c78f7137	241	d += surface_stride(surface);
1fc3d392	242	}
221bb2d5	243
c78f7137	244	dpy_gfx_update(s->con, 0, 0, s->width, s->height);
0add30cf	245	s->blanked = 1;
1fc3d392 AJ	246	}
1fc3d392 AJ	247
1fc3d392 AJ	248	static void g364fb_update_display(void *opaque)
	249	{
	250	G364State *s = opaque;
c78f7137	251	DisplaySurface *surface = qemu_console_surface(s->con);
1fc3d392	252
e9a07334 JK	253	qemu_flush_coalesced_mmio_buffer();
e9a07334 JK	254
0add30cf	255	if (s->width == 0 \|\| s->height == 0)
221bb2d5 AJ	256	return;
221bb2d5 AJ	257
c78f7137 GH	258	if (s->width != surface_width(surface) \|\|
	259	s->height != surface_height(surface)) {
	260	qemu_console_resize(s->con, s->width, s->height);
221bb2d5	261	}
0add30cf AJ	262
	263	if (s->ctla & CTLA_FORCE_BLANK) {
	264	g364fb_draw_blank(s);
	265	} else if (s->depth == 8) {
	266	g364fb_draw_graphic8(s);
	267	} else {
b213b370	268	error_report("g364: unknown guest depth %d", s->depth);
1fc3d392	269	}
0add30cf AJ	270
0add30cf AJ	271	qemu_irq_raise(s->irq);
1fc3d392 AJ	272	}
1fc3d392 AJ	273
86178a57	274	static inline void g364fb_invalidate_display(void *opaque)
1fc3d392 AJ	275	{
1fc3d392 AJ	276	G364State *s = opaque;
0add30cf AJ	277
0add30cf AJ	278	s->blanked = 0;
fd4aa979	279	memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
1fc3d392 AJ	280	}
1fc3d392 AJ	281
97a3f6ff	282	static void g364fb_reset(G364State *s)
1fc3d392	283	{
0add30cf AJ	284	qemu_irq_lower(s->irq);
	285
	286	memset(s->color_palette, 0, sizeof(s->color_palette));
	287	memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
	288	memset(s->cursor, 0, sizeof(s->cursor));
	289	s->cursor_position = 0;
	290	s->ctla = 0;
	291	s->top_of_screen = 0;
	292	s->width = s->height = 0;
	293	memset(s->vram, 0, s->vram_size);
97a3f6ff	294	g364fb_invalidate_display(s);
1fc3d392 AJ	295	}
1fc3d392 AJ	296
d7098135 LC	297	static void g364fb_screen_dump(void opaque, const char filename, bool cswitch,
d7098135 LC	298	Error **errp)
1fc3d392 AJ	299	{
1fc3d392 AJ	300	G364State *s = opaque;
61a3f955	301	int ret, y, x;
1fc3d392 AJ	302	uint8_t index;
	303	uint8_t *data_buffer;
	304	FILE *f;
	305
e9a07334 JK	306	qemu_flush_coalesced_mmio_buffer();
e9a07334 JK	307
0add30cf	308	if (s->depth != 8) {
61a3f955	309	error_setg(errp, "g364: unknown guest depth %d", s->depth);
0add30cf AJ	310	return;
	311	}
	312
1fc3d392	313	f = fopen(filename, "wb");
61a3f955 LC	314	if (!f) {
	315	error_setg(errp, "failed to open file '%s': %s", filename,
	316	strerror(errno));
1fc3d392	317	return;
61a3f955	318	}
1fc3d392	319
0add30cf AJ	320	if (s->ctla & CTLA_FORCE_BLANK) {
0add30cf AJ	321	/* blank screen */
61a3f955 LC	322	ret = fprintf(f, "P4\n%d %d\n", s->width, s->height);
	323	if (ret < 0) {
	324	goto write_err;
	325	}
0add30cf	326	for (y = 0; y < s->height; y++)
61a3f955 LC	327	for (x = 0; x < s->width; x++) {
	328	ret = fputc(0, f);
	329	if (ret == EOF) {
	330	goto write_err;
	331	}
	332	}
0add30cf AJ	333	} else {
0add30cf AJ	334	data_buffer = s->vram + s->top_of_screen;
61a3f955 LC	335	ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	336	if (ret < 0) {
	337	goto write_err;
	338	}
0add30cf AJ	339	for (y = 0; y < s->height; y++)
	340	for (x = 0; x < s->width; x++, data_buffer++) {
	341	index = *data_buffer;
61a3f955 LC	342	ret = fputc(s->color_palette[index][0], f);
	343	if (ret == EOF) {
	344	goto write_err;
	345	}
	346	ret = fputc(s->color_palette[index][1], f);
	347	if (ret == EOF) {
	348	goto write_err;
	349	}
	350	ret = fputc(s->color_palette[index][2], f);
	351	if (ret == EOF) {
	352	goto write_err;
	353	}
1fc3d392	354	}
0add30cf AJ	355	}
0add30cf AJ	356
61a3f955	357	out:
1fc3d392	358	fclose(f);
61a3f955 LC	359	return;
	360
	361	write_err:
	362	error_setg(errp, "failed to write to file '%s': %s", filename,
	363	strerror(errno));
	364	unlink(filename);
	365	goto out;
1fc3d392 AJ	366	}
	367
	368	/* called for accesses to io ports */
97a3f6ff	369	static uint64_t g364fb_ctrl_read(void *opaque,
a8170e5e	370	hwaddr addr,
97a3f6ff	371	unsigned int size)
1fc3d392	372	{
0add30cf	373	G364State *s = opaque;
1fc3d392 AJ	374	uint32_t val;
1fc3d392 AJ	375
0add30cf AJ	376	if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
	377	/* cursor pattern */
	378	int idx = (addr - REG_CURS_PAT) >> 3;
	379	val = s->cursor[idx];
	380	} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
	381	/* cursor palette */
	382	int idx = (addr - REG_CURS_PAL) >> 3;
	383	val = ((uint32_t)s->cursor_palette[idx][0] << 16);
	384	val \|= ((uint32_t)s->cursor_palette[idx][1] << 8);
	385	val \|= ((uint32_t)s->cursor_palette[idx][2] << 0);
	386	} else {
	387	switch (addr) {
0add30cf AJ	388	case REG_DISPLAY:
	389	val = s->width / 4;
	390	break;
	391	case REG_VDISPLAY:
	392	val = s->height * 2;
	393	break;
	394	case REG_CTLA:
	395	val = s->ctla;
	396	break;
	397	default:
	398	{
b213b370 HP	399	error_report("g364: invalid read at [" TARGET_FMT_plx "]",
b213b370 HP	400	addr);
0add30cf AJ	401	val = 0;
	402	break;
	403	}
	404	}
1fc3d392 AJ	405	}
1fc3d392 AJ	406
b213b370	407	trace_g364fb_read(addr, val);
1fc3d392 AJ	408
	409	return val;
	410	}
	411
0add30cf	412	static void g364fb_update_depth(G364State *s)
1fc3d392	413	{
38972938	414	static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
0add30cf AJ	415	s->depth = depths[(s->ctla & 0x00700000) >> 20];
0add30cf AJ	416	}
1fc3d392	417
0add30cf AJ	418	static void g364_invalidate_cursor_position(G364State *s)
0add30cf AJ	419	{
c78f7137	420	DisplaySurface *surface = qemu_console_surface(s->con);
fd4aa979	421	int ymin, ymax, start, end;
1fc3d392	422
0add30cf AJ	423	/* invalidate only near the cursor */
	424	ymin = s->cursor_position & 0xfff;
	425	ymax = MIN(s->height, ymin + 64);
c78f7137 GH	426	start = ymin * surface_stride(surface);
c78f7137 GH	427	end = (ymax + 1) * surface_stride(surface);
1fc3d392	428
fd4aa979	429	memory_region_set_dirty(&s->mem_vram, start, end - start);
0add30cf AJ	430	}
0add30cf AJ	431
97a3f6ff	432	static void g364fb_ctrl_write(void *opaque,
a8170e5e	433	hwaddr addr,
97a3f6ff HP	434	uint64_t val,
97a3f6ff HP	435	unsigned int size)
0add30cf AJ	436	{
	437	G364State *s = opaque;
	438
b213b370	439	trace_g364fb_write(addr, val);
0add30cf AJ	440
0add30cf AJ	441	if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
1fc3d392	442	/* color palette */
0add30cf AJ	443	int idx = (addr - REG_CLR_PAL) >> 3;
	444	s->color_palette[idx][0] = (val >> 16) & 0xff;
	445	s->color_palette[idx][1] = (val >> 8) & 0xff;
	446	s->color_palette[idx][2] = val & 0xff;
	447	g364fb_invalidate_display(s);
	448	} else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
	449	/* cursor pattern */
	450	int idx = (addr - REG_CURS_PAT) >> 3;
	451	s->cursor[idx] = val;
	452	g364fb_invalidate_display(s);
	453	} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
	454	/* cursor palette */
	455	int idx = (addr - REG_CURS_PAL) >> 3;
	456	s->cursor_palette[idx][0] = (val >> 16) & 0xff;
	457	s->cursor_palette[idx][1] = (val >> 8) & 0xff;
	458	s->cursor_palette[idx][2] = val & 0xff;
	459	g364fb_invalidate_display(s);
1fc3d392 AJ	460	} else {
1fc3d392 AJ	461	switch (addr) {
97a3f6ff HP	462	case REG_BOOT: /* Boot timing */
	463	case 0x00108: /* Line timing: half sync */
	464	case 0x00110: /* Line timing: back porch */
	465	case 0x00120: /* Line timing: short display */
	466	case 0x00128: /* Frame timing: broad pulse */
	467	case 0x00130: /* Frame timing: v sync */
	468	case 0x00138: /* Frame timing: v preequalise */
	469	case 0x00140: /* Frame timing: v postequalise */
	470	case 0x00148: /* Frame timing: v blank */
	471	case 0x00158: /* Line timing: line time */
	472	case 0x00160: /* Frame store: line start */
	473	case 0x00168: /* vram cycle: mem init */
	474	case 0x00170: /* vram cycle: transfer delay */
	475	case 0x00200: /* vram cycle: mask register */
	476	/* ignore */
	477	break;
	478	case REG_TOP:
	479	s->top_of_screen = val;
	480	g364fb_invalidate_display(s);
	481	break;
	482	case REG_DISPLAY:
	483	s->width = val * 4;
	484	break;
	485	case REG_VDISPLAY:
	486	s->height = val / 2;
	487	break;
	488	case REG_CTLA:
	489	s->ctla = val;
	490	g364fb_update_depth(s);
	491	g364fb_invalidate_display(s);
	492	break;
	493	case REG_CURS_POS:
	494	g364_invalidate_cursor_position(s);
	495	s->cursor_position = val;
	496	g364_invalidate_cursor_position(s);
	497	break;
	498	case REG_RESET:
	499	g364fb_reset(s);
	500	break;
	501	default:
	502	error_report("g364: invalid write of 0x%" PRIx64
	503	" at [" TARGET_FMT_plx "]", val, addr);
	504	break;
1fc3d392 AJ	505	}
1fc3d392 AJ	506	}
0add30cf	507	qemu_irq_lower(s->irq);
1fc3d392 AJ	508	}
1fc3d392 AJ	509
97a3f6ff HP	510	static const MemoryRegionOps g364fb_ctrl_ops = {
	511	.read = g364fb_ctrl_read,
	512	.write = g364fb_ctrl_write,
	513	.endianness = DEVICE_LITTLE_ENDIAN,
	514	.impl.min_access_size = 4,
	515	.impl.max_access_size = 4,
1fc3d392 AJ	516	};
1fc3d392 AJ	517
97a3f6ff	518	static int g364fb_post_load(void *opaque, int version_id)
1fc3d392 AJ	519	{
1fc3d392 AJ	520	G364State *s = opaque;
0add30cf AJ	521
	522	/* force refresh */
	523	g364fb_update_depth(s);
	524	g364fb_invalidate_display(s);
1fc3d392	525
0add30cf	526	return 0;
1fc3d392 AJ	527	}
1fc3d392 AJ	528
97a3f6ff HP	529	static const VMStateDescription vmstate_g364fb = {
	530	.name = "g364fb",
	531	.version_id = 1,
	532	.minimum_version_id = 1,
	533	.minimum_version_id_old = 1,
	534	.post_load = g364fb_post_load,
	535	.fields = (VMStateField[]) {
	536	VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
	537	VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
	538	VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
	539	VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
	540	VMSTATE_UINT32(cursor_position, G364State),
	541	VMSTATE_UINT32(ctla, G364State),
	542	VMSTATE_UINT32(top_of_screen, G364State),
	543	VMSTATE_UINT32(width, G364State),
	544	VMSTATE_UINT32(height, G364State),
	545	VMSTATE_END_OF_LIST()
	546	}
	547	};
1fc3d392	548
97a3f6ff	549	static void g364fb_init(DeviceState dev, G364State s)
1fc3d392	550	{
97a3f6ff	551	s->vram = g_malloc0(s->vram_size);
1fc3d392	552
c78f7137 GH	553	s->con = graphic_console_init(g364fb_update_display,
	554	g364fb_invalidate_display,
	555	g364fb_screen_dump, NULL, s);
1fc3d392	556
97a3f6ff	557	memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
c5705a77	558	memory_region_init_ram_ptr(&s->mem_vram, "vram",
97a3f6ff	559	s->vram_size, s->vram);
c5705a77	560	vmstate_register_ram(&s->mem_vram, dev);
97a3f6ff HP	561	memory_region_set_coalescing(&s->mem_vram);
	562	}
	563
	564	typedef struct {
	565	SysBusDevice busdev;
	566	G364State g364;
	567	} G364SysBusState;
1fc3d392	568
97a3f6ff HP	569	static int g364fb_sysbus_init(SysBusDevice *dev)
	570	{
	571	G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
	572
	573	g364fb_init(&dev->qdev, s);
	574	sysbus_init_irq(dev, &s->irq);
750ecd44 AK	575	sysbus_init_mmio(dev, &s->mem_ctrl);
750ecd44 AK	576	sysbus_init_mmio(dev, &s->mem_vram);
1fc3d392 AJ	577
	578	return 0;
	579	}
97a3f6ff HP	580
	581	static void g364fb_sysbus_reset(DeviceState *d)
	582	{
	583	G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
	584	g364fb_reset(&s->g364);
	585	}
	586
999e12bb AL	587	static Property g364fb_sysbus_properties[] = {
	588	DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
	589	8 * 1024 * 1024),
	590	DEFINE_PROP_END_OF_LIST(),
	591	};
	592
	593	static void g364fb_sysbus_class_init(ObjectClass klass, void data)
	594	{
39bffca2	595	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	596	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	597
	598	k->init = g364fb_sysbus_init;
39bffca2 AL	599	dc->desc = "G364 framebuffer";
	600	dc->reset = g364fb_sysbus_reset;
	601	dc->vmsd = &vmstate_g364fb;
	602	dc->props = g364fb_sysbus_properties;
999e12bb AL	603	}
999e12bb AL	604
8c43a6f0	605	static const TypeInfo g364fb_sysbus_info = {
39bffca2 AL	606	.name = "sysbus-g364",
	607	.parent = TYPE_SYS_BUS_DEVICE,
	608	.instance_size = sizeof(G364SysBusState),
	609	.class_init = g364fb_sysbus_class_init,
97a3f6ff HP	610	};
97a3f6ff HP	611
83f7d43a	612	static void g364fb_register_types(void)
97a3f6ff	613	{
39bffca2	614	type_register_static(&g364fb_sysbus_info);
97a3f6ff HP	615	}
97a3f6ff HP	616
83f7d43a	617	type_init(g364fb_register_types)