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acpi-build: fix build on glib < 2.14
[qemu.git] / hw / gpio / omap_gpio.c
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e5c6b25a 1/*
2 * TI OMAP processors GPIO emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca 21#include "hw/hw.h"
0d09e41a 22#include "hw/arm/omap.h"
83c9f4ca 23#include "hw/sysbus.h"
77831c20 24
e5c6b25a 25struct omap_gpio_s {
26 qemu_irq irq;
e5c6b25a 27 qemu_irq handler[16];
28
29 uint16_t inputs;
30 uint16_t outputs;
31 uint16_t dir;
32 uint16_t edge;
33 uint16_t mask;
34 uint16_t ints;
35 uint16_t pins;
36};
37
1d300b5f
AF		 38#define TYPE_OMAP1_GPIO "omap-gpio"
39#define OMAP1_GPIO(obj) \
40 OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
41
77831c20 42struct omap_gpif_s {
1d300b5f
AF		 43 SysBusDevice parent_obj;
44
9244b42d 45 MemoryRegion iomem;
77831c20
JR		 46 int mpu_model;
47 void *clk;
48 struct omap_gpio_s omap1;
49};
50
51/* General-Purpose I/O of OMAP1 */
e5c6b25a 52static void omap_gpio_set(void *opaque, int line, int level)
53{
77831c20 54 struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
e5c6b25a 55 uint16_t prev = s->inputs;
56
57 if (level)
58 s->inputs |= 1 << line;
59 else
60 s->inputs &= ~(1 << line);
61
62 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
63 (1 << line) & s->dir & ~s->mask) {
64 s->ints |= 1 << line;
65 qemu_irq_raise(s->irq);
66 }
67}
68
a8170e5e 69static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
9244b42d 70 unsigned size)
e5c6b25a 71{
72 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
73 int offset = addr & OMAP_MPUI_REG_MASK;
74
9244b42d
AK		 75 if (size != 2) {
76 return omap_badwidth_read16(opaque, addr);
77 }
78
e5c6b25a 79 switch (offset) {
80 case 0x00: /* DATA_INPUT */
81 return s->inputs & s->pins;
82
83 case 0x04: /* DATA_OUTPUT */
84 return s->outputs;
85
86 case 0x08: /* DIRECTION_CONTROL */
87 return s->dir;
88
89 case 0x0c: /* INTERRUPT_CONTROL */
90 return s->edge;
91
92 case 0x10: /* INTERRUPT_MASK */
93 return s->mask;
94
95 case 0x14: /* INTERRUPT_STATUS */
96 return s->ints;
97
98 case 0x18: /* PIN_CONTROL (not in OMAP310) */
99 OMAP_BAD_REG(addr);
100 return s->pins;
101 }
102
103 OMAP_BAD_REG(addr);
104 return 0;
105}
106
a8170e5e 107static void omap_gpio_write(void *opaque, hwaddr addr,
9244b42d 108 uint64_t value, unsigned size)
e5c6b25a 109{
110 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
111 int offset = addr & OMAP_MPUI_REG_MASK;
112 uint16_t diff;
113 int ln;
114
9244b42d
AK		 115 if (size != 2) {
116 return omap_badwidth_write16(opaque, addr, value);
117 }
118
e5c6b25a 119 switch (offset) {
120 case 0x00: /* DATA_INPUT */
121 OMAP_RO_REG(addr);
122 return;
123
124 case 0x04: /* DATA_OUTPUT */
125 diff = (s->outputs ^ value) & ~s->dir;
126 s->outputs = value;
127 while ((ln = ffs(diff))) {
128 ln --;
129 if (s->handler[ln])
130 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
131 diff &= ~(1 << ln);
132 }
133 break;
134
135 case 0x08: /* DIRECTION_CONTROL */
136 diff = s->outputs & (s->dir ^ value);
137 s->dir = value;
138
139 value = s->outputs & ~s->dir;
140 while ((ln = ffs(diff))) {
141 ln --;
142 if (s->handler[ln])
143 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
144 diff &= ~(1 << ln);
145 }
146 break;
147
148 case 0x0c: /* INTERRUPT_CONTROL */
149 s->edge = value;
150 break;
151
152 case 0x10: /* INTERRUPT_MASK */
153 s->mask = value;
154 break;
155
156 case 0x14: /* INTERRUPT_STATUS */
157 s->ints &= ~value;
158 if (!s->ints)
159 qemu_irq_lower(s->irq);
160 break;
161
162 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
163 OMAP_BAD_REG(addr);
164 s->pins = value;
165 break;
166
167 default:
168 OMAP_BAD_REG(addr);
169 return;
170 }
171}
172
173/* *Some* sources say the memory region is 32-bit. */
9244b42d
AK		 174static const MemoryRegionOps omap_gpio_ops = {
175 .read = omap_gpio_read,
176 .write = omap_gpio_write,
177 .endianness = DEVICE_NATIVE_ENDIAN,
e5c6b25a 178};
179
77831c20 180static void omap_gpio_reset(struct omap_gpio_s *s)
e5c6b25a 181{
182 s->inputs = 0;
183 s->outputs = ~0;
184 s->dir = ~0;
185 s->edge = ~0;
186 s->mask = ~0;
187 s->ints = 0;
188 s->pins = ~0;
189}
190
d82310f7 191struct omap2_gpio_s {
192 qemu_irq irq[2];
193 qemu_irq wkup;
77831c20 194 qemu_irq *handler;
9244b42d 195 MemoryRegion iomem;
d82310f7 196
77831c20 197 uint8_t revision;
d82310f7 198 uint8_t config[2];
199 uint32_t inputs;
200 uint32_t outputs;
201 uint32_t dir;
202 uint32_t level[2];
203 uint32_t edge[2];
204 uint32_t mask[2];
205 uint32_t wumask;
206 uint32_t ints[2];
207 uint32_t debounce;
208 uint8_t delay;
209};
210
74d1e352
AF		 211#define TYPE_OMAP2_GPIO "omap2-gpio"
212#define OMAP2_GPIO(obj) \
213 OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
214
77831c20 215struct omap2_gpif_s {
74d1e352
AF		 216 SysBusDevice parent_obj;
217
9244b42d 218 MemoryRegion iomem;
77831c20
JR		 219 int mpu_model;
220 void *iclk;
221 void *fclk[6];
222 int modulecount;
223 struct omap2_gpio_s *modules;
224 qemu_irq *handler;
225 int autoidle;
226 int gpo;
227};
228
229/* General-Purpose Interface of OMAP2/3 */
d82310f7 230static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
77831c20 231 int line)
d82310f7 232{
233 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
234}
235
236static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
237{
238 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
239 return;
240 if (!(s->config[0] & (3 << 3))) /* Force Idle */
241 return;
242 if (!(s->wumask & (1 << line)))
243 return;
244
245 qemu_irq_raise(s->wkup);
246}
247
248static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
249 uint32_t diff)
250{
251 int ln;
252
253 s->outputs ^= diff;
254 diff &= ~s->dir;
255 while ((ln = ffs(diff))) {
256 ln --;
257 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
258 diff &= ~(1 << ln);
259 }
260}
261
262static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
263{
264 s->ints[line] |= s->dir &
265 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
266 omap2_gpio_module_int_update(s, line);
267}
268
269static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
270{
271 s->ints[0] |= 1 << line;
272 omap2_gpio_module_int_update(s, 0);
273 s->ints[1] |= 1 << line;
274 omap2_gpio_module_int_update(s, 1);
275 omap2_gpio_module_wake(s, line);
276}
277
77831c20 278static void omap2_gpio_set(void *opaque, int line, int level)
d82310f7 279{
77831c20
JR		 280 struct omap2_gpif_s *p = opaque;
281 struct omap2_gpio_s *s = &p->modules[line >> 5];
d82310f7 282
77831c20 283 line &= 31;
d82310f7 284 if (level) {
285 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
286 omap2_gpio_module_int(s, line);
287 s->inputs |= 1 << line;
288 } else {
289 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
290 omap2_gpio_module_int(s, line);
291 s->inputs &= ~(1 << line);
292 }
293}
294
295static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
296{
297 s->config[0] = 0;
298 s->config[1] = 2;
299 s->ints[0] = 0;
300 s->ints[1] = 0;
301 s->mask[0] = 0;
302 s->mask[1] = 0;
303 s->wumask = 0;
304 s->dir = ~0;
305 s->level[0] = 0;
306 s->level[1] = 0;
307 s->edge[0] = 0;
308 s->edge[1] = 0;
309 s->debounce = 0;
310 s->delay = 0;
311}
312
a8170e5e 313static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
d82310f7 314{
315 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
316
317 switch (addr) {
318 case 0x00: /* GPIO_REVISION */
77831c20 319 return s->revision;
d82310f7 320
321 case 0x10: /* GPIO_SYSCONFIG */
322 return s->config[0];
323
324 case 0x14: /* GPIO_SYSSTATUS */
325 return 0x01;
326
327 case 0x18: /* GPIO_IRQSTATUS1 */
328 return s->ints[0];
329
330 case 0x1c: /* GPIO_IRQENABLE1 */
331 case 0x60: /* GPIO_CLEARIRQENABLE1 */
332 case 0x64: /* GPIO_SETIRQENABLE1 */
333 return s->mask[0];
334
335 case 0x20: /* GPIO_WAKEUPENABLE */
336 case 0x80: /* GPIO_CLEARWKUENA */
337 case 0x84: /* GPIO_SETWKUENA */
338 return s->wumask;
339
340 case 0x28: /* GPIO_IRQSTATUS2 */
341 return s->ints[1];
342
343 case 0x2c: /* GPIO_IRQENABLE2 */
344 case 0x70: /* GPIO_CLEARIRQENABLE2 */
345 case 0x74: /* GPIO_SETIREQNEABLE2 */
346 return s->mask[1];
347
348 case 0x30: /* GPIO_CTRL */
349 return s->config[1];
350
351 case 0x34: /* GPIO_OE */
352 return s->dir;
353
354 case 0x38: /* GPIO_DATAIN */
355 return s->inputs;
356
357 case 0x3c: /* GPIO_DATAOUT */
358 case 0x90: /* GPIO_CLEARDATAOUT */
359 case 0x94: /* GPIO_SETDATAOUT */
360 return s->outputs;
361
362 case 0x40: /* GPIO_LEVELDETECT0 */
363 return s->level[0];
364
365 case 0x44: /* GPIO_LEVELDETECT1 */
366 return s->level[1];
367
368 case 0x48: /* GPIO_RISINGDETECT */
369 return s->edge[0];
370
371 case 0x4c: /* GPIO_FALLINGDETECT */
372 return s->edge[1];
373
374 case 0x50: /* GPIO_DEBOUNCENABLE */
375 return s->debounce;
376
377 case 0x54: /* GPIO_DEBOUNCINGTIME */
378 return s->delay;
379 }
380
381 OMAP_BAD_REG(addr);
382 return 0;
383}
384
a8170e5e 385static void omap2_gpio_module_write(void *opaque, hwaddr addr,
d82310f7 386 uint32_t value)
387{
388 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
389 uint32_t diff;
390 int ln;
391
392 switch (addr) {
393 case 0x00: /* GPIO_REVISION */
394 case 0x14: /* GPIO_SYSSTATUS */
395 case 0x38: /* GPIO_DATAIN */
396 OMAP_RO_REG(addr);
397 break;
398
399 case 0x10: /* GPIO_SYSCONFIG */
400 if (((value >> 3) & 3) == 3)
401 fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
402 if (value & 2)
403 omap2_gpio_module_reset(s);
404 s->config[0] = value & 0x1d;
405 break;
406
407 case 0x18: /* GPIO_IRQSTATUS1 */
408 if (s->ints[0] & value) {
409 s->ints[0] &= ~value;
410 omap2_gpio_module_level_update(s, 0);
411 }
412 break;
413
414 case 0x1c: /* GPIO_IRQENABLE1 */
415 s->mask[0] = value;
416 omap2_gpio_module_int_update(s, 0);
417 break;
418
419 case 0x20: /* GPIO_WAKEUPENABLE */
420 s->wumask = value;
421 break;
422
423 case 0x28: /* GPIO_IRQSTATUS2 */
424 if (s->ints[1] & value) {
425 s->ints[1] &= ~value;
426 omap2_gpio_module_level_update(s, 1);
427 }
428 break;
429
430 case 0x2c: /* GPIO_IRQENABLE2 */
431 s->mask[1] = value;
432 omap2_gpio_module_int_update(s, 1);
433 break;
434
435 case 0x30: /* GPIO_CTRL */
436 s->config[1] = value & 7;
437 break;
438
439 case 0x34: /* GPIO_OE */
440 diff = s->outputs & (s->dir ^ value);
441 s->dir = value;
442
443 value = s->outputs & ~s->dir;
444 while ((ln = ffs(diff))) {
445 diff &= ~(1 <<-- ln);
446 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
447 }
448
449 omap2_gpio_module_level_update(s, 0);
450 omap2_gpio_module_level_update(s, 1);
451 break;
452
453 case 0x3c: /* GPIO_DATAOUT */
454 omap2_gpio_module_out_update(s, s->outputs ^ value);
455 break;
456
457 case 0x40: /* GPIO_LEVELDETECT0 */
458 s->level[0] = value;
459 omap2_gpio_module_level_update(s, 0);
460 omap2_gpio_module_level_update(s, 1);
461 break;
462
463 case 0x44: /* GPIO_LEVELDETECT1 */
464 s->level[1] = value;
465 omap2_gpio_module_level_update(s, 0);
466 omap2_gpio_module_level_update(s, 1);
467 break;
468
469 case 0x48: /* GPIO_RISINGDETECT */
470 s->edge[0] = value;
471 break;
472
473 case 0x4c: /* GPIO_FALLINGDETECT */
474 s->edge[1] = value;
475 break;
476
477 case 0x50: /* GPIO_DEBOUNCENABLE */
478 s->debounce = value;
479 break;
480
481 case 0x54: /* GPIO_DEBOUNCINGTIME */
482 s->delay = value;
483 break;
484
485 case 0x60: /* GPIO_CLEARIRQENABLE1 */
486 s->mask[0] &= ~value;
487 omap2_gpio_module_int_update(s, 0);
488 break;
489
490 case 0x64: /* GPIO_SETIRQENABLE1 */
491 s->mask[0] |= value;
492 omap2_gpio_module_int_update(s, 0);
493 break;
494
495 case 0x70: /* GPIO_CLEARIRQENABLE2 */
496 s->mask[1] &= ~value;
497 omap2_gpio_module_int_update(s, 1);
498 break;
499
500 case 0x74: /* GPIO_SETIREQNEABLE2 */
501 s->mask[1] |= value;
502 omap2_gpio_module_int_update(s, 1);
503 break;
504
505 case 0x80: /* GPIO_CLEARWKUENA */
506 s->wumask &= ~value;
507 break;
508
509 case 0x84: /* GPIO_SETWKUENA */
510 s->wumask |= value;
511 break;
512
513 case 0x90: /* GPIO_CLEARDATAOUT */
514 omap2_gpio_module_out_update(s, s->outputs & value);
515 break;
516
517 case 0x94: /* GPIO_SETDATAOUT */
518 omap2_gpio_module_out_update(s, ~s->outputs & value);
519 break;
520
521 default:
522 OMAP_BAD_REG(addr);
523 return;
524 }
525}
526
a8170e5e 527static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
d82310f7 528{
e1556ad5 529 return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
d82310f7 530}
531
a8170e5e 532static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
d82310f7 533 uint32_t value)
534{
535 uint32_t cur = 0;
536 uint32_t mask = 0xffff;
537
538 switch (addr & ~3) {
539 case 0x00: /* GPIO_REVISION */
540 case 0x14: /* GPIO_SYSSTATUS */
541 case 0x38: /* GPIO_DATAIN */
542 OMAP_RO_REG(addr);
543 break;
544
545 case 0x10: /* GPIO_SYSCONFIG */
546 case 0x1c: /* GPIO_IRQENABLE1 */
547 case 0x20: /* GPIO_WAKEUPENABLE */
548 case 0x2c: /* GPIO_IRQENABLE2 */
549 case 0x30: /* GPIO_CTRL */
550 case 0x34: /* GPIO_OE */
551 case 0x3c: /* GPIO_DATAOUT */
552 case 0x40: /* GPIO_LEVELDETECT0 */
553 case 0x44: /* GPIO_LEVELDETECT1 */
554 case 0x48: /* GPIO_RISINGDETECT */
555 case 0x4c: /* GPIO_FALLINGDETECT */
556 case 0x50: /* GPIO_DEBOUNCENABLE */
557 case 0x54: /* GPIO_DEBOUNCINGTIME */
558 cur = omap2_gpio_module_read(opaque, addr & ~3) &
559 ~(mask << ((addr & 3) << 3));
560
561 /* Fall through. */
562 case 0x18: /* GPIO_IRQSTATUS1 */
563 case 0x28: /* GPIO_IRQSTATUS2 */
564 case 0x60: /* GPIO_CLEARIRQENABLE1 */
565 case 0x64: /* GPIO_SETIRQENABLE1 */
566 case 0x70: /* GPIO_CLEARIRQENABLE2 */
567 case 0x74: /* GPIO_SETIREQNEABLE2 */
568 case 0x80: /* GPIO_CLEARWKUENA */
569 case 0x84: /* GPIO_SETWKUENA */
570 case 0x90: /* GPIO_CLEARDATAOUT */
571 case 0x94: /* GPIO_SETDATAOUT */
572 value <<= (addr & 3) << 3;
573 omap2_gpio_module_write(opaque, addr, cur | value);
574 break;
575
576 default:
577 OMAP_BAD_REG(addr);
578 return;
579 }
580}
581
9244b42d
AK		 582static const MemoryRegionOps omap2_gpio_module_ops = {
583 .old_mmio = {
584 .read = {
585 omap2_gpio_module_readp,
586 omap2_gpio_module_readp,
587 omap2_gpio_module_read,
588 },
589 .write = {
590 omap2_gpio_module_writep,
591 omap2_gpio_module_writep,
592 omap2_gpio_module_write,
593 },
594 },
595 .endianness = DEVICE_NATIVE_ENDIAN,
d82310f7 596};
597
77831c20 598static void omap_gpif_reset(DeviceState *dev)
d82310f7 599{
1d300b5f
AF		 600 struct omap_gpif_s *s = OMAP1_GPIO(dev);
601
77831c20 602 omap_gpio_reset(&s->omap1);
d82310f7 603}
604
77831c20 605static void omap2_gpif_reset(DeviceState *dev)
d82310f7 606{
74d1e352 607 struct omap2_gpif_s *s = OMAP2_GPIO(dev);
d82310f7 608 int i;
74d1e352 609
77831c20
JR		 610 for (i = 0; i < s->modulecount; i++) {
611 omap2_gpio_module_reset(&s->modules[i]);
612 }
d82310f7 613 s->autoidle = 0;
614 s->gpo = 0;
615}
616
a8170e5e 617static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
9244b42d 618 unsigned size)
d82310f7 619{
77831c20 620 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
d82310f7 621
622 switch (addr) {
623 case 0x00: /* IPGENERICOCPSPL_REVISION */
624 return 0x18;
625
626 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
627 return s->autoidle;
628
629 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
630 return 0x01;
631
632 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
633 return 0x00;
634
635 case 0x40: /* IPGENERICOCPSPL_GPO */
636 return s->gpo;
637
638 case 0x50: /* IPGENERICOCPSPL_GPI */
639 return 0x00;
640 }
641
642 OMAP_BAD_REG(addr);
643 return 0;
644}
645
a8170e5e 646static void omap2_gpif_top_write(void *opaque, hwaddr addr,
9244b42d 647 uint64_t value, unsigned size)
d82310f7 648{
77831c20 649 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
d82310f7 650
651 switch (addr) {
652 case 0x00: /* IPGENERICOCPSPL_REVISION */
653 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
654 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
655 case 0x50: /* IPGENERICOCPSPL_GPI */
656 OMAP_RO_REG(addr);
657 break;
658
659 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
660 if (value & (1 << 1)) /* SOFTRESET */
74d1e352 661 omap2_gpif_reset(DEVICE(s));
d82310f7 662 s->autoidle = value & 1;
663 break;
664
665 case 0x40: /* IPGENERICOCPSPL_GPO */
666 s->gpo = value & 1;
667 break;
668
669 default:
670 OMAP_BAD_REG(addr);
671 return;
672 }
673}
674
9244b42d
AK		 675static const MemoryRegionOps omap2_gpif_top_ops = {
676 .read = omap2_gpif_top_read,
677 .write = omap2_gpif_top_write,
678 .endianness = DEVICE_NATIVE_ENDIAN,
d82310f7 679};
680
1d300b5f 681static int omap_gpio_init(SysBusDevice *sbd)
d82310f7 682{
1d300b5f
AF		 683 DeviceState *dev = DEVICE(sbd);
684 struct omap_gpif_s *s = OMAP1_GPIO(dev);
685
77831c20
JR		 686 if (!s->clk) {
687 hw_error("omap-gpio: clk not connected\n");
688 }
1d300b5f
AF		 689 qdev_init_gpio_in(dev, omap_gpio_set, 16);
690 qdev_init_gpio_out(dev, s->omap1.handler, 16);
691 sysbus_init_irq(sbd, &s->omap1.irq);
b7163687 692 memory_region_init_io(&s->iomem, OBJECT(s), &omap_gpio_ops, &s->omap1,
9244b42d 693 "omap.gpio", 0x1000);
1d300b5f 694 sysbus_init_mmio(sbd, &s->iomem);
77831c20
JR		 695 return 0;
696}
d82310f7 697
74d1e352 698static int omap2_gpio_init(SysBusDevice *sbd)
77831c20 699{
74d1e352
AF		 700 DeviceState *dev = DEVICE(sbd);
701 struct omap2_gpif_s *s = OMAP2_GPIO(dev);
77831c20 702 int i;
74d1e352 703
77831c20
JR		 704 if (!s->iclk) {
705 hw_error("omap2-gpio: iclk not connected\n");
706 }
707 if (s->mpu_model < omap3430) {
708 s->modulecount = (s->mpu_model < omap2430) ? 4 : 5;
b7163687 709 memory_region_init_io(&s->iomem, OBJECT(s), &omap2_gpif_top_ops, s,
9244b42d 710 "omap2.gpio", 0x1000);
74d1e352 711 sysbus_init_mmio(sbd, &s->iomem);
77831c20
JR		 712 } else {
713 s->modulecount = 6;
714 }
7267c094
AL		 715 s->modules = g_malloc0(s->modulecount * sizeof(struct omap2_gpio_s));
716 s->handler = g_malloc0(s->modulecount * 32 * sizeof(qemu_irq));
74d1e352
AF		 717 qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
718 qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
77831c20
JR		 719 for (i = 0; i < s->modulecount; i++) {
720 struct omap2_gpio_s *m = &s->modules[i];
721 if (!s->fclk[i]) {
722 hw_error("omap2-gpio: fclk%d not connected\n", i);
723 }
724 m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
725 m->handler = &s->handler[i * 32];
74d1e352
AF		 726 sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
727 sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
728 sysbus_init_irq(sbd, &m->wkup);
b7163687 729 memory_region_init_io(&m->iomem, OBJECT(s), &omap2_gpio_module_ops, m,
9244b42d 730 "omap.gpio-module", 0x1000);
74d1e352 731 sysbus_init_mmio(sbd, &m->iomem);
77831c20
JR		 732 }
733 return 0;
734}
d82310f7 735
77831c20
JR		 736/* Using qdev pointer properties for the clocks is not ideal.
737 * qdev should support a generic means of defining a 'port' with
738 * an arbitrary interface for connecting two devices. Then we
739 * could reframe the omap clock API in terms of clock ports,
740 * and get some type safety. For now the best qdev provides is
741 * passing an arbitrary pointer.
742 * (It's not possible to pass in the string which is the clock
743 * name, because this device does not have the necessary information
744 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
745 * translation.)
746 */
d82310f7 747
999e12bb
AL		 748static Property omap_gpio_properties[] = {
749 DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
750 DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk),
751 DEFINE_PROP_END_OF_LIST(),
77831c20 752};
d82310f7 753
999e12bb
AL		 754static void omap_gpio_class_init(ObjectClass *klass, void *data)
755{
39bffca2 756 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL		 757 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
758
759 k->init = omap_gpio_init;
39bffca2
AL		 760 dc->reset = omap_gpif_reset;
761 dc->props = omap_gpio_properties;
999e12bb
AL		 762}
763
8c43a6f0 764static const TypeInfo omap_gpio_info = {
1d300b5f 765 .name = TYPE_OMAP1_GPIO,
39bffca2
AL		 766 .parent = TYPE_SYS_BUS_DEVICE,
767 .instance_size = sizeof(struct omap_gpif_s),
768 .class_init = omap_gpio_class_init,
999e12bb
AL		 769};
770
771static Property omap2_gpio_properties[] = {
772 DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
773 DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk),
774 DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]),
775 DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]),
776 DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]),
777 DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]),
778 DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]),
779 DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]),
780 DEFINE_PROP_END_OF_LIST(),
781};
782
783static void omap2_gpio_class_init(ObjectClass *klass, void *data)
784{
39bffca2 785 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL		 786 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
787
788 k->init = omap2_gpio_init;
39bffca2
AL		 789 dc->reset = omap2_gpif_reset;
790 dc->props = omap2_gpio_properties;
999e12bb
AL		 791}
792
8c43a6f0 793static const TypeInfo omap2_gpio_info = {
74d1e352 794 .name = TYPE_OMAP2_GPIO,
39bffca2
AL		 795 .parent = TYPE_SYS_BUS_DEVICE,
796 .instance_size = sizeof(struct omap2_gpif_s),
797 .class_init = omap2_gpio_class_init,
77831c20 798};
d82310f7 799
83f7d43a 800static void omap_gpio_register_types(void)
d82310f7 801{
39bffca2
AL		 802 type_register_static(&omap_gpio_info);
803 type_register_static(&omap2_gpio_info);
d82310f7 804}
805
83f7d43a 806type_init(omap_gpio_register_types)
Qemu copy for testing