[qemu.git] / hw / gpio / pl061.c

/*
 * Arm PrimeCell PL061 General Purpose IO with additional
 * Luminary Micro Stellaris bits.
 *
 * Copyright (c) 2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"

//#define DEBUG_PL061 1

#ifdef DEBUG_PL061
#define DPRINTF(fmt, ...) \
do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

static const uint8_t pl061_id[12] =
  { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
static const uint8_t pl061_id_luminary[12] =
  { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };

#define TYPE_PL061 "pl061"
#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)

typedef struct PL061State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t locked;
    uint32_t data;
    uint32_t old_data;
    uint32_t dir;
    uint32_t isense;
    uint32_t ibe;
    uint32_t iev;
    uint32_t im;
    uint32_t istate;
    uint32_t afsel;
    uint32_t dr2r;
    uint32_t dr4r;
    uint32_t dr8r;
    uint32_t odr;
    uint32_t pur;
    uint32_t pdr;
    uint32_t slr;
    uint32_t den;
    uint32_t cr;
    uint32_t float_high;
    uint32_t amsel;
    qemu_irq irq;
    qemu_irq out[8];
    const unsigned char *id;
} PL061State;

static const VMStateDescription vmstate_pl061 = {
    .name = "pl061",
    .version_id = 2,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(locked, PL061State),
        VMSTATE_UINT32(data, PL061State),
        VMSTATE_UINT32(old_data, PL061State),
        VMSTATE_UINT32(dir, PL061State),
        VMSTATE_UINT32(isense, PL061State),
        VMSTATE_UINT32(ibe, PL061State),
        VMSTATE_UINT32(iev, PL061State),
        VMSTATE_UINT32(im, PL061State),
        VMSTATE_UINT32(istate, PL061State),
        VMSTATE_UINT32(afsel, PL061State),
        VMSTATE_UINT32(dr2r, PL061State),
        VMSTATE_UINT32(dr4r, PL061State),
        VMSTATE_UINT32(dr8r, PL061State),
        VMSTATE_UINT32(odr, PL061State),
        VMSTATE_UINT32(pur, PL061State),
        VMSTATE_UINT32(pdr, PL061State),
        VMSTATE_UINT32(slr, PL061State),
        VMSTATE_UINT32(den, PL061State),
        VMSTATE_UINT32(cr, PL061State),
        VMSTATE_UINT32(float_high, PL061State),
        VMSTATE_UINT32_V(amsel, PL061State, 2),
        VMSTATE_END_OF_LIST()
    }
};

static void pl061_update(PL061State *s)
{
    uint8_t changed;
    uint8_t mask;
    uint8_t out;
    int i;

    /* Outputs float high.  */
    /* FIXME: This is board dependent.  */
    out = (s->data & s->dir) | ~s->dir;
    changed = s->old_data ^ out;
    if (!changed)
        return;

    s->old_data = out;
    for (i = 0; i < 8; i++) {
        mask = 1 << i;
        if (changed & mask) {
            DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
            qemu_set_irq(s->out[i], (out & mask) != 0);
        }
    }

    /* FIXME: Implement input interrupts.  */
}

static uint64_t pl061_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL061State *s = (PL061State *)opaque;

    if (offset >= 0xfd0 && offset < 0x1000) {
        return s->id[(offset - 0xfd0) >> 2];
    }
    if (offset < 0x400) {
        return s->data & (offset >> 2);
    }
    switch (offset) {
    case 0x400: /* Direction */
        return s->dir;
    case 0x404: /* Interrupt sense */
        return s->isense;
    case 0x408: /* Interrupt both edges */
        return s->ibe;
    case 0x40c: /* Interrupt event */
        return s->iev;
    case 0x410: /* Interrupt mask */
        return s->im;
    case 0x414: /* Raw interrupt status */
        return s->istate;
    case 0x418: /* Masked interrupt status */
        return s->istate | s->im;
    case 0x420: /* Alternate function select */
        return s->afsel;
    case 0x500: /* 2mA drive */
        return s->dr2r;
    case 0x504: /* 4mA drive */
        return s->dr4r;
    case 0x508: /* 8mA drive */
        return s->dr8r;
    case 0x50c: /* Open drain */
        return s->odr;
    case 0x510: /* Pull-up */
        return s->pur;
    case 0x514: /* Pull-down */
        return s->pdr;
    case 0x518: /* Slew rate control */
        return s->slr;
    case 0x51c: /* Digital enable */
        return s->den;
    case 0x520: /* Lock */
        return s->locked;
    case 0x524: /* Commit */
        return s->cr;
    case 0x528: /* Analog mode select */
        return s->amsel;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl061_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl061_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL061State *s = (PL061State *)opaque;
    uint8_t mask;

    if (offset < 0x400) {
        mask = (offset >> 2) & s->dir;
        s->data = (s->data & ~mask) | (value & mask);
        pl061_update(s);
        return;
    }
    switch (offset) {
    case 0x400: /* Direction */
        s->dir = value & 0xff;
        break;
    case 0x404: /* Interrupt sense */
        s->isense = value & 0xff;
        break;
    case 0x408: /* Interrupt both edges */
        s->ibe = value & 0xff;
        break;
    case 0x40c: /* Interrupt event */
        s->iev = value & 0xff;
        break;
    case 0x410: /* Interrupt mask */
        s->im = value & 0xff;
        break;
    case 0x41c: /* Interrupt clear */
        s->istate &= ~value;
        break;
    case 0x420: /* Alternate function select */
        mask = s->cr;
        s->afsel = (s->afsel & ~mask) | (value & mask);
        break;
    case 0x500: /* 2mA drive */
        s->dr2r = value & 0xff;
        break;
    case 0x504: /* 4mA drive */
        s->dr4r = value & 0xff;
        break;
    case 0x508: /* 8mA drive */
        s->dr8r = value & 0xff;
        break;
    case 0x50c: /* Open drain */
        s->odr = value & 0xff;
        break;
    case 0x510: /* Pull-up */
        s->pur = value & 0xff;
        break;
    case 0x514: /* Pull-down */
        s->pdr = value & 0xff;
        break;
    case 0x518: /* Slew rate control */
        s->slr = value & 0xff;
        break;
    case 0x51c: /* Digital enable */
        s->den = value & 0xff;
        break;
    case 0x520: /* Lock */
        s->locked = (value != 0xacce551);
        break;
    case 0x524: /* Commit */
        if (!s->locked)
            s->cr = value & 0xff;
        break;
    case 0x528:
        s->amsel = value & 0xff;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl061_write: Bad offset %x\n", (int)offset);
    }
    pl061_update(s);
}

static void pl061_reset(PL061State *s)
{
  s->locked = 1;
  s->cr = 0xff;
}

static void pl061_set_irq(void * opaque, int irq, int level)
{
    PL061State *s = (PL061State *)opaque;
    uint8_t mask;

    mask = 1 << irq;
    if ((s->dir & mask) == 0) {
        s->data &= ~mask;
        if (level)
            s->data |= mask;
        pl061_update(s);
    }
}

static const MemoryRegionOps pl061_ops = {
    .read = pl061_read,
    .write = pl061_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pl061_initfn(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    PL061State *s = PL061(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    qdev_init_gpio_in(dev, pl061_set_irq, 8);
    qdev_init_gpio_out(dev, s->out, 8);
    pl061_reset(s);
    return 0;
}

static void pl061_luminary_init(Object *obj)
{
    PL061State *s = PL061(obj);

    s->id = pl061_id_luminary;
}

static void pl061_init(Object *obj)
{
    PL061State *s = PL061(obj);

    s->id = pl061_id;
}

static void pl061_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pl061_initfn;
    dc->vmsd = &vmstate_pl061;
}

static const TypeInfo pl061_info = {
    .name          = TYPE_PL061,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL061State),
    .instance_init = pl061_init,
    .class_init    = pl061_class_init,
};

static const TypeInfo pl061_luminary_info = {
    .name          = "pl061_luminary",
    .parent        = TYPE_PL061,
    .instance_init = pl061_luminary_init,
};

static void pl061_register_types(void)
{
    type_register_static(&pl061_info);
    type_register_static(&pl061_luminary_info);
}

type_init(pl061_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* Arm PrimeCell PL061 General Purpose IO with additional
	3	* Luminary Micro Stellaris bits.
	4	*
	5	* Copyright (c) 2007 CodeSourcery.
	6	* Written by Paul Brook
	7	*
8e31bf38	8	* This code is licensed under the GPL.
9ee6e8bb PB	9	*/
9ee6e8bb PB	10
83c9f4ca	11	#include "hw/sysbus.h"
9ee6e8bb PB	12
	13	//#define DEBUG_PL061 1
	14
	15	#ifdef DEBUG_PL061
001faf32 BS	16	#define DPRINTF(fmt, ...) \
	17	do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
	18	#define BADF(fmt, ...) \
	19	do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
9ee6e8bb	20	#else
001faf32 BS	21	#define DPRINTF(fmt, ...) do {} while(0)
	22	#define BADF(fmt, ...) \
	23	do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
9ee6e8bb PB	24	#endif
	25
	26	static const uint8_t pl061_id[12] =
7063f49f PM	27	{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
7063f49f PM	28	static const uint8_t pl061_id_luminary[12] =
9ee6e8bb PB	29	{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
9ee6e8bb PB	30
692a76d1 AF	31	#define TYPE_PL061 "pl061"
	32	#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
	33
ee663e96	34	typedef struct PL061State {
692a76d1 AF	35	SysBusDevice parent_obj;
692a76d1 AF	36
3cf89f8a	37	MemoryRegion iomem;
a35faa94 PM	38	uint32_t locked;
	39	uint32_t data;
	40	uint32_t old_data;
	41	uint32_t dir;
	42	uint32_t isense;
	43	uint32_t ibe;
	44	uint32_t iev;
	45	uint32_t im;
	46	uint32_t istate;
	47	uint32_t afsel;
	48	uint32_t dr2r;
	49	uint32_t dr4r;
	50	uint32_t dr8r;
	51	uint32_t odr;
	52	uint32_t pur;
	53	uint32_t pdr;
	54	uint32_t slr;
	55	uint32_t den;
	56	uint32_t cr;
	57	uint32_t float_high;
b3aaff11	58	uint32_t amsel;
9ee6e8bb PB	59	qemu_irq irq;
9ee6e8bb PB	60	qemu_irq out[8];
7063f49f	61	const unsigned char *id;
ee663e96	62	} PL061State;
9ee6e8bb	63
a35faa94 PM	64	static const VMStateDescription vmstate_pl061 = {
a35faa94 PM	65	.name = "pl061",
b3aaff11	66	.version_id = 2,
a35faa94 PM	67	.minimum_version_id = 1,
a35faa94 PM	68	.fields = (VMStateField[]) {
ee663e96 AF	69	VMSTATE_UINT32(locked, PL061State),
	70	VMSTATE_UINT32(data, PL061State),
	71	VMSTATE_UINT32(old_data, PL061State),
	72	VMSTATE_UINT32(dir, PL061State),
	73	VMSTATE_UINT32(isense, PL061State),
	74	VMSTATE_UINT32(ibe, PL061State),
	75	VMSTATE_UINT32(iev, PL061State),
	76	VMSTATE_UINT32(im, PL061State),
	77	VMSTATE_UINT32(istate, PL061State),
	78	VMSTATE_UINT32(afsel, PL061State),
	79	VMSTATE_UINT32(dr2r, PL061State),
	80	VMSTATE_UINT32(dr4r, PL061State),
	81	VMSTATE_UINT32(dr8r, PL061State),
	82	VMSTATE_UINT32(odr, PL061State),
	83	VMSTATE_UINT32(pur, PL061State),
	84	VMSTATE_UINT32(pdr, PL061State),
	85	VMSTATE_UINT32(slr, PL061State),
	86	VMSTATE_UINT32(den, PL061State),
	87	VMSTATE_UINT32(cr, PL061State),
	88	VMSTATE_UINT32(float_high, PL061State),
	89	VMSTATE_UINT32_V(amsel, PL061State, 2),
a35faa94 PM	90	VMSTATE_END_OF_LIST()
	91	}
	92	};
	93
ee663e96	94	static void pl061_update(PL061State *s)
9ee6e8bb PB	95	{
	96	uint8_t changed;
	97	uint8_t mask;
775616c3	98	uint8_t out;
9ee6e8bb PB	99	int i;
9ee6e8bb PB	100
775616c3 PB	101	/* Outputs float high. */
	102	/* FIXME: This is board dependent. */
	103	out = (s->data & s->dir) \| ~s->dir;
	104	changed = s->old_data ^ out;
9ee6e8bb PB	105	if (!changed)
	106	return;
	107
775616c3	108	s->old_data = out;
9ee6e8bb PB	109	for (i = 0; i < 8; i++) {
9ee6e8bb PB	110	mask = 1 << i;
b78c2b3a	111	if (changed & mask) {
775616c3 PB	112	DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
775616c3 PB	113	qemu_set_irq(s->out[i], (out & mask) != 0);
9ee6e8bb PB	114	}
	115	}
	116
	117	/* FIXME: Implement input interrupts. */
	118	}
	119
a8170e5e	120	static uint64_t pl061_read(void *opaque, hwaddr offset,
3cf89f8a	121	unsigned size)
9ee6e8bb	122	{
ee663e96	123	PL061State s = (PL061State )opaque;
9ee6e8bb	124
9ee6e8bb	125	if (offset >= 0xfd0 && offset < 0x1000) {
7063f49f	126	return s->id[(offset - 0xfd0) >> 2];
9ee6e8bb PB	127	}
	128	if (offset < 0x400) {
	129	return s->data & (offset >> 2);
	130	}
	131	switch (offset) {
	132	case 0x400: /* Direction */
	133	return s->dir;
	134	case 0x404: /* Interrupt sense */
	135	return s->isense;
	136	case 0x408: /* Interrupt both edges */
	137	return s->ibe;
ff2712ba	138	case 0x40c: /* Interrupt event */
9ee6e8bb PB	139	return s->iev;
	140	case 0x410: /* Interrupt mask */
	141	return s->im;
	142	case 0x414: /* Raw interrupt status */
	143	return s->istate;
	144	case 0x418: /* Masked interrupt status */
	145	return s->istate \| s->im;
	146	case 0x420: /* Alternate function select */
	147	return s->afsel;
	148	case 0x500: /* 2mA drive */
	149	return s->dr2r;
	150	case 0x504: /* 4mA drive */
	151	return s->dr4r;
	152	case 0x508: /* 8mA drive */
	153	return s->dr8r;
	154	case 0x50c: /* Open drain */
	155	return s->odr;
	156	case 0x510: /* Pull-up */
	157	return s->pur;
	158	case 0x514: /* Pull-down */
	159	return s->pdr;
	160	case 0x518: /* Slew rate control */
	161	return s->slr;
	162	case 0x51c: /* Digital enable */
	163	return s->den;
	164	case 0x520: /* Lock */
	165	return s->locked;
	166	case 0x524: /* Commit */
	167	return s->cr;
b3aaff11 PM	168	case 0x528: /* Analog mode select */
b3aaff11 PM	169	return s->amsel;
9ee6e8bb	170	default:
abff909c PM	171	qemu_log_mask(LOG_GUEST_ERROR,
abff909c PM	172	"pl061_read: Bad offset %x\n", (int)offset);
9ee6e8bb PB	173	return 0;
	174	}
	175	}
	176
a8170e5e	177	static void pl061_write(void *opaque, hwaddr offset,
3cf89f8a	178	uint64_t value, unsigned size)
9ee6e8bb	179	{
ee663e96	180	PL061State s = (PL061State )opaque;
9ee6e8bb PB	181	uint8_t mask;
9ee6e8bb PB	182
9ee6e8bb PB	183	if (offset < 0x400) {
	184	mask = (offset >> 2) & s->dir;
	185	s->data = (s->data & ~mask) \| (value & mask);
	186	pl061_update(s);
	187	return;
	188	}
	189	switch (offset) {
	190	case 0x400: /* Direction */
a35faa94	191	s->dir = value & 0xff;
9ee6e8bb PB	192	break;
9ee6e8bb PB	193	case 0x404: /* Interrupt sense */
a35faa94	194	s->isense = value & 0xff;
9ee6e8bb PB	195	break;
9ee6e8bb PB	196	case 0x408: /* Interrupt both edges */
a35faa94	197	s->ibe = value & 0xff;
9ee6e8bb	198	break;
ff2712ba	199	case 0x40c: /* Interrupt event */
a35faa94	200	s->iev = value & 0xff;
9ee6e8bb PB	201	break;
9ee6e8bb PB	202	case 0x410: /* Interrupt mask */
a35faa94	203	s->im = value & 0xff;
9ee6e8bb PB	204	break;
	205	case 0x41c: /* Interrupt clear */
	206	s->istate &= ~value;
	207	break;
	208	case 0x420: /* Alternate function select */
	209	mask = s->cr;
	210	s->afsel = (s->afsel & ~mask) \| (value & mask);
	211	break;
	212	case 0x500: /* 2mA drive */
a35faa94	213	s->dr2r = value & 0xff;
9ee6e8bb PB	214	break;
9ee6e8bb PB	215	case 0x504: /* 4mA drive */
a35faa94	216	s->dr4r = value & 0xff;
9ee6e8bb PB	217	break;
9ee6e8bb PB	218	case 0x508: /* 8mA drive */
a35faa94	219	s->dr8r = value & 0xff;
9ee6e8bb PB	220	break;
9ee6e8bb PB	221	case 0x50c: /* Open drain */
a35faa94	222	s->odr = value & 0xff;
9ee6e8bb PB	223	break;
9ee6e8bb PB	224	case 0x510: /* Pull-up */
a35faa94	225	s->pur = value & 0xff;
9ee6e8bb PB	226	break;
9ee6e8bb PB	227	case 0x514: /* Pull-down */
a35faa94	228	s->pdr = value & 0xff;
9ee6e8bb PB	229	break;
9ee6e8bb PB	230	case 0x518: /* Slew rate control */
a35faa94	231	s->slr = value & 0xff;
9ee6e8bb PB	232	break;
9ee6e8bb PB	233	case 0x51c: /* Digital enable */
a35faa94	234	s->den = value & 0xff;
9ee6e8bb PB	235	break;
	236	case 0x520: /* Lock */
	237	s->locked = (value != 0xacce551);
	238	break;
	239	case 0x524: /* Commit */
	240	if (!s->locked)
a35faa94	241	s->cr = value & 0xff;
9ee6e8bb	242	break;
b3aaff11 PM	243	case 0x528:
	244	s->amsel = value & 0xff;
	245	break;
9ee6e8bb	246	default:
abff909c PM	247	qemu_log_mask(LOG_GUEST_ERROR,
abff909c PM	248	"pl061_write: Bad offset %x\n", (int)offset);
9ee6e8bb PB	249	}
	250	pl061_update(s);
	251	}
	252
ee663e96	253	static void pl061_reset(PL061State *s)
9ee6e8bb PB	254	{
	255	s->locked = 1;
	256	s->cr = 0xff;
	257	}
	258
9596ebb7	259	static void pl061_set_irq(void * opaque, int irq, int level)
9ee6e8bb	260	{
ee663e96	261	PL061State s = (PL061State )opaque;
9ee6e8bb PB	262	uint8_t mask;
	263
	264	mask = 1 << irq;
	265	if ((s->dir & mask) == 0) {
	266	s->data &= ~mask;
	267	if (level)
	268	s->data \|= mask;
	269	pl061_update(s);
	270	}
	271	}
	272
3cf89f8a AK	273	static const MemoryRegionOps pl061_ops = {
	274	.read = pl061_read,
	275	.write = pl061_write,
	276	.endianness = DEVICE_NATIVE_ENDIAN,
9ee6e8bb PB	277	};
9ee6e8bb PB	278
692a76d1	279	static int pl061_initfn(SysBusDevice *sbd)
9ee6e8bb	280	{
692a76d1 AF	281	DeviceState *dev = DEVICE(sbd);
	282	PL061State *s = PL061(dev);
	283
b7163687	284	memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000);
692a76d1 AF	285	sysbus_init_mmio(sbd, &s->iomem);
	286	sysbus_init_irq(sbd, &s->irq);
	287	qdev_init_gpio_in(dev, pl061_set_irq, 8);
	288	qdev_init_gpio_out(dev, s->out, 8);
9ee6e8bb	289	pl061_reset(s);
81a322d4	290	return 0;
9ee6e8bb	291	}
40905a6a	292
692a76d1	293	static void pl061_luminary_init(Object *obj)
7063f49f	294	{
692a76d1 AF	295	PL061State *s = PL061(obj);
	296
	297	s->id = pl061_id_luminary;
7063f49f PM	298	}
7063f49f PM	299
692a76d1	300	static void pl061_init(Object *obj)
7063f49f	301	{
692a76d1 AF	302	PL061State *s = PL061(obj);
	303
	304	s->id = pl061_id;
7063f49f PM	305	}
7063f49f PM	306
999e12bb AL	307	static void pl061_class_init(ObjectClass klass, void data)
999e12bb AL	308	{
39bffca2	309	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	310	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
999e12bb AL	311
692a76d1	312	k->init = pl061_initfn;
39bffca2	313	dc->vmsd = &vmstate_pl061;
999e12bb AL	314	}
999e12bb AL	315
8c43a6f0	316	static const TypeInfo pl061_info = {
692a76d1	317	.name = TYPE_PL061,
39bffca2	318	.parent = TYPE_SYS_BUS_DEVICE,
ee663e96	319	.instance_size = sizeof(PL061State),
692a76d1	320	.instance_init = pl061_init,
39bffca2	321	.class_init = pl061_class_init,
a35faa94 PM	322	};
a35faa94 PM	323
8c43a6f0	324	static const TypeInfo pl061_luminary_info = {
39bffca2	325	.name = "pl061_luminary",
692a76d1 AF	326	.parent = TYPE_PL061,
692a76d1 AF	327	.instance_init = pl061_luminary_init,
a35faa94 PM	328	};
a35faa94 PM	329
83f7d43a	330	static void pl061_register_types(void)
40905a6a	331	{
39bffca2 AL	332	type_register_static(&pl061_info);
39bffca2 AL	333	type_register_static(&pl061_luminary_info);
40905a6a PB	334	}
40905a6a PB	335
83f7d43a	336	type_init(pl061_register_types)