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502a5395 | 1 | /* |
3cbee15b | 2 | * QEMU Grackle PCI host (heathrow OldWorld PowerMac) |
502a5395 | 3 | * |
3cbee15b JM |
4 | * Copyright (c) 2006-2007 Fabrice Bellard |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
5fafdf24 | 6 | * |
502a5395 PB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
426f17bb | 26 | #include "sysbus.h" |
3cbee15b | 27 | #include "ppc_mac.h" |
87ecb68b PB |
28 | #include "pci.h" |
29 | ||
ea026b2f BS |
30 | /* debug Grackle */ |
31 | //#define DEBUG_GRACKLE | |
32 | ||
33 | #ifdef DEBUG_GRACKLE | |
001faf32 BS |
34 | #define GRACKLE_DPRINTF(fmt, ...) \ |
35 | do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0) | |
ea026b2f | 36 | #else |
001faf32 | 37 | #define GRACKLE_DPRINTF(fmt, ...) |
ea026b2f BS |
38 | #endif |
39 | ||
502a5395 PB |
40 | typedef target_phys_addr_t pci_addr_t; |
41 | #include "pci_host.h" | |
42 | ||
426f17bb BS |
43 | typedef struct GrackleState { |
44 | SysBusDevice busdev; | |
45 | PCIHostState host_state; | |
46 | } GrackleState; | |
502a5395 PB |
47 | |
48 | static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, | |
49 | uint32_t val) | |
50 | { | |
51 | GrackleState *s = opaque; | |
ea026b2f BS |
52 | |
53 | GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, | |
54 | val); | |
502a5395 PB |
55 | #ifdef TARGET_WORDS_BIGENDIAN |
56 | val = bswap32(val); | |
57 | #endif | |
426f17bb | 58 | s->host_state.config_reg = val; |
502a5395 PB |
59 | } |
60 | ||
61 | static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) | |
62 | { | |
63 | GrackleState *s = opaque; | |
64 | uint32_t val; | |
65 | ||
426f17bb | 66 | val = s->host_state.config_reg; |
502a5395 PB |
67 | #ifdef TARGET_WORDS_BIGENDIAN |
68 | val = bswap32(val); | |
69 | #endif | |
ea026b2f BS |
70 | GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, |
71 | val); | |
502a5395 PB |
72 | return val; |
73 | } | |
74 | ||
d60efc6b | 75 | static CPUWriteMemoryFunc * const pci_grackle_config_write[] = { |
502a5395 PB |
76 | &pci_grackle_config_writel, |
77 | &pci_grackle_config_writel, | |
78 | &pci_grackle_config_writel, | |
79 | }; | |
80 | ||
d60efc6b | 81 | static CPUReadMemoryFunc * const pci_grackle_config_read[] = { |
502a5395 PB |
82 | &pci_grackle_config_readl, |
83 | &pci_grackle_config_readl, | |
84 | &pci_grackle_config_readl, | |
85 | }; | |
86 | ||
d60efc6b | 87 | static CPUWriteMemoryFunc * const pci_grackle_write[] = { |
502a5395 PB |
88 | &pci_host_data_writeb, |
89 | &pci_host_data_writew, | |
90 | &pci_host_data_writel, | |
91 | }; | |
92 | ||
d60efc6b | 93 | static CPUReadMemoryFunc * const pci_grackle_read[] = { |
502a5395 PB |
94 | &pci_host_data_readb, |
95 | &pci_host_data_readw, | |
96 | &pci_host_data_readl, | |
97 | }; | |
98 | ||
d2b59317 PB |
99 | /* Don't know if this matches real hardware, but it agrees with OHW. */ |
100 | static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) | |
502a5395 | 101 | { |
d2b59317 PB |
102 | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
103 | } | |
104 | ||
d537cf6c | 105 | static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) |
d2b59317 | 106 | { |
ea026b2f | 107 | GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level); |
3cbee15b | 108 | qemu_set_irq(pic[irq_num + 0x15], level); |
502a5395 PB |
109 | } |
110 | ||
9b64997f BS |
111 | static void pci_grackle_save(QEMUFile* f, void *opaque) |
112 | { | |
113 | PCIDevice *d = opaque; | |
114 | ||
115 | pci_device_save(d, f); | |
116 | } | |
117 | ||
118 | static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id) | |
119 | { | |
120 | PCIDevice *d = opaque; | |
121 | ||
122 | if (version_id != 1) | |
123 | return -EINVAL; | |
124 | ||
125 | return pci_device_load(d, f); | |
126 | } | |
127 | ||
6e6b7363 BS |
128 | static void pci_grackle_reset(void *opaque) |
129 | { | |
130 | } | |
131 | ||
d537cf6c | 132 | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) |
426f17bb BS |
133 | { |
134 | DeviceState *dev; | |
135 | SysBusDevice *s; | |
136 | GrackleState *d; | |
137 | ||
138 | dev = qdev_create(NULL, "grackle"); | |
139 | qdev_init(dev); | |
140 | s = sysbus_from_qdev(dev); | |
141 | d = FROM_SYSBUS(GrackleState, s); | |
142 | d->host_state.bus = pci_register_bus(NULL, "pci", | |
143 | pci_grackle_set_irq, | |
144 | pci_grackle_map_irq, | |
145 | pic, 0, 4); | |
146 | ||
147 | pci_create_simple(d->host_state.bus, 0, "grackle"); | |
148 | ||
149 | sysbus_mmio_map(s, 0, base); | |
150 | sysbus_mmio_map(s, 1, base + 0x00200000); | |
151 | ||
152 | return d->host_state.bus; | |
153 | } | |
154 | ||
155 | static void pci_grackle_init_device(SysBusDevice *dev) | |
156 | { | |
157 | GrackleState *s; | |
158 | int pci_mem_config, pci_mem_data; | |
159 | ||
160 | s = FROM_SYSBUS(GrackleState, dev); | |
161 | ||
162 | pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, | |
163 | pci_grackle_config_write, s); | |
164 | pci_mem_data = cpu_register_io_memory(pci_grackle_read, | |
165 | pci_grackle_write, | |
166 | &s->host_state); | |
167 | sysbus_init_mmio(dev, 0x1000, pci_mem_config); | |
168 | sysbus_init_mmio(dev, 0x1000, pci_mem_data); | |
169 | ||
170 | register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, | |
171 | &s->host_state); | |
172 | qemu_register_reset(pci_grackle_reset, &s->host_state); | |
173 | pci_grackle_reset(&s->host_state); | |
174 | } | |
175 | ||
176 | static void pci_dec_21154_init_device(SysBusDevice *dev) | |
502a5395 PB |
177 | { |
178 | GrackleState *s; | |
502a5395 PB |
179 | int pci_mem_config, pci_mem_data; |
180 | ||
426f17bb | 181 | s = FROM_SYSBUS(GrackleState, dev); |
502a5395 | 182 | |
1eed09cb | 183 | pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, |
502a5395 | 184 | pci_grackle_config_write, s); |
1eed09cb | 185 | pci_mem_data = cpu_register_io_memory(pci_grackle_read, |
426f17bb BS |
186 | pci_grackle_write, |
187 | &s->host_state); | |
188 | sysbus_init_mmio(dev, 0x1000, pci_mem_config); | |
189 | sysbus_init_mmio(dev, 0x1000, pci_mem_data); | |
190 | } | |
191 | ||
192 | static void grackle_pci_host_init(PCIDevice *d) | |
193 | { | |
deb54399 AL |
194 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); |
195 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106); | |
502a5395 PB |
196 | d->config[0x08] = 0x00; // revision |
197 | d->config[0x09] = 0x01; | |
173a543b | 198 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
6407f373 | 199 | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type |
426f17bb | 200 | } |
502a5395 | 201 | |
426f17bb BS |
202 | static void dec_21154_pci_host_init(PCIDevice *d) |
203 | { | |
502a5395 | 204 | /* PCI2PCI bridge same values as PearPC - check this */ |
4ebcf884 BS |
205 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC); |
206 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); | |
502a5395 | 207 | d->config[0x08] = 0x02; // revision |
173a543b | 208 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); |
6407f373 | 209 | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type |
502a5395 PB |
210 | |
211 | d->config[0x18] = 0x0; // primary_bus | |
212 | d->config[0x19] = 0x1; // secondary_bus | |
213 | d->config[0x1a] = 0x1; // subordinate_bus | |
214 | d->config[0x1c] = 0x10; // io_base | |
215 | d->config[0x1d] = 0x20; // io_limit | |
3b46e624 | 216 | |
502a5395 PB |
217 | d->config[0x20] = 0x80; // memory_base |
218 | d->config[0x21] = 0x80; | |
219 | d->config[0x22] = 0x90; // memory_limit | |
220 | d->config[0x23] = 0x80; | |
3b46e624 | 221 | |
502a5395 PB |
222 | d->config[0x24] = 0x00; // prefetchable_memory_base |
223 | d->config[0x25] = 0x84; | |
224 | d->config[0x26] = 0x00; // prefetchable_memory_limit | |
225 | d->config[0x27] = 0x85; | |
426f17bb BS |
226 | } |
227 | ||
228 | static PCIDeviceInfo grackle_pci_host_info = { | |
229 | .qdev.name = "grackle", | |
230 | .qdev.size = sizeof(PCIDevice), | |
231 | .init = grackle_pci_host_init, | |
232 | }; | |
6e6b7363 | 233 | |
426f17bb BS |
234 | static PCIDeviceInfo dec_21154_pci_host_info = { |
235 | .qdev.name = "DEC 21154", | |
236 | .qdev.size = sizeof(PCIDevice), | |
237 | .init = dec_21154_pci_host_init, | |
238 | }; | |
239 | ||
240 | static void grackle_register_devices(void) | |
241 | { | |
242 | sysbus_register_dev("grackle", sizeof(GrackleState), | |
243 | pci_grackle_init_device); | |
244 | pci_qdev_register(&grackle_pci_host_info); | |
245 | sysbus_register_dev("DEC 21154", sizeof(GrackleState), | |
246 | pci_dec_21154_init_device); | |
247 | pci_qdev_register(&dec_21154_pci_host_info); | |
502a5395 | 248 | } |
426f17bb BS |
249 | |
250 | device_init(grackle_register_devices) |