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Commit | Line | Data |
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502a5395 | 1 | /* |
3cbee15b | 2 | * QEMU Grackle PCI host (heathrow OldWorld PowerMac) |
502a5395 | 3 | * |
3cbee15b JM |
4 | * Copyright (c) 2006-2007 Fabrice Bellard |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
5fafdf24 | 6 | * |
502a5395 PB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include "vl.h" | |
3cbee15b | 27 | #include "ppc_mac.h" |
502a5395 PB |
28 | typedef target_phys_addr_t pci_addr_t; |
29 | #include "pci_host.h" | |
30 | ||
31 | typedef PCIHostState GrackleState; | |
32 | ||
33 | static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, | |
34 | uint32_t val) | |
35 | { | |
36 | GrackleState *s = opaque; | |
37 | #ifdef TARGET_WORDS_BIGENDIAN | |
38 | val = bswap32(val); | |
39 | #endif | |
40 | s->config_reg = val; | |
41 | } | |
42 | ||
43 | static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) | |
44 | { | |
45 | GrackleState *s = opaque; | |
46 | uint32_t val; | |
47 | ||
48 | val = s->config_reg; | |
49 | #ifdef TARGET_WORDS_BIGENDIAN | |
50 | val = bswap32(val); | |
51 | #endif | |
52 | return val; | |
53 | } | |
54 | ||
55 | static CPUWriteMemoryFunc *pci_grackle_config_write[] = { | |
56 | &pci_grackle_config_writel, | |
57 | &pci_grackle_config_writel, | |
58 | &pci_grackle_config_writel, | |
59 | }; | |
60 | ||
61 | static CPUReadMemoryFunc *pci_grackle_config_read[] = { | |
62 | &pci_grackle_config_readl, | |
63 | &pci_grackle_config_readl, | |
64 | &pci_grackle_config_readl, | |
65 | }; | |
66 | ||
67 | static CPUWriteMemoryFunc *pci_grackle_write[] = { | |
68 | &pci_host_data_writeb, | |
69 | &pci_host_data_writew, | |
70 | &pci_host_data_writel, | |
71 | }; | |
72 | ||
73 | static CPUReadMemoryFunc *pci_grackle_read[] = { | |
74 | &pci_host_data_readb, | |
75 | &pci_host_data_readw, | |
76 | &pci_host_data_readl, | |
77 | }; | |
78 | ||
d2b59317 PB |
79 | /* Don't know if this matches real hardware, but it agrees with OHW. */ |
80 | static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) | |
502a5395 | 81 | { |
d2b59317 PB |
82 | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
83 | } | |
84 | ||
d537cf6c | 85 | static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) |
d2b59317 | 86 | { |
3cbee15b | 87 | qemu_set_irq(pic[irq_num + 0x15], level); |
502a5395 PB |
88 | } |
89 | ||
d537cf6c | 90 | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) |
502a5395 PB |
91 | { |
92 | GrackleState *s; | |
93 | PCIDevice *d; | |
94 | int pci_mem_config, pci_mem_data; | |
95 | ||
96 | s = qemu_mallocz(sizeof(GrackleState)); | |
80b3ada7 | 97 | s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq, |
3cbee15b | 98 | pic, 0, 4); |
502a5395 | 99 | |
5fafdf24 | 100 | pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, |
502a5395 PB |
101 | pci_grackle_config_write, s); |
102 | pci_mem_data = cpu_register_io_memory(0, pci_grackle_read, | |
103 | pci_grackle_write, s); | |
104 | cpu_register_physical_memory(base, 0x1000, pci_mem_config); | |
105 | cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); | |
5fafdf24 | 106 | d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice), |
502a5395 PB |
107 | 0, NULL, NULL); |
108 | d->config[0x00] = 0x57; // vendor_id | |
109 | d->config[0x01] = 0x10; | |
110 | d->config[0x02] = 0x02; // device_id | |
111 | d->config[0x03] = 0x00; | |
112 | d->config[0x08] = 0x00; // revision | |
113 | d->config[0x09] = 0x01; | |
114 | d->config[0x0a] = 0x00; // class_sub = host | |
115 | d->config[0x0b] = 0x06; // class_base = PCI_bridge | |
116 | d->config[0x0e] = 0x00; // header_type | |
117 | ||
502a5395 PB |
118 | #if 0 |
119 | /* PCI2PCI bridge same values as PearPC - check this */ | |
120 | d->config[0x00] = 0x11; // vendor_id | |
121 | d->config[0x01] = 0x10; | |
122 | d->config[0x02] = 0x26; // device_id | |
123 | d->config[0x03] = 0x00; | |
124 | d->config[0x08] = 0x02; // revision | |
125 | d->config[0x0a] = 0x04; // class_sub = pci2pci | |
126 | d->config[0x0b] = 0x06; // class_base = PCI_bridge | |
127 | d->config[0x0e] = 0x01; // header_type | |
128 | ||
129 | d->config[0x18] = 0x0; // primary_bus | |
130 | d->config[0x19] = 0x1; // secondary_bus | |
131 | d->config[0x1a] = 0x1; // subordinate_bus | |
132 | d->config[0x1c] = 0x10; // io_base | |
133 | d->config[0x1d] = 0x20; // io_limit | |
3b46e624 | 134 | |
502a5395 PB |
135 | d->config[0x20] = 0x80; // memory_base |
136 | d->config[0x21] = 0x80; | |
137 | d->config[0x22] = 0x90; // memory_limit | |
138 | d->config[0x23] = 0x80; | |
3b46e624 | 139 | |
502a5395 PB |
140 | d->config[0x24] = 0x00; // prefetchable_memory_base |
141 | d->config[0x25] = 0x84; | |
142 | d->config[0x26] = 0x00; // prefetchable_memory_limit | |
143 | d->config[0x27] = 0x85; | |
144 | #endif | |
145 | return s->bus; | |
146 | } | |
147 |