[qemu.git] / hw / grackle_pci.c

/*
 * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
 *
 * Copyright (c) 2006-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "ppc_mac.h"
#include "pci.h"

/* debug Grackle */
//#define DEBUG_GRACKLE

#ifdef DEBUG_GRACKLE
#define GRACKLE_DPRINTF(fmt, ...)                               \
    do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0)
#else
#define GRACKLE_DPRINTF(fmt, ...)
#endif

typedef a_target_phys_addr a_pci_addr;
#include "pci_host.h"

typedef struct GrackleState {
    SysBusDevice busdev;
    PCIHostState host_state;
} GrackleState;

static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr,
                                       uint32_t val)
{
    GrackleState *s = opaque;

    GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
                    val);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    s->host_state.config_reg = val;
}

static uint32_t pci_grackle_config_readl (void *opaque, a_target_phys_addr addr)
{
    GrackleState *s = opaque;
    uint32_t val;

    val = s->host_state.config_reg;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
                    val);
    return val;
}

static CPUWriteMemoryFunc * const pci_grackle_config_write[] = {
    &pci_grackle_config_writel,
    &pci_grackle_config_writel,
    &pci_grackle_config_writel,
};

static CPUReadMemoryFunc * const pci_grackle_config_read[] = {
    &pci_grackle_config_readl,
    &pci_grackle_config_readl,
    &pci_grackle_config_readl,
};

static CPUWriteMemoryFunc * const pci_grackle_write[] = {
    &pci_host_data_writeb,
    &pci_host_data_writew,
    &pci_host_data_writel,
};

static CPUReadMemoryFunc * const pci_grackle_read[] = {
    &pci_host_data_readb,
    &pci_host_data_readw,
    &pci_host_data_readl,
};

/* Don't know if this matches real hardware, but it agrees with OHW.  */
static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return (irq_num + (pci_dev->devfn >> 3)) & 3;
}

static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
    qemu_set_irq(pic[irq_num + 0x15], level);
}

static void pci_grackle_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;

    pci_device_save(d, f);
}

static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;

    if (version_id != 1)
        return -EINVAL;

    return pci_device_load(d, f);
}

static void pci_grackle_reset(void *opaque)
{
}

PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    GrackleState *d;

    dev = qdev_create(NULL, "grackle");
    qdev_init(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(GrackleState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_grackle_set_irq,
                                         pci_grackle_map_irq,
                                         pic, 0, 4);

    pci_create_simple(d->host_state.bus, 0, "grackle");

    sysbus_mmio_map(s, 0, base);
    sysbus_mmio_map(s, 1, base + 0x00200000);

    return d->host_state.bus;
}

static int pci_grackle_init_device(SysBusDevice *dev)
{
    GrackleState *s;
    int pci_mem_config, pci_mem_data;

    s = FROM_SYSBUS(GrackleState, dev);

    pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
                                            pci_grackle_config_write, s);
    pci_mem_data = cpu_register_io_memory(pci_grackle_read,
                                          pci_grackle_write,
                                          &s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,
                    &s->host_state);
    qemu_register_reset(pci_grackle_reset, &s->host_state);
    pci_grackle_reset(&s->host_state);
    return 0;
}

static int pci_dec_21154_init_device(SysBusDevice *dev)
{
    GrackleState *s;
    int pci_mem_config, pci_mem_data;

    s = FROM_SYSBUS(GrackleState, dev);

    pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
                                            pci_grackle_config_write, s);
    pci_mem_data = cpu_register_io_memory(pci_grackle_read,
                                          pci_grackle_write,
                                          &s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int grackle_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
    d->config[0x08] = 0x00; // revision
    d->config[0x09] = 0x01;
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    return 0;
}

static int dec_21154_pci_host_init(PCIDevice *d)
{
    /* PCI2PCI bridge same values as PearPC - check this */
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
    d->config[0x08] = 0x02; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type

    d->config[0x18] = 0x0;  // primary_bus
    d->config[0x19] = 0x1;  // secondary_bus
    d->config[0x1a] = 0x1;  // subordinate_bus
    d->config[0x1c] = 0x10; // io_base
    d->config[0x1d] = 0x20; // io_limit

    d->config[0x20] = 0x80; // memory_base
    d->config[0x21] = 0x80;
    d->config[0x22] = 0x90; // memory_limit
    d->config[0x23] = 0x80;

    d->config[0x24] = 0x00; // prefetchable_memory_base
    d->config[0x25] = 0x84;
    d->config[0x26] = 0x00; // prefetchable_memory_limit
    d->config[0x27] = 0x85;
    return 0;
}

static PCIDeviceInfo grackle_pci_host_info = {
    .qdev.name = "grackle",
    .qdev.size = sizeof(PCIDevice),
    .init      = grackle_pci_host_init,
};

static PCIDeviceInfo dec_21154_pci_host_info = {
    .qdev.name = "DEC 21154",
    .qdev.size = sizeof(PCIDevice),
    .init      = dec_21154_pci_host_init,
};

static void grackle_register_devices(void)
{
    sysbus_register_dev("grackle", sizeof(GrackleState),
                        pci_grackle_init_device);
    pci_qdev_register(&grackle_pci_host_info);
    sysbus_register_dev("DEC 21154", sizeof(GrackleState),
                        pci_dec_21154_init_device);
    pci_qdev_register(&dec_21154_pci_host_info);
}

device_init(grackle_register_devices)
Commit	Line	Data
502a5395	1	/*
3cbee15b	2	* QEMU Grackle PCI host (heathrow OldWorld PowerMac)
502a5395	3	*
3cbee15b JM	4	* Copyright (c) 2006-2007 Fabrice Bellard
3cbee15b JM	5	* Copyright (c) 2007 Jocelyn Mayer
5fafdf24	6	*
502a5395 PB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
426f17bb	26	#include "sysbus.h"
3cbee15b	27	#include "ppc_mac.h"
87ecb68b PB	28	#include "pci.h"
87ecb68b PB	29
ea026b2f BS	30	/* debug Grackle */
	31	//#define DEBUG_GRACKLE
	32
	33	#ifdef DEBUG_GRACKLE
001faf32 BS	34	#define GRACKLE_DPRINTF(fmt, ...) \
001faf32 BS	35	do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0)
ea026b2f	36	#else
001faf32	37	#define GRACKLE_DPRINTF(fmt, ...)
ea026b2f BS	38	#endif
ea026b2f BS	39
99a0949b	40	typedef a_target_phys_addr a_pci_addr;
502a5395 PB	41	#include "pci_host.h"
502a5395 PB	42
426f17bb BS	43	typedef struct GrackleState {
	44	SysBusDevice busdev;
	45	PCIHostState host_state;
	46	} GrackleState;
502a5395	47
99a0949b	48	static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr,
502a5395 PB	49	uint32_t val)
	50	{
	51	GrackleState *s = opaque;
ea026b2f BS	52
	53	GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
	54	val);
502a5395 PB	55	#ifdef TARGET_WORDS_BIGENDIAN
	56	val = bswap32(val);
	57	#endif
426f17bb	58	s->host_state.config_reg = val;
502a5395 PB	59	}
502a5395 PB	60
99a0949b	61	static uint32_t pci_grackle_config_readl (void *opaque, a_target_phys_addr addr)
502a5395 PB	62	{
	63	GrackleState *s = opaque;
	64	uint32_t val;
	65
426f17bb	66	val = s->host_state.config_reg;
502a5395 PB	67	#ifdef TARGET_WORDS_BIGENDIAN
	68	val = bswap32(val);
	69	#endif
ea026b2f BS	70	GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
ea026b2f BS	71	val);
502a5395 PB	72	return val;
	73	}
	74
d60efc6b	75	static CPUWriteMemoryFunc * const pci_grackle_config_write[] = {
502a5395 PB	76	&pci_grackle_config_writel,
	77	&pci_grackle_config_writel,
	78	&pci_grackle_config_writel,
	79	};
	80
d60efc6b	81	static CPUReadMemoryFunc * const pci_grackle_config_read[] = {
502a5395 PB	82	&pci_grackle_config_readl,
	83	&pci_grackle_config_readl,
	84	&pci_grackle_config_readl,
	85	};
	86
d60efc6b	87	static CPUWriteMemoryFunc * const pci_grackle_write[] = {
502a5395 PB	88	&pci_host_data_writeb,
	89	&pci_host_data_writew,
	90	&pci_host_data_writel,
	91	};
	92
d60efc6b	93	static CPUReadMemoryFunc * const pci_grackle_read[] = {
502a5395 PB	94	&pci_host_data_readb,
	95	&pci_host_data_readw,
	96	&pci_host_data_readl,
	97	};
	98
d2b59317 PB	99	/* Don't know if this matches real hardware, but it agrees with OHW. */
d2b59317 PB	100	static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	101	{
d2b59317 PB	102	return (irq_num + (pci_dev->devfn >> 3)) & 3;
	103	}
	104
5d4e84c8	105	static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
d2b59317	106	{
5d4e84c8 JQ	107	qemu_irq *pic = opaque;
5d4e84c8 JQ	108
ea026b2f	109	GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
3cbee15b	110	qemu_set_irq(pic[irq_num + 0x15], level);
502a5395 PB	111	}
502a5395 PB	112
9b64997f BS	113	static void pci_grackle_save(QEMUFile* f, void *opaque)
	114	{
	115	PCIDevice *d = opaque;
	116
	117	pci_device_save(d, f);
	118	}
	119
	120	static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
	121	{
	122	PCIDevice *d = opaque;
	123
	124	if (version_id != 1)
	125	return -EINVAL;
	126
	127	return pci_device_load(d, f);
	128	}
	129
6e6b7363 BS	130	static void pci_grackle_reset(void *opaque)
	131	{
	132	}
	133
d537cf6c	134	PCIBus pci_grackle_init(uint32_t base, qemu_irq pic)
426f17bb BS	135	{
	136	DeviceState *dev;
	137	SysBusDevice *s;
	138	GrackleState *d;
	139
	140	dev = qdev_create(NULL, "grackle");
	141	qdev_init(dev);
	142	s = sysbus_from_qdev(dev);
	143	d = FROM_SYSBUS(GrackleState, s);
cdd0935c	144	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
426f17bb BS	145	pci_grackle_set_irq,
	146	pci_grackle_map_irq,
	147	pic, 0, 4);
	148
	149	pci_create_simple(d->host_state.bus, 0, "grackle");
	150
	151	sysbus_mmio_map(s, 0, base);
	152	sysbus_mmio_map(s, 1, base + 0x00200000);
	153
	154	return d->host_state.bus;
	155	}
	156
81a322d4	157	static int pci_grackle_init_device(SysBusDevice *dev)
426f17bb BS	158	{
	159	GrackleState *s;
	160	int pci_mem_config, pci_mem_data;
	161
	162	s = FROM_SYSBUS(GrackleState, dev);
	163
	164	pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
	165	pci_grackle_config_write, s);
	166	pci_mem_data = cpu_register_io_memory(pci_grackle_read,
	167	pci_grackle_write,
	168	&s->host_state);
	169	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	170	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	171
	172	register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,
	173	&s->host_state);
	174	qemu_register_reset(pci_grackle_reset, &s->host_state);
	175	pci_grackle_reset(&s->host_state);
81a322d4	176	return 0;
426f17bb BS	177	}
426f17bb BS	178
81a322d4	179	static int pci_dec_21154_init_device(SysBusDevice *dev)
502a5395 PB	180	{
502a5395 PB	181	GrackleState *s;
502a5395 PB	182	int pci_mem_config, pci_mem_data;
502a5395 PB	183
426f17bb	184	s = FROM_SYSBUS(GrackleState, dev);
502a5395	185
1eed09cb	186	pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
502a5395	187	pci_grackle_config_write, s);
1eed09cb	188	pci_mem_data = cpu_register_io_memory(pci_grackle_read,
426f17bb BS	189	pci_grackle_write,
	190	&s->host_state);
	191	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	192	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	193	return 0;
426f17bb BS	194	}
426f17bb BS	195
81a322d4	196	static int grackle_pci_host_init(PCIDevice *d)
426f17bb	197	{
deb54399 AL	198	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
deb54399 AL	199	pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
502a5395 PB	200	d->config[0x08] = 0x00; // revision
502a5395 PB	201	d->config[0x09] = 0x01;
173a543b	202	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
6407f373	203	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
81a322d4	204	return 0;
426f17bb	205	}
502a5395	206
81a322d4	207	static int dec_21154_pci_host_init(PCIDevice *d)
426f17bb	208	{
502a5395	209	/* PCI2PCI bridge same values as PearPC - check this */
4ebcf884 BS	210	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
4ebcf884 BS	211	pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
502a5395	212	d->config[0x08] = 0x02; // revision
173a543b	213	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
6407f373	214	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
502a5395 PB	215
	216	d->config[0x18] = 0x0; // primary_bus
	217	d->config[0x19] = 0x1; // secondary_bus
	218	d->config[0x1a] = 0x1; // subordinate_bus
	219	d->config[0x1c] = 0x10; // io_base
	220	d->config[0x1d] = 0x20; // io_limit
3b46e624	221
502a5395 PB	222	d->config[0x20] = 0x80; // memory_base
	223	d->config[0x21] = 0x80;
	224	d->config[0x22] = 0x90; // memory_limit
	225	d->config[0x23] = 0x80;
3b46e624	226
502a5395 PB	227	d->config[0x24] = 0x00; // prefetchable_memory_base
	228	d->config[0x25] = 0x84;
	229	d->config[0x26] = 0x00; // prefetchable_memory_limit
	230	d->config[0x27] = 0x85;
81a322d4	231	return 0;
426f17bb BS	232	}
	233
	234	static PCIDeviceInfo grackle_pci_host_info = {
	235	.qdev.name = "grackle",
	236	.qdev.size = sizeof(PCIDevice),
	237	.init = grackle_pci_host_init,
	238	};
6e6b7363	239
426f17bb BS	240	static PCIDeviceInfo dec_21154_pci_host_info = {
	241	.qdev.name = "DEC 21154",
	242	.qdev.size = sizeof(PCIDevice),
	243	.init = dec_21154_pci_host_init,
	244	};
	245
	246	static void grackle_register_devices(void)
	247	{
	248	sysbus_register_dev("grackle", sizeof(GrackleState),
	249	pci_grackle_init_device);
	250	pci_qdev_register(&grackle_pci_host_info);
	251	sysbus_register_dev("DEC 21154", sizeof(GrackleState),
	252	pci_dec_21154_init_device);
	253	pci_qdev_register(&dec_21154_pci_host_info);
502a5395	254	}
426f17bb BS	255
426f17bb BS	256	device_init(grackle_register_devices)