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502a5395 1/*
3cbee15b 2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
502a5395 3 *
3cbee15b
JM
4 * Copyright (c) 2006-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
5fafdf24 6 *
502a5395
PB
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
87ecb68b 26#include "hw.h"
3cbee15b 27#include "ppc_mac.h"
87ecb68b
PB
28#include "pci.h"
29
ea026b2f
BS
30/* debug Grackle */
31//#define DEBUG_GRACKLE
32
33#ifdef DEBUG_GRACKLE
34#define GRACKLE_DPRINTF(fmt, args...) \
35do { printf("GRACKLE: " fmt , ##args); } while (0)
36#else
37#define GRACKLE_DPRINTF(fmt, args...)
38#endif
39
502a5395
PB
40typedef target_phys_addr_t pci_addr_t;
41#include "pci_host.h"
42
43typedef PCIHostState GrackleState;
44
45static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
46 uint32_t val)
47{
48 GrackleState *s = opaque;
ea026b2f
BS
49
50 GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
51 val);
502a5395
PB
52#ifdef TARGET_WORDS_BIGENDIAN
53 val = bswap32(val);
54#endif
55 s->config_reg = val;
56}
57
58static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
59{
60 GrackleState *s = opaque;
61 uint32_t val;
62
63 val = s->config_reg;
64#ifdef TARGET_WORDS_BIGENDIAN
65 val = bswap32(val);
66#endif
ea026b2f
BS
67 GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
68 val);
502a5395
PB
69 return val;
70}
71
72static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
73 &pci_grackle_config_writel,
74 &pci_grackle_config_writel,
75 &pci_grackle_config_writel,
76};
77
78static CPUReadMemoryFunc *pci_grackle_config_read[] = {
79 &pci_grackle_config_readl,
80 &pci_grackle_config_readl,
81 &pci_grackle_config_readl,
82};
83
84static CPUWriteMemoryFunc *pci_grackle_write[] = {
85 &pci_host_data_writeb,
86 &pci_host_data_writew,
87 &pci_host_data_writel,
88};
89
90static CPUReadMemoryFunc *pci_grackle_read[] = {
91 &pci_host_data_readb,
92 &pci_host_data_readw,
93 &pci_host_data_readl,
94};
95
d2b59317
PB
96/* Don't know if this matches real hardware, but it agrees with OHW. */
97static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395 98{
d2b59317
PB
99 return (irq_num + (pci_dev->devfn >> 3)) & 3;
100}
101
d537cf6c 102static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
d2b59317 103{
ea026b2f 104 GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
3cbee15b 105 qemu_set_irq(pic[irq_num + 0x15], level);
502a5395
PB
106}
107
d537cf6c 108PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
502a5395
PB
109{
110 GrackleState *s;
111 PCIDevice *d;
112 int pci_mem_config, pci_mem_data;
113
114 s = qemu_mallocz(sizeof(GrackleState));
80b3ada7 115 s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq,
3cbee15b 116 pic, 0, 4);
502a5395 117
5fafdf24 118 pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
502a5395
PB
119 pci_grackle_config_write, s);
120 pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
121 pci_grackle_write, s);
122 cpu_register_physical_memory(base, 0x1000, pci_mem_config);
123 cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
5fafdf24 124 d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
502a5395
PB
125 0, NULL, NULL);
126 d->config[0x00] = 0x57; // vendor_id
127 d->config[0x01] = 0x10;
128 d->config[0x02] = 0x02; // device_id
129 d->config[0x03] = 0x00;
130 d->config[0x08] = 0x00; // revision
131 d->config[0x09] = 0x01;
132 d->config[0x0a] = 0x00; // class_sub = host
133 d->config[0x0b] = 0x06; // class_base = PCI_bridge
134 d->config[0x0e] = 0x00; // header_type
135
502a5395
PB
136#if 0
137 /* PCI2PCI bridge same values as PearPC - check this */
138 d->config[0x00] = 0x11; // vendor_id
139 d->config[0x01] = 0x10;
140 d->config[0x02] = 0x26; // device_id
141 d->config[0x03] = 0x00;
142 d->config[0x08] = 0x02; // revision
143 d->config[0x0a] = 0x04; // class_sub = pci2pci
144 d->config[0x0b] = 0x06; // class_base = PCI_bridge
145 d->config[0x0e] = 0x01; // header_type
146
147 d->config[0x18] = 0x0; // primary_bus
148 d->config[0x19] = 0x1; // secondary_bus
149 d->config[0x1a] = 0x1; // subordinate_bus
150 d->config[0x1c] = 0x10; // io_base
151 d->config[0x1d] = 0x20; // io_limit
3b46e624 152
502a5395
PB
153 d->config[0x20] = 0x80; // memory_base
154 d->config[0x21] = 0x80;
155 d->config[0x22] = 0x90; // memory_limit
156 d->config[0x23] = 0x80;
3b46e624 157
502a5395
PB
158 d->config[0x24] = 0x00; // prefetchable_memory_base
159 d->config[0x25] = 0x84;
160 d->config[0x26] = 0x00; // prefetchable_memory_limit
161 d->config[0x27] = 0x85;
162#endif
163 return s->bus;
164}