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[qemu.git] / hw / gt64xxx.c
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fde7d5bd
TS		 1/*
2 * QEMU GT64120 PCI host
3 *
4de9b249 4 * Copyright (c) 2006,2007 Aurelien Jarno
5fafdf24 5 *
fde7d5bd
TS		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
87ecb68b
PB		 25#include "hw.h"
26#include "mips.h"
27#include "pci.h"
fde7d5bd 28#include "pci_host.h"
4f5e19e6 29#include "pc.h"
fde7d5bd 30
05b4ff43
TS		 31//#define DEBUG
32
33#ifdef DEBUG
d0f2c4c6 34#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
05b4ff43 35#else
d0f2c4c6 36#define DPRINTF(fmt, ...)
05b4ff43
TS		 37#endif
38
fde7d5bd
TS		 39#define GT_REGS (0x1000 >> 2)
40
41/* CPU Configuration */
42#define GT_CPU (0x000 >> 2)
43#define GT_MULTI (0x120 >> 2)
44
45/* CPU Address Decode */
46#define GT_SCS10LD (0x008 >> 2)
47#define GT_SCS10HD (0x010 >> 2)
48#define GT_SCS32LD (0x018 >> 2)
49#define GT_SCS32HD (0x020 >> 2)
50#define GT_CS20LD (0x028 >> 2)
51#define GT_CS20HD (0x030 >> 2)
52#define GT_CS3BOOTLD (0x038 >> 2)
53#define GT_CS3BOOTHD (0x040 >> 2)
54#define GT_PCI0IOLD (0x048 >> 2)
55#define GT_PCI0IOHD (0x050 >> 2)
56#define GT_PCI0M0LD (0x058 >> 2)
57#define GT_PCI0M0HD (0x060 >> 2)
fde7d5bd
TS		 58#define GT_PCI0M1LD (0x080 >> 2)
59#define GT_PCI0M1HD (0x088 >> 2)
60#define GT_PCI1IOLD (0x090 >> 2)
61#define GT_PCI1IOHD (0x098 >> 2)
62#define GT_PCI1M0LD (0x0a0 >> 2)
63#define GT_PCI1M0HD (0x0a8 >> 2)
64#define GT_PCI1M1LD (0x0b0 >> 2)
65#define GT_PCI1M1HD (0x0b8 >> 2)
05b4ff43 66#define GT_ISD (0x068 >> 2)
fde7d5bd
TS		 67
68#define GT_SCS10AR (0x0d0 >> 2)
69#define GT_SCS32AR (0x0d8 >> 2)
70#define GT_CS20R (0x0e0 >> 2)
71#define GT_CS3BOOTR (0x0e8 >> 2)
72
73#define GT_PCI0IOREMAP (0x0f0 >> 2)
74#define GT_PCI0M0REMAP (0x0f8 >> 2)
75#define GT_PCI0M1REMAP (0x100 >> 2)
76#define GT_PCI1IOREMAP (0x108 >> 2)
77#define GT_PCI1M0REMAP (0x110 >> 2)
78#define GT_PCI1M1REMAP (0x118 >> 2)
79
80/* CPU Error Report */
81#define GT_CPUERR_ADDRLO (0x070 >> 2)
82#define GT_CPUERR_ADDRHI (0x078 >> 2)
83#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
84#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
85#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
86
87/* CPU Sync Barrier */
88#define GT_PCI0SYNC (0x0c0 >> 2)
89#define GT_PCI1SYNC (0x0c8 >> 2)
90
91/* SDRAM and Device Address Decode */
92#define GT_SCS0LD (0x400 >> 2)
93#define GT_SCS0HD (0x404 >> 2)
94#define GT_SCS1LD (0x408 >> 2)
95#define GT_SCS1HD (0x40c >> 2)
96#define GT_SCS2LD (0x410 >> 2)
97#define GT_SCS2HD (0x414 >> 2)
98#define GT_SCS3LD (0x418 >> 2)
99#define GT_SCS3HD (0x41c >> 2)
100#define GT_CS0LD (0x420 >> 2)
101#define GT_CS0HD (0x424 >> 2)
102#define GT_CS1LD (0x428 >> 2)
103#define GT_CS1HD (0x42c >> 2)
104#define GT_CS2LD (0x430 >> 2)
105#define GT_CS2HD (0x434 >> 2)
106#define GT_CS3LD (0x438 >> 2)
107#define GT_CS3HD (0x43c >> 2)
108#define GT_BOOTLD (0x440 >> 2)
109#define GT_BOOTHD (0x444 >> 2)
110#define GT_ADERR (0x470 >> 2)
111
112/* SDRAM Configuration */
113#define GT_SDRAM_CFG (0x448 >> 2)
114#define GT_SDRAM_OPMODE (0x474 >> 2)
115#define GT_SDRAM_BM (0x478 >> 2)
116#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
117
118/* SDRAM Parameters */
119#define GT_SDRAM_B0 (0x44c >> 2)
120#define GT_SDRAM_B1 (0x450 >> 2)
121#define GT_SDRAM_B2 (0x454 >> 2)
122#define GT_SDRAM_B3 (0x458 >> 2)
123
124/* Device Parameters */
125#define GT_DEV_B0 (0x45c >> 2)
126#define GT_DEV_B1 (0x460 >> 2)
127#define GT_DEV_B2 (0x464 >> 2)
128#define GT_DEV_B3 (0x468 >> 2)
129#define GT_DEV_BOOT (0x46c >> 2)
130
131/* ECC */
132#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
133#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
134#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
135#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
136#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
137
138/* DMA Record */
139#define GT_DMA0_CNT (0x800 >> 2)
140#define GT_DMA1_CNT (0x804 >> 2)
141#define GT_DMA2_CNT (0x808 >> 2)
142#define GT_DMA3_CNT (0x80c >> 2)
143#define GT_DMA0_SA (0x810 >> 2)
144#define GT_DMA1_SA (0x814 >> 2)
145#define GT_DMA2_SA (0x818 >> 2)
146#define GT_DMA3_SA (0x81c >> 2)
147#define GT_DMA0_DA (0x820 >> 2)
148#define GT_DMA1_DA (0x824 >> 2)
149#define GT_DMA2_DA (0x828 >> 2)
150#define GT_DMA3_DA (0x82c >> 2)
151#define GT_DMA0_NEXT (0x830 >> 2)
152#define GT_DMA1_NEXT (0x834 >> 2)
153#define GT_DMA2_NEXT (0x838 >> 2)
154#define GT_DMA3_NEXT (0x83c >> 2)
155#define GT_DMA0_CUR (0x870 >> 2)
156#define GT_DMA1_CUR (0x874 >> 2)
157#define GT_DMA2_CUR (0x878 >> 2)
158#define GT_DMA3_CUR (0x87c >> 2)
159
160/* DMA Channel Control */
161#define GT_DMA0_CTRL (0x840 >> 2)
162#define GT_DMA1_CTRL (0x844 >> 2)
163#define GT_DMA2_CTRL (0x848 >> 2)
164#define GT_DMA3_CTRL (0x84c >> 2)
165
166/* DMA Arbiter */
167#define GT_DMA_ARB (0x860 >> 2)
168
169/* Timer/Counter */
170#define GT_TC0 (0x850 >> 2)
171#define GT_TC1 (0x854 >> 2)
172#define GT_TC2 (0x858 >> 2)
173#define GT_TC3 (0x85c >> 2)
174#define GT_TC_CONTROL (0x864 >> 2)
175
176/* PCI Internal */
177#define GT_PCI0_CMD (0xc00 >> 2)
178#define GT_PCI0_TOR (0xc04 >> 2)
179#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
180#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
181#define GT_PCI0_BS_CS20 (0xc10 >> 2)
182#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
183#define GT_PCI1_IACK (0xc30 >> 2)
184#define GT_PCI0_IACK (0xc34 >> 2)
185#define GT_PCI0_BARE (0xc3c >> 2)
186#define GT_PCI0_PREFMBR (0xc40 >> 2)
187#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
188#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
189#define GT_PCI0_CS20_BAR (0xc50 >> 2)
190#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
191#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
192#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
193#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
194#define GT_PCI1_CMD (0xc80 >> 2)
195#define GT_PCI1_TOR (0xc84 >> 2)
196#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
197#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
198#define GT_PCI1_BS_CS20 (0xc90 >> 2)
199#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
200#define GT_PCI1_BARE (0xcbc >> 2)
201#define GT_PCI1_PREFMBR (0xcc0 >> 2)
202#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
203#define GT_PCI1_SCS32_BAR (0xccc >> 2)
204#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
205#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
206#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
207#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
208#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
209#define GT_PCI1_CFGADDR (0xcf0 >> 2)
210#define GT_PCI1_CFGDATA (0xcf4 >> 2)
211#define GT_PCI0_CFGADDR (0xcf8 >> 2)
212#define GT_PCI0_CFGDATA (0xcfc >> 2)
213
214/* Interrupts */
215#define GT_INTRCAUSE (0xc18 >> 2)
216#define GT_INTRMASK (0xc1c >> 2)
217#define GT_PCI0_ICMASK (0xc24 >> 2)
218#define GT_PCI0_SERR0MASK (0xc28 >> 2)
219#define GT_CPU_INTSEL (0xc70 >> 2)
220#define GT_PCI0_INTSEL (0xc74 >> 2)
221#define GT_HINTRCAUSE (0xc98 >> 2)
222#define GT_HINTRMASK (0xc9c >> 2)
223#define GT_PCI0_HICMASK (0xca4 >> 2)
224#define GT_PCI1_SERR1MASK (0xca8 >> 2)
225
a0a8793e 226#define PCI_MAPPING_ENTRY(regname) \
c227f099
AL		 227 target_phys_addr_t regname ##_start; \
228 target_phys_addr_t regname ##_length; \
a0a8793e
TS		 229 int regname ##_handle
230
fde7d5bd 231typedef struct GT64120State {
c2dd2a23
AJ		 232 SysBusDevice busdev;
233 PCIHostState pci;
fde7d5bd 234 uint32_t regs[GT_REGS];
a0a8793e
TS		 235 PCI_MAPPING_ENTRY(PCI0IO);
236 PCI_MAPPING_ENTRY(ISD);
fde7d5bd
TS		 237} GT64120State;
238
a0a8793e
TS		 239/* Adjust range to avoid touching space which isn't mappable via PCI */
240/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
241 0x1fc00000 - 0x1fd00000 */
c227f099
AL		 242static void check_reserved_space (target_phys_addr_t *start,
243 target_phys_addr_t *length)
a0a8793e 244{
c227f099
AL		 245 target_phys_addr_t begin = *start;
246 target_phys_addr_t end = *start + *length;
a0a8793e
TS		 247
248 if (end >= 0x1e000000LL && end < 0x1f100000LL)
249 end = 0x1e000000LL;
250 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
251 begin = 0x1f100000LL;
252 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
253 end = 0x1fc00000LL;
254 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
255 begin = 0x1fd00000LL;
256 /* XXX: This is broken when a reserved range splits the requested range */
257 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
258 end = 0x1e000000LL;
259 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
260 end = 0x1fc00000LL;
261
262 *start = begin;
263 *length = end - begin;
264}
265
266static void gt64120_isd_mapping(GT64120State *s)
267{
c227f099
AL		 268 target_phys_addr_t start = s->regs[GT_ISD] << 21;
269 target_phys_addr_t length = 0x1000;
a0a8793e
TS		 270
271 if (s->ISD_length)
272 cpu_register_physical_memory(s->ISD_start, s->ISD_length,
273 IO_MEM_UNASSIGNED);
274 check_reserved_space(&start, &length);
275 length = 0x1000;
276 /* Map new address */
82f24fcc 277 DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx" -> "TARGET_FMT_plx"@"TARGET_FMT_plx", %x\n", s->ISD_length, s->ISD_start,
a0a8793e
TS		 278 length, start, s->ISD_handle);
279 s->ISD_start = start;
280 s->ISD_length = length;
281 cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
282}
283
9414cc6f 284static void gt64120_pci_mapping(GT64120State *s)
2a1086d9 285{
9414cc6f
TS		 286 /* Update IO mapping */
287 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
288 {
3b46e624 289 /* Unmap old IO address */
9414cc6f
TS		 290 if (s->PCI0IO_length)
291 {
3b46e624 292 cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
9414cc6f
TS		 293 }
294 /* Map new IO address */
295 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
296 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
297 isa_mem_base = s->PCI0IO_start;
968d683c 298 isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
9414cc6f 299 }
2a1086d9
TS		 300}
301
c227f099 302static void gt64120_writel (void *opaque, target_phys_addr_t addr,
fde7d5bd
TS		 303 uint32_t val)
304{
305 GT64120State *s = opaque;
306 uint32_t saddr;
307
c6c99c3f 308 if (!(s->regs[GT_CPU] & 0x00001000))
1931e260 309 val = bswap32(val);
0da75eb1 310
fde7d5bd
TS		 311 saddr = (addr & 0xfff) >> 2;
312 switch (saddr) {
0da75eb1
TS		 313
314 /* CPU Configuration */
fde7d5bd
TS		 315 case GT_CPU:
316 s->regs[GT_CPU] = val;
fde7d5bd
TS		 317 break;
318 case GT_MULTI:
0da75eb1 319 /* Read-only register as only one GT64xxx is present on the CPU bus */
fde7d5bd
TS		 320 break;
321
322 /* CPU Address Decode */
323 case GT_PCI0IOLD:
324 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
325 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
9414cc6f 326 gt64120_pci_mapping(s);
fde7d5bd
TS		 327 break;
328 case GT_PCI0M0LD:
329 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
330 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
fde7d5bd
TS		 331 break;
332 case GT_PCI0M1LD:
333 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
334 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
fde7d5bd
TS		 335 break;
336 case GT_PCI1IOLD:
337 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
338 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
fde7d5bd
TS		 339 break;
340 case GT_PCI1M0LD:
341 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
342 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
fde7d5bd
TS		 343 break;
344 case GT_PCI1M1LD:
345 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
346 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
fde7d5bd
TS		 347 break;
348 case GT_PCI0IOHD:
bb433bef
TS		 349 s->regs[saddr] = val & 0x0000007f;
350 gt64120_pci_mapping(s);
351 break;
fde7d5bd
TS		 352 case GT_PCI0M0HD:
353 case GT_PCI0M1HD:
354 case GT_PCI1IOHD:
355 case GT_PCI1M0HD:
356 case GT_PCI1M1HD:
357 s->regs[saddr] = val & 0x0000007f;
fde7d5bd 358 break;
a0a8793e
TS		 359 case GT_ISD:
360 s->regs[saddr] = val & 0x00007fff;
361 gt64120_isd_mapping(s);
362 break;
363
fde7d5bd
TS		 364 case GT_PCI0IOREMAP:
365 case GT_PCI0M0REMAP:
366 case GT_PCI0M1REMAP:
367 case GT_PCI1IOREMAP:
368 case GT_PCI1M0REMAP:
369 case GT_PCI1M1REMAP:
370 s->regs[saddr] = val & 0x000007ff;
fde7d5bd
TS		 371 break;
372
373 /* CPU Error Report */
374 case GT_CPUERR_ADDRLO:
375 case GT_CPUERR_ADDRHI:
376 case GT_CPUERR_DATALO:
377 case GT_CPUERR_DATAHI:
378 case GT_CPUERR_PARITY:
0da75eb1
TS		 379 /* Read-only registers, do nothing */
380 break;
381
382 /* CPU Sync Barrier */
383 case GT_PCI0SYNC:
384 case GT_PCI1SYNC:
385 /* Read-only registers, do nothing */
fde7d5bd
TS		 386 break;
387
05b4ff43
TS		 388 /* SDRAM and Device Address Decode */
389 case GT_SCS0LD:
390 case GT_SCS0HD:
391 case GT_SCS1LD:
392 case GT_SCS1HD:
393 case GT_SCS2LD:
394 case GT_SCS2HD:
395 case GT_SCS3LD:
396 case GT_SCS3HD:
397 case GT_CS0LD:
398 case GT_CS0HD:
399 case GT_CS1LD:
400 case GT_CS1HD:
401 case GT_CS2LD:
402 case GT_CS2HD:
403 case GT_CS3LD:
404 case GT_CS3HD:
405 case GT_BOOTLD:
406 case GT_BOOTHD:
407 case GT_ADERR:
408 /* SDRAM Configuration */
409 case GT_SDRAM_CFG:
410 case GT_SDRAM_OPMODE:
411 case GT_SDRAM_BM:
412 case GT_SDRAM_ADDRDECODE:
413 /* Accept and ignore SDRAM interleave configuration */
414 s->regs[saddr] = val;
415 break;
416
417 /* Device Parameters */
418 case GT_DEV_B0:
419 case GT_DEV_B1:
420 case GT_DEV_B2:
421 case GT_DEV_B3:
422 case GT_DEV_BOOT:
423 /* Not implemented */
d0f2c4c6 424 DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
05b4ff43
TS		 425 break;
426
fde7d5bd
TS		 427 /* ECC */
428 case GT_ECC_ERRDATALO:
429 case GT_ECC_ERRDATAHI:
430 case GT_ECC_MEM:
431 case GT_ECC_CALC:
432 case GT_ECC_ERRADDR:
0da75eb1 433 /* Read-only registers, do nothing */
fde7d5bd
TS		 434 break;
435
05b4ff43
TS		 436 /* DMA Record */
437 case GT_DMA0_CNT:
438 case GT_DMA1_CNT:
439 case GT_DMA2_CNT:
440 case GT_DMA3_CNT:
441 case GT_DMA0_SA:
442 case GT_DMA1_SA:
443 case GT_DMA2_SA:
444 case GT_DMA3_SA:
445 case GT_DMA0_DA:
446 case GT_DMA1_DA:
447 case GT_DMA2_DA:
448 case GT_DMA3_DA:
449 case GT_DMA0_NEXT:
450 case GT_DMA1_NEXT:
451 case GT_DMA2_NEXT:
452 case GT_DMA3_NEXT:
453 case GT_DMA0_CUR:
454 case GT_DMA1_CUR:
455 case GT_DMA2_CUR:
456 case GT_DMA3_CUR:
457 /* Not implemented */
d0f2c4c6 458 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
05b4ff43
TS		 459 break;
460
461 /* DMA Channel Control */
462 case GT_DMA0_CTRL:
463 case GT_DMA1_CTRL:
464 case GT_DMA2_CTRL:
465 case GT_DMA3_CTRL:
466 /* Not implemented */
d0f2c4c6 467 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
05b4ff43
TS		 468 break;
469
470 /* DMA Arbiter */
471 case GT_DMA_ARB:
472 /* Not implemented */
d0f2c4c6 473 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
05b4ff43
TS		 474 break;
475
476 /* Timer/Counter */
477 case GT_TC0:
478 case GT_TC1:
479 case GT_TC2:
480 case GT_TC3:
481 case GT_TC_CONTROL:
482 /* Not implemented */
d0f2c4c6 483 DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
05b4ff43
TS		 484 break;
485
fde7d5bd
TS		 486 /* PCI Internal */
487 case GT_PCI0_CMD:
488 case GT_PCI1_CMD:
489 s->regs[saddr] = val & 0x0401fc0f;
490 break;
05b4ff43
TS		 491 case GT_PCI0_TOR:
492 case GT_PCI0_BS_SCS10:
493 case GT_PCI0_BS_SCS32:
494 case GT_PCI0_BS_CS20:
495 case GT_PCI0_BS_CS3BT:
496 case GT_PCI1_IACK:
497 case GT_PCI0_IACK:
498 case GT_PCI0_BARE:
499 case GT_PCI0_PREFMBR:
500 case GT_PCI0_SCS10_BAR:
501 case GT_PCI0_SCS32_BAR:
502 case GT_PCI0_CS20_BAR:
503 case GT_PCI0_CS3BT_BAR:
504 case GT_PCI0_SSCS10_BAR:
505 case GT_PCI0_SSCS32_BAR:
506 case GT_PCI0_SCS3BT_BAR:
507 case GT_PCI1_TOR:
508 case GT_PCI1_BS_SCS10:
509 case GT_PCI1_BS_SCS32:
510 case GT_PCI1_BS_CS20:
511 case GT_PCI1_BS_CS3BT:
512 case GT_PCI1_BARE:
513 case GT_PCI1_PREFMBR:
514 case GT_PCI1_SCS10_BAR:
515 case GT_PCI1_SCS32_BAR:
516 case GT_PCI1_CS20_BAR:
517 case GT_PCI1_CS3BT_BAR:
518 case GT_PCI1_SSCS10_BAR:
519 case GT_PCI1_SSCS32_BAR:
520 case GT_PCI1_SCS3BT_BAR:
521 case GT_PCI1_CFGADDR:
522 case GT_PCI1_CFGDATA:
523 /* not implemented */
524 break;
fde7d5bd 525 case GT_PCI0_CFGADDR:
c2dd2a23 526 s->pci.config_reg = val & 0x80fffffc;
fde7d5bd
TS		 527 break;
528 case GT_PCI0_CFGDATA:
c2dd2a23 529 if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
c6c99c3f 530 val = bswap32(val);
c2dd2a23
AJ		 531 if (s->pci.config_reg & (1u << 31))
532 pci_data_write(s->pci.bus, s->pci.config_reg, val, 4);
05b4ff43
TS		 533 break;
534
535 /* Interrupts */
536 case GT_INTRCAUSE:
537 /* not really implemented */
538 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
539 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
d0f2c4c6 540 DPRINTF("INTRCAUSE %x\n", val);
05b4ff43
TS		 541 break;
542 case GT_INTRMASK:
543 s->regs[saddr] = val & 0x3c3ffffe;
d0f2c4c6 544 DPRINTF("INTRMASK %x\n", val);
05b4ff43
TS		 545 break;
546 case GT_PCI0_ICMASK:
547 s->regs[saddr] = val & 0x03fffffe;
d0f2c4c6 548 DPRINTF("ICMASK %x\n", val);
05b4ff43
TS		 549 break;
550 case GT_PCI0_SERR0MASK:
551 s->regs[saddr] = val & 0x0000003f;
d0f2c4c6 552 DPRINTF("SERR0MASK %x\n", val);
05b4ff43
TS		 553 break;
554
555 /* Reserved when only PCI_0 is configured. */
556 case GT_HINTRCAUSE:
557 case GT_CPU_INTSEL:
558 case GT_PCI0_INTSEL:
559 case GT_HINTRMASK:
560 case GT_PCI0_HICMASK:
561 case GT_PCI1_SERR1MASK:
562 /* not implemented */
fde7d5bd
TS		 563 break;
564
0da75eb1
TS		 565 /* SDRAM Parameters */
566 case GT_SDRAM_B0:
567 case GT_SDRAM_B1:
568 case GT_SDRAM_B2:
569 case GT_SDRAM_B3:
570 /* We don't simulate electrical parameters of the SDRAM.
571 Accept, but ignore the values. */
572 s->regs[saddr] = val;
573 break;
574
fde7d5bd 575 default:
d0f2c4c6 576 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 577 break;
578 }
579}
580
581static uint32_t gt64120_readl (void *opaque,
c227f099 582 target_phys_addr_t addr)
fde7d5bd
TS		 583{
584 GT64120State *s = opaque;
585 uint32_t val;
586 uint32_t saddr;
587
fde7d5bd 588 saddr = (addr & 0xfff) >> 2;
fde7d5bd
TS		 589 switch (saddr) {
590
0da75eb1
TS		 591 /* CPU Configuration */
592 case GT_MULTI:
593 /* Only one GT64xxx is present on the CPU bus, return
594 the initial value */
595 val = s->regs[saddr];
596 break;
597
fde7d5bd
TS		 598 /* CPU Error Report */
599 case GT_CPUERR_ADDRLO:
600 case GT_CPUERR_ADDRHI:
601 case GT_CPUERR_DATALO:
602 case GT_CPUERR_DATAHI:
603 case GT_CPUERR_PARITY:
0da75eb1 604 /* Emulated memory has no error, always return the initial
5fafdf24 605 values */
0da75eb1
TS		 606 val = s->regs[saddr];
607 break;
608
609 /* CPU Sync Barrier */
610 case GT_PCI0SYNC:
611 case GT_PCI1SYNC:
612 /* Reading those register should empty all FIFO on the PCI
613 bus, which are not emulated. The return value should be
614 a random value that should be ignored. */
5fafdf24 615 val = 0xc000ffee;
fde7d5bd
TS		 616 break;
617
618 /* ECC */
619 case GT_ECC_ERRDATALO:
620 case GT_ECC_ERRDATAHI:
621 case GT_ECC_MEM:
622 case GT_ECC_CALC:
623 case GT_ECC_ERRADDR:
0da75eb1 624 /* Emulated memory has no error, always return the initial
5fafdf24 625 values */
0da75eb1 626 val = s->regs[saddr];
fde7d5bd
TS		 627 break;
628
629 case GT_CPU:
05b4ff43
TS		 630 case GT_SCS10LD:
631 case GT_SCS10HD:
632 case GT_SCS32LD:
633 case GT_SCS32HD:
634 case GT_CS20LD:
635 case GT_CS20HD:
636 case GT_CS3BOOTLD:
637 case GT_CS3BOOTHD:
638 case GT_SCS10AR:
639 case GT_SCS32AR:
640 case GT_CS20R:
641 case GT_CS3BOOTR:
fde7d5bd
TS		 642 case GT_PCI0IOLD:
643 case GT_PCI0M0LD:
644 case GT_PCI0M1LD:
645 case GT_PCI1IOLD:
646 case GT_PCI1M0LD:
647 case GT_PCI1M1LD:
648 case GT_PCI0IOHD:
649 case GT_PCI0M0HD:
650 case GT_PCI0M1HD:
651 case GT_PCI1IOHD:
652 case GT_PCI1M0HD:
653 case GT_PCI1M1HD:
fde7d5bd
TS		 654 case GT_PCI0IOREMAP:
655 case GT_PCI0M0REMAP:
656 case GT_PCI0M1REMAP:
657 case GT_PCI1IOREMAP:
658 case GT_PCI1M0REMAP:
659 case GT_PCI1M1REMAP:
05b4ff43 660 case GT_ISD:
fde7d5bd
TS		 661 val = s->regs[saddr];
662 break;
663 case GT_PCI0_IACK:
5fafdf24 664 /* Read the IRQ number */
4de9b249 665 val = pic_read_irq(isa_pic);
fde7d5bd
TS		 666 break;
667
05b4ff43
TS		 668 /* SDRAM and Device Address Decode */
669 case GT_SCS0LD:
670 case GT_SCS0HD:
671 case GT_SCS1LD:
672 case GT_SCS1HD:
673 case GT_SCS2LD:
674 case GT_SCS2HD:
675 case GT_SCS3LD:
676 case GT_SCS3HD:
677 case GT_CS0LD:
678 case GT_CS0HD:
679 case GT_CS1LD:
680 case GT_CS1HD:
681 case GT_CS2LD:
682 case GT_CS2HD:
683 case GT_CS3LD:
684 case GT_CS3HD:
685 case GT_BOOTLD:
686 case GT_BOOTHD:
687 case GT_ADERR:
688 val = s->regs[saddr];
689 break;
690
691 /* SDRAM Configuration */
692 case GT_SDRAM_CFG:
693 case GT_SDRAM_OPMODE:
694 case GT_SDRAM_BM:
695 case GT_SDRAM_ADDRDECODE:
696 val = s->regs[saddr];
697 break;
698
0da75eb1
TS		 699 /* SDRAM Parameters */
700 case GT_SDRAM_B0:
701 case GT_SDRAM_B1:
702 case GT_SDRAM_B2:
703 case GT_SDRAM_B3:
704 /* We don't simulate electrical parameters of the SDRAM.
705 Just return the last written value. */
706 val = s->regs[saddr];
707 break;
708
05b4ff43
TS		 709 /* Device Parameters */
710 case GT_DEV_B0:
711 case GT_DEV_B1:
712 case GT_DEV_B2:
713 case GT_DEV_B3:
714 case GT_DEV_BOOT:
715 val = s->regs[saddr];
716 break;
717
718 /* DMA Record */
719 case GT_DMA0_CNT:
720 case GT_DMA1_CNT:
721 case GT_DMA2_CNT:
722 case GT_DMA3_CNT:
723 case GT_DMA0_SA:
724 case GT_DMA1_SA:
725 case GT_DMA2_SA:
726 case GT_DMA3_SA:
727 case GT_DMA0_DA:
728 case GT_DMA1_DA:
729 case GT_DMA2_DA:
730 case GT_DMA3_DA:
731 case GT_DMA0_NEXT:
732 case GT_DMA1_NEXT:
733 case GT_DMA2_NEXT:
734 case GT_DMA3_NEXT:
735 case GT_DMA0_CUR:
736 case GT_DMA1_CUR:
737 case GT_DMA2_CUR:
738 case GT_DMA3_CUR:
739 val = s->regs[saddr];
740 break;
741
742 /* DMA Channel Control */
743 case GT_DMA0_CTRL:
744 case GT_DMA1_CTRL:
745 case GT_DMA2_CTRL:
746 case GT_DMA3_CTRL:
747 val = s->regs[saddr];
748 break;
749
750 /* DMA Arbiter */
751 case GT_DMA_ARB:
752 val = s->regs[saddr];
753 break;
754
755 /* Timer/Counter */
756 case GT_TC0:
757 case GT_TC1:
758 case GT_TC2:
759 case GT_TC3:
760 case GT_TC_CONTROL:
761 val = s->regs[saddr];
762 break;
763
fde7d5bd
TS		 764 /* PCI Internal */
765 case GT_PCI0_CFGADDR:
c2dd2a23 766 val = s->pci.config_reg;
fde7d5bd
TS		 767 break;
768 case GT_PCI0_CFGDATA:
c2dd2a23 769 if (!(s->pci.config_reg & (1 << 31)))
c6c99c3f
AJ		 770 val = 0xffffffff;
771 else
c2dd2a23
AJ		 772 val = pci_data_read(s->pci.bus, s->pci.config_reg, 4);
773 if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
c6c99c3f 774 val = bswap32(val);
05b4ff43
TS		 775 break;
776
777 case GT_PCI0_CMD:
778 case GT_PCI0_TOR:
779 case GT_PCI0_BS_SCS10:
780 case GT_PCI0_BS_SCS32:
781 case GT_PCI0_BS_CS20:
782 case GT_PCI0_BS_CS3BT:
783 case GT_PCI1_IACK:
784 case GT_PCI0_BARE:
785 case GT_PCI0_PREFMBR:
786 case GT_PCI0_SCS10_BAR:
787 case GT_PCI0_SCS32_BAR:
788 case GT_PCI0_CS20_BAR:
789 case GT_PCI0_CS3BT_BAR:
790 case GT_PCI0_SSCS10_BAR:
791 case GT_PCI0_SSCS32_BAR:
792 case GT_PCI0_SCS3BT_BAR:
793 case GT_PCI1_CMD:
794 case GT_PCI1_TOR:
795 case GT_PCI1_BS_SCS10:
796 case GT_PCI1_BS_SCS32:
797 case GT_PCI1_BS_CS20:
798 case GT_PCI1_BS_CS3BT:
799 case GT_PCI1_BARE:
800 case GT_PCI1_PREFMBR:
801 case GT_PCI1_SCS10_BAR:
802 case GT_PCI1_SCS32_BAR:
803 case GT_PCI1_CS20_BAR:
804 case GT_PCI1_CS3BT_BAR:
805 case GT_PCI1_SSCS10_BAR:
806 case GT_PCI1_SSCS32_BAR:
807 case GT_PCI1_SCS3BT_BAR:
808 case GT_PCI1_CFGADDR:
809 case GT_PCI1_CFGDATA:
810 val = s->regs[saddr];
811 break;
812
813 /* Interrupts */
814 case GT_INTRCAUSE:
815 val = s->regs[saddr];
d0f2c4c6 816 DPRINTF("INTRCAUSE %x\n", val);
05b4ff43
TS		 817 break;
818 case GT_INTRMASK:
819 val = s->regs[saddr];
d0f2c4c6 820 DPRINTF("INTRMASK %x\n", val);
05b4ff43
TS		 821 break;
822 case GT_PCI0_ICMASK:
823 val = s->regs[saddr];
d0f2c4c6 824 DPRINTF("ICMASK %x\n", val);
05b4ff43
TS		 825 break;
826 case GT_PCI0_SERR0MASK:
827 val = s->regs[saddr];
d0f2c4c6 828 DPRINTF("SERR0MASK %x\n", val);
05b4ff43
TS		 829 break;
830
831 /* Reserved when only PCI_0 is configured. */
832 case GT_HINTRCAUSE:
833 case GT_CPU_INTSEL:
834 case GT_PCI0_INTSEL:
835 case GT_HINTRMASK:
836 case GT_PCI0_HICMASK:
837 case GT_PCI1_SERR1MASK:
838 val = s->regs[saddr];
fde7d5bd
TS		 839 break;
840
841 default:
842 val = s->regs[saddr];
d0f2c4c6 843 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 844 break;
845 }
846
c6c99c3f 847 if (!(s->regs[GT_CPU] & 0x00001000))
1931e260
TS		 848 val = bswap32(val);
849
05b4ff43 850 return val;
fde7d5bd
TS		 851}
852
d60efc6b 853static CPUWriteMemoryFunc * const gt64120_write[] = {
fde7d5bd
TS		 854 &gt64120_writel,
855 &gt64120_writel,
856 &gt64120_writel,
857};
858
d60efc6b 859static CPUReadMemoryFunc * const gt64120_read[] = {
fde7d5bd
TS		 860 &gt64120_readl,
861 &gt64120_readl,
862 &gt64120_readl,
863};
864
c2dd2a23 865static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
fde7d5bd
TS		 866{
867 int slot;
868
869 slot = (pci_dev->devfn >> 3);
870
871 switch (slot) {
872 /* PIIX4 USB */
873 case 10:
874 return 3;
875 /* AMD 79C973 Ethernet */
876 case 11:
d4a4d056 877 return 1;
fde7d5bd
TS		 878 /* Crystal 4281 Sound */
879 case 12:
d4a4d056 880 return 2;
fde7d5bd
TS		 881 /* PCI slot 1 to 4 */
882 case 18 ... 21:
883 return ((slot - 18) + irq_num) & 0x03;
884 /* Unknown device, don't do any translation */
885 default:
886 return irq_num;
887 }
888}
889
fde7d5bd
TS		 890static int pci_irq_levels[4];
891
c2dd2a23 892static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
fde7d5bd
TS		 893{
894 int i, pic_irq, pic_level;
5d4e84c8 895 qemu_irq *pic = opaque;
fde7d5bd
TS		 896
897 pci_irq_levels[irq_num] = level;
898
899 /* now we change the pic irq level according to the piix irq mappings */
900 /* XXX: optimize */
901 pic_irq = piix4_dev->config[0x60 + irq_num];
902 if (pic_irq < 16) {
903 /* The pic level is the logical OR of all the PCI irqs mapped
904 to it */
905 pic_level = 0;
906 for (i = 0; i < 4; i++) {
907 if (pic_irq == piix4_dev->config[0x60 + i])
908 pic_level |= pci_irq_levels[i];
909 }
d537cf6c 910 qemu_set_irq(pic[pic_irq], pic_level);
fde7d5bd
TS		 911 }
912}
913
914
9596ebb7 915static void gt64120_reset(void *opaque)
fde7d5bd
TS		 916{
917 GT64120State *s = opaque;
918
30b6f3a8
TS		 919 /* FIXME: Malta specific hw assumptions ahead */
920
fde7d5bd
TS		 921 /* CPU Configuration */
922#ifdef TARGET_WORDS_BIGENDIAN
923 s->regs[GT_CPU] = 0x00000000;
924#else
bc687ec9 925 s->regs[GT_CPU] = 0x00001000;
fde7d5bd 926#endif
30b6f3a8
TS		 927 s->regs[GT_MULTI] = 0x00000003;
928
929 /* CPU Address decode */
930 s->regs[GT_SCS10LD] = 0x00000000;
931 s->regs[GT_SCS10HD] = 0x00000007;
932 s->regs[GT_SCS32LD] = 0x00000008;
933 s->regs[GT_SCS32HD] = 0x0000000f;
934 s->regs[GT_CS20LD] = 0x000000e0;
935 s->regs[GT_CS20HD] = 0x00000070;
936 s->regs[GT_CS3BOOTLD] = 0x000000f8;
937 s->regs[GT_CS3BOOTHD] = 0x0000007f;
fde7d5bd 938
fde7d5bd
TS		 939 s->regs[GT_PCI0IOLD] = 0x00000080;
940 s->regs[GT_PCI0IOHD] = 0x0000000f;
941 s->regs[GT_PCI0M0LD] = 0x00000090;
942 s->regs[GT_PCI0M0HD] = 0x0000001f;
30b6f3a8 943 s->regs[GT_ISD] = 0x000000a0;
fde7d5bd
TS		 944 s->regs[GT_PCI0M1LD] = 0x00000790;
945 s->regs[GT_PCI0M1HD] = 0x0000001f;
946 s->regs[GT_PCI1IOLD] = 0x00000100;
947 s->regs[GT_PCI1IOHD] = 0x0000000f;
948 s->regs[GT_PCI1M0LD] = 0x00000110;
949 s->regs[GT_PCI1M0HD] = 0x0000001f;
950 s->regs[GT_PCI1M1LD] = 0x00000120;
951 s->regs[GT_PCI1M1HD] = 0x0000002f;
30b6f3a8
TS		 952
953 s->regs[GT_SCS10AR] = 0x00000000;
954 s->regs[GT_SCS32AR] = 0x00000008;
955 s->regs[GT_CS20R] = 0x000000e0;
956 s->regs[GT_CS3BOOTR] = 0x000000f8;
957
fde7d5bd
TS		 958 s->regs[GT_PCI0IOREMAP] = 0x00000080;
959 s->regs[GT_PCI0M0REMAP] = 0x00000090;
960 s->regs[GT_PCI0M1REMAP] = 0x00000790;
961 s->regs[GT_PCI1IOREMAP] = 0x00000100;
962 s->regs[GT_PCI1M0REMAP] = 0x00000110;
963 s->regs[GT_PCI1M1REMAP] = 0x00000120;
964
965 /* CPU Error Report */
966 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
967 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
968 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
969 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
970 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
971
30b6f3a8
TS		 972 /* CPU Sync Barrier */
973 s->regs[GT_PCI0SYNC] = 0x00000000;
974 s->regs[GT_PCI1SYNC] = 0x00000000;
975
976 /* SDRAM and Device Address Decode */
977 s->regs[GT_SCS0LD] = 0x00000000;
978 s->regs[GT_SCS0HD] = 0x00000007;
979 s->regs[GT_SCS1LD] = 0x00000008;
980 s->regs[GT_SCS1HD] = 0x0000000f;
981 s->regs[GT_SCS2LD] = 0x00000010;
982 s->regs[GT_SCS2HD] = 0x00000017;
983 s->regs[GT_SCS3LD] = 0x00000018;
984 s->regs[GT_SCS3HD] = 0x0000001f;
985 s->regs[GT_CS0LD] = 0x000000c0;
986 s->regs[GT_CS0HD] = 0x000000c7;
987 s->regs[GT_CS1LD] = 0x000000c8;
988 s->regs[GT_CS1HD] = 0x000000cf;
989 s->regs[GT_CS2LD] = 0x000000d0;
990 s->regs[GT_CS2HD] = 0x000000df;
991 s->regs[GT_CS3LD] = 0x000000f0;
992 s->regs[GT_CS3HD] = 0x000000fb;
993 s->regs[GT_BOOTLD] = 0x000000fc;
994 s->regs[GT_BOOTHD] = 0x000000ff;
995 s->regs[GT_ADERR] = 0xffffffff;
996
997 /* SDRAM Configuration */
998 s->regs[GT_SDRAM_CFG] = 0x00000200;
999 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1000 s->regs[GT_SDRAM_BM] = 0x00000007;
1001 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1002
1003 /* SDRAM Parameters */
1004 s->regs[GT_SDRAM_B0] = 0x00000005;
1005 s->regs[GT_SDRAM_B1] = 0x00000005;
1006 s->regs[GT_SDRAM_B2] = 0x00000005;
1007 s->regs[GT_SDRAM_B3] = 0x00000005;
1008
fde7d5bd
TS		 1009 /* ECC */
1010 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1011 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1012 s->regs[GT_ECC_MEM] = 0x00000000;
1013 s->regs[GT_ECC_CALC] = 0x00000000;
1014 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1015
30b6f3a8
TS		 1016 /* Device Parameters */
1017 s->regs[GT_DEV_B0] = 0x386fffff;
1018 s->regs[GT_DEV_B1] = 0x386fffff;
1019 s->regs[GT_DEV_B2] = 0x386fffff;
1020 s->regs[GT_DEV_B3] = 0x386fffff;
1021 s->regs[GT_DEV_BOOT] = 0x146fffff;
0da75eb1 1022
30b6f3a8
TS		 1023 /* DMA registers are all zeroed at reset */
1024
1025 /* Timer/Counter */
1026 s->regs[GT_TC0] = 0xffffffff;
1027 s->regs[GT_TC1] = 0x00ffffff;
1028 s->regs[GT_TC2] = 0x00ffffff;
1029 s->regs[GT_TC3] = 0x00ffffff;
1030 s->regs[GT_TC_CONTROL] = 0x00000000;
1031
1032 /* PCI Internal */
fde7d5bd
TS		 1033#ifdef TARGET_WORDS_BIGENDIAN
1034 s->regs[GT_PCI0_CMD] = 0x00000000;
fde7d5bd
TS		 1035#else
1036 s->regs[GT_PCI0_CMD] = 0x00010001;
fde7d5bd 1037#endif
30b6f3a8
TS		 1038 s->regs[GT_PCI0_TOR] = 0x0000070f;
1039 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1040 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1041 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1042 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
fde7d5bd 1043 s->regs[GT_PCI1_IACK] = 0x00000000;
30b6f3a8
TS		 1044 s->regs[GT_PCI0_IACK] = 0x00000000;
1045 s->regs[GT_PCI0_BARE] = 0x0000000f;
1046 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1047 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1048 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1049 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1050 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1051 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1052 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1053 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1054#ifdef TARGET_WORDS_BIGENDIAN
1055 s->regs[GT_PCI1_CMD] = 0x00000000;
1056#else
1057 s->regs[GT_PCI1_CMD] = 0x00010001;
1058#endif
1059 s->regs[GT_PCI1_TOR] = 0x0000070f;
1060 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1061 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1062 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1063 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1064 s->regs[GT_PCI1_BARE] = 0x0000000f;
1065 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1066 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1067 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1068 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1069 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1070 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1071 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1072 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1073 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1074 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1075 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
30b6f3a8
TS		 1076
1077 /* Interrupt registers are all zeroed at reset */
fde7d5bd 1078
a0a8793e 1079 gt64120_isd_mapping(s);
9414cc6f 1080 gt64120_pci_mapping(s);
fde7d5bd
TS		 1081}
1082
c2dd2a23
AJ		 1083PCIBus *gt64120_register(qemu_irq *pic)
1084{
1085 SysBusDevice *s;
1086 GT64120State *d;
1087 DeviceState *dev;
1088
1089 dev = qdev_create(NULL, "gt64120");
1090 qdev_init_nofail(dev);
1091 s = sysbus_from_qdev(dev);
1092 d = FROM_SYSBUS(GT64120State, s);
1093 d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
1094 gt64120_pci_set_irq, gt64120_pci_map_irq,
1095 pic, PCI_DEVFN(18, 0), 4);
1096 d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
1097 DEVICE_NATIVE_ENDIAN);
1098
1099 pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
1100 return d->pci.bus;
1101}
1102
1103static int gt64120_init(SysBusDevice *dev)
fde7d5bd
TS		 1104{
1105 GT64120State *s;
fde7d5bd 1106
c2dd2a23 1107 s = FROM_SYSBUS(GT64120State, dev);
9414cc6f 1108
8e5977e5
AJ		 1109 /* FIXME: This value is computed from registers during reset, but some
1110 devices (e.g. VGA card) need to know it when they are registered.
1111 This also mean that changing the register to change the mapping
1112 does not fully work. */
1113 isa_mem_base = 0x10000000;
c2dd2a23 1114 qemu_register_reset(gt64120_reset, s);
c2dd2a23
AJ		 1115 return 0;
1116}
fde7d5bd 1117
c2dd2a23
AJ		 1118static int gt64120_pci_init(PCIDevice *d)
1119{
0f78cf0c 1120 /* FIXME: Malta specific hw assumptions ahead */
c2dd2a23
AJ		 1121 pci_set_word(d->config + PCI_COMMAND, 0);
1122 pci_set_word(d->config + PCI_STATUS,
1123 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
c2dd2a23 1124 pci_config_set_prog_interface(d->config, 0);
c2dd2a23
AJ		 1125 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1126 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1127 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1128 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1129 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1130 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1131 pci_set_byte(d->config + 0x3d, 0x01);
0f78cf0c 1132
c2dd2a23
AJ		 1133 return 0;
1134}
a0a8793e 1135
c2dd2a23
AJ		 1136static PCIDeviceInfo gt64120_pci_info = {
1137 .qdev.name = "gt64120_pci",
1138 .qdev.size = sizeof(PCIDevice),
1139 .init = gt64120_pci_init,
231f5f43
IY		 1140 .vendor_id = PCI_VENDOR_ID_MARVELL,
1141 .device_id = PCI_DEVICE_ID_MARVELL_GT6412X,
1142 .revision = 0x10,
1143 .class_id = PCI_CLASS_BRIDGE_HOST,
c2dd2a23 1144};
1823082c 1145
c2dd2a23
AJ		 1146static void gt64120_pci_register_devices(void)
1147{
1148 sysbus_register_dev("gt64120", sizeof(GT64120State),
1149 gt64120_init);
1150 pci_qdev_register(&gt64120_pci_info);
fde7d5bd 1151}
c2dd2a23
AJ		 1152
1153device_init(gt64120_pci_register_devices)
Qemu copy for testing