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fde7d5bd TS |
1 | /* |
2 | * QEMU GT64120 PCI host | |
3 | * | |
4de9b249 | 4 | * Copyright (c) 2006,2007 Aurelien Jarno |
fde7d5bd TS |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "vl.h" | |
05b4ff43 | 26 | |
fde7d5bd TS |
27 | typedef target_phys_addr_t pci_addr_t; |
28 | #include "pci_host.h" | |
29 | ||
05b4ff43 TS |
30 | //#define DEBUG |
31 | ||
32 | #ifdef DEBUG | |
33 | #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) | |
34 | #else | |
35 | #define dprintf(fmt, ...) | |
36 | #endif | |
37 | ||
fde7d5bd TS |
38 | #define GT_REGS (0x1000 >> 2) |
39 | ||
40 | /* CPU Configuration */ | |
41 | #define GT_CPU (0x000 >> 2) | |
42 | #define GT_MULTI (0x120 >> 2) | |
43 | ||
44 | /* CPU Address Decode */ | |
45 | #define GT_SCS10LD (0x008 >> 2) | |
46 | #define GT_SCS10HD (0x010 >> 2) | |
47 | #define GT_SCS32LD (0x018 >> 2) | |
48 | #define GT_SCS32HD (0x020 >> 2) | |
49 | #define GT_CS20LD (0x028 >> 2) | |
50 | #define GT_CS20HD (0x030 >> 2) | |
51 | #define GT_CS3BOOTLD (0x038 >> 2) | |
52 | #define GT_CS3BOOTHD (0x040 >> 2) | |
53 | #define GT_PCI0IOLD (0x048 >> 2) | |
54 | #define GT_PCI0IOHD (0x050 >> 2) | |
55 | #define GT_PCI0M0LD (0x058 >> 2) | |
56 | #define GT_PCI0M0HD (0x060 >> 2) | |
fde7d5bd TS |
57 | #define GT_PCI0M1LD (0x080 >> 2) |
58 | #define GT_PCI0M1HD (0x088 >> 2) | |
59 | #define GT_PCI1IOLD (0x090 >> 2) | |
60 | #define GT_PCI1IOHD (0x098 >> 2) | |
61 | #define GT_PCI1M0LD (0x0a0 >> 2) | |
62 | #define GT_PCI1M0HD (0x0a8 >> 2) | |
63 | #define GT_PCI1M1LD (0x0b0 >> 2) | |
64 | #define GT_PCI1M1HD (0x0b8 >> 2) | |
05b4ff43 | 65 | #define GT_ISD (0x068 >> 2) |
fde7d5bd TS |
66 | |
67 | #define GT_SCS10AR (0x0d0 >> 2) | |
68 | #define GT_SCS32AR (0x0d8 >> 2) | |
69 | #define GT_CS20R (0x0e0 >> 2) | |
70 | #define GT_CS3BOOTR (0x0e8 >> 2) | |
71 | ||
72 | #define GT_PCI0IOREMAP (0x0f0 >> 2) | |
73 | #define GT_PCI0M0REMAP (0x0f8 >> 2) | |
74 | #define GT_PCI0M1REMAP (0x100 >> 2) | |
75 | #define GT_PCI1IOREMAP (0x108 >> 2) | |
76 | #define GT_PCI1M0REMAP (0x110 >> 2) | |
77 | #define GT_PCI1M1REMAP (0x118 >> 2) | |
78 | ||
79 | /* CPU Error Report */ | |
80 | #define GT_CPUERR_ADDRLO (0x070 >> 2) | |
81 | #define GT_CPUERR_ADDRHI (0x078 >> 2) | |
82 | #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ | |
83 | #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ | |
84 | #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ | |
85 | ||
86 | /* CPU Sync Barrier */ | |
87 | #define GT_PCI0SYNC (0x0c0 >> 2) | |
88 | #define GT_PCI1SYNC (0x0c8 >> 2) | |
89 | ||
90 | /* SDRAM and Device Address Decode */ | |
91 | #define GT_SCS0LD (0x400 >> 2) | |
92 | #define GT_SCS0HD (0x404 >> 2) | |
93 | #define GT_SCS1LD (0x408 >> 2) | |
94 | #define GT_SCS1HD (0x40c >> 2) | |
95 | #define GT_SCS2LD (0x410 >> 2) | |
96 | #define GT_SCS2HD (0x414 >> 2) | |
97 | #define GT_SCS3LD (0x418 >> 2) | |
98 | #define GT_SCS3HD (0x41c >> 2) | |
99 | #define GT_CS0LD (0x420 >> 2) | |
100 | #define GT_CS0HD (0x424 >> 2) | |
101 | #define GT_CS1LD (0x428 >> 2) | |
102 | #define GT_CS1HD (0x42c >> 2) | |
103 | #define GT_CS2LD (0x430 >> 2) | |
104 | #define GT_CS2HD (0x434 >> 2) | |
105 | #define GT_CS3LD (0x438 >> 2) | |
106 | #define GT_CS3HD (0x43c >> 2) | |
107 | #define GT_BOOTLD (0x440 >> 2) | |
108 | #define GT_BOOTHD (0x444 >> 2) | |
109 | #define GT_ADERR (0x470 >> 2) | |
110 | ||
111 | /* SDRAM Configuration */ | |
112 | #define GT_SDRAM_CFG (0x448 >> 2) | |
113 | #define GT_SDRAM_OPMODE (0x474 >> 2) | |
114 | #define GT_SDRAM_BM (0x478 >> 2) | |
115 | #define GT_SDRAM_ADDRDECODE (0x47c >> 2) | |
116 | ||
117 | /* SDRAM Parameters */ | |
118 | #define GT_SDRAM_B0 (0x44c >> 2) | |
119 | #define GT_SDRAM_B1 (0x450 >> 2) | |
120 | #define GT_SDRAM_B2 (0x454 >> 2) | |
121 | #define GT_SDRAM_B3 (0x458 >> 2) | |
122 | ||
123 | /* Device Parameters */ | |
124 | #define GT_DEV_B0 (0x45c >> 2) | |
125 | #define GT_DEV_B1 (0x460 >> 2) | |
126 | #define GT_DEV_B2 (0x464 >> 2) | |
127 | #define GT_DEV_B3 (0x468 >> 2) | |
128 | #define GT_DEV_BOOT (0x46c >> 2) | |
129 | ||
130 | /* ECC */ | |
131 | #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ | |
132 | #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ | |
133 | #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ | |
134 | #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ | |
135 | #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ | |
136 | ||
137 | /* DMA Record */ | |
138 | #define GT_DMA0_CNT (0x800 >> 2) | |
139 | #define GT_DMA1_CNT (0x804 >> 2) | |
140 | #define GT_DMA2_CNT (0x808 >> 2) | |
141 | #define GT_DMA3_CNT (0x80c >> 2) | |
142 | #define GT_DMA0_SA (0x810 >> 2) | |
143 | #define GT_DMA1_SA (0x814 >> 2) | |
144 | #define GT_DMA2_SA (0x818 >> 2) | |
145 | #define GT_DMA3_SA (0x81c >> 2) | |
146 | #define GT_DMA0_DA (0x820 >> 2) | |
147 | #define GT_DMA1_DA (0x824 >> 2) | |
148 | #define GT_DMA2_DA (0x828 >> 2) | |
149 | #define GT_DMA3_DA (0x82c >> 2) | |
150 | #define GT_DMA0_NEXT (0x830 >> 2) | |
151 | #define GT_DMA1_NEXT (0x834 >> 2) | |
152 | #define GT_DMA2_NEXT (0x838 >> 2) | |
153 | #define GT_DMA3_NEXT (0x83c >> 2) | |
154 | #define GT_DMA0_CUR (0x870 >> 2) | |
155 | #define GT_DMA1_CUR (0x874 >> 2) | |
156 | #define GT_DMA2_CUR (0x878 >> 2) | |
157 | #define GT_DMA3_CUR (0x87c >> 2) | |
158 | ||
159 | /* DMA Channel Control */ | |
160 | #define GT_DMA0_CTRL (0x840 >> 2) | |
161 | #define GT_DMA1_CTRL (0x844 >> 2) | |
162 | #define GT_DMA2_CTRL (0x848 >> 2) | |
163 | #define GT_DMA3_CTRL (0x84c >> 2) | |
164 | ||
165 | /* DMA Arbiter */ | |
166 | #define GT_DMA_ARB (0x860 >> 2) | |
167 | ||
168 | /* Timer/Counter */ | |
169 | #define GT_TC0 (0x850 >> 2) | |
170 | #define GT_TC1 (0x854 >> 2) | |
171 | #define GT_TC2 (0x858 >> 2) | |
172 | #define GT_TC3 (0x85c >> 2) | |
173 | #define GT_TC_CONTROL (0x864 >> 2) | |
174 | ||
175 | /* PCI Internal */ | |
176 | #define GT_PCI0_CMD (0xc00 >> 2) | |
177 | #define GT_PCI0_TOR (0xc04 >> 2) | |
178 | #define GT_PCI0_BS_SCS10 (0xc08 >> 2) | |
179 | #define GT_PCI0_BS_SCS32 (0xc0c >> 2) | |
180 | #define GT_PCI0_BS_CS20 (0xc10 >> 2) | |
181 | #define GT_PCI0_BS_CS3BT (0xc14 >> 2) | |
182 | #define GT_PCI1_IACK (0xc30 >> 2) | |
183 | #define GT_PCI0_IACK (0xc34 >> 2) | |
184 | #define GT_PCI0_BARE (0xc3c >> 2) | |
185 | #define GT_PCI0_PREFMBR (0xc40 >> 2) | |
186 | #define GT_PCI0_SCS10_BAR (0xc48 >> 2) | |
187 | #define GT_PCI0_SCS32_BAR (0xc4c >> 2) | |
188 | #define GT_PCI0_CS20_BAR (0xc50 >> 2) | |
189 | #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) | |
190 | #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) | |
191 | #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) | |
192 | #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) | |
193 | #define GT_PCI1_CMD (0xc80 >> 2) | |
194 | #define GT_PCI1_TOR (0xc84 >> 2) | |
195 | #define GT_PCI1_BS_SCS10 (0xc88 >> 2) | |
196 | #define GT_PCI1_BS_SCS32 (0xc8c >> 2) | |
197 | #define GT_PCI1_BS_CS20 (0xc90 >> 2) | |
198 | #define GT_PCI1_BS_CS3BT (0xc94 >> 2) | |
199 | #define GT_PCI1_BARE (0xcbc >> 2) | |
200 | #define GT_PCI1_PREFMBR (0xcc0 >> 2) | |
201 | #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) | |
202 | #define GT_PCI1_SCS32_BAR (0xccc >> 2) | |
203 | #define GT_PCI1_CS20_BAR (0xcd0 >> 2) | |
204 | #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) | |
205 | #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) | |
206 | #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) | |
207 | #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) | |
208 | #define GT_PCI1_CFGADDR (0xcf0 >> 2) | |
209 | #define GT_PCI1_CFGDATA (0xcf4 >> 2) | |
210 | #define GT_PCI0_CFGADDR (0xcf8 >> 2) | |
211 | #define GT_PCI0_CFGDATA (0xcfc >> 2) | |
212 | ||
213 | /* Interrupts */ | |
214 | #define GT_INTRCAUSE (0xc18 >> 2) | |
215 | #define GT_INTRMASK (0xc1c >> 2) | |
216 | #define GT_PCI0_ICMASK (0xc24 >> 2) | |
217 | #define GT_PCI0_SERR0MASK (0xc28 >> 2) | |
218 | #define GT_CPU_INTSEL (0xc70 >> 2) | |
219 | #define GT_PCI0_INTSEL (0xc74 >> 2) | |
220 | #define GT_HINTRCAUSE (0xc98 >> 2) | |
221 | #define GT_HINTRMASK (0xc9c >> 2) | |
222 | #define GT_PCI0_HICMASK (0xca4 >> 2) | |
223 | #define GT_PCI1_SERR1MASK (0xca8 >> 2) | |
224 | ||
225 | ||
226 | typedef PCIHostState GT64120PCIState; | |
227 | ||
228 | typedef struct GT64120State { | |
229 | GT64120PCIState *pci; | |
230 | uint32_t regs[GT_REGS]; | |
35f1de31 TS |
231 | target_phys_addr_t PCI0IO_start; |
232 | target_phys_addr_t PCI0IO_length; | |
fde7d5bd TS |
233 | } GT64120State; |
234 | ||
235 | static void gt64120_pci_mapping(GT64120State *s) | |
236 | { | |
fde7d5bd | 237 | /* Update IO mapping */ |
90e950d1 TS |
238 | if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) |
239 | { | |
35f1de31 TS |
240 | /* Unmap old IO address */ |
241 | if (s->PCI0IO_length) | |
242 | { | |
243 | cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); | |
244 | } | |
245 | /* Map new IO address */ | |
246 | s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; | |
247 | s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; | |
11f29511 | 248 | isa_mem_base = s->PCI0IO_start; |
35f1de31 | 249 | isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); |
90e950d1 | 250 | } |
fde7d5bd TS |
251 | } |
252 | ||
253 | static void gt64120_writel (void *opaque, target_phys_addr_t addr, | |
254 | uint32_t val) | |
255 | { | |
256 | GT64120State *s = opaque; | |
257 | uint32_t saddr; | |
258 | ||
0da75eb1 TS |
259 | #ifdef TARGET_WORDS_BIGENDIAN |
260 | val = bswap32(val); | |
261 | #endif | |
262 | ||
fde7d5bd TS |
263 | saddr = (addr & 0xfff) >> 2; |
264 | switch (saddr) { | |
0da75eb1 TS |
265 | |
266 | /* CPU Configuration */ | |
fde7d5bd TS |
267 | case GT_CPU: |
268 | s->regs[GT_CPU] = val; | |
fde7d5bd TS |
269 | break; |
270 | case GT_MULTI: | |
0da75eb1 | 271 | /* Read-only register as only one GT64xxx is present on the CPU bus */ |
fde7d5bd TS |
272 | break; |
273 | ||
274 | /* CPU Address Decode */ | |
275 | case GT_PCI0IOLD: | |
276 | s->regs[GT_PCI0IOLD] = val & 0x00007fff; | |
277 | s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; | |
278 | gt64120_pci_mapping(s); | |
279 | break; | |
280 | case GT_PCI0M0LD: | |
281 | s->regs[GT_PCI0M0LD] = val & 0x00007fff; | |
282 | s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; | |
283 | gt64120_pci_mapping(s); | |
284 | break; | |
285 | case GT_PCI0M1LD: | |
286 | s->regs[GT_PCI0M1LD] = val & 0x00007fff; | |
287 | s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; | |
288 | gt64120_pci_mapping(s); | |
289 | break; | |
290 | case GT_PCI1IOLD: | |
291 | s->regs[GT_PCI1IOLD] = val & 0x00007fff; | |
292 | s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; | |
293 | gt64120_pci_mapping(s); | |
294 | break; | |
295 | case GT_PCI1M0LD: | |
296 | s->regs[GT_PCI1M0LD] = val & 0x00007fff; | |
297 | s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; | |
298 | gt64120_pci_mapping(s); | |
299 | break; | |
300 | case GT_PCI1M1LD: | |
301 | s->regs[GT_PCI1M1LD] = val & 0x00007fff; | |
302 | s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; | |
303 | gt64120_pci_mapping(s); | |
304 | break; | |
305 | case GT_PCI0IOHD: | |
306 | case GT_PCI0M0HD: | |
307 | case GT_PCI0M1HD: | |
308 | case GT_PCI1IOHD: | |
309 | case GT_PCI1M0HD: | |
310 | case GT_PCI1M1HD: | |
311 | s->regs[saddr] = val & 0x0000007f; | |
312 | gt64120_pci_mapping(s); | |
313 | break; | |
314 | case GT_PCI0IOREMAP: | |
315 | case GT_PCI0M0REMAP: | |
316 | case GT_PCI0M1REMAP: | |
317 | case GT_PCI1IOREMAP: | |
318 | case GT_PCI1M0REMAP: | |
319 | case GT_PCI1M1REMAP: | |
320 | s->regs[saddr] = val & 0x000007ff; | |
321 | gt64120_pci_mapping(s); | |
322 | break; | |
323 | ||
324 | /* CPU Error Report */ | |
325 | case GT_CPUERR_ADDRLO: | |
326 | case GT_CPUERR_ADDRHI: | |
327 | case GT_CPUERR_DATALO: | |
328 | case GT_CPUERR_DATAHI: | |
329 | case GT_CPUERR_PARITY: | |
0da75eb1 TS |
330 | /* Read-only registers, do nothing */ |
331 | break; | |
332 | ||
333 | /* CPU Sync Barrier */ | |
334 | case GT_PCI0SYNC: | |
335 | case GT_PCI1SYNC: | |
336 | /* Read-only registers, do nothing */ | |
fde7d5bd TS |
337 | break; |
338 | ||
05b4ff43 TS |
339 | /* SDRAM and Device Address Decode */ |
340 | case GT_SCS0LD: | |
341 | case GT_SCS0HD: | |
342 | case GT_SCS1LD: | |
343 | case GT_SCS1HD: | |
344 | case GT_SCS2LD: | |
345 | case GT_SCS2HD: | |
346 | case GT_SCS3LD: | |
347 | case GT_SCS3HD: | |
348 | case GT_CS0LD: | |
349 | case GT_CS0HD: | |
350 | case GT_CS1LD: | |
351 | case GT_CS1HD: | |
352 | case GT_CS2LD: | |
353 | case GT_CS2HD: | |
354 | case GT_CS3LD: | |
355 | case GT_CS3HD: | |
356 | case GT_BOOTLD: | |
357 | case GT_BOOTHD: | |
358 | case GT_ADERR: | |
359 | /* SDRAM Configuration */ | |
360 | case GT_SDRAM_CFG: | |
361 | case GT_SDRAM_OPMODE: | |
362 | case GT_SDRAM_BM: | |
363 | case GT_SDRAM_ADDRDECODE: | |
364 | /* Accept and ignore SDRAM interleave configuration */ | |
365 | s->regs[saddr] = val; | |
366 | break; | |
367 | ||
368 | /* Device Parameters */ | |
369 | case GT_DEV_B0: | |
370 | case GT_DEV_B1: | |
371 | case GT_DEV_B2: | |
372 | case GT_DEV_B3: | |
373 | case GT_DEV_BOOT: | |
374 | /* Not implemented */ | |
375 | dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2); | |
376 | break; | |
377 | ||
fde7d5bd TS |
378 | /* ECC */ |
379 | case GT_ECC_ERRDATALO: | |
380 | case GT_ECC_ERRDATAHI: | |
381 | case GT_ECC_MEM: | |
382 | case GT_ECC_CALC: | |
383 | case GT_ECC_ERRADDR: | |
0da75eb1 | 384 | /* Read-only registers, do nothing */ |
fde7d5bd TS |
385 | break; |
386 | ||
05b4ff43 TS |
387 | /* DMA Record */ |
388 | case GT_DMA0_CNT: | |
389 | case GT_DMA1_CNT: | |
390 | case GT_DMA2_CNT: | |
391 | case GT_DMA3_CNT: | |
392 | case GT_DMA0_SA: | |
393 | case GT_DMA1_SA: | |
394 | case GT_DMA2_SA: | |
395 | case GT_DMA3_SA: | |
396 | case GT_DMA0_DA: | |
397 | case GT_DMA1_DA: | |
398 | case GT_DMA2_DA: | |
399 | case GT_DMA3_DA: | |
400 | case GT_DMA0_NEXT: | |
401 | case GT_DMA1_NEXT: | |
402 | case GT_DMA2_NEXT: | |
403 | case GT_DMA3_NEXT: | |
404 | case GT_DMA0_CUR: | |
405 | case GT_DMA1_CUR: | |
406 | case GT_DMA2_CUR: | |
407 | case GT_DMA3_CUR: | |
408 | /* Not implemented */ | |
409 | dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
410 | break; | |
411 | ||
412 | /* DMA Channel Control */ | |
413 | case GT_DMA0_CTRL: | |
414 | case GT_DMA1_CTRL: | |
415 | case GT_DMA2_CTRL: | |
416 | case GT_DMA3_CTRL: | |
417 | /* Not implemented */ | |
418 | dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
419 | break; | |
420 | ||
421 | /* DMA Arbiter */ | |
422 | case GT_DMA_ARB: | |
423 | /* Not implemented */ | |
424 | dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
425 | break; | |
426 | ||
427 | /* Timer/Counter */ | |
428 | case GT_TC0: | |
429 | case GT_TC1: | |
430 | case GT_TC2: | |
431 | case GT_TC3: | |
432 | case GT_TC_CONTROL: | |
433 | /* Not implemented */ | |
434 | dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2); | |
435 | break; | |
436 | ||
fde7d5bd TS |
437 | /* PCI Internal */ |
438 | case GT_PCI0_CMD: | |
439 | case GT_PCI1_CMD: | |
440 | s->regs[saddr] = val & 0x0401fc0f; | |
441 | break; | |
05b4ff43 TS |
442 | case GT_PCI0_TOR: |
443 | case GT_PCI0_BS_SCS10: | |
444 | case GT_PCI0_BS_SCS32: | |
445 | case GT_PCI0_BS_CS20: | |
446 | case GT_PCI0_BS_CS3BT: | |
447 | case GT_PCI1_IACK: | |
448 | case GT_PCI0_IACK: | |
449 | case GT_PCI0_BARE: | |
450 | case GT_PCI0_PREFMBR: | |
451 | case GT_PCI0_SCS10_BAR: | |
452 | case GT_PCI0_SCS32_BAR: | |
453 | case GT_PCI0_CS20_BAR: | |
454 | case GT_PCI0_CS3BT_BAR: | |
455 | case GT_PCI0_SSCS10_BAR: | |
456 | case GT_PCI0_SSCS32_BAR: | |
457 | case GT_PCI0_SCS3BT_BAR: | |
458 | case GT_PCI1_TOR: | |
459 | case GT_PCI1_BS_SCS10: | |
460 | case GT_PCI1_BS_SCS32: | |
461 | case GT_PCI1_BS_CS20: | |
462 | case GT_PCI1_BS_CS3BT: | |
463 | case GT_PCI1_BARE: | |
464 | case GT_PCI1_PREFMBR: | |
465 | case GT_PCI1_SCS10_BAR: | |
466 | case GT_PCI1_SCS32_BAR: | |
467 | case GT_PCI1_CS20_BAR: | |
468 | case GT_PCI1_CS3BT_BAR: | |
469 | case GT_PCI1_SSCS10_BAR: | |
470 | case GT_PCI1_SSCS32_BAR: | |
471 | case GT_PCI1_SCS3BT_BAR: | |
472 | case GT_PCI1_CFGADDR: | |
473 | case GT_PCI1_CFGDATA: | |
474 | /* not implemented */ | |
475 | break; | |
fde7d5bd TS |
476 | case GT_PCI0_CFGADDR: |
477 | s->pci->config_reg = val & 0x80fffffc; | |
478 | break; | |
479 | case GT_PCI0_CFGDATA: | |
05b4ff43 TS |
480 | if (s->pci->config_reg & (1u << 31)) |
481 | pci_host_data_writel(s->pci, 0, val); | |
482 | break; | |
483 | ||
484 | /* Interrupts */ | |
485 | case GT_INTRCAUSE: | |
486 | /* not really implemented */ | |
487 | s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); | |
488 | s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); | |
489 | dprintf("INTRCAUSE %x\n", val); | |
490 | break; | |
491 | case GT_INTRMASK: | |
492 | s->regs[saddr] = val & 0x3c3ffffe; | |
493 | dprintf("INTRMASK %x\n", val); | |
494 | break; | |
495 | case GT_PCI0_ICMASK: | |
496 | s->regs[saddr] = val & 0x03fffffe; | |
497 | dprintf("ICMASK %x\n", val); | |
498 | break; | |
499 | case GT_PCI0_SERR0MASK: | |
500 | s->regs[saddr] = val & 0x0000003f; | |
501 | dprintf("SERR0MASK %x\n", val); | |
502 | break; | |
503 | ||
504 | /* Reserved when only PCI_0 is configured. */ | |
505 | case GT_HINTRCAUSE: | |
506 | case GT_CPU_INTSEL: | |
507 | case GT_PCI0_INTSEL: | |
508 | case GT_HINTRMASK: | |
509 | case GT_PCI0_HICMASK: | |
510 | case GT_PCI1_SERR1MASK: | |
511 | /* not implemented */ | |
fde7d5bd TS |
512 | break; |
513 | ||
0da75eb1 TS |
514 | /* SDRAM Parameters */ |
515 | case GT_SDRAM_B0: | |
516 | case GT_SDRAM_B1: | |
517 | case GT_SDRAM_B2: | |
518 | case GT_SDRAM_B3: | |
519 | /* We don't simulate electrical parameters of the SDRAM. | |
520 | Accept, but ignore the values. */ | |
521 | s->regs[saddr] = val; | |
522 | break; | |
523 | ||
fde7d5bd | 524 | default: |
05b4ff43 | 525 | dprintf ("Bad register offset 0x%x\n", (int)addr); |
fde7d5bd TS |
526 | break; |
527 | } | |
528 | } | |
529 | ||
530 | static uint32_t gt64120_readl (void *opaque, | |
531 | target_phys_addr_t addr) | |
532 | { | |
533 | GT64120State *s = opaque; | |
534 | uint32_t val; | |
535 | uint32_t saddr; | |
536 | ||
537 | val = 0; | |
538 | saddr = (addr & 0xfff) >> 2; | |
539 | ||
540 | switch (saddr) { | |
541 | ||
0da75eb1 TS |
542 | /* CPU Configuration */ |
543 | case GT_MULTI: | |
544 | /* Only one GT64xxx is present on the CPU bus, return | |
545 | the initial value */ | |
546 | val = s->regs[saddr]; | |
547 | break; | |
548 | ||
fde7d5bd TS |
549 | /* CPU Error Report */ |
550 | case GT_CPUERR_ADDRLO: | |
551 | case GT_CPUERR_ADDRHI: | |
552 | case GT_CPUERR_DATALO: | |
553 | case GT_CPUERR_DATAHI: | |
554 | case GT_CPUERR_PARITY: | |
0da75eb1 TS |
555 | /* Emulated memory has no error, always return the initial |
556 | values */ | |
557 | val = s->regs[saddr]; | |
558 | break; | |
559 | ||
560 | /* CPU Sync Barrier */ | |
561 | case GT_PCI0SYNC: | |
562 | case GT_PCI1SYNC: | |
563 | /* Reading those register should empty all FIFO on the PCI | |
564 | bus, which are not emulated. The return value should be | |
565 | a random value that should be ignored. */ | |
566 | val = 0xc000ffee; | |
fde7d5bd TS |
567 | break; |
568 | ||
569 | /* ECC */ | |
570 | case GT_ECC_ERRDATALO: | |
571 | case GT_ECC_ERRDATAHI: | |
572 | case GT_ECC_MEM: | |
573 | case GT_ECC_CALC: | |
574 | case GT_ECC_ERRADDR: | |
0da75eb1 TS |
575 | /* Emulated memory has no error, always return the initial |
576 | values */ | |
577 | val = s->regs[saddr]; | |
fde7d5bd TS |
578 | break; |
579 | ||
580 | case GT_CPU: | |
05b4ff43 TS |
581 | case GT_SCS10LD: |
582 | case GT_SCS10HD: | |
583 | case GT_SCS32LD: | |
584 | case GT_SCS32HD: | |
585 | case GT_CS20LD: | |
586 | case GT_CS20HD: | |
587 | case GT_CS3BOOTLD: | |
588 | case GT_CS3BOOTHD: | |
589 | case GT_SCS10AR: | |
590 | case GT_SCS32AR: | |
591 | case GT_CS20R: | |
592 | case GT_CS3BOOTR: | |
fde7d5bd TS |
593 | case GT_PCI0IOLD: |
594 | case GT_PCI0M0LD: | |
595 | case GT_PCI0M1LD: | |
596 | case GT_PCI1IOLD: | |
597 | case GT_PCI1M0LD: | |
598 | case GT_PCI1M1LD: | |
599 | case GT_PCI0IOHD: | |
600 | case GT_PCI0M0HD: | |
601 | case GT_PCI0M1HD: | |
602 | case GT_PCI1IOHD: | |
603 | case GT_PCI1M0HD: | |
604 | case GT_PCI1M1HD: | |
fde7d5bd TS |
605 | case GT_PCI0IOREMAP: |
606 | case GT_PCI0M0REMAP: | |
607 | case GT_PCI0M1REMAP: | |
608 | case GT_PCI1IOREMAP: | |
609 | case GT_PCI1M0REMAP: | |
610 | case GT_PCI1M1REMAP: | |
05b4ff43 | 611 | case GT_ISD: |
fde7d5bd TS |
612 | val = s->regs[saddr]; |
613 | break; | |
614 | case GT_PCI0_IACK: | |
4de9b249 TS |
615 | /* Read the IRQ number */ |
616 | val = pic_read_irq(isa_pic); | |
fde7d5bd TS |
617 | break; |
618 | ||
05b4ff43 TS |
619 | /* SDRAM and Device Address Decode */ |
620 | case GT_SCS0LD: | |
621 | case GT_SCS0HD: | |
622 | case GT_SCS1LD: | |
623 | case GT_SCS1HD: | |
624 | case GT_SCS2LD: | |
625 | case GT_SCS2HD: | |
626 | case GT_SCS3LD: | |
627 | case GT_SCS3HD: | |
628 | case GT_CS0LD: | |
629 | case GT_CS0HD: | |
630 | case GT_CS1LD: | |
631 | case GT_CS1HD: | |
632 | case GT_CS2LD: | |
633 | case GT_CS2HD: | |
634 | case GT_CS3LD: | |
635 | case GT_CS3HD: | |
636 | case GT_BOOTLD: | |
637 | case GT_BOOTHD: | |
638 | case GT_ADERR: | |
639 | val = s->regs[saddr]; | |
640 | break; | |
641 | ||
642 | /* SDRAM Configuration */ | |
643 | case GT_SDRAM_CFG: | |
644 | case GT_SDRAM_OPMODE: | |
645 | case GT_SDRAM_BM: | |
646 | case GT_SDRAM_ADDRDECODE: | |
647 | val = s->regs[saddr]; | |
648 | break; | |
649 | ||
0da75eb1 TS |
650 | /* SDRAM Parameters */ |
651 | case GT_SDRAM_B0: | |
652 | case GT_SDRAM_B1: | |
653 | case GT_SDRAM_B2: | |
654 | case GT_SDRAM_B3: | |
655 | /* We don't simulate electrical parameters of the SDRAM. | |
656 | Just return the last written value. */ | |
657 | val = s->regs[saddr]; | |
658 | break; | |
659 | ||
05b4ff43 TS |
660 | /* Device Parameters */ |
661 | case GT_DEV_B0: | |
662 | case GT_DEV_B1: | |
663 | case GT_DEV_B2: | |
664 | case GT_DEV_B3: | |
665 | case GT_DEV_BOOT: | |
666 | val = s->regs[saddr]; | |
667 | break; | |
668 | ||
669 | /* DMA Record */ | |
670 | case GT_DMA0_CNT: | |
671 | case GT_DMA1_CNT: | |
672 | case GT_DMA2_CNT: | |
673 | case GT_DMA3_CNT: | |
674 | case GT_DMA0_SA: | |
675 | case GT_DMA1_SA: | |
676 | case GT_DMA2_SA: | |
677 | case GT_DMA3_SA: | |
678 | case GT_DMA0_DA: | |
679 | case GT_DMA1_DA: | |
680 | case GT_DMA2_DA: | |
681 | case GT_DMA3_DA: | |
682 | case GT_DMA0_NEXT: | |
683 | case GT_DMA1_NEXT: | |
684 | case GT_DMA2_NEXT: | |
685 | case GT_DMA3_NEXT: | |
686 | case GT_DMA0_CUR: | |
687 | case GT_DMA1_CUR: | |
688 | case GT_DMA2_CUR: | |
689 | case GT_DMA3_CUR: | |
690 | val = s->regs[saddr]; | |
691 | break; | |
692 | ||
693 | /* DMA Channel Control */ | |
694 | case GT_DMA0_CTRL: | |
695 | case GT_DMA1_CTRL: | |
696 | case GT_DMA2_CTRL: | |
697 | case GT_DMA3_CTRL: | |
698 | val = s->regs[saddr]; | |
699 | break; | |
700 | ||
701 | /* DMA Arbiter */ | |
702 | case GT_DMA_ARB: | |
703 | val = s->regs[saddr]; | |
704 | break; | |
705 | ||
706 | /* Timer/Counter */ | |
707 | case GT_TC0: | |
708 | case GT_TC1: | |
709 | case GT_TC2: | |
710 | case GT_TC3: | |
711 | case GT_TC_CONTROL: | |
712 | val = s->regs[saddr]; | |
713 | break; | |
714 | ||
fde7d5bd TS |
715 | /* PCI Internal */ |
716 | case GT_PCI0_CFGADDR: | |
717 | val = s->pci->config_reg; | |
718 | break; | |
719 | case GT_PCI0_CFGDATA: | |
05b4ff43 TS |
720 | if (!(s->pci->config_reg & (1u << 31))) |
721 | val = 0xffffffff; | |
722 | else | |
723 | val = pci_data_read(s->pci->bus, s->pci->config_reg, 4); | |
724 | break; | |
725 | ||
726 | case GT_PCI0_CMD: | |
727 | case GT_PCI0_TOR: | |
728 | case GT_PCI0_BS_SCS10: | |
729 | case GT_PCI0_BS_SCS32: | |
730 | case GT_PCI0_BS_CS20: | |
731 | case GT_PCI0_BS_CS3BT: | |
732 | case GT_PCI1_IACK: | |
733 | case GT_PCI0_BARE: | |
734 | case GT_PCI0_PREFMBR: | |
735 | case GT_PCI0_SCS10_BAR: | |
736 | case GT_PCI0_SCS32_BAR: | |
737 | case GT_PCI0_CS20_BAR: | |
738 | case GT_PCI0_CS3BT_BAR: | |
739 | case GT_PCI0_SSCS10_BAR: | |
740 | case GT_PCI0_SSCS32_BAR: | |
741 | case GT_PCI0_SCS3BT_BAR: | |
742 | case GT_PCI1_CMD: | |
743 | case GT_PCI1_TOR: | |
744 | case GT_PCI1_BS_SCS10: | |
745 | case GT_PCI1_BS_SCS32: | |
746 | case GT_PCI1_BS_CS20: | |
747 | case GT_PCI1_BS_CS3BT: | |
748 | case GT_PCI1_BARE: | |
749 | case GT_PCI1_PREFMBR: | |
750 | case GT_PCI1_SCS10_BAR: | |
751 | case GT_PCI1_SCS32_BAR: | |
752 | case GT_PCI1_CS20_BAR: | |
753 | case GT_PCI1_CS3BT_BAR: | |
754 | case GT_PCI1_SSCS10_BAR: | |
755 | case GT_PCI1_SSCS32_BAR: | |
756 | case GT_PCI1_SCS3BT_BAR: | |
757 | case GT_PCI1_CFGADDR: | |
758 | case GT_PCI1_CFGDATA: | |
759 | val = s->regs[saddr]; | |
760 | break; | |
761 | ||
762 | /* Interrupts */ | |
763 | case GT_INTRCAUSE: | |
764 | val = s->regs[saddr]; | |
765 | dprintf("INTRCAUSE %x\n", val); | |
766 | break; | |
767 | case GT_INTRMASK: | |
768 | val = s->regs[saddr]; | |
769 | dprintf("INTRMASK %x\n", val); | |
770 | break; | |
771 | case GT_PCI0_ICMASK: | |
772 | val = s->regs[saddr]; | |
773 | dprintf("ICMASK %x\n", val); | |
774 | break; | |
775 | case GT_PCI0_SERR0MASK: | |
776 | val = s->regs[saddr]; | |
777 | dprintf("SERR0MASK %x\n", val); | |
778 | break; | |
779 | ||
780 | /* Reserved when only PCI_0 is configured. */ | |
781 | case GT_HINTRCAUSE: | |
782 | case GT_CPU_INTSEL: | |
783 | case GT_PCI0_INTSEL: | |
784 | case GT_HINTRMASK: | |
785 | case GT_PCI0_HICMASK: | |
786 | case GT_PCI1_SERR1MASK: | |
787 | val = s->regs[saddr]; | |
fde7d5bd TS |
788 | break; |
789 | ||
790 | default: | |
791 | val = s->regs[saddr]; | |
05b4ff43 | 792 | dprintf ("Bad register offset 0x%x\n", (int)addr); |
fde7d5bd TS |
793 | break; |
794 | } | |
795 | ||
0da75eb1 | 796 | #ifdef TARGET_WORDS_BIGENDIAN |
05b4ff43 | 797 | val = bswap32(val); |
0da75eb1 | 798 | #endif |
05b4ff43 | 799 | return val; |
fde7d5bd TS |
800 | } |
801 | ||
802 | static CPUWriteMemoryFunc *gt64120_write[] = { | |
803 | >64120_writel, | |
804 | >64120_writel, | |
805 | >64120_writel, | |
806 | }; | |
807 | ||
808 | static CPUReadMemoryFunc *gt64120_read[] = { | |
809 | >64120_readl, | |
810 | >64120_readl, | |
811 | >64120_readl, | |
812 | }; | |
813 | ||
814 | static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num) | |
815 | { | |
816 | int slot; | |
817 | ||
818 | slot = (pci_dev->devfn >> 3); | |
819 | ||
820 | switch (slot) { | |
821 | /* PIIX4 USB */ | |
822 | case 10: | |
823 | return 3; | |
824 | /* AMD 79C973 Ethernet */ | |
825 | case 11: | |
d4a4d056 | 826 | return 1; |
fde7d5bd TS |
827 | /* Crystal 4281 Sound */ |
828 | case 12: | |
d4a4d056 | 829 | return 2; |
fde7d5bd TS |
830 | /* PCI slot 1 to 4 */ |
831 | case 18 ... 21: | |
832 | return ((slot - 18) + irq_num) & 0x03; | |
833 | /* Unknown device, don't do any translation */ | |
834 | default: | |
835 | return irq_num; | |
836 | } | |
837 | } | |
838 | ||
839 | extern PCIDevice *piix4_dev; | |
840 | static int pci_irq_levels[4]; | |
841 | ||
d537cf6c | 842 | static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level) |
fde7d5bd TS |
843 | { |
844 | int i, pic_irq, pic_level; | |
845 | ||
846 | pci_irq_levels[irq_num] = level; | |
847 | ||
848 | /* now we change the pic irq level according to the piix irq mappings */ | |
849 | /* XXX: optimize */ | |
850 | pic_irq = piix4_dev->config[0x60 + irq_num]; | |
851 | if (pic_irq < 16) { | |
852 | /* The pic level is the logical OR of all the PCI irqs mapped | |
853 | to it */ | |
854 | pic_level = 0; | |
855 | for (i = 0; i < 4; i++) { | |
856 | if (pic_irq == piix4_dev->config[0x60 + i]) | |
857 | pic_level |= pci_irq_levels[i]; | |
858 | } | |
d537cf6c | 859 | qemu_set_irq(pic[pic_irq], pic_level); |
fde7d5bd TS |
860 | } |
861 | } | |
862 | ||
863 | ||
864 | void gt64120_reset(void *opaque) | |
865 | { | |
866 | GT64120State *s = opaque; | |
867 | ||
868 | /* CPU Configuration */ | |
869 | #ifdef TARGET_WORDS_BIGENDIAN | |
870 | s->regs[GT_CPU] = 0x00000000; | |
871 | #else | |
bc687ec9 | 872 | s->regs[GT_CPU] = 0x00001000; |
fde7d5bd TS |
873 | #endif |
874 | s->regs[GT_MULTI] = 0x00000000; | |
875 | ||
876 | /* CPU Address decode FIXME: not complete*/ | |
877 | s->regs[GT_PCI0IOLD] = 0x00000080; | |
878 | s->regs[GT_PCI0IOHD] = 0x0000000f; | |
879 | s->regs[GT_PCI0M0LD] = 0x00000090; | |
880 | s->regs[GT_PCI0M0HD] = 0x0000001f; | |
881 | s->regs[GT_PCI0M1LD] = 0x00000790; | |
882 | s->regs[GT_PCI0M1HD] = 0x0000001f; | |
883 | s->regs[GT_PCI1IOLD] = 0x00000100; | |
884 | s->regs[GT_PCI1IOHD] = 0x0000000f; | |
885 | s->regs[GT_PCI1M0LD] = 0x00000110; | |
886 | s->regs[GT_PCI1M0HD] = 0x0000001f; | |
887 | s->regs[GT_PCI1M1LD] = 0x00000120; | |
888 | s->regs[GT_PCI1M1HD] = 0x0000002f; | |
889 | s->regs[GT_PCI0IOREMAP] = 0x00000080; | |
890 | s->regs[GT_PCI0M0REMAP] = 0x00000090; | |
891 | s->regs[GT_PCI0M1REMAP] = 0x00000790; | |
892 | s->regs[GT_PCI1IOREMAP] = 0x00000100; | |
893 | s->regs[GT_PCI1M0REMAP] = 0x00000110; | |
894 | s->regs[GT_PCI1M1REMAP] = 0x00000120; | |
895 | ||
896 | /* CPU Error Report */ | |
897 | s->regs[GT_CPUERR_ADDRLO] = 0x00000000; | |
898 | s->regs[GT_CPUERR_ADDRHI] = 0x00000000; | |
899 | s->regs[GT_CPUERR_DATALO] = 0xffffffff; | |
900 | s->regs[GT_CPUERR_DATAHI] = 0xffffffff; | |
901 | s->regs[GT_CPUERR_PARITY] = 0x000000ff; | |
902 | ||
903 | /* ECC */ | |
904 | s->regs[GT_ECC_ERRDATALO] = 0x00000000; | |
905 | s->regs[GT_ECC_ERRDATAHI] = 0x00000000; | |
906 | s->regs[GT_ECC_MEM] = 0x00000000; | |
907 | s->regs[GT_ECC_CALC] = 0x00000000; | |
908 | s->regs[GT_ECC_ERRADDR] = 0x00000000; | |
909 | ||
0da75eb1 TS |
910 | /* SDRAM Parameters */ |
911 | s->regs[GT_SDRAM_B0] = 0x00000005; | |
912 | s->regs[GT_SDRAM_B1] = 0x00000005; | |
913 | s->regs[GT_SDRAM_B2] = 0x00000005; | |
914 | s->regs[GT_SDRAM_B3] = 0x00000005; | |
915 | ||
fde7d5bd TS |
916 | /* PCI Internal FIXME: not complete*/ |
917 | #ifdef TARGET_WORDS_BIGENDIAN | |
918 | s->regs[GT_PCI0_CMD] = 0x00000000; | |
919 | s->regs[GT_PCI1_CMD] = 0x00000000; | |
920 | #else | |
921 | s->regs[GT_PCI0_CMD] = 0x00010001; | |
922 | s->regs[GT_PCI1_CMD] = 0x00010001; | |
923 | #endif | |
924 | s->regs[GT_PCI0_IACK] = 0x00000000; | |
925 | s->regs[GT_PCI1_IACK] = 0x00000000; | |
926 | ||
927 | gt64120_pci_mapping(s); | |
928 | } | |
929 | ||
bc687ec9 TS |
930 | static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len) |
931 | { | |
932 | uint32_t val = pci_default_read_config(d, address, len); | |
933 | #ifdef TARGET_WORDS_BIGENDIAN | |
934 | val = bswap32(val); | |
935 | #endif | |
936 | return val; | |
937 | } | |
938 | ||
939 | static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val, | |
940 | int len) | |
941 | { | |
942 | #ifdef TARGET_WORDS_BIGENDIAN | |
943 | val = bswap32(val); | |
944 | #endif | |
945 | pci_default_write_config(d, address, val, len); | |
946 | } | |
947 | ||
d537cf6c | 948 | PCIBus *pci_gt64120_init(qemu_irq *pic) |
fde7d5bd TS |
949 | { |
950 | GT64120State *s; | |
951 | PCIDevice *d; | |
952 | int gt64120; | |
953 | ||
954 | s = qemu_mallocz(sizeof(GT64120State)); | |
955 | s->pci = qemu_mallocz(sizeof(GT64120PCIState)); | |
956 | gt64120_reset(s); | |
957 | ||
958 | s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq, | |
959 | pic, 144, 4); | |
960 | ||
961 | gt64120 = cpu_register_io_memory(0, gt64120_read, | |
962 | gt64120_write, s); | |
963 | cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120); | |
964 | ||
965 | d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), | |
bc687ec9 | 966 | 0, gt64120_read_config, gt64120_write_config); |
fde7d5bd TS |
967 | |
968 | d->config[0x00] = 0xab; // vendor_id | |
969 | d->config[0x01] = 0x11; | |
bc687ec9 TS |
970 | d->config[0x02] = 0x20; // device_id |
971 | d->config[0x03] = 0x46; | |
fde7d5bd TS |
972 | d->config[0x04] = 0x06; |
973 | d->config[0x05] = 0x00; | |
974 | d->config[0x06] = 0x80; | |
975 | d->config[0x07] = 0xa2; | |
976 | d->config[0x08] = 0x10; | |
977 | d->config[0x09] = 0x00; | |
978 | d->config[0x0A] = 0x80; | |
979 | d->config[0x0B] = 0x05; | |
980 | d->config[0x0C] = 0x08; | |
981 | d->config[0x0D] = 0x40; | |
982 | d->config[0x0E] = 0x00; | |
983 | d->config[0x0F] = 0x00; | |
984 | d->config[0x17] = 0x08; | |
985 | d->config[0x1B] = 0x1c; | |
986 | d->config[0x1F] = 0x1f; | |
987 | d->config[0x23] = 0x14; | |
988 | d->config[0x27] = 0x14; | |
989 | d->config[0x3D] = 0x01; | |
990 | ||
991 | return s->pci->bus; | |
992 | } |