[qemu.git] / hw / gt64xxx.c

/*
 * QEMU GT64120 PCI host
 *
 * Copyright (c) 2006,2007 Aurelien Jarno
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "vl.h"
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"

#define GT_REGS			(0x1000 >> 2)

/* CPU Configuration */
#define GT_CPU    		(0x000 >> 2)
#define GT_MULTI    		(0x120 >> 2)

/* CPU Address Decode */
#define GT_SCS10LD    		(0x008 >> 2)
#define GT_SCS10HD    		(0x010 >> 2)
#define GT_SCS32LD    		(0x018 >> 2)
#define GT_SCS32HD    		(0x020 >> 2)
#define GT_CS20LD    		(0x028 >> 2)
#define GT_CS20HD    		(0x030 >> 2)
#define GT_CS3BOOTLD    	(0x038 >> 2)
#define GT_CS3BOOTHD    	(0x040 >> 2)
#define GT_PCI0IOLD    		(0x048 >> 2)
#define GT_PCI0IOHD    		(0x050 >> 2)
#define GT_PCI0M0LD    		(0x058 >> 2)
#define GT_PCI0M0HD    		(0x060 >> 2)
#define GT_ISD    		(0x068 >> 2)

#define GT_PCI0M1LD    		(0x080 >> 2)
#define GT_PCI0M1HD    		(0x088 >> 2)
#define GT_PCI1IOLD    		(0x090 >> 2)
#define GT_PCI1IOHD    		(0x098 >> 2)
#define GT_PCI1M0LD    		(0x0a0 >> 2)
#define GT_PCI1M0HD    		(0x0a8 >> 2)
#define GT_PCI1M1LD    		(0x0b0 >> 2)
#define GT_PCI1M1HD    		(0x0b8 >> 2)
#define GT_PCI1M1LD    		(0x0b0 >> 2)
#define GT_PCI1M1HD    		(0x0b8 >> 2)

#define GT_SCS10AR    		(0x0d0 >> 2)
#define GT_SCS32AR    		(0x0d8 >> 2)
#define GT_CS20R    		(0x0e0 >> 2)
#define GT_CS3BOOTR    		(0x0e8 >> 2)

#define GT_PCI0IOREMAP    	(0x0f0 >> 2)
#define GT_PCI0M0REMAP    	(0x0f8 >> 2)
#define GT_PCI0M1REMAP    	(0x100 >> 2)
#define GT_PCI1IOREMAP    	(0x108 >> 2)
#define GT_PCI1M0REMAP    	(0x110 >> 2)
#define GT_PCI1M1REMAP    	(0x118 >> 2)

/* CPU Error Report */
#define GT_CPUERR_ADDRLO    	(0x070 >> 2)
#define GT_CPUERR_ADDRHI    	(0x078 >> 2)
#define GT_CPUERR_DATALO    	(0x128 >> 2)		/* GT-64120A only  */
#define GT_CPUERR_DATAHI    	(0x130 >> 2)		/* GT-64120A only  */
#define GT_CPUERR_PARITY    	(0x138 >> 2)		/* GT-64120A only  */

/* CPU Sync Barrier */
#define GT_PCI0SYNC    		(0x0c0 >> 2)
#define GT_PCI1SYNC    		(0x0c8 >> 2)

/* SDRAM and Device Address Decode */
#define GT_SCS0LD    		(0x400 >> 2)
#define GT_SCS0HD    		(0x404 >> 2)
#define GT_SCS1LD    		(0x408 >> 2)
#define GT_SCS1HD    		(0x40c >> 2)
#define GT_SCS2LD    		(0x410 >> 2)
#define GT_SCS2HD    		(0x414 >> 2)
#define GT_SCS3LD    		(0x418 >> 2)
#define GT_SCS3HD    		(0x41c >> 2)
#define GT_CS0LD    		(0x420 >> 2)
#define GT_CS0HD    		(0x424 >> 2)
#define GT_CS1LD    		(0x428 >> 2)
#define GT_CS1HD    		(0x42c >> 2)
#define GT_CS2LD    		(0x430 >> 2)
#define GT_CS2HD    		(0x434 >> 2)
#define GT_CS3LD    		(0x438 >> 2)
#define GT_CS3HD    		(0x43c >> 2)
#define GT_BOOTLD    		(0x440 >> 2)
#define GT_BOOTHD    		(0x444 >> 2)
#define GT_ADERR    		(0x470 >> 2)

/* SDRAM Configuration */
#define GT_SDRAM_CFG    	(0x448 >> 2)
#define GT_SDRAM_OPMODE    	(0x474 >> 2)
#define GT_SDRAM_BM    		(0x478 >> 2)
#define GT_SDRAM_ADDRDECODE    	(0x47c >> 2)

/* SDRAM Parameters */
#define GT_SDRAM_B0    		(0x44c >> 2)
#define GT_SDRAM_B1    		(0x450 >> 2)
#define GT_SDRAM_B2    		(0x454 >> 2)
#define GT_SDRAM_B3    		(0x458 >> 2)

/* Device Parameters */
#define GT_DEV_B0    		(0x45c >> 2)
#define GT_DEV_B1    		(0x460 >> 2)
#define GT_DEV_B2    		(0x464 >> 2)
#define GT_DEV_B3    		(0x468 >> 2)
#define GT_DEV_BOOT    		(0x46c >> 2)

/* ECC */
#define GT_ECC_ERRDATALO	(0x480 >> 2)		/* GT-64120A only  */
#define GT_ECC_ERRDATAHI	(0x484 >> 2)		/* GT-64120A only  */
#define GT_ECC_MEM		(0x488 >> 2)		/* GT-64120A only  */
#define GT_ECC_CALC		(0x48c >> 2)		/* GT-64120A only  */
#define GT_ECC_ERRADDR		(0x490 >> 2)		/* GT-64120A only  */

/* DMA Record */
#define GT_DMA0_CNT    		(0x800 >> 2)
#define GT_DMA1_CNT    		(0x804 >> 2)
#define GT_DMA2_CNT    		(0x808 >> 2)
#define GT_DMA3_CNT    		(0x80c >> 2)
#define GT_DMA0_SA    		(0x810 >> 2)
#define GT_DMA1_SA    		(0x814 >> 2)
#define GT_DMA2_SA    		(0x818 >> 2)
#define GT_DMA3_SA    		(0x81c >> 2)
#define GT_DMA0_DA    		(0x820 >> 2)
#define GT_DMA1_DA    		(0x824 >> 2)
#define GT_DMA2_DA    		(0x828 >> 2)
#define GT_DMA3_DA    		(0x82c >> 2)
#define GT_DMA0_NEXT    	(0x830 >> 2)
#define GT_DMA1_NEXT    	(0x834 >> 2)
#define GT_DMA2_NEXT    	(0x838 >> 2)
#define GT_DMA3_NEXT    	(0x83c >> 2)
#define GT_DMA0_CUR    		(0x870 >> 2)
#define GT_DMA1_CUR    		(0x874 >> 2)
#define GT_DMA2_CUR    		(0x878 >> 2)
#define GT_DMA3_CUR    		(0x87c >> 2)

/* DMA Channel Control */
#define GT_DMA0_CTRL    	(0x840 >> 2)
#define GT_DMA1_CTRL    	(0x844 >> 2)
#define GT_DMA2_CTRL    	(0x848 >> 2)
#define GT_DMA3_CTRL    	(0x84c >> 2)

/* DMA Arbiter */
#define GT_DMA_ARB    		(0x860 >> 2)

/* Timer/Counter */
#define GT_TC0    		(0x850 >> 2)
#define GT_TC1    		(0x854 >> 2)
#define GT_TC2    		(0x858 >> 2)
#define GT_TC3    		(0x85c >> 2)
#define GT_TC_CONTROL    	(0x864 >> 2)

/* PCI Internal */
#define GT_PCI0_CMD    		(0xc00 >> 2)
#define GT_PCI0_TOR    		(0xc04 >> 2)
#define GT_PCI0_BS_SCS10    	(0xc08 >> 2)
#define GT_PCI0_BS_SCS32    	(0xc0c >> 2)
#define GT_PCI0_BS_CS20    	(0xc10 >> 2)
#define GT_PCI0_BS_CS3BT    	(0xc14 >> 2)
#define GT_PCI1_IACK    	(0xc30 >> 2)
#define GT_PCI0_IACK    	(0xc34 >> 2)
#define GT_PCI0_BARE    	(0xc3c >> 2)
#define GT_PCI0_PREFMBR    	(0xc40 >> 2)
#define GT_PCI0_SCS10_BAR    	(0xc48 >> 2)
#define GT_PCI0_SCS32_BAR    	(0xc4c >> 2)
#define GT_PCI0_CS20_BAR    	(0xc50 >> 2)
#define GT_PCI0_CS3BT_BAR    	(0xc54 >> 2)
#define GT_PCI0_SSCS10_BAR    	(0xc58 >> 2)
#define GT_PCI0_SSCS32_BAR    	(0xc5c >> 2)
#define GT_PCI0_SCS3BT_BAR    	(0xc64 >> 2)
#define GT_PCI1_CMD    		(0xc80 >> 2)
#define GT_PCI1_TOR    		(0xc84 >> 2)
#define GT_PCI1_BS_SCS10    	(0xc88 >> 2)
#define GT_PCI1_BS_SCS32    	(0xc8c >> 2)
#define GT_PCI1_BS_CS20    	(0xc90 >> 2)
#define GT_PCI1_BS_CS3BT    	(0xc94 >> 2)
#define GT_PCI1_BARE    	(0xcbc >> 2)
#define GT_PCI1_PREFMBR    	(0xcc0 >> 2)
#define GT_PCI1_SCS10_BAR    	(0xcc8 >> 2)
#define GT_PCI1_SCS32_BAR    	(0xccc >> 2)
#define GT_PCI1_CS20_BAR    	(0xcd0 >> 2)
#define GT_PCI1_CS3BT_BAR    	(0xcd4 >> 2)
#define GT_PCI1_SSCS10_BAR    	(0xcd8 >> 2)
#define GT_PCI1_SSCS32_BAR    	(0xcdc >> 2)
#define GT_PCI1_SCS3BT_BAR    	(0xce4 >> 2)
#define GT_PCI1_CFGADDR    	(0xcf0 >> 2)
#define GT_PCI1_CFGDATA    	(0xcf4 >> 2)
#define GT_PCI0_CFGADDR    	(0xcf8 >> 2)
#define GT_PCI0_CFGDATA    	(0xcfc >> 2)

/* Interrupts */
#define GT_INTRCAUSE    	(0xc18 >> 2)
#define GT_INTRMASK    		(0xc1c >> 2)
#define GT_PCI0_ICMASK    	(0xc24 >> 2)
#define GT_PCI0_SERR0MASK    	(0xc28 >> 2)
#define GT_CPU_INTSEL    	(0xc70 >> 2)
#define GT_PCI0_INTSEL    	(0xc74 >> 2)
#define GT_HINTRCAUSE    	(0xc98 >> 2)
#define GT_HINTRMASK    	(0xc9c >> 2)
#define GT_PCI0_HICMASK    	(0xca4 >> 2)
#define GT_PCI1_SERR1MASK    	(0xca8 >> 2)


typedef PCIHostState GT64120PCIState;

typedef struct GT64120State {
    GT64120PCIState *pci;
    uint32_t regs[GT_REGS];
    target_phys_addr_t PCI0IO_start;
    target_phys_addr_t PCI0IO_length;
} GT64120State;

static void gt64120_pci_mapping(GT64120State *s)
{
    /* Update IO mapping */
    if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
    {
      /* Unmap old IO address */	    
      if (s->PCI0IO_length)
      {
        cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);	     
      }
      /* Map new IO address */
      s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
      s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
      isa_mem_base = s->PCI0IO_start;
      isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
    }
}

static void gt64120_writel (void *opaque, target_phys_addr_t addr,
                            uint32_t val)
{
    GT64120State *s = opaque;
    uint32_t saddr;

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    saddr = (addr & 0xfff) >> 2;
    switch (saddr) {

    /* CPU Configuration */
    case GT_CPU:
        s->regs[GT_CPU] = val;
        break;
    case GT_MULTI:
	/* Read-only register as only one GT64xxx is present on the CPU bus */
        break;

    /* CPU Address Decode */
    case GT_PCI0IOLD:
        s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
        s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
        gt64120_pci_mapping(s);
        break;
    case GT_PCI0M0LD:
        s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
        s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
        gt64120_pci_mapping(s);
        break;
    case GT_PCI0M1LD:
        s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
        s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
        gt64120_pci_mapping(s);
        break;
    case GT_PCI1IOLD:
        s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
        s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
        gt64120_pci_mapping(s);
        break;
    case GT_PCI1M0LD:
        s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
        s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
        gt64120_pci_mapping(s);
        break;
    case GT_PCI1M1LD:
        s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
        s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
        gt64120_pci_mapping(s);
        break;
    case GT_PCI0IOHD:
    case GT_PCI0M0HD:
    case GT_PCI0M1HD:
    case GT_PCI1IOHD:
    case GT_PCI1M0HD:
    case GT_PCI1M1HD:
        s->regs[saddr] = val & 0x0000007f;
        gt64120_pci_mapping(s);
        break;
    case GT_PCI0IOREMAP:
    case GT_PCI0M0REMAP:
    case GT_PCI0M1REMAP:
    case GT_PCI1IOREMAP:
    case GT_PCI1M0REMAP:
    case GT_PCI1M1REMAP:
        s->regs[saddr] = val & 0x000007ff;
        gt64120_pci_mapping(s);
        break;

    /* CPU Error Report */
    case GT_CPUERR_ADDRLO:
    case GT_CPUERR_ADDRHI:
    case GT_CPUERR_DATALO:
    case GT_CPUERR_DATAHI:
    case GT_CPUERR_PARITY:
	/* Read-only registers, do nothing */
        break;

    /* CPU Sync Barrier */
    case GT_PCI0SYNC:
    case GT_PCI1SYNC:
	/* Read-only registers, do nothing */
        break;

    /* ECC */
    case GT_ECC_ERRDATALO:
    case GT_ECC_ERRDATAHI:
    case GT_ECC_MEM:
    case GT_ECC_CALC:
    case GT_ECC_ERRADDR:
        /* Read-only registers, do nothing */
        break;

    /* PCI Internal */
    case GT_PCI0_CMD:
    case GT_PCI1_CMD:
        s->regs[saddr] = val & 0x0401fc0f;
        break;
    case GT_PCI0_CFGADDR:
        s->pci->config_reg = val & 0x80fffffc;
        break;
    case GT_PCI0_CFGDATA:
        pci_host_data_writel(s->pci, 0, val);
        break;

    /* SDRAM Parameters */
    case GT_SDRAM_B0:
    case GT_SDRAM_B1:
    case GT_SDRAM_B2:
    case GT_SDRAM_B3:
        /* We don't simulate electrical parameters of the SDRAM.
           Accept, but ignore the values. */
        s->regs[saddr] = val;
        break;

    default:
#if 0
        printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
#endif
        break;
    }
}

static uint32_t gt64120_readl (void *opaque,
                               target_phys_addr_t addr)
{
    GT64120State *s = opaque;
    uint32_t val;
    uint32_t saddr;

    val = 0;
    saddr = (addr & 0xfff) >> 2;

    switch (saddr) {

    /* CPU Configuration */
    case GT_MULTI:
        /* Only one GT64xxx is present on the CPU bus, return
           the initial value */
        val = s->regs[saddr];
        break;

    /* CPU Error Report */
    case GT_CPUERR_ADDRLO:
    case GT_CPUERR_ADDRHI:
    case GT_CPUERR_DATALO:
    case GT_CPUERR_DATAHI:
    case GT_CPUERR_PARITY:
        /* Emulated memory has no error, always return the initial
           values */ 
        val = s->regs[saddr];
        break;

    /* CPU Sync Barrier */
    case GT_PCI0SYNC:
    case GT_PCI1SYNC:
        /* Reading those register should empty all FIFO on the PCI
           bus, which are not emulated. The return value should be
           a random value that should be ignored. */
        val = 0xc000ffee; 
        break;

    /* ECC */
    case GT_ECC_ERRDATALO:
    case GT_ECC_ERRDATAHI:
    case GT_ECC_MEM:
    case GT_ECC_CALC:
    case GT_ECC_ERRADDR:
        /* Emulated memory has no error, always return the initial
           values */ 
        val = s->regs[saddr];
        break;

    case GT_CPU:
    case GT_PCI0IOLD:
    case GT_PCI0M0LD:
    case GT_PCI0M1LD:
    case GT_PCI1IOLD:
    case GT_PCI1M0LD:
    case GT_PCI1M1LD:
    case GT_PCI0IOHD:
    case GT_PCI0M0HD:
    case GT_PCI0M1HD:
    case GT_PCI1IOHD:
    case GT_PCI1M0HD:
    case GT_PCI1M1HD:
    case GT_PCI0_CMD:
    case GT_PCI1_CMD:
    case GT_PCI0IOREMAP:
    case GT_PCI0M0REMAP:
    case GT_PCI0M1REMAP:
    case GT_PCI1IOREMAP:
    case GT_PCI1M0REMAP:
    case GT_PCI1M1REMAP:
        val = s->regs[saddr];
        break;
    case GT_PCI0_IACK:
        /* Read the IRQ number */ 
        val = pic_read_irq(isa_pic);
        break;

    /* SDRAM Parameters */
    case GT_SDRAM_B0:
    case GT_SDRAM_B1:
    case GT_SDRAM_B2:
    case GT_SDRAM_B3:
        /* We don't simulate electrical parameters of the SDRAM.
           Just return the last written value. */
        val = s->regs[saddr];
        break;

    /* PCI Internal */
    case GT_PCI0_CFGADDR:
        val = s->pci->config_reg;
        break;
    case GT_PCI0_CFGDATA:
        val = pci_host_data_readl(s->pci, 0);
        break;

    default:
        val = s->regs[saddr];
#if 0
        printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
#endif
        break;
    }

#ifdef TARGET_WORDS_BIGENDIAN
    return bswap32(val);
#else
    return val;
#endif
}

static CPUWriteMemoryFunc *gt64120_write[] = {
    &gt64120_writel,
    &gt64120_writel,
    &gt64120_writel,
};

static CPUReadMemoryFunc *gt64120_read[] = {
    &gt64120_readl,
    &gt64120_readl,
    &gt64120_readl,
};

static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int slot;

    slot = (pci_dev->devfn >> 3);

    switch (slot) {
      /* PIIX4 USB */
      case 10:
        return 3;
      /* AMD 79C973 Ethernet */
      case 11:
        return 0;
      /* Crystal 4281 Sound */
      case 12:
        return 0;
      /* PCI slot 1 to 4 */
      case 18 ... 21:
        return ((slot - 18) + irq_num) & 0x03;
      /* Unknown device, don't do any translation */
      default:
        return irq_num;
    }
}

extern PCIDevice *piix4_dev;
static int pci_irq_levels[4];

static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
{
    int i, pic_irq, pic_level;

    pci_irq_levels[irq_num] = level;

    /* now we change the pic irq level according to the piix irq mappings */
    /* XXX: optimize */
    pic_irq = piix4_dev->config[0x60 + irq_num];
    if (pic_irq < 16) {
        /* The pic level is the logical OR of all the PCI irqs mapped
           to it */
        pic_level = 0;
        for (i = 0; i < 4; i++) {
            if (pic_irq == piix4_dev->config[0x60 + i])
                pic_level |= pci_irq_levels[i];
        }
        qemu_set_irq(pic[pic_irq], pic_level);
    }
}


void gt64120_reset(void *opaque)
{
    GT64120State *s = opaque;

    /* CPU Configuration */
#ifdef TARGET_WORDS_BIGENDIAN
    s->regs[GT_CPU]           = 0x00000000;
#else
    s->regs[GT_CPU]           = 0x00000800;
#endif
    s->regs[GT_MULTI]         = 0x00000000;

    /* CPU Address decode FIXME: not complete*/
    s->regs[GT_PCI0IOLD]      = 0x00000080;
    s->regs[GT_PCI0IOHD]      = 0x0000000f;
    s->regs[GT_PCI0M0LD]      = 0x00000090;
    s->regs[GT_PCI0M0HD]      = 0x0000001f;
    s->regs[GT_PCI0M1LD]      = 0x00000790;
    s->regs[GT_PCI0M1HD]      = 0x0000001f;
    s->regs[GT_PCI1IOLD]      = 0x00000100;
    s->regs[GT_PCI1IOHD]      = 0x0000000f;
    s->regs[GT_PCI1M0LD]      = 0x00000110;
    s->regs[GT_PCI1M0HD]      = 0x0000001f;
    s->regs[GT_PCI1M1LD]      = 0x00000120;
    s->regs[GT_PCI1M1HD]      = 0x0000002f;
    s->regs[GT_PCI0IOREMAP]   = 0x00000080;
    s->regs[GT_PCI0M0REMAP]   = 0x00000090;
    s->regs[GT_PCI0M1REMAP]   = 0x00000790;
    s->regs[GT_PCI1IOREMAP]   = 0x00000100;
    s->regs[GT_PCI1M0REMAP]   = 0x00000110;
    s->regs[GT_PCI1M1REMAP]   = 0x00000120;

    /* CPU Error Report */
    s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
    s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
    s->regs[GT_CPUERR_DATALO] = 0xffffffff;
    s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
    s->regs[GT_CPUERR_PARITY] = 0x000000ff;

    /* ECC */
    s->regs[GT_ECC_ERRDATALO] = 0x00000000;
    s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
    s->regs[GT_ECC_MEM]       = 0x00000000;
    s->regs[GT_ECC_CALC]      = 0x00000000;
    s->regs[GT_ECC_ERRADDR]   = 0x00000000;

    /* SDRAM Parameters */
    s->regs[GT_SDRAM_B0]      = 0x00000005;    
    s->regs[GT_SDRAM_B1]      = 0x00000005;    
    s->regs[GT_SDRAM_B2]      = 0x00000005;    
    s->regs[GT_SDRAM_B3]      = 0x00000005;    

    /* PCI Internal FIXME: not complete*/
#ifdef TARGET_WORDS_BIGENDIAN
    s->regs[GT_PCI0_CMD]      = 0x00000000;
    s->regs[GT_PCI1_CMD]      = 0x00000000;
#else
    s->regs[GT_PCI0_CMD]      = 0x00010001;
    s->regs[GT_PCI1_CMD]      = 0x00010001;
#endif
    s->regs[GT_PCI0_IACK]     = 0x00000000;
    s->regs[GT_PCI1_IACK]     = 0x00000000;

    gt64120_pci_mapping(s);
}

PCIBus *pci_gt64120_init(qemu_irq *pic)
{
    GT64120State *s;
    PCIDevice *d;
    int gt64120;

    s = qemu_mallocz(sizeof(GT64120State));
    s->pci = qemu_mallocz(sizeof(GT64120PCIState));
    gt64120_reset(s);

    s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
                                   pic, 144, 4);

    gt64120 = cpu_register_io_memory(0, gt64120_read,
                                     gt64120_write, s);
    cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);

    d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
                            0, NULL, NULL);

    d->config[0x00] = 0xab; // vendor_id
    d->config[0x01] = 0x11;
    d->config[0x02] = 0x46; // device_id
    d->config[0x03] = 0x20;
    d->config[0x04] = 0x06;
    d->config[0x05] = 0x00;
    d->config[0x06] = 0x80;
    d->config[0x07] = 0xa2;
    d->config[0x08] = 0x10;
    d->config[0x09] = 0x00;
    d->config[0x0A] = 0x80;
    d->config[0x0B] = 0x05;
    d->config[0x0C] = 0x08;
    d->config[0x0D] = 0x40;
    d->config[0x0E] = 0x00;
    d->config[0x0F] = 0x00;
    d->config[0x17] = 0x08;
    d->config[0x1B] = 0x1c;
    d->config[0x1F] = 0x1f;
    d->config[0x23] = 0x14;
    d->config[0x27] = 0x14;
    d->config[0x3D] = 0x01;

    return s->pci->bus;
}
Commit	Line	Data
fde7d5bd TS	1	/*
	2	* QEMU GT64120 PCI host
	3	*
4de9b249	4	* Copyright (c) 2006,2007 Aurelien Jarno
fde7d5bd TS	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "vl.h"
	26	typedef target_phys_addr_t pci_addr_t;
	27	#include "pci_host.h"
	28
	29	#define GT_REGS (0x1000 >> 2)
	30
	31	/* CPU Configuration */
	32	#define GT_CPU (0x000 >> 2)
	33	#define GT_MULTI (0x120 >> 2)
	34
	35	/* CPU Address Decode */
	36	#define GT_SCS10LD (0x008 >> 2)
	37	#define GT_SCS10HD (0x010 >> 2)
	38	#define GT_SCS32LD (0x018 >> 2)
	39	#define GT_SCS32HD (0x020 >> 2)
	40	#define GT_CS20LD (0x028 >> 2)
	41	#define GT_CS20HD (0x030 >> 2)
	42	#define GT_CS3BOOTLD (0x038 >> 2)
	43	#define GT_CS3BOOTHD (0x040 >> 2)
	44	#define GT_PCI0IOLD (0x048 >> 2)
	45	#define GT_PCI0IOHD (0x050 >> 2)
	46	#define GT_PCI0M0LD (0x058 >> 2)
	47	#define GT_PCI0M0HD (0x060 >> 2)
	48	#define GT_ISD (0x068 >> 2)
	49
	50	#define GT_PCI0M1LD (0x080 >> 2)
	51	#define GT_PCI0M1HD (0x088 >> 2)
	52	#define GT_PCI1IOLD (0x090 >> 2)
	53	#define GT_PCI1IOHD (0x098 >> 2)
	54	#define GT_PCI1M0LD (0x0a0 >> 2)
	55	#define GT_PCI1M0HD (0x0a8 >> 2)
	56	#define GT_PCI1M1LD (0x0b0 >> 2)
	57	#define GT_PCI1M1HD (0x0b8 >> 2)
	58	#define GT_PCI1M1LD (0x0b0 >> 2)
	59	#define GT_PCI1M1HD (0x0b8 >> 2)
	60
	61	#define GT_SCS10AR (0x0d0 >> 2)
	62	#define GT_SCS32AR (0x0d8 >> 2)
	63	#define GT_CS20R (0x0e0 >> 2)
	64	#define GT_CS3BOOTR (0x0e8 >> 2)
	65
	66	#define GT_PCI0IOREMAP (0x0f0 >> 2)
	67	#define GT_PCI0M0REMAP (0x0f8 >> 2)
	68	#define GT_PCI0M1REMAP (0x100 >> 2)
69	#define GT_PCI1IOREMAP (0x108 >> 2)
70	#define GT_PCI1M0REMAP (0x110 >> 2)
71	#define GT_PCI1M1REMAP (0x118 >> 2)
72
73	/* CPU Error Report */
74	#define GT_CPUERR_ADDRLO (0x070 >> 2)
75	#define GT_CPUERR_ADDRHI (0x078 >> 2)
76	#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
77	#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
78	#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
79
80	/* CPU Sync Barrier */
81	#define GT_PCI0SYNC (0x0c0 >> 2)
82	#define GT_PCI1SYNC (0x0c8 >> 2)
83
84	/* SDRAM and Device Address Decode */
85	#define GT_SCS0LD (0x400 >> 2)
86	#define GT_SCS0HD (0x404 >> 2)
87	#define GT_SCS1LD (0x408 >> 2)
88	#define GT_SCS1HD (0x40c >> 2)
89	#define GT_SCS2LD (0x410 >> 2)
90	#define GT_SCS2HD (0x414 >> 2)
91	#define GT_SCS3LD (0x418 >> 2)
92	#define GT_SCS3HD (0x41c >> 2)
93	#define GT_CS0LD (0x420 >> 2)
94	#define GT_CS0HD (0x424 >> 2)
95	#define GT_CS1LD (0x428 >> 2)
96	#define GT_CS1HD (0x42c >> 2)
97	#define GT_CS2LD (0x430 >> 2)
98	#define GT_CS2HD (0x434 >> 2)
99	#define GT_CS3LD (0x438 >> 2)
100	#define GT_CS3HD (0x43c >> 2)
101	#define GT_BOOTLD (0x440 >> 2)
102	#define GT_BOOTHD (0x444 >> 2)
103	#define GT_ADERR (0x470 >> 2)
104
105	/* SDRAM Configuration */
106	#define GT_SDRAM_CFG (0x448 >> 2)
107	#define GT_SDRAM_OPMODE (0x474 >> 2)
108	#define GT_SDRAM_BM (0x478 >> 2)
109	#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
110
111	/* SDRAM Parameters */
112	#define GT_SDRAM_B0 (0x44c >> 2)
113	#define GT_SDRAM_B1 (0x450 >> 2)
114	#define GT_SDRAM_B2 (0x454 >> 2)
115	#define GT_SDRAM_B3 (0x458 >> 2)
116
117	/* Device Parameters */
118	#define GT_DEV_B0 (0x45c >> 2)
119	#define GT_DEV_B1 (0x460 >> 2)
120	#define GT_DEV_B2 (0x464 >> 2)
121	#define GT_DEV_B3 (0x468 >> 2)
122	#define GT_DEV_BOOT (0x46c >> 2)
123
124	/* ECC */
125	#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
126	#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
127	#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
128	#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
129	#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
130
131	/* DMA Record */
132	#define GT_DMA0_CNT (0x800 >> 2)
133	#define GT_DMA1_CNT (0x804 >> 2)
134	#define GT_DMA2_CNT (0x808 >> 2)
135	#define GT_DMA3_CNT (0x80c >> 2)
136	#define GT_DMA0_SA (0x810 >> 2)
137	#define GT_DMA1_SA (0x814 >> 2)
138	#define GT_DMA2_SA (0x818 >> 2)
139	#define GT_DMA3_SA (0x81c >> 2)
140	#define GT_DMA0_DA (0x820 >> 2)
141	#define GT_DMA1_DA (0x824 >> 2)
142	#define GT_DMA2_DA (0x828 >> 2)
143	#define GT_DMA3_DA (0x82c >> 2)
144	#define GT_DMA0_NEXT (0x830 >> 2)
145	#define GT_DMA1_NEXT (0x834 >> 2)
146	#define GT_DMA2_NEXT (0x838 >> 2)
147	#define GT_DMA3_NEXT (0x83c >> 2)
148	#define GT_DMA0_CUR (0x870 >> 2)
149	#define GT_DMA1_CUR (0x874 >> 2)
150	#define GT_DMA2_CUR (0x878 >> 2)
151	#define GT_DMA3_CUR (0x87c >> 2)
152
153	/* DMA Channel Control */
154	#define GT_DMA0_CTRL (0x840 >> 2)
155	#define GT_DMA1_CTRL (0x844 >> 2)
156	#define GT_DMA2_CTRL (0x848 >> 2)
157	#define GT_DMA3_CTRL (0x84c >> 2)
158
159	/* DMA Arbiter */
160	#define GT_DMA_ARB (0x860 >> 2)
161
162	/* Timer/Counter */
163	#define GT_TC0 (0x850 >> 2)
164	#define GT_TC1 (0x854 >> 2)
165	#define GT_TC2 (0x858 >> 2)
166	#define GT_TC3 (0x85c >> 2)
167	#define GT_TC_CONTROL (0x864 >> 2)
168
169	/* PCI Internal */
170	#define GT_PCI0_CMD (0xc00 >> 2)
171	#define GT_PCI0_TOR (0xc04 >> 2)
172	#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
173	#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
174	#define GT_PCI0_BS_CS20 (0xc10 >> 2)
175	#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
176	#define GT_PCI1_IACK (0xc30 >> 2)
177	#define GT_PCI0_IACK (0xc34 >> 2)
178	#define GT_PCI0_BARE (0xc3c >> 2)
179	#define GT_PCI0_PREFMBR (0xc40 >> 2)
180	#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
181	#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
182	#define GT_PCI0_CS20_BAR (0xc50 >> 2)
183	#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
184	#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
185	#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
186	#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
187	#define GT_PCI1_CMD (0xc80 >> 2)
188	#define GT_PCI1_TOR (0xc84 >> 2)
189	#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
190	#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
191	#define GT_PCI1_BS_CS20 (0xc90 >> 2)
192	#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
193	#define GT_PCI1_BARE (0xcbc >> 2)
194	#define GT_PCI1_PREFMBR (0xcc0 >> 2)
195	#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
196	#define GT_PCI1_SCS32_BAR (0xccc >> 2)
197	#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
198	#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
199	#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
200	#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
201	#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
202	#define GT_PCI1_CFGADDR (0xcf0 >> 2)
203	#define GT_PCI1_CFGDATA (0xcf4 >> 2)
204	#define GT_PCI0_CFGADDR (0xcf8 >> 2)
205	#define GT_PCI0_CFGDATA (0xcfc >> 2)
206
207	/* Interrupts */
208	#define GT_INTRCAUSE (0xc18 >> 2)
209	#define GT_INTRMASK (0xc1c >> 2)
210	#define GT_PCI0_ICMASK (0xc24 >> 2)
211	#define GT_PCI0_SERR0MASK (0xc28 >> 2)
212	#define GT_CPU_INTSEL (0xc70 >> 2)
213	#define GT_PCI0_INTSEL (0xc74 >> 2)
214	#define GT_HINTRCAUSE (0xc98 >> 2)
215	#define GT_HINTRMASK (0xc9c >> 2)
216	#define GT_PCI0_HICMASK (0xca4 >> 2)
217	#define GT_PCI1_SERR1MASK (0xca8 >> 2)
218
219
220	typedef PCIHostState GT64120PCIState;
221
222	typedef struct GT64120State {
223	GT64120PCIState *pci;
224	uint32_t regs[GT_REGS];
35f1de31 TS	225	target_phys_addr_t PCI0IO_start;
35f1de31 TS	226	target_phys_addr_t PCI0IO_length;
fde7d5bd TS	227	} GT64120State;
	228
	229	static void gt64120_pci_mapping(GT64120State *s)
	230	{
fde7d5bd	231	/* Update IO mapping */
90e950d1 TS	232	if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
90e950d1 TS	233	{
35f1de31 TS	234	/* Unmap old IO address */
	235	if (s->PCI0IO_length)
	236	{
	237	cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
	238	}
	239	/* Map new IO address */
	240	s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
	241	s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
11f29511	242	isa_mem_base = s->PCI0IO_start;
35f1de31	243	isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
90e950d1	244	}
fde7d5bd TS	245	}
	246
	247	static void gt64120_writel (void *opaque, target_phys_addr_t addr,
	248	uint32_t val)
	249	{
	250	GT64120State *s = opaque;
	251	uint32_t saddr;
	252
0da75eb1 TS	253	#ifdef TARGET_WORDS_BIGENDIAN
	254	val = bswap32(val);
	255	#endif
	256
fde7d5bd TS	257	saddr = (addr & 0xfff) >> 2;
fde7d5bd TS	258	switch (saddr) {
0da75eb1 TS	259
0da75eb1 TS	260	/* CPU Configuration */
fde7d5bd TS	261	case GT_CPU:
fde7d5bd TS	262	s->regs[GT_CPU] = val;
fde7d5bd TS	263	break;
fde7d5bd TS	264	case GT_MULTI:
0da75eb1	265	/* Read-only register as only one GT64xxx is present on the CPU bus */
fde7d5bd TS	266	break;
	267
	268	/* CPU Address Decode */
	269	case GT_PCI0IOLD:
	270	s->regs[GT_PCI0IOLD] = val & 0x00007fff;
	271	s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
	272	gt64120_pci_mapping(s);
	273	break;
	274	case GT_PCI0M0LD:
	275	s->regs[GT_PCI0M0LD] = val & 0x00007fff;
	276	s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
	277	gt64120_pci_mapping(s);
	278	break;
	279	case GT_PCI0M1LD:
	280	s->regs[GT_PCI0M1LD] = val & 0x00007fff;
	281	s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
	282	gt64120_pci_mapping(s);
	283	break;
	284	case GT_PCI1IOLD:
	285	s->regs[GT_PCI1IOLD] = val & 0x00007fff;
	286	s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
	287	gt64120_pci_mapping(s);
	288	break;
	289	case GT_PCI1M0LD:
	290	s->regs[GT_PCI1M0LD] = val & 0x00007fff;
	291	s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
	292	gt64120_pci_mapping(s);
	293	break;
	294	case GT_PCI1M1LD:
	295	s->regs[GT_PCI1M1LD] = val & 0x00007fff;
	296	s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
	297	gt64120_pci_mapping(s);
	298	break;
	299	case GT_PCI0IOHD:
	300	case GT_PCI0M0HD:
	301	case GT_PCI0M1HD:
	302	case GT_PCI1IOHD:
	303	case GT_PCI1M0HD:
	304	case GT_PCI1M1HD:
	305	s->regs[saddr] = val & 0x0000007f;
	306	gt64120_pci_mapping(s);
	307	break;
	308	case GT_PCI0IOREMAP:
	309	case GT_PCI0M0REMAP:
	310	case GT_PCI0M1REMAP:
	311	case GT_PCI1IOREMAP:
	312	case GT_PCI1M0REMAP:
	313	case GT_PCI1M1REMAP:
	314	s->regs[saddr] = val & 0x000007ff;
	315	gt64120_pci_mapping(s);
	316	break;
	317
	318	/* CPU Error Report */
	319	case GT_CPUERR_ADDRLO:
	320	case GT_CPUERR_ADDRHI:
	321	case GT_CPUERR_DATALO:
	322	case GT_CPUERR_DATAHI:
	323	case GT_CPUERR_PARITY:
0da75eb1 TS	324	/* Read-only registers, do nothing */
	325	break;
	326
	327	/* CPU Sync Barrier */
	328	case GT_PCI0SYNC:
	329	case GT_PCI1SYNC:
	330	/* Read-only registers, do nothing */
fde7d5bd TS	331	break;
	332
	333	/* ECC */
	334	case GT_ECC_ERRDATALO:
	335	case GT_ECC_ERRDATAHI:
	336	case GT_ECC_MEM:
	337	case GT_ECC_CALC:
	338	case GT_ECC_ERRADDR:
0da75eb1	339	/* Read-only registers, do nothing */
fde7d5bd TS	340	break;
	341
	342	/* PCI Internal */
	343	case GT_PCI0_CMD:
	344	case GT_PCI1_CMD:
	345	s->regs[saddr] = val & 0x0401fc0f;
	346	break;
	347	case GT_PCI0_CFGADDR:
	348	s->pci->config_reg = val & 0x80fffffc;
	349	break;
	350	case GT_PCI0_CFGDATA:
	351	pci_host_data_writel(s->pci, 0, val);
	352	break;
	353
0da75eb1 TS	354	/* SDRAM Parameters */
	355	case GT_SDRAM_B0:
	356	case GT_SDRAM_B1:
	357	case GT_SDRAM_B2:
	358	case GT_SDRAM_B3:
	359	/* We don't simulate electrical parameters of the SDRAM.
	360	Accept, but ignore the values. */
	361	s->regs[saddr] = val;
	362	break;
	363
fde7d5bd TS	364	default:
	365	#if 0
	366	printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
	367	#endif
	368	break;
	369	}
	370	}
	371
	372	static uint32_t gt64120_readl (void *opaque,
	373	target_phys_addr_t addr)
	374	{
	375	GT64120State *s = opaque;
	376	uint32_t val;
	377	uint32_t saddr;
	378
	379	val = 0;
	380	saddr = (addr & 0xfff) >> 2;
	381
	382	switch (saddr) {
	383
0da75eb1 TS	384	/* CPU Configuration */
	385	case GT_MULTI:
	386	/* Only one GT64xxx is present on the CPU bus, return
	387	the initial value */
	388	val = s->regs[saddr];
	389	break;
	390
fde7d5bd TS	391	/* CPU Error Report */
	392	case GT_CPUERR_ADDRLO:
	393	case GT_CPUERR_ADDRHI:
	394	case GT_CPUERR_DATALO:
	395	case GT_CPUERR_DATAHI:
	396	case GT_CPUERR_PARITY:
0da75eb1 TS	397	/* Emulated memory has no error, always return the initial
	398	values */
	399	val = s->regs[saddr];
	400	break;
	401
	402	/* CPU Sync Barrier */
	403	case GT_PCI0SYNC:
	404	case GT_PCI1SYNC:
	405	/* Reading those register should empty all FIFO on the PCI
	406	bus, which are not emulated. The return value should be
	407	a random value that should be ignored. */
	408	val = 0xc000ffee;
fde7d5bd TS	409	break;
	410
	411	/* ECC */
	412	case GT_ECC_ERRDATALO:
	413	case GT_ECC_ERRDATAHI:
	414	case GT_ECC_MEM:
	415	case GT_ECC_CALC:
	416	case GT_ECC_ERRADDR:
0da75eb1 TS	417	/* Emulated memory has no error, always return the initial
	418	values */
	419	val = s->regs[saddr];
fde7d5bd TS	420	break;
	421
	422	case GT_CPU:
fde7d5bd TS	423	case GT_PCI0IOLD:
	424	case GT_PCI0M0LD:
	425	case GT_PCI0M1LD:
	426	case GT_PCI1IOLD:
	427	case GT_PCI1M0LD:
	428	case GT_PCI1M1LD:
	429	case GT_PCI0IOHD:
	430	case GT_PCI0M0HD:
	431	case GT_PCI0M1HD:
	432	case GT_PCI1IOHD:
	433	case GT_PCI1M0HD:
	434	case GT_PCI1M1HD:
	435	case GT_PCI0_CMD:
	436	case GT_PCI1_CMD:
	437	case GT_PCI0IOREMAP:
	438	case GT_PCI0M0REMAP:
	439	case GT_PCI0M1REMAP:
	440	case GT_PCI1IOREMAP:
	441	case GT_PCI1M0REMAP:
	442	case GT_PCI1M1REMAP:
	443	val = s->regs[saddr];
	444	break;
	445	case GT_PCI0_IACK:
4de9b249 TS	446	/* Read the IRQ number */
4de9b249 TS	447	val = pic_read_irq(isa_pic);
fde7d5bd TS	448	break;
fde7d5bd TS	449
0da75eb1 TS	450	/* SDRAM Parameters */
	451	case GT_SDRAM_B0:
	452	case GT_SDRAM_B1:
	453	case GT_SDRAM_B2:
	454	case GT_SDRAM_B3:
	455	/* We don't simulate electrical parameters of the SDRAM.
	456	Just return the last written value. */
	457	val = s->regs[saddr];
	458	break;
	459
fde7d5bd TS	460	/* PCI Internal */
	461	case GT_PCI0_CFGADDR:
	462	val = s->pci->config_reg;
	463	break;
	464	case GT_PCI0_CFGDATA:
	465	val = pci_host_data_readl(s->pci, 0);
	466	break;
	467
	468	default:
	469	val = s->regs[saddr];
	470	#if 0
	471	printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
	472	#endif
	473	break;
	474	}
	475
0da75eb1 TS	476	#ifdef TARGET_WORDS_BIGENDIAN
	477	return bswap32(val);
	478	#else
fde7d5bd	479	return val;
0da75eb1	480	#endif
fde7d5bd TS	481	}
	482
	483	static CPUWriteMemoryFunc *gt64120_write[] = {
	484	&gt64120_writel,
	485	&gt64120_writel,
	486	&gt64120_writel,
	487	};
	488
	489	static CPUReadMemoryFunc *gt64120_read[] = {
	490	&gt64120_readl,
	491	&gt64120_readl,
	492	&gt64120_readl,
	493	};
	494
	495	static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
	496	{
	497	int slot;
	498
	499	slot = (pci_dev->devfn >> 3);
	500
	501	switch (slot) {
	502	/* PIIX4 USB */
	503	case 10:
	504	return 3;
	505	/* AMD 79C973 Ethernet */
	506	case 11:
	507	return 0;
	508	/* Crystal 4281 Sound */
	509	case 12:
	510	return 0;
	511	/* PCI slot 1 to 4 */
	512	case 18 ... 21:
	513	return ((slot - 18) + irq_num) & 0x03;
	514	/* Unknown device, don't do any translation */
	515	default:
	516	return irq_num;
	517	}
	518	}
	519
	520	extern PCIDevice *piix4_dev;
	521	static int pci_irq_levels[4];
	522
d537cf6c	523	static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
fde7d5bd TS	524	{
	525	int i, pic_irq, pic_level;
	526
	527	pci_irq_levels[irq_num] = level;
	528
	529	/* now we change the pic irq level according to the piix irq mappings */
	530	/* XXX: optimize */
	531	pic_irq = piix4_dev->config[0x60 + irq_num];
	532	if (pic_irq < 16) {
	533	/* The pic level is the logical OR of all the PCI irqs mapped
	534	to it */
	535	pic_level = 0;
	536	for (i = 0; i < 4; i++) {
	537	if (pic_irq == piix4_dev->config[0x60 + i])
	538	pic_level \|= pci_irq_levels[i];
	539	}
d537cf6c	540	qemu_set_irq(pic[pic_irq], pic_level);
fde7d5bd TS	541	}
	542	}
	543
	544
	545	void gt64120_reset(void *opaque)
	546	{
	547	GT64120State *s = opaque;
	548
	549	/* CPU Configuration */
	550	#ifdef TARGET_WORDS_BIGENDIAN
	551	s->regs[GT_CPU] = 0x00000000;
	552	#else
	553	s->regs[GT_CPU] = 0x00000800;
	554	#endif
	555	s->regs[GT_MULTI] = 0x00000000;
	556
	557	/* CPU Address decode FIXME: not complete*/
	558	s->regs[GT_PCI0IOLD] = 0x00000080;
	559	s->regs[GT_PCI0IOHD] = 0x0000000f;
	560	s->regs[GT_PCI0M0LD] = 0x00000090;
	561	s->regs[GT_PCI0M0HD] = 0x0000001f;
	562	s->regs[GT_PCI0M1LD] = 0x00000790;
	563	s->regs[GT_PCI0M1HD] = 0x0000001f;
	564	s->regs[GT_PCI1IOLD] = 0x00000100;
	565	s->regs[GT_PCI1IOHD] = 0x0000000f;
	566	s->regs[GT_PCI1M0LD] = 0x00000110;
	567	s->regs[GT_PCI1M0HD] = 0x0000001f;
	568	s->regs[GT_PCI1M1LD] = 0x00000120;
	569	s->regs[GT_PCI1M1HD] = 0x0000002f;
	570	s->regs[GT_PCI0IOREMAP] = 0x00000080;
	571	s->regs[GT_PCI0M0REMAP] = 0x00000090;
	572	s->regs[GT_PCI0M1REMAP] = 0x00000790;
	573	s->regs[GT_PCI1IOREMAP] = 0x00000100;
	574	s->regs[GT_PCI1M0REMAP] = 0x00000110;
	575	s->regs[GT_PCI1M1REMAP] = 0x00000120;
	576
	577	/* CPU Error Report */
	578	s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
	579	s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
	580	s->regs[GT_CPUERR_DATALO] = 0xffffffff;
	581	s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
	582	s->regs[GT_CPUERR_PARITY] = 0x000000ff;
	583
	584	/* ECC */
	585	s->regs[GT_ECC_ERRDATALO] = 0x00000000;
	586	s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
	587	s->regs[GT_ECC_MEM] = 0x00000000;
	588	s->regs[GT_ECC_CALC] = 0x00000000;
	589	s->regs[GT_ECC_ERRADDR] = 0x00000000;
	590
0da75eb1 TS	591	/* SDRAM Parameters */
	592	s->regs[GT_SDRAM_B0] = 0x00000005;
	593	s->regs[GT_SDRAM_B1] = 0x00000005;
	594	s->regs[GT_SDRAM_B2] = 0x00000005;
	595	s->regs[GT_SDRAM_B3] = 0x00000005;
	596
fde7d5bd TS	597	/* PCI Internal FIXME: not complete*/
	598	#ifdef TARGET_WORDS_BIGENDIAN
	599	s->regs[GT_PCI0_CMD] = 0x00000000;
	600	s->regs[GT_PCI1_CMD] = 0x00000000;
	601	#else
	602	s->regs[GT_PCI0_CMD] = 0x00010001;
	603	s->regs[GT_PCI1_CMD] = 0x00010001;
	604	#endif
	605	s->regs[GT_PCI0_IACK] = 0x00000000;
	606	s->regs[GT_PCI1_IACK] = 0x00000000;
	607
	608	gt64120_pci_mapping(s);
	609	}
	610
d537cf6c	611	PCIBus pci_gt64120_init(qemu_irq pic)
fde7d5bd TS	612	{
	613	GT64120State *s;
	614	PCIDevice *d;
	615	int gt64120;
	616
	617	s = qemu_mallocz(sizeof(GT64120State));
	618	s->pci = qemu_mallocz(sizeof(GT64120PCIState));
	619	gt64120_reset(s);
	620
	621	s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
	622	pic, 144, 4);
	623
	624	gt64120 = cpu_register_io_memory(0, gt64120_read,
	625	gt64120_write, s);
	626	cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);
	627
	628	d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
	629	0, NULL, NULL);
	630
	631	d->config[0x00] = 0xab; // vendor_id
	632	d->config[0x01] = 0x11;
	633	d->config[0x02] = 0x46; // device_id
	634	d->config[0x03] = 0x20;
	635	d->config[0x04] = 0x06;
	636	d->config[0x05] = 0x00;
	637	d->config[0x06] = 0x80;
	638	d->config[0x07] = 0xa2;
	639	d->config[0x08] = 0x10;
	640	d->config[0x09] = 0x00;
	641	d->config[0x0A] = 0x80;
	642	d->config[0x0B] = 0x05;
	643	d->config[0x0C] = 0x08;
	644	d->config[0x0D] = 0x40;
	645	d->config[0x0E] = 0x00;
	646	d->config[0x0F] = 0x00;
	647	d->config[0x17] = 0x08;
	648	d->config[0x1B] = 0x1c;
	649	d->config[0x1F] = 0x1f;
	650	d->config[0x23] = 0x14;
	651	d->config[0x27] = 0x14;
	652	d->config[0x3D] = 0x01;
	653
	654	return s->pci->bus;
	655	}