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fde7d5bd
TS		 1/*
2 * QEMU GT64120 PCI host
3 *
4de9b249 4 * Copyright (c) 2006,2007 Aurelien Jarno
fde7d5bd
TS		 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "vl.h"
05b4ff43 26
fde7d5bd
TS		 27typedef target_phys_addr_t pci_addr_t;
28#include "pci_host.h"
29
05b4ff43
TS		 30//#define DEBUG
31
32#ifdef DEBUG
33#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
34#else
35#define dprintf(fmt, ...)
36#endif
37
fde7d5bd
TS		 38#define GT_REGS (0x1000 >> 2)
39
40/* CPU Configuration */
41#define GT_CPU (0x000 >> 2)
42#define GT_MULTI (0x120 >> 2)
43
44/* CPU Address Decode */
45#define GT_SCS10LD (0x008 >> 2)
46#define GT_SCS10HD (0x010 >> 2)
47#define GT_SCS32LD (0x018 >> 2)
48#define GT_SCS32HD (0x020 >> 2)
49#define GT_CS20LD (0x028 >> 2)
50#define GT_CS20HD (0x030 >> 2)
51#define GT_CS3BOOTLD (0x038 >> 2)
52#define GT_CS3BOOTHD (0x040 >> 2)
53#define GT_PCI0IOLD (0x048 >> 2)
54#define GT_PCI0IOHD (0x050 >> 2)
55#define GT_PCI0M0LD (0x058 >> 2)
56#define GT_PCI0M0HD (0x060 >> 2)
fde7d5bd
TS		 57#define GT_PCI0M1LD (0x080 >> 2)
58#define GT_PCI0M1HD (0x088 >> 2)
59#define GT_PCI1IOLD (0x090 >> 2)
60#define GT_PCI1IOHD (0x098 >> 2)
61#define GT_PCI1M0LD (0x0a0 >> 2)
62#define GT_PCI1M0HD (0x0a8 >> 2)
63#define GT_PCI1M1LD (0x0b0 >> 2)
64#define GT_PCI1M1HD (0x0b8 >> 2)
05b4ff43 65#define GT_ISD (0x068 >> 2)
fde7d5bd
TS		 66
67#define GT_SCS10AR (0x0d0 >> 2)
68#define GT_SCS32AR (0x0d8 >> 2)
69#define GT_CS20R (0x0e0 >> 2)
70#define GT_CS3BOOTR (0x0e8 >> 2)
71
72#define GT_PCI0IOREMAP (0x0f0 >> 2)
73#define GT_PCI0M0REMAP (0x0f8 >> 2)
74#define GT_PCI0M1REMAP (0x100 >> 2)
75#define GT_PCI1IOREMAP (0x108 >> 2)
76#define GT_PCI1M0REMAP (0x110 >> 2)
77#define GT_PCI1M1REMAP (0x118 >> 2)
78
79/* CPU Error Report */
80#define GT_CPUERR_ADDRLO (0x070 >> 2)
81#define GT_CPUERR_ADDRHI (0x078 >> 2)
82#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
83#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
84#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
85
86/* CPU Sync Barrier */
87#define GT_PCI0SYNC (0x0c0 >> 2)
88#define GT_PCI1SYNC (0x0c8 >> 2)
89
90/* SDRAM and Device Address Decode */
91#define GT_SCS0LD (0x400 >> 2)
92#define GT_SCS0HD (0x404 >> 2)
93#define GT_SCS1LD (0x408 >> 2)
94#define GT_SCS1HD (0x40c >> 2)
95#define GT_SCS2LD (0x410 >> 2)
96#define GT_SCS2HD (0x414 >> 2)
97#define GT_SCS3LD (0x418 >> 2)
98#define GT_SCS3HD (0x41c >> 2)
99#define GT_CS0LD (0x420 >> 2)
100#define GT_CS0HD (0x424 >> 2)
101#define GT_CS1LD (0x428 >> 2)
102#define GT_CS1HD (0x42c >> 2)
103#define GT_CS2LD (0x430 >> 2)
104#define GT_CS2HD (0x434 >> 2)
105#define GT_CS3LD (0x438 >> 2)
106#define GT_CS3HD (0x43c >> 2)
107#define GT_BOOTLD (0x440 >> 2)
108#define GT_BOOTHD (0x444 >> 2)
109#define GT_ADERR (0x470 >> 2)
110
111/* SDRAM Configuration */
112#define GT_SDRAM_CFG (0x448 >> 2)
113#define GT_SDRAM_OPMODE (0x474 >> 2)
114#define GT_SDRAM_BM (0x478 >> 2)
115#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
116
117/* SDRAM Parameters */
118#define GT_SDRAM_B0 (0x44c >> 2)
119#define GT_SDRAM_B1 (0x450 >> 2)
120#define GT_SDRAM_B2 (0x454 >> 2)
121#define GT_SDRAM_B3 (0x458 >> 2)
122
123/* Device Parameters */
124#define GT_DEV_B0 (0x45c >> 2)
125#define GT_DEV_B1 (0x460 >> 2)
126#define GT_DEV_B2 (0x464 >> 2)
127#define GT_DEV_B3 (0x468 >> 2)
128#define GT_DEV_BOOT (0x46c >> 2)
129
130/* ECC */
131#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
132#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
133#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
134#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
135#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
136
137/* DMA Record */
138#define GT_DMA0_CNT (0x800 >> 2)
139#define GT_DMA1_CNT (0x804 >> 2)
140#define GT_DMA2_CNT (0x808 >> 2)
141#define GT_DMA3_CNT (0x80c >> 2)
142#define GT_DMA0_SA (0x810 >> 2)
143#define GT_DMA1_SA (0x814 >> 2)
144#define GT_DMA2_SA (0x818 >> 2)
145#define GT_DMA3_SA (0x81c >> 2)
146#define GT_DMA0_DA (0x820 >> 2)
147#define GT_DMA1_DA (0x824 >> 2)
148#define GT_DMA2_DA (0x828 >> 2)
149#define GT_DMA3_DA (0x82c >> 2)
150#define GT_DMA0_NEXT (0x830 >> 2)
151#define GT_DMA1_NEXT (0x834 >> 2)
152#define GT_DMA2_NEXT (0x838 >> 2)
153#define GT_DMA3_NEXT (0x83c >> 2)
154#define GT_DMA0_CUR (0x870 >> 2)
155#define GT_DMA1_CUR (0x874 >> 2)
156#define GT_DMA2_CUR (0x878 >> 2)
157#define GT_DMA3_CUR (0x87c >> 2)
158
159/* DMA Channel Control */
160#define GT_DMA0_CTRL (0x840 >> 2)
161#define GT_DMA1_CTRL (0x844 >> 2)
162#define GT_DMA2_CTRL (0x848 >> 2)
163#define GT_DMA3_CTRL (0x84c >> 2)
164
165/* DMA Arbiter */
166#define GT_DMA_ARB (0x860 >> 2)
167
168/* Timer/Counter */
169#define GT_TC0 (0x850 >> 2)
170#define GT_TC1 (0x854 >> 2)
171#define GT_TC2 (0x858 >> 2)
172#define GT_TC3 (0x85c >> 2)
173#define GT_TC_CONTROL (0x864 >> 2)
174
175/* PCI Internal */
176#define GT_PCI0_CMD (0xc00 >> 2)
177#define GT_PCI0_TOR (0xc04 >> 2)
178#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
179#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
180#define GT_PCI0_BS_CS20 (0xc10 >> 2)
181#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
182#define GT_PCI1_IACK (0xc30 >> 2)
183#define GT_PCI0_IACK (0xc34 >> 2)
184#define GT_PCI0_BARE (0xc3c >> 2)
185#define GT_PCI0_PREFMBR (0xc40 >> 2)
186#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
187#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
188#define GT_PCI0_CS20_BAR (0xc50 >> 2)
189#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
190#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
191#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
192#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
193#define GT_PCI1_CMD (0xc80 >> 2)
194#define GT_PCI1_TOR (0xc84 >> 2)
195#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
196#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
197#define GT_PCI1_BS_CS20 (0xc90 >> 2)
198#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
199#define GT_PCI1_BARE (0xcbc >> 2)
200#define GT_PCI1_PREFMBR (0xcc0 >> 2)
201#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
202#define GT_PCI1_SCS32_BAR (0xccc >> 2)
203#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
204#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
205#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
206#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
207#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
208#define GT_PCI1_CFGADDR (0xcf0 >> 2)
209#define GT_PCI1_CFGDATA (0xcf4 >> 2)
210#define GT_PCI0_CFGADDR (0xcf8 >> 2)
211#define GT_PCI0_CFGDATA (0xcfc >> 2)
212
213/* Interrupts */
214#define GT_INTRCAUSE (0xc18 >> 2)
215#define GT_INTRMASK (0xc1c >> 2)
216#define GT_PCI0_ICMASK (0xc24 >> 2)
217#define GT_PCI0_SERR0MASK (0xc28 >> 2)
218#define GT_CPU_INTSEL (0xc70 >> 2)
219#define GT_PCI0_INTSEL (0xc74 >> 2)
220#define GT_HINTRCAUSE (0xc98 >> 2)
221#define GT_HINTRMASK (0xc9c >> 2)
222#define GT_PCI0_HICMASK (0xca4 >> 2)
223#define GT_PCI1_SERR1MASK (0xca8 >> 2)
224
2a1086d9
TS		 225#define PCI_MAPPING_ENTRY(regname) \
226 target_phys_addr_t regname ##_start; \
227 target_phys_addr_t regname ##_length; \
228 int regname ##_handle
229
230#define PCI_REMAPPING_ENTRY(regname) \
231 target_phys_addr_t regname ##_start; \
232 target_phys_addr_t regname ##_length; \
233 target_phys_addr_t regname ##_offset; \
234 int regname ##_handle
fde7d5bd
TS		 235
236typedef PCIHostState GT64120PCIState;
237
238typedef struct GT64120State {
239 GT64120PCIState *pci;
240 uint32_t regs[GT_REGS];
2a1086d9
TS		 241 PCI_MAPPING_ENTRY(SCS10);
242 PCI_REMAPPING_ENTRY(SCS10AR);
243 PCI_MAPPING_ENTRY(SCS32);
244 PCI_REMAPPING_ENTRY(SCS32AR);
245 PCI_MAPPING_ENTRY(CS20);
246 PCI_REMAPPING_ENTRY(CS20R);
247 PCI_MAPPING_ENTRY(CS3BOOT);
248 PCI_REMAPPING_ENTRY(CS3BOOTR);
249 PCI_MAPPING_ENTRY(PCI0IO);
250 PCI_REMAPPING_ENTRY(PCI0IOREMAP);
251 PCI_MAPPING_ENTRY(PCI0M0);
252 PCI_REMAPPING_ENTRY(PCI0M0REMAP);
253 PCI_MAPPING_ENTRY(PCI0M1);
254 PCI_REMAPPING_ENTRY(PCI0M1REMAP);
255 PCI_MAPPING_ENTRY(PCI1IO);
256 PCI_REMAPPING_ENTRY(PCI1IOREMAP);
257 PCI_MAPPING_ENTRY(PCI1M0);
258 PCI_REMAPPING_ENTRY(PCI1M0REMAP);
259 PCI_MAPPING_ENTRY(PCI1M1);
260 PCI_REMAPPING_ENTRY(PCI1M1REMAP);
261 PCI_MAPPING_ENTRY(ISD);
fde7d5bd
TS		 262} GT64120State;
263
2a1086d9
TS		 264/* Adjust range to avoid touching space which isn't mappable via PCI */
265/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
266 0x1fc00000 - 0x1fd00000 */
267static void check_reserved_space (target_phys_addr_t *start,
268 target_phys_addr_t *length)
fde7d5bd 269{
2a1086d9
TS		 270 target_phys_addr_t begin = *start;
271 target_phys_addr_t end = *start + *length;
272
273 if (end >= 0x1e000000LL && end < 0x1f100000LL)
274 end = 0x1e000000LL;
275 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
276 begin = 0x1f100000LL;
277 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
278 end = 0x1fc00000LL;
279 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
280 begin = 0x1fd00000LL;
281 /* XXX: This is broken when a reserved range splits the requested range */
282 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
283 end = 0x1e000000LL;
284 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
285 end = 0x1fc00000LL;
286
287 *start = begin;
288 *length = end - begin;
289}
290
291/* XXX: cpu_register_physical_memory isn't really suited for dynamic mappings
292 since it doesn't layer several mappings over the same address range.
293 This should keep track of mappings as set of 2 MB pages / 20 mappings. */
294
295#define BUILD_UPDATE_PCI_MAPPING(reg, remap) \
296static void gt64120_## reg ##_mapping(GT64120State *s) \
297{ \
298 target_phys_addr_t start = s->regs[GT_## reg ##LD] << 21; \
299 target_phys_addr_t length = ((s->regs[GT_## reg ##HD] + 1) - \
300 (s->regs[GT_## reg ##LD] & 0x7f)) << 21; \
301 \
302 /* Unmap old address */ \
303 if (s->remap ##_length) \
304 cpu_register_physical_memory(s->remap ##_start, \
305 s->remap ##_length, \
306 IO_MEM_UNASSIGNED); \
307 s->remap ##_length = 0; \
308 if (s->reg ##_length) \
309 cpu_register_physical_memory(s->reg ##_start, \
310 s->reg ##_length, \
311 IO_MEM_UNASSIGNED); \
312 \
313 if ((s->regs[GT_## reg ##LD] & 0x7f) <= s->regs[GT_## reg ##HD]) \
314 { \
315 check_reserved_space(&start, &length); \
316 /* Map new address */ \
317dprintf("PCI " # reg ": %x@%x -> %x@%x, %x\n", s->reg ##_length, s->reg ##_start, length, start, s->reg ##_handle); \
318 s->reg ##_start = start; \
319 s->reg ##_length = length; \
320 cpu_register_physical_memory(s->reg ##_start, \
321 s->reg ##_length, \
322 s->reg ##_handle); \
323 } else \
324dprintf("PCI " # reg ": %x@%x disabled, %x\n", s->reg ##_length, s->reg ##_start, s->reg ##_handle); \
325} \
326 \
327static void gt64120_## remap ##_mapping(GT64120State *s) \
328{ \
329 /* XXX: range calculation is broken */ \
330 target_phys_addr_t start = (s->reg ## _start & ~(0x7ff << 21)) | \
331 (s->regs[GT_## remap] << 21); \
332 target_phys_addr_t length = s->reg ##_length; \
333 \
334 if (s->remap ##_length) \
335 cpu_register_physical_memory(s->remap ##_start, \
336 s->remap ##_length, \
337 IO_MEM_UNASSIGNED); \
338 check_reserved_space(&start, &length); \
339 s->remap ##_start = start; \
340 s->remap ##_length = length; \
341 s->remap ##_offset = s->reg ##_start - start; \
342dprintf("PCI " # remap ": %x@%x +> %x@%x, %x\n", s->reg ##_length, s->reg ##_start, length, start, s->remap ##_handle); \
343 cpu_register_physical_memory(s->remap ##_start, \
344 s->remap ##_length, \
345 s->remap ##_handle); \
346}
347
348BUILD_UPDATE_PCI_MAPPING(SCS10, SCS10AR)
349BUILD_UPDATE_PCI_MAPPING(SCS32, SCS32AR)
350BUILD_UPDATE_PCI_MAPPING(CS20, CS20R)
351BUILD_UPDATE_PCI_MAPPING(CS3BOOT, CS3BOOTR)
352BUILD_UPDATE_PCI_MAPPING(PCI0IO, PCI0IOREMAP)
353BUILD_UPDATE_PCI_MAPPING(PCI0M0, PCI0M0REMAP)
354BUILD_UPDATE_PCI_MAPPING(PCI0M1, PCI0M1REMAP)
355BUILD_UPDATE_PCI_MAPPING(PCI1IO, PCI1IOREMAP)
356BUILD_UPDATE_PCI_MAPPING(PCI1M0, PCI1M0REMAP)
357BUILD_UPDATE_PCI_MAPPING(PCI1M1, PCI1M1REMAP)
358
359static void gt64120_isd_mapping(GT64120State *s)
360{
361 if (s->ISD_length)
362 cpu_register_physical_memory(s->ISD_start, s->ISD_length,
363 IO_MEM_UNASSIGNED);
364dprintf("PCI ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start, 0x1000, s->regs[GT_ISD] << 21, s->ISD_handle);
365 s->ISD_start = s->regs[GT_ISD] << 21;
366 s->ISD_length = 0x1000;
367 cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
368}
369
370static void gt64120_mmio_writeb (void *opaque, target_phys_addr_t addr,
371 uint32_t val)
372{
373 cpu_outb(NULL, addr & 0xffff, val);
374}
375
376static void gt64120_mmio_writew (void *opaque, target_phys_addr_t addr,
377 uint32_t val)
378{
379#ifdef TARGET_WORDS_BIGENDIAN
380 val = bswap16(val);
381#endif
382 cpu_outw(NULL, addr & 0xffff, val);
383}
384
385static void gt64120_mmio_writel (void *opaque, target_phys_addr_t addr,
386 uint32_t val)
387{
388#ifdef TARGET_WORDS_BIGENDIAN
389 val = bswap32(val);
390#endif
391 cpu_outl(NULL, addr & 0xffff, val);
392}
393
394static uint32_t gt64120_mmio_readb (void *opaque, target_phys_addr_t addr)
395{
396 uint32_t val;
397
398 val = cpu_inb(NULL, addr & 0xffff);
399 return val;
fde7d5bd
TS		 400}
401
2a1086d9
TS		 402static uint32_t gt64120_mmio_readw (void *opaque, target_phys_addr_t addr)
403{
404 uint32_t val;
405
406 val = cpu_inw(NULL, addr & 0xffff);
407#ifdef TARGET_WORDS_BIGENDIAN
408 val = bswap16(val);
409#endif
410 return val;
411}
412
413static uint32_t gt64120_mmio_readl (void *opaque, target_phys_addr_t addr)
414{
415 uint32_t val;
416
417 val = cpu_inl(NULL, addr & 0xffff);
418#ifdef TARGET_WORDS_BIGENDIAN
419 val = bswap32(val);
420#endif
421 return val;
422}
423
424static CPUWriteMemoryFunc *gt64120_mmio_write[] = {
425 &gt64120_mmio_writeb,
426 &gt64120_mmio_writew,
427 &gt64120_mmio_writel,
428};
429
430static CPUReadMemoryFunc *gt64120_mmio_read[] = {
431 &gt64120_mmio_readb,
432 &gt64120_mmio_readw,
433 &gt64120_mmio_readl,
434};
435
fde7d5bd
TS		 436static void gt64120_writel (void *opaque, target_phys_addr_t addr,
437 uint32_t val)
438{
439 GT64120State *s = opaque;
440 uint32_t saddr;
441
0da75eb1
TS		 442#ifdef TARGET_WORDS_BIGENDIAN
443 val = bswap32(val);
444#endif
445
fde7d5bd
TS		 446 saddr = (addr & 0xfff) >> 2;
447 switch (saddr) {
0da75eb1
TS		 448
449 /* CPU Configuration */
fde7d5bd
TS		 450 case GT_CPU:
451 s->regs[GT_CPU] = val;
fde7d5bd
TS		 452 break;
453 case GT_MULTI:
0da75eb1 454 /* Read-only register as only one GT64xxx is present on the CPU bus */
fde7d5bd
TS		 455 break;
456
457 /* CPU Address Decode */
2a1086d9
TS		 458 case GT_SCS10LD:
459 s->regs[GT_SCS10LD] = val & 0x00007fff;
460 s->regs[GT_SCS10AR] = val & 0x000007ff;
461 gt64120_SCS10_mapping(s);
462 break;
463 case GT_SCS32LD:
464 s->regs[GT_SCS32LD] = val & 0x00007fff;
465 s->regs[GT_SCS32AR] = val & 0x000007ff;
466//
467// gt64120_SCS32_mapping(s);
468 break;
469 case GT_CS20LD:
470 s->regs[GT_CS20LD] = val & 0x00007fff;
471 s->regs[GT_CS20R] = val & 0x000007ff;
472 gt64120_CS20_mapping(s);
473 break;
474 case GT_CS3BOOTLD:
475 s->regs[GT_CS3BOOTLD] = val & 0x00007fff;
476 s->regs[GT_CS3BOOTR] = val & 0x000007ff;
477 gt64120_CS3BOOT_mapping(s);
478 break;
479 case GT_SCS10HD:
480 s->regs[saddr] = val & 0x0000007f;
481 gt64120_SCS10_mapping(s);
482 break;
483 case GT_SCS32HD:
484 s->regs[saddr] = val & 0x0000007f;
485//
486// gt64120_SCS32_mapping(s);
487 break;
488 case GT_CS20HD:
489 s->regs[saddr] = val & 0x0000007f;
490 gt64120_CS20_mapping(s);
491 break;
492 case GT_CS3BOOTHD:
493 s->regs[saddr] = val & 0x0000007f;
494 gt64120_CS3BOOT_mapping(s);
495 break;
fde7d5bd
TS		 496 case GT_PCI0IOLD:
497 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
498 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
2a1086d9 499 gt64120_PCI0IO_mapping(s);
fde7d5bd
TS		 500 break;
501 case GT_PCI0M0LD:
502 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
503 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
2a1086d9 504 gt64120_PCI0M0_mapping(s);
fde7d5bd
TS		 505 break;
506 case GT_PCI0M1LD:
507 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
508 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
2a1086d9 509 gt64120_PCI0M1_mapping(s);
fde7d5bd
TS		 510 break;
511 case GT_PCI1IOLD:
512 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
513 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
2a1086d9 514 gt64120_PCI1IO_mapping(s);
fde7d5bd
TS		 515 break;
516 case GT_PCI1M0LD:
517 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
518 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
2a1086d9 519 gt64120_PCI1M1_mapping(s);
fde7d5bd
TS		 520 break;
521 case GT_PCI1M1LD:
522 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
523 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
2a1086d9 524 gt64120_PCI1M1_mapping(s);
fde7d5bd
TS		 525 break;
526 case GT_PCI0IOHD:
2a1086d9
TS		 527 s->regs[saddr] = val & 0x0000007f;
528 gt64120_PCI0IO_mapping(s);
529 break;
fde7d5bd 530 case GT_PCI0M0HD:
2a1086d9
TS		 531 s->regs[saddr] = val & 0x0000007f;
532 gt64120_PCI0M0_mapping(s);
533 break;
fde7d5bd 534 case GT_PCI0M1HD:
2a1086d9
TS		 535 s->regs[saddr] = val & 0x0000007f;
536 gt64120_PCI0M1_mapping(s);
537 break;
fde7d5bd 538 case GT_PCI1IOHD:
2a1086d9
TS		 539 s->regs[saddr] = val & 0x0000007f;
540 gt64120_PCI1IO_mapping(s);
541 break;
fde7d5bd 542 case GT_PCI1M0HD:
2a1086d9
TS		 543 s->regs[saddr] = val & 0x0000007f;
544 gt64120_PCI1M0_mapping(s);
545 break;
fde7d5bd
TS		 546 case GT_PCI1M1HD:
547 s->regs[saddr] = val & 0x0000007f;
2a1086d9
TS		 548 gt64120_PCI1M1_mapping(s);
549 break;
550 case GT_ISD:
551 s->regs[saddr] = val & 0x00007fff;
552 gt64120_isd_mapping(s);
553 break;
554
555 case GT_SCS10AR:
556 s->regs[saddr] = val & 0x000007ff;
557 gt64120_SCS10AR_mapping(s);
558 break;
559 case GT_SCS32AR:
560 s->regs[saddr] = val & 0x000007ff;
561 gt64120_SCS32AR_mapping(s);
562 break;
563 case GT_CS20R:
564 s->regs[saddr] = val & 0x000007ff;
565 gt64120_CS20R_mapping(s);
566 break;
567 case GT_CS3BOOTR:
568 s->regs[saddr] = val & 0x000007ff;
569 gt64120_CS3BOOTR_mapping(s);
fde7d5bd
TS		 570 break;
571 case GT_PCI0IOREMAP:
2a1086d9
TS		 572 s->regs[saddr] = val & 0x000007ff;
573 gt64120_PCI0IOREMAP_mapping(s);
574 break;
fde7d5bd 575 case GT_PCI0M0REMAP:
2a1086d9
TS		 576 s->regs[saddr] = val & 0x000007ff;
577 gt64120_PCI0M0REMAP_mapping(s);
578 break;
fde7d5bd 579 case GT_PCI0M1REMAP:
2a1086d9
TS		 580 s->regs[saddr] = val & 0x000007ff;
581 gt64120_PCI0M1REMAP_mapping(s);
582 break;
fde7d5bd 583 case GT_PCI1IOREMAP:
2a1086d9
TS		 584 s->regs[saddr] = val & 0x000007ff;
585 gt64120_PCI1IOREMAP_mapping(s);
586 break;
fde7d5bd 587 case GT_PCI1M0REMAP:
2a1086d9
TS		 588 s->regs[saddr] = val & 0x000007ff;
589 gt64120_PCI1M0REMAP_mapping(s);
590 break;
fde7d5bd
TS		 591 case GT_PCI1M1REMAP:
592 s->regs[saddr] = val & 0x000007ff;
2a1086d9 593 gt64120_PCI1M1REMAP_mapping(s);
fde7d5bd
TS		 594 break;
595
596 /* CPU Error Report */
597 case GT_CPUERR_ADDRLO:
598 case GT_CPUERR_ADDRHI:
599 case GT_CPUERR_DATALO:
600 case GT_CPUERR_DATAHI:
601 case GT_CPUERR_PARITY:
0da75eb1
TS		 602 /* Read-only registers, do nothing */
603 break;
604
605 /* CPU Sync Barrier */
606 case GT_PCI0SYNC:
607 case GT_PCI1SYNC:
608 /* Read-only registers, do nothing */
fde7d5bd
TS		 609 break;
610
05b4ff43
TS		 611 /* SDRAM and Device Address Decode */
612 case GT_SCS0LD:
613 case GT_SCS0HD:
614 case GT_SCS1LD:
615 case GT_SCS1HD:
616 case GT_SCS2LD:
617 case GT_SCS2HD:
618 case GT_SCS3LD:
619 case GT_SCS3HD:
620 case GT_CS0LD:
621 case GT_CS0HD:
622 case GT_CS1LD:
623 case GT_CS1HD:
624 case GT_CS2LD:
625 case GT_CS2HD:
626 case GT_CS3LD:
627 case GT_CS3HD:
628 case GT_BOOTLD:
629 case GT_BOOTHD:
630 case GT_ADERR:
631 /* SDRAM Configuration */
632 case GT_SDRAM_CFG:
633 case GT_SDRAM_OPMODE:
634 case GT_SDRAM_BM:
635 case GT_SDRAM_ADDRDECODE:
636 /* Accept and ignore SDRAM interleave configuration */
637 s->regs[saddr] = val;
638 break;
639
640 /* Device Parameters */
641 case GT_DEV_B0:
642 case GT_DEV_B1:
643 case GT_DEV_B2:
644 case GT_DEV_B3:
645 case GT_DEV_BOOT:
646 /* Not implemented */
647 dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
648 break;
649
fde7d5bd
TS		 650 /* ECC */
651 case GT_ECC_ERRDATALO:
652 case GT_ECC_ERRDATAHI:
653 case GT_ECC_MEM:
654 case GT_ECC_CALC:
655 case GT_ECC_ERRADDR:
0da75eb1 656 /* Read-only registers, do nothing */
fde7d5bd
TS		 657 break;
658
05b4ff43
TS		 659 /* DMA Record */
660 case GT_DMA0_CNT:
661 case GT_DMA1_CNT:
662 case GT_DMA2_CNT:
663 case GT_DMA3_CNT:
664 case GT_DMA0_SA:
665 case GT_DMA1_SA:
666 case GT_DMA2_SA:
667 case GT_DMA3_SA:
668 case GT_DMA0_DA:
669 case GT_DMA1_DA:
670 case GT_DMA2_DA:
671 case GT_DMA3_DA:
672 case GT_DMA0_NEXT:
673 case GT_DMA1_NEXT:
674 case GT_DMA2_NEXT:
675 case GT_DMA3_NEXT:
676 case GT_DMA0_CUR:
677 case GT_DMA1_CUR:
678 case GT_DMA2_CUR:
679 case GT_DMA3_CUR:
680 /* Not implemented */
681 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
682 break;
683
684 /* DMA Channel Control */
685 case GT_DMA0_CTRL:
686 case GT_DMA1_CTRL:
687 case GT_DMA2_CTRL:
688 case GT_DMA3_CTRL:
689 /* Not implemented */
690 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
691 break;
692
693 /* DMA Arbiter */
694 case GT_DMA_ARB:
695 /* Not implemented */
696 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
697 break;
698
699 /* Timer/Counter */
700 case GT_TC0:
701 case GT_TC1:
702 case GT_TC2:
703 case GT_TC3:
704 case GT_TC_CONTROL:
705 /* Not implemented */
706 dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
707 break;
708
fde7d5bd
TS		 709 /* PCI Internal */
710 case GT_PCI0_CMD:
711 case GT_PCI1_CMD:
712 s->regs[saddr] = val & 0x0401fc0f;
713 break;
05b4ff43
TS		 714 case GT_PCI0_TOR:
715 case GT_PCI0_BS_SCS10:
716 case GT_PCI0_BS_SCS32:
717 case GT_PCI0_BS_CS20:
718 case GT_PCI0_BS_CS3BT:
719 case GT_PCI1_IACK:
720 case GT_PCI0_IACK:
721 case GT_PCI0_BARE:
722 case GT_PCI0_PREFMBR:
723 case GT_PCI0_SCS10_BAR:
724 case GT_PCI0_SCS32_BAR:
725 case GT_PCI0_CS20_BAR:
726 case GT_PCI0_CS3BT_BAR:
727 case GT_PCI0_SSCS10_BAR:
728 case GT_PCI0_SSCS32_BAR:
729 case GT_PCI0_SCS3BT_BAR:
730 case GT_PCI1_TOR:
731 case GT_PCI1_BS_SCS10:
732 case GT_PCI1_BS_SCS32:
733 case GT_PCI1_BS_CS20:
734 case GT_PCI1_BS_CS3BT:
735 case GT_PCI1_BARE:
736 case GT_PCI1_PREFMBR:
737 case GT_PCI1_SCS10_BAR:
738 case GT_PCI1_SCS32_BAR:
739 case GT_PCI1_CS20_BAR:
740 case GT_PCI1_CS3BT_BAR:
741 case GT_PCI1_SSCS10_BAR:
742 case GT_PCI1_SSCS32_BAR:
743 case GT_PCI1_SCS3BT_BAR:
744 case GT_PCI1_CFGADDR:
745 case GT_PCI1_CFGDATA:
746 /* not implemented */
747 break;
fde7d5bd
TS		 748 case GT_PCI0_CFGADDR:
749 s->pci->config_reg = val & 0x80fffffc;
750 break;
751 case GT_PCI0_CFGDATA:
05b4ff43
TS		 752 if (s->pci->config_reg & (1u << 31))
753 pci_host_data_writel(s->pci, 0, val);
754 break;
755
756 /* Interrupts */
757 case GT_INTRCAUSE:
758 /* not really implemented */
759 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
760 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
761 dprintf("INTRCAUSE %x\n", val);
762 break;
763 case GT_INTRMASK:
764 s->regs[saddr] = val & 0x3c3ffffe;
765 dprintf("INTRMASK %x\n", val);
766 break;
767 case GT_PCI0_ICMASK:
768 s->regs[saddr] = val & 0x03fffffe;
769 dprintf("ICMASK %x\n", val);
770 break;
771 case GT_PCI0_SERR0MASK:
772 s->regs[saddr] = val & 0x0000003f;
773 dprintf("SERR0MASK %x\n", val);
774 break;
775
776 /* Reserved when only PCI_0 is configured. */
777 case GT_HINTRCAUSE:
778 case GT_CPU_INTSEL:
779 case GT_PCI0_INTSEL:
780 case GT_HINTRMASK:
781 case GT_PCI0_HICMASK:
782 case GT_PCI1_SERR1MASK:
783 /* not implemented */
fde7d5bd
TS		 784 break;
785
0da75eb1
TS		 786 /* SDRAM Parameters */
787 case GT_SDRAM_B0:
788 case GT_SDRAM_B1:
789 case GT_SDRAM_B2:
790 case GT_SDRAM_B3:
791 /* We don't simulate electrical parameters of the SDRAM.
792 Accept, but ignore the values. */
793 s->regs[saddr] = val;
794 break;
795
fde7d5bd 796 default:
05b4ff43 797 dprintf ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 798 break;
799 }
800}
801
802static uint32_t gt64120_readl (void *opaque,
803 target_phys_addr_t addr)
804{
805 GT64120State *s = opaque;
806 uint32_t val;
807 uint32_t saddr;
808
809 val = 0;
810 saddr = (addr & 0xfff) >> 2;
811
812 switch (saddr) {
813
0da75eb1
TS		 814 /* CPU Configuration */
815 case GT_MULTI:
816 /* Only one GT64xxx is present on the CPU bus, return
817 the initial value */
818 val = s->regs[saddr];
819 break;
820
fde7d5bd
TS		 821 /* CPU Error Report */
822 case GT_CPUERR_ADDRLO:
823 case GT_CPUERR_ADDRHI:
824 case GT_CPUERR_DATALO:
825 case GT_CPUERR_DATAHI:
826 case GT_CPUERR_PARITY:
0da75eb1
TS		 827 /* Emulated memory has no error, always return the initial
828 values */
829 val = s->regs[saddr];
830 break;
831
832 /* CPU Sync Barrier */
833 case GT_PCI0SYNC:
834 case GT_PCI1SYNC:
835 /* Reading those register should empty all FIFO on the PCI
836 bus, which are not emulated. The return value should be
837 a random value that should be ignored. */
838 val = 0xc000ffee;
fde7d5bd
TS		 839 break;
840
841 /* ECC */
842 case GT_ECC_ERRDATALO:
843 case GT_ECC_ERRDATAHI:
844 case GT_ECC_MEM:
845 case GT_ECC_CALC:
846 case GT_ECC_ERRADDR:
0da75eb1
TS		 847 /* Emulated memory has no error, always return the initial
848 values */
849 val = s->regs[saddr];
fde7d5bd
TS		 850 break;
851
852 case GT_CPU:
05b4ff43
TS		 853 case GT_SCS10LD:
854 case GT_SCS10HD:
855 case GT_SCS32LD:
856 case GT_SCS32HD:
857 case GT_CS20LD:
858 case GT_CS20HD:
859 case GT_CS3BOOTLD:
860 case GT_CS3BOOTHD:
861 case GT_SCS10AR:
862 case GT_SCS32AR:
863 case GT_CS20R:
864 case GT_CS3BOOTR:
fde7d5bd
TS		 865 case GT_PCI0IOLD:
866 case GT_PCI0M0LD:
867 case GT_PCI0M1LD:
868 case GT_PCI1IOLD:
869 case GT_PCI1M0LD:
870 case GT_PCI1M1LD:
871 case GT_PCI0IOHD:
872 case GT_PCI0M0HD:
873 case GT_PCI0M1HD:
874 case GT_PCI1IOHD:
875 case GT_PCI1M0HD:
876 case GT_PCI1M1HD:
fde7d5bd
TS		 877 case GT_PCI0IOREMAP:
878 case GT_PCI0M0REMAP:
879 case GT_PCI0M1REMAP:
880 case GT_PCI1IOREMAP:
881 case GT_PCI1M0REMAP:
882 case GT_PCI1M1REMAP:
05b4ff43 883 case GT_ISD:
fde7d5bd
TS		 884 val = s->regs[saddr];
885 break;
886 case GT_PCI0_IACK:
4de9b249
TS		 887 /* Read the IRQ number */
888 val = pic_read_irq(isa_pic);
fde7d5bd
TS		 889 break;
890
05b4ff43
TS		 891 /* SDRAM and Device Address Decode */
892 case GT_SCS0LD:
893 case GT_SCS0HD:
894 case GT_SCS1LD:
895 case GT_SCS1HD:
896 case GT_SCS2LD:
897 case GT_SCS2HD:
898 case GT_SCS3LD:
899 case GT_SCS3HD:
900 case GT_CS0LD:
901 case GT_CS0HD:
902 case GT_CS1LD:
903 case GT_CS1HD:
904 case GT_CS2LD:
905 case GT_CS2HD:
906 case GT_CS3LD:
907 case GT_CS3HD:
908 case GT_BOOTLD:
909 case GT_BOOTHD:
910 case GT_ADERR:
911 val = s->regs[saddr];
912 break;
913
914 /* SDRAM Configuration */
915 case GT_SDRAM_CFG:
916 case GT_SDRAM_OPMODE:
917 case GT_SDRAM_BM:
918 case GT_SDRAM_ADDRDECODE:
919 val = s->regs[saddr];
920 break;
921
0da75eb1
TS		 922 /* SDRAM Parameters */
923 case GT_SDRAM_B0:
924 case GT_SDRAM_B1:
925 case GT_SDRAM_B2:
926 case GT_SDRAM_B3:
927 /* We don't simulate electrical parameters of the SDRAM.
928 Just return the last written value. */
929 val = s->regs[saddr];
930 break;
931
05b4ff43
TS		 932 /* Device Parameters */
933 case GT_DEV_B0:
934 case GT_DEV_B1:
935 case GT_DEV_B2:
936 case GT_DEV_B3:
937 case GT_DEV_BOOT:
938 val = s->regs[saddr];
939 break;
940
941 /* DMA Record */
942 case GT_DMA0_CNT:
943 case GT_DMA1_CNT:
944 case GT_DMA2_CNT:
945 case GT_DMA3_CNT:
946 case GT_DMA0_SA:
947 case GT_DMA1_SA:
948 case GT_DMA2_SA:
949 case GT_DMA3_SA:
950 case GT_DMA0_DA:
951 case GT_DMA1_DA:
952 case GT_DMA2_DA:
953 case GT_DMA3_DA:
954 case GT_DMA0_NEXT:
955 case GT_DMA1_NEXT:
956 case GT_DMA2_NEXT:
957 case GT_DMA3_NEXT:
958 case GT_DMA0_CUR:
959 case GT_DMA1_CUR:
960 case GT_DMA2_CUR:
961 case GT_DMA3_CUR:
962 val = s->regs[saddr];
963 break;
964
965 /* DMA Channel Control */
966 case GT_DMA0_CTRL:
967 case GT_DMA1_CTRL:
968 case GT_DMA2_CTRL:
969 case GT_DMA3_CTRL:
970 val = s->regs[saddr];
971 break;
972
973 /* DMA Arbiter */
974 case GT_DMA_ARB:
975 val = s->regs[saddr];
976 break;
977
978 /* Timer/Counter */
979 case GT_TC0:
980 case GT_TC1:
981 case GT_TC2:
982 case GT_TC3:
983 case GT_TC_CONTROL:
984 val = s->regs[saddr];
985 break;
986
fde7d5bd
TS		 987 /* PCI Internal */
988 case GT_PCI0_CFGADDR:
989 val = s->pci->config_reg;
990 break;
991 case GT_PCI0_CFGDATA:
05b4ff43
TS		 992 if (!(s->pci->config_reg & (1u << 31)))
993 val = 0xffffffff;
994 else
f00cb701 995 val = pci_host_data_readl(s->pci, 0);
05b4ff43
TS		 996 break;
997
998 case GT_PCI0_CMD:
999 case GT_PCI0_TOR:
1000 case GT_PCI0_BS_SCS10:
1001 case GT_PCI0_BS_SCS32:
1002 case GT_PCI0_BS_CS20:
1003 case GT_PCI0_BS_CS3BT:
1004 case GT_PCI1_IACK:
1005 case GT_PCI0_BARE:
1006 case GT_PCI0_PREFMBR:
1007 case GT_PCI0_SCS10_BAR:
1008 case GT_PCI0_SCS32_BAR:
1009 case GT_PCI0_CS20_BAR:
1010 case GT_PCI0_CS3BT_BAR:
1011 case GT_PCI0_SSCS10_BAR:
1012 case GT_PCI0_SSCS32_BAR:
1013 case GT_PCI0_SCS3BT_BAR:
1014 case GT_PCI1_CMD:
1015 case GT_PCI1_TOR:
1016 case GT_PCI1_BS_SCS10:
1017 case GT_PCI1_BS_SCS32:
1018 case GT_PCI1_BS_CS20:
1019 case GT_PCI1_BS_CS3BT:
1020 case GT_PCI1_BARE:
1021 case GT_PCI1_PREFMBR:
1022 case GT_PCI1_SCS10_BAR:
1023 case GT_PCI1_SCS32_BAR:
1024 case GT_PCI1_CS20_BAR:
1025 case GT_PCI1_CS3BT_BAR:
1026 case GT_PCI1_SSCS10_BAR:
1027 case GT_PCI1_SSCS32_BAR:
1028 case GT_PCI1_SCS3BT_BAR:
1029 case GT_PCI1_CFGADDR:
1030 case GT_PCI1_CFGDATA:
1031 val = s->regs[saddr];
1032 break;
1033
1034 /* Interrupts */
1035 case GT_INTRCAUSE:
1036 val = s->regs[saddr];
1037 dprintf("INTRCAUSE %x\n", val);
1038 break;
1039 case GT_INTRMASK:
1040 val = s->regs[saddr];
1041 dprintf("INTRMASK %x\n", val);
1042 break;
1043 case GT_PCI0_ICMASK:
1044 val = s->regs[saddr];
1045 dprintf("ICMASK %x\n", val);
1046 break;
1047 case GT_PCI0_SERR0MASK:
1048 val = s->regs[saddr];
1049 dprintf("SERR0MASK %x\n", val);
1050 break;
1051
1052 /* Reserved when only PCI_0 is configured. */
1053 case GT_HINTRCAUSE:
1054 case GT_CPU_INTSEL:
1055 case GT_PCI0_INTSEL:
1056 case GT_HINTRMASK:
1057 case GT_PCI0_HICMASK:
1058 case GT_PCI1_SERR1MASK:
1059 val = s->regs[saddr];
fde7d5bd
TS		 1060 break;
1061
1062 default:
1063 val = s->regs[saddr];
05b4ff43 1064 dprintf ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 1065 break;
1066 }
1067
0da75eb1 1068#ifdef TARGET_WORDS_BIGENDIAN
05b4ff43 1069 val = bswap32(val);
0da75eb1 1070#endif
05b4ff43 1071 return val;
fde7d5bd
TS		 1072}
1073
1074static CPUWriteMemoryFunc *gt64120_write[] = {
1075 &gt64120_writel,
1076 &gt64120_writel,
1077 &gt64120_writel,
1078};
1079
1080static CPUReadMemoryFunc *gt64120_read[] = {
1081 &gt64120_readl,
1082 &gt64120_readl,
1083 &gt64120_readl,
1084};
1085
1086static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
1087{
1088 int slot;
1089
1090 slot = (pci_dev->devfn >> 3);
1091
1092 switch (slot) {
1093 /* PIIX4 USB */
1094 case 10:
1095 return 3;
1096 /* AMD 79C973 Ethernet */
1097 case 11:
d4a4d056 1098 return 1;
fde7d5bd
TS		 1099 /* Crystal 4281 Sound */
1100 case 12:
d4a4d056 1101 return 2;
fde7d5bd
TS		 1102 /* PCI slot 1 to 4 */
1103 case 18 ... 21:
1104 return ((slot - 18) + irq_num) & 0x03;
1105 /* Unknown device, don't do any translation */
1106 default:
1107 return irq_num;
1108 }
1109}
1110
1111extern PCIDevice *piix4_dev;
1112static int pci_irq_levels[4];
1113
d537cf6c 1114static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
fde7d5bd
TS		 1115{
1116 int i, pic_irq, pic_level;
1117
1118 pci_irq_levels[irq_num] = level;
1119
1120 /* now we change the pic irq level according to the piix irq mappings */
1121 /* XXX: optimize */
1122 pic_irq = piix4_dev->config[0x60 + irq_num];
1123 if (pic_irq < 16) {
1124 /* The pic level is the logical OR of all the PCI irqs mapped
1125 to it */
1126 pic_level = 0;
1127 for (i = 0; i < 4; i++) {
1128 if (pic_irq == piix4_dev->config[0x60 + i])
1129 pic_level |= pci_irq_levels[i];
1130 }
d537cf6c 1131 qemu_set_irq(pic[pic_irq], pic_level);
fde7d5bd
TS		 1132 }
1133}
1134
1135
1136void gt64120_reset(void *opaque)
1137{
1138 GT64120State *s = opaque;
1139
30b6f3a8
TS		 1140 /* FIXME: Malta specific hw assumptions ahead */
1141
fde7d5bd
TS		 1142 /* CPU Configuration */
1143#ifdef TARGET_WORDS_BIGENDIAN
1144 s->regs[GT_CPU] = 0x00000000;
1145#else
bc687ec9 1146 s->regs[GT_CPU] = 0x00001000;
fde7d5bd 1147#endif
30b6f3a8
TS		 1148 s->regs[GT_MULTI] = 0x00000003;
1149
1150 /* CPU Address decode */
1151 s->regs[GT_SCS10LD] = 0x00000000;
1152 s->regs[GT_SCS10HD] = 0x00000007;
1153 s->regs[GT_SCS32LD] = 0x00000008;
1154 s->regs[GT_SCS32HD] = 0x0000000f;
1155 s->regs[GT_CS20LD] = 0x000000e0;
1156 s->regs[GT_CS20HD] = 0x00000070;
1157 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1158 s->regs[GT_CS3BOOTHD] = 0x0000007f;
fde7d5bd 1159
fde7d5bd
TS		 1160 s->regs[GT_PCI0IOLD] = 0x00000080;
1161 s->regs[GT_PCI0IOHD] = 0x0000000f;
1162 s->regs[GT_PCI0M0LD] = 0x00000090;
1163 s->regs[GT_PCI0M0HD] = 0x0000001f;
30b6f3a8 1164 s->regs[GT_ISD] = 0x000000a0;
fde7d5bd
TS		 1165 s->regs[GT_PCI0M1LD] = 0x00000790;
1166 s->regs[GT_PCI0M1HD] = 0x0000001f;
1167 s->regs[GT_PCI1IOLD] = 0x00000100;
1168 s->regs[GT_PCI1IOHD] = 0x0000000f;
1169 s->regs[GT_PCI1M0LD] = 0x00000110;
1170 s->regs[GT_PCI1M0HD] = 0x0000001f;
1171 s->regs[GT_PCI1M1LD] = 0x00000120;
1172 s->regs[GT_PCI1M1HD] = 0x0000002f;
30b6f3a8
TS		 1173
1174 s->regs[GT_SCS10AR] = 0x00000000;
1175 s->regs[GT_SCS32AR] = 0x00000008;
1176 s->regs[GT_CS20R] = 0x000000e0;
1177 s->regs[GT_CS3BOOTR] = 0x000000f8;
1178
fde7d5bd
TS		 1179 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1180 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1181 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1182 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1183 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1184 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1185
1186 /* CPU Error Report */
1187 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1188 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1189 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1190 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1191 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1192
30b6f3a8
TS		 1193 /* CPU Sync Barrier */
1194 s->regs[GT_PCI0SYNC] = 0x00000000;
1195 s->regs[GT_PCI1SYNC] = 0x00000000;
1196
1197 /* SDRAM and Device Address Decode */
1198 s->regs[GT_SCS0LD] = 0x00000000;
1199 s->regs[GT_SCS0HD] = 0x00000007;
1200 s->regs[GT_SCS1LD] = 0x00000008;
1201 s->regs[GT_SCS1HD] = 0x0000000f;
1202 s->regs[GT_SCS2LD] = 0x00000010;
1203 s->regs[GT_SCS2HD] = 0x00000017;
1204 s->regs[GT_SCS3LD] = 0x00000018;
1205 s->regs[GT_SCS3HD] = 0x0000001f;
1206 s->regs[GT_CS0LD] = 0x000000c0;
1207 s->regs[GT_CS0HD] = 0x000000c7;
1208 s->regs[GT_CS1LD] = 0x000000c8;
1209 s->regs[GT_CS1HD] = 0x000000cf;
1210 s->regs[GT_CS2LD] = 0x000000d0;
1211 s->regs[GT_CS2HD] = 0x000000df;
1212 s->regs[GT_CS3LD] = 0x000000f0;
1213 s->regs[GT_CS3HD] = 0x000000fb;
1214 s->regs[GT_BOOTLD] = 0x000000fc;
1215 s->regs[GT_BOOTHD] = 0x000000ff;
1216 s->regs[GT_ADERR] = 0xffffffff;
1217
1218 /* SDRAM Configuration */
1219 s->regs[GT_SDRAM_CFG] = 0x00000200;
1220 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1221 s->regs[GT_SDRAM_BM] = 0x00000007;
1222 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1223
1224 /* SDRAM Parameters */
1225 s->regs[GT_SDRAM_B0] = 0x00000005;
1226 s->regs[GT_SDRAM_B1] = 0x00000005;
1227 s->regs[GT_SDRAM_B2] = 0x00000005;
1228 s->regs[GT_SDRAM_B3] = 0x00000005;
1229
fde7d5bd
TS		 1230 /* ECC */
1231 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1232 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1233 s->regs[GT_ECC_MEM] = 0x00000000;
1234 s->regs[GT_ECC_CALC] = 0x00000000;
1235 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1236
30b6f3a8
TS		 1237 /* Device Parameters */
1238 s->regs[GT_DEV_B0] = 0x386fffff;
1239 s->regs[GT_DEV_B1] = 0x386fffff;
1240 s->regs[GT_DEV_B2] = 0x386fffff;
1241 s->regs[GT_DEV_B3] = 0x386fffff;
1242 s->regs[GT_DEV_BOOT] = 0x146fffff;
0da75eb1 1243
30b6f3a8
TS		 1244 /* DMA registers are all zeroed at reset */
1245
1246 /* Timer/Counter */
1247 s->regs[GT_TC0] = 0xffffffff;
1248 s->regs[GT_TC1] = 0x00ffffff;
1249 s->regs[GT_TC2] = 0x00ffffff;
1250 s->regs[GT_TC3] = 0x00ffffff;
1251 s->regs[GT_TC_CONTROL] = 0x00000000;
1252
1253 /* PCI Internal */
fde7d5bd
TS		 1254#ifdef TARGET_WORDS_BIGENDIAN
1255 s->regs[GT_PCI0_CMD] = 0x00000000;
fde7d5bd
TS		 1256#else
1257 s->regs[GT_PCI0_CMD] = 0x00010001;
fde7d5bd 1258#endif
30b6f3a8
TS		 1259 s->regs[GT_PCI0_TOR] = 0x0000070f;
1260 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1261 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1262 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1263 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
fde7d5bd 1264 s->regs[GT_PCI1_IACK] = 0x00000000;
30b6f3a8
TS		 1265 s->regs[GT_PCI0_IACK] = 0x00000000;
1266 s->regs[GT_PCI0_BARE] = 0x0000000f;
1267 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1268 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1269 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1270 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1271 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1272 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1273 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1274 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1275#ifdef TARGET_WORDS_BIGENDIAN
1276 s->regs[GT_PCI1_CMD] = 0x00000000;
1277#else
1278 s->regs[GT_PCI1_CMD] = 0x00010001;
1279#endif
1280 s->regs[GT_PCI1_TOR] = 0x0000070f;
1281 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1282 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1283 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1284 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1285 s->regs[GT_PCI1_BARE] = 0x0000000f;
1286 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1287 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1288 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1289 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1290 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1291 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1292 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1293 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1294 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1295 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1296 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1297 s->regs[GT_PCI0_CFGDATA] = 0x00000000;
1298
1299 /* Interrupt registers are all zeroed at reset */
fde7d5bd 1300
2a1086d9
TS		 1301 gt64120_isd_mapping(s);
1302 gt64120_SCS10_mapping(s);
1303// gt64120_SCS32_mapping(s);
1304 gt64120_CS20_mapping(s);
1305 gt64120_CS3BOOT_mapping(s);
1306 gt64120_PCI0IO_mapping(s);
1307 gt64120_PCI0M0_mapping(s);
1308 gt64120_PCI0M1_mapping(s);
1309 gt64120_PCI1IO_mapping(s);
1310 gt64120_PCI1M0_mapping(s);
1311 gt64120_PCI1M1_mapping(s);
fde7d5bd
TS		 1312}
1313
bc687ec9
TS		 1314static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
1315{
1316 uint32_t val = pci_default_read_config(d, address, len);
1317#ifdef TARGET_WORDS_BIGENDIAN
1318 val = bswap32(val);
1319#endif
1320 return val;
1321}
1322
1323static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
1324 int len)
1325{
1326#ifdef TARGET_WORDS_BIGENDIAN
1327 val = bswap32(val);
1328#endif
1329 pci_default_write_config(d, address, val, len);
1330}
1331
1823082c
TS		 1332static void gt64120_save(QEMUFile* f, void *opaque)
1333{
1334 PCIDevice *d = opaque;
1335 pci_device_save(d, f);
1336}
1337
1338static int gt64120_load(QEMUFile* f, void *opaque, int version_id)
1339{
1340 PCIDevice *d = opaque;
1341 int ret;
1342
1343 if (version_id != 1)
1344 return -EINVAL;
1345 ret = pci_device_load(d, f);
1346 if (ret < 0)
1347 return ret;
1348 return 0;
1349}
1350
d537cf6c 1351PCIBus *pci_gt64120_init(qemu_irq *pic)
fde7d5bd
TS		 1352{
1353 GT64120State *s;
1354 PCIDevice *d;
fde7d5bd
TS		 1355
1356 s = qemu_mallocz(sizeof(GT64120State));
1357 s->pci = qemu_mallocz(sizeof(GT64120PCIState));
fde7d5bd
TS		 1358 s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
1359 pic, 144, 4);
1360
2a1086d9
TS		 1361 s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);
1362 s->PCI0IO_handle = cpu_register_io_memory(0, gt64120_mmio_read,
1363 gt64120_mmio_write, s);
1364 gt64120_reset(s);
fde7d5bd
TS		 1365
1366 d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
bc687ec9 1367 0, gt64120_read_config, gt64120_write_config);
fde7d5bd 1368
0f78cf0c
TS		 1369 /* FIXME: Malta specific hw assumptions ahead */
1370
fde7d5bd
TS		 1371 d->config[0x00] = 0xab; // vendor_id
1372 d->config[0x01] = 0x11;
bc687ec9
TS		 1373 d->config[0x02] = 0x20; // device_id
1374 d->config[0x03] = 0x46;
0f78cf0c
TS		 1375
1376 d->config[0x04] = 0x00;
fde7d5bd
TS		 1377 d->config[0x05] = 0x00;
1378 d->config[0x06] = 0x80;
0f78cf0c
TS		 1379 d->config[0x07] = 0x02;
1380
fde7d5bd
TS		 1381 d->config[0x08] = 0x10;
1382 d->config[0x09] = 0x00;
0f78cf0c
TS		 1383 d->config[0x0A] = 0x00;
1384 d->config[0x0B] = 0x06;
1385
1386 d->config[0x10] = 0x08;
1387 d->config[0x14] = 0x08;
1388 d->config[0x17] = 0x01;
fde7d5bd
TS		 1389 d->config[0x1B] = 0x1c;
1390 d->config[0x1F] = 0x1f;
1391 d->config[0x23] = 0x14;
0f78cf0c 1392 d->config[0x24] = 0x01;
fde7d5bd
TS		 1393 d->config[0x27] = 0x14;
1394 d->config[0x3D] = 0x01;
1395
1823082c
TS		 1396 register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
1397
fde7d5bd
TS		 1398 return s->pci->bus;
1399}
Qemu copy for testing