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Commit | Line | Data |
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a72bd606 HD |
1 | /* |
2 | * QEMU HP-PARISC PCI support functions. | |
3 | * | |
4 | */ | |
5 | ||
6 | #include "qemu/osdep.h" | |
a72bd606 HD |
7 | #include "hppa_sys.h" |
8 | #include "qemu/log.h" | |
9 | #include "sysemu/sysemu.h" | |
10 | #include "trace.h" | |
11 | ||
12 | ||
13 | /* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ | |
14 | ||
15 | static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) | |
16 | { | |
17 | return 0; | |
18 | } | |
19 | ||
20 | static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) | |
21 | { | |
22 | } | |
23 | ||
24 | const MemoryRegionOps hppa_pci_ignore_ops = { | |
25 | .read = ignore_read, | |
26 | .write = ignore_write, | |
27 | .endianness = DEVICE_BIG_ENDIAN, | |
28 | .valid = { | |
29 | .min_access_size = 1, | |
30 | .max_access_size = 8, | |
31 | }, | |
32 | .impl = { | |
33 | .min_access_size = 1, | |
34 | .max_access_size = 8, | |
35 | }, | |
36 | }; | |
37 | ||
38 | ||
39 | /* PCI config space reads/writes, to byte-word addressable memory. */ | |
40 | static uint64_t bw_conf1_read(void *opaque, hwaddr addr, | |
41 | unsigned size) | |
42 | { | |
43 | PCIBus *b = opaque; | |
44 | return pci_data_read(b, addr, size); | |
45 | } | |
46 | ||
47 | static void bw_conf1_write(void *opaque, hwaddr addr, | |
48 | uint64_t val, unsigned size) | |
49 | { | |
50 | PCIBus *b = opaque; | |
51 | pci_data_write(b, addr, val, size); | |
52 | } | |
53 | ||
54 | const MemoryRegionOps hppa_pci_conf1_ops = { | |
55 | .read = bw_conf1_read, | |
56 | .write = bw_conf1_write, | |
57 | .endianness = DEVICE_BIG_ENDIAN, | |
58 | .impl = { | |
59 | .min_access_size = 1, | |
60 | .max_access_size = 4, | |
61 | }, | |
62 | }; | |
63 | ||
64 | /* PCI/EISA Interrupt Acknowledge Cycle. */ | |
65 | ||
66 | static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) | |
67 | { | |
68 | return pic_read_irq(isa_pic); | |
69 | } | |
70 | ||
71 | static void special_write(void *opaque, hwaddr addr, | |
72 | uint64_t val, unsigned size) | |
73 | { | |
74 | trace_hppa_pci_iack_write(); | |
75 | } | |
76 | ||
77 | const MemoryRegionOps hppa_pci_iack_ops = { | |
78 | .read = iack_read, | |
79 | .write = special_write, | |
80 | .endianness = DEVICE_BIG_ENDIAN, | |
81 | .valid = { | |
82 | .min_access_size = 4, | |
83 | .max_access_size = 4, | |
84 | }, | |
85 | .impl = { | |
86 | .min_access_size = 4, | |
87 | .max_access_size = 4, | |
88 | }, | |
89 | }; |