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[mirror_qemu.git] / hw / i386 / intel_iommu_internal.h
CommitLineData
1da12ec4
LT		 1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * Lots of defines copied from kernel/include/linux/intel-iommu.h:
22 * Copyright (C) 2006-2008 Intel Corporation
23 * Author: Ashok Raj <ashok.raj@intel.com>
24 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
25 *
26 */
27
28#ifndef HW_I386_INTEL_IOMMU_INTERNAL_H
29#define HW_I386_INTEL_IOMMU_INTERNAL_H
30#include "hw/i386/intel_iommu.h"
31
32/*
33 * Intel IOMMU register specification
34 */
35#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
36#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
37#define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */
38#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
39#define DMAR_ECAP_REG_HI 0X14
40#define DMAR_GCMD_REG 0x18 /* Global command */
41#define DMAR_GSTS_REG 0x1c /* Global status */
42#define DMAR_RTADDR_REG 0x20 /* Root entry table */
43#define DMAR_RTADDR_REG_HI 0X24
44#define DMAR_CCMD_REG 0x28 /* Context command */
45#define DMAR_CCMD_REG_HI 0x2c
46#define DMAR_FSTS_REG 0x34 /* Fault status */
47#define DMAR_FECTL_REG 0x38 /* Fault control */
48#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data */
49#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr */
50#define DMAR_FEUADDR_REG 0x44 /* Upper address */
51#define DMAR_AFLOG_REG 0x58 /* Advanced fault control */
52#define DMAR_AFLOG_REG_HI 0X5c
53#define DMAR_PMEN_REG 0x64 /* Enable protected memory region */
54#define DMAR_PLMBASE_REG 0x68 /* PMRR low addr */
55#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
56#define DMAR_PHMBASE_REG 0x70 /* PMRR high base addr */
57#define DMAR_PHMBASE_REG_HI 0X74
58#define DMAR_PHMLIMIT_REG 0x78 /* PMRR high limit */
59#define DMAR_PHMLIMIT_REG_HI 0x7c
60#define DMAR_IQH_REG 0x80 /* Invalidation queue head */
61#define DMAR_IQH_REG_HI 0X84
62#define DMAR_IQT_REG 0x88 /* Invalidation queue tail */
63#define DMAR_IQT_REG_HI 0X8c
64#define DMAR_IQA_REG 0x90 /* Invalidation queue addr */
65#define DMAR_IQA_REG_HI 0x94
66#define DMAR_ICS_REG 0x9c /* Invalidation complete status */
67#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr */
68#define DMAR_IRTA_REG_HI 0xbc
69#define DMAR_IECTL_REG 0xa0 /* Invalidation event control */
70#define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */
71#define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */
72#define DMAR_IEUADDR_REG 0xac /* Invalidation event address */
73#define DMAR_PQH_REG 0xc0 /* Page request queue head */
74#define DMAR_PQH_REG_HI 0xc4
75#define DMAR_PQT_REG 0xc8 /* Page request queue tail*/
76#define DMAR_PQT_REG_HI 0xcc
77#define DMAR_PQA_REG 0xd0 /* Page request queue address */
78#define DMAR_PQA_REG_HI 0xd4
79#define DMAR_PRS_REG 0xdc /* Page request status */
80#define DMAR_PECTL_REG 0xe0 /* Page request event control */
81#define DMAR_PEDATA_REG 0xe4 /* Page request event data */
82#define DMAR_PEADDR_REG 0xe8 /* Page request event address */
83#define DMAR_PEUADDR_REG 0xec /* Page event upper address */
84#define DMAR_MTRRCAP_REG 0x100 /* MTRR capability */
85#define DMAR_MTRRCAP_REG_HI 0x104
86#define DMAR_MTRRDEF_REG 0x108 /* MTRR default type */
87#define DMAR_MTRRDEF_REG_HI 0x10c
88
89/* IOTLB registers */
90#define DMAR_IOTLB_REG_OFFSET 0xf0 /* Offset to the IOTLB registers */
91#define DMAR_IVA_REG DMAR_IOTLB_REG_OFFSET /* Invalidate address */
92#define DMAR_IVA_REG_HI (DMAR_IVA_REG + 4)
93/* IOTLB invalidate register */
94#define DMAR_IOTLB_REG (DMAR_IOTLB_REG_OFFSET + 0x8)
95#define DMAR_IOTLB_REG_HI (DMAR_IOTLB_REG + 4)
96
97/* FRCD */
98#define DMAR_FRCD_REG_OFFSET 0x220 /* Offset to the fault recording regs */
99/* NOTICE: If you change the DMAR_FRCD_REG_NR, please remember to change the
100 * DMAR_REG_SIZE in include/hw/i386/intel_iommu.h.
101 * #define DMAR_REG_SIZE (DMAR_FRCD_REG_OFFSET + 16 * DMAR_FRCD_REG_NR)
102 */
103#define DMAR_FRCD_REG_NR 1ULL /* Num of fault recording regs */
104
105#define DMAR_FRCD_REG_0_0 0x220 /* The 0th fault recording regs */
106#define DMAR_FRCD_REG_0_1 0x224
107#define DMAR_FRCD_REG_0_2 0x228
108#define DMAR_FRCD_REG_0_3 0x22c
109
110/* Interrupt Address Range */
111#define VTD_INTERRUPT_ADDR_FIRST 0xfee00000ULL
112#define VTD_INTERRUPT_ADDR_LAST 0xfeefffffULL
651e4cef
PX		 113#define VTD_INTERRUPT_ADDR_SIZE (VTD_INTERRUPT_ADDR_LAST - \
114 VTD_INTERRUPT_ADDR_FIRST + 1)
1da12ec4 115
b5a280c0 116/* The shift of source_id in the key of IOTLB hash table */
ec1a78ce
JW		 117#define VTD_IOTLB_SID_SHIFT 26
118#define VTD_IOTLB_LVL_SHIFT 42
119#define VTD_IOTLB_PASID_SHIFT 44
b5a280c0
LT		 120#define VTD_IOTLB_MAX_SIZE 1024 /* Max size of the hash table */
121
1da12ec4
LT		 122/* IOTLB_REG */
123#define VTD_TLB_GLOBAL_FLUSH (1ULL << 60) /* Global invalidation */
124#define VTD_TLB_DSI_FLUSH (2ULL << 60) /* Domain-selective */
125#define VTD_TLB_PSI_FLUSH (3ULL << 60) /* Page-selective */
126#define VTD_TLB_FLUSH_GRANU_MASK (3ULL << 60)
127#define VTD_TLB_GLOBAL_FLUSH_A (1ULL << 57)
128#define VTD_TLB_DSI_FLUSH_A (2ULL << 57)
129#define VTD_TLB_PSI_FLUSH_A (3ULL << 57)
130#define VTD_TLB_FLUSH_GRANU_MASK_A (3ULL << 57)
131#define VTD_TLB_IVT (1ULL << 63)
b5a280c0
LT		 132#define VTD_TLB_DID(val) (((val) >> 32) & VTD_DOMAIN_ID_MASK)
133
134/* IVA_REG */
37f51384 135#define VTD_IVA_ADDR(val) ((val) & ~0xfffULL)
b5a280c0 136#define VTD_IVA_AM(val) ((val) & 0x3fULL)
1da12ec4
LT		 137
138/* GCMD_REG */
139#define VTD_GCMD_TE (1UL << 31)
140#define VTD_GCMD_SRTP (1UL << 30)
141#define VTD_GCMD_SFL (1UL << 29)
142#define VTD_GCMD_EAFL (1UL << 28)
143#define VTD_GCMD_WBF (1UL << 27)
144#define VTD_GCMD_QIE (1UL << 26)
145#define VTD_GCMD_IRE (1UL << 25)
146#define VTD_GCMD_SIRTP (1UL << 24)
147#define VTD_GCMD_CFI (1UL << 23)
148
149/* GSTS_REG */
150#define VTD_GSTS_TES (1UL << 31)
151#define VTD_GSTS_RTPS (1UL << 30)
152#define VTD_GSTS_FLS (1UL << 29)
153#define VTD_GSTS_AFLS (1UL << 28)
154#define VTD_GSTS_WBFS (1UL << 27)
155#define VTD_GSTS_QIES (1UL << 26)
156#define VTD_GSTS_IRES (1UL << 25)
157#define VTD_GSTS_IRTPS (1UL << 24)
158#define VTD_GSTS_CFIS (1UL << 23)
159
160/* CCMD_REG */
161#define VTD_CCMD_ICC (1ULL << 63)
162#define VTD_CCMD_GLOBAL_INVL (1ULL << 61)
163#define VTD_CCMD_DOMAIN_INVL (2ULL << 61)
164#define VTD_CCMD_DEVICE_INVL (3ULL << 61)
165#define VTD_CCMD_CIRG_MASK (3ULL << 61)
166#define VTD_CCMD_GLOBAL_INVL_A (1ULL << 59)
167#define VTD_CCMD_DOMAIN_INVL_A (2ULL << 59)
168#define VTD_CCMD_DEVICE_INVL_A (3ULL << 59)
169#define VTD_CCMD_CAIG_MASK (3ULL << 59)
d92fa2dc
LT		 170#define VTD_CCMD_DID(val) ((val) & VTD_DOMAIN_ID_MASK)
171#define VTD_CCMD_SID(val) (((val) >> 16) & 0xffffULL)
172#define VTD_CCMD_FM(val) (((val) >> 32) & 3ULL)
1da12ec4
LT		 173
174/* RTADDR_REG */
fb43cf73 175#define VTD_RTADDR_SMT (1ULL << 10)
92e5d85e 176#define VTD_RTADDR_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
1da12ec4 177
a5861439 178/* IRTA_REG */
92e5d85e 179#define VTD_IRTA_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
28589311 180#define VTD_IRTA_EIME (1ULL << 11)
a5861439
PX		 181#define VTD_IRTA_SIZE_MASK (0xfULL)
182
1da12ec4
LT		 183/* ECAP_REG */
184/* (offset >> 4) << 8 */
185#define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
186#define VTD_ECAP_QI (1ULL << 1)
554f5e16 187#define VTD_ECAP_DT (1ULL << 2)
d54bd7f8
PX		 188/* Interrupt Remapping support */
189#define VTD_ECAP_IR (1ULL << 3)
28589311 190#define VTD_ECAP_EIM (1ULL << 4)
dbaabb25 191#define VTD_ECAP_PT (1ULL << 6)
b8ffd7d6 192#define VTD_ECAP_SC (1ULL << 7)
a3f409cb 193#define VTD_ECAP_MHMV (15ULL << 20)
4a4f219e 194#define VTD_ECAP_SRS (1ULL << 31)
1b2b1237 195#define VTD_ECAP_PASID (1ULL << 40)
c0c1d351 196#define VTD_ECAP_SMTS (1ULL << 43)
4a4f219e 197#define VTD_ECAP_SLTS (1ULL << 46)
1da12ec4
LT		 198
199/* CAP_REG */
200/* (offset >> 4) << 24 */
201#define VTD_CAP_FRO (DMAR_FRCD_REG_OFFSET << 20)
202#define VTD_CAP_NFR ((DMAR_FRCD_REG_NR - 1) << 40)
203#define VTD_DOMAIN_ID_SHIFT 16 /* 16-bit domain id for 64K domains */
d92fa2dc 204#define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
1da12ec4 205#define VTD_CAP_ND (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
92e5d85e
PS		 206#define VTD_ADDRESS_SIZE(aw) (1ULL << (aw))
207#define VTD_CAP_MGAW(aw) ((((aw) - 1) & 0x3fULL) << 16)
d66b969b 208#define VTD_MAMV 18ULL
b5a280c0
LT		 209#define VTD_CAP_MAMV (VTD_MAMV << 48)
210#define VTD_CAP_PSI (1ULL << 39)
d66b969b 211#define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35))
ccc23bb0
PX		 212#define VTD_CAP_DRAIN_WRITE (1ULL << 54)
213#define VTD_CAP_DRAIN_READ (1ULL << 55)
214#define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE)
3b40f0e5 215#define VTD_CAP_CM (1ULL << 7)
1b2b1237
JW		 216#define VTD_PASID_ID_SHIFT 20
217#define VTD_PASID_ID_MASK ((1ULL << VTD_PASID_ID_SHIFT) - 1)
1da12ec4
LT		 218
219/* Supported Adjusted Guest Address Widths */
220#define VTD_CAP_SAGAW_SHIFT 8
221#define VTD_CAP_SAGAW_MASK (0x1fULL << VTD_CAP_SAGAW_SHIFT)
222 /* 39-bit AGAW, 3-level page-table */
223#define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT)
224 /* 48-bit AGAW, 4-level page-table */
225#define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
1da12ec4
LT		 226
227/* IQT_REG */
c0c1d351
LY		 228#define VTD_IQT_QT(dw_bit, val) (dw_bit ? (((val) >> 5) & 0x3fffULL) : \
229 (((val) >> 4) & 0x7fffULL))
230#define VTD_IQT_QT_256_RSV_BIT 0x10
1da12ec4
LT		 231
232/* IQA_REG */
92e5d85e 233#define VTD_IQA_IQA_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
1da12ec4 234#define VTD_IQA_QS 0x7ULL
c0c1d351 235#define VTD_IQA_DW_MASK 0x800
1da12ec4
LT		 236
237/* IQH_REG */
a4544c45
LY		 238#define VTD_IQH_QH_SHIFT_4 4
239#define VTD_IQH_QH_SHIFT_5 5
1da12ec4
LT		 240#define VTD_IQH_QH_MASK 0x7fff0ULL
241
242/* ICS_REG */
243#define VTD_ICS_IWC 1UL
244
245/* IECTL_REG */
246#define VTD_IECTL_IM (1UL << 31)
247#define VTD_IECTL_IP (1UL << 30)
248
249/* FSTS_REG */
250#define VTD_FSTS_FRI_MASK 0xff00UL
251#define VTD_FSTS_FRI(val) ((((uint32_t)(val)) << 8) & VTD_FSTS_FRI_MASK)
252#define VTD_FSTS_IQE (1UL << 4)
253#define VTD_FSTS_PPF (1UL << 1)
254#define VTD_FSTS_PFO 1UL
255
256/* FECTL_REG */
257#define VTD_FECTL_IM (1UL << 31)
258#define VTD_FECTL_IP (1UL << 30)
259
260/* Fault Recording Register */
261/* For the high 64-bit of 128-bit */
262#define VTD_FRCD_F (1ULL << 63)
263#define VTD_FRCD_T (1ULL << 62)
264#define VTD_FRCD_FR(val) (((val) & 0xffULL) << 32)
265#define VTD_FRCD_SID_MASK 0xffffULL
266#define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK)
267/* For the low 64-bit of 128-bit */
37f51384 268#define VTD_FRCD_FI(val) ((val) & ~0xfffULL)
1b2b1237
JW		 269#define VTD_FRCD_PV(val) (((val) & 0xffffULL) << 40)
270#define VTD_FRCD_PP(val) (((val) & 0x1) << 31)
1da12ec4
LT		 271
272/* DMA Remapping Fault Conditions */
273typedef enum VTDFaultReason {
274 VTD_FR_RESERVED = 0, /* Reserved for Advanced Fault logging */
275 VTD_FR_ROOT_ENTRY_P = 1, /* The Present(P) field of root-entry is 0 */
276 VTD_FR_CONTEXT_ENTRY_P, /* The Present(P) field of context-entry is 0 */
277 VTD_FR_CONTEXT_ENTRY_INV, /* Invalid programming of a context-entry */
278 VTD_FR_ADDR_BEYOND_MGAW, /* Input-address above (2^x-1) */
279 VTD_FR_WRITE, /* No write permission */
280 VTD_FR_READ, /* No read permission */
281 /* Fail to access a second-level paging entry (not SL_PML4E) */
282 VTD_FR_PAGING_ENTRY_INV,
283 VTD_FR_ROOT_TABLE_INV, /* Fail to access a root-entry */
284 VTD_FR_CONTEXT_TABLE_INV, /* Fail to access a context-entry */
285 /* Non-zero reserved field in a present root-entry */
286 VTD_FR_ROOT_ENTRY_RSVD,
287 /* Non-zero reserved field in a present context-entry */
288 VTD_FR_CONTEXT_ENTRY_RSVD,
289 /* Non-zero reserved field in a second-level paging entry with at lease one
290 * Read(R) and Write(W) or Execute(E) field is Set.
291 */
292 VTD_FR_PAGING_ENTRY_RSVD,
293 /* Translation request or translated request explicitly blocked dut to the
294 * programming of the Translation Type (T) field in the present
295 * context-entry.
296 */
297 VTD_FR_CONTEXT_ENTRY_TT,
ea97a1bd
JW		 298 /* Output address in the interrupt address range */
299 VTD_FR_INTERRUPT_ADDR = 0xE,
a4ca297e
PX		 300
301 /* Interrupt remapping transition faults */
302 VTD_FR_IR_REQ_RSVD = 0x20, /* One or more IR request reserved
303 * fields set */
304 VTD_FR_IR_INDEX_OVER = 0x21, /* Index value greater than max */
305 VTD_FR_IR_ENTRY_P = 0x22, /* Present (P) not set in IRTE */
306 VTD_FR_IR_ROOT_INVAL = 0x23, /* IR Root table invalid */
307 VTD_FR_IR_IRTE_RSVD = 0x24, /* IRTE Rsvd field non-zero with
308 * Present flag set */
309 VTD_FR_IR_REQ_COMPAT = 0x25, /* Encountered compatible IR
310 * request while disabled */
311 VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */
312
fb43cf73
LY		 313 VTD_FR_PASID_TABLE_INV = 0x58, /*Invalid PASID table entry */
314
ea97a1bd
JW		 315 /* Output address in the interrupt address range for scalable mode */
316 VTD_FR_SM_INTERRUPT_ADDR = 0x87,
1da12ec4
LT		 317 VTD_FR_MAX, /* Guard */
318} VTDFaultReason;
319
d92fa2dc
LT		 320#define VTD_CONTEXT_CACHE_GEN_MAX 0xffffffffUL
321
02a2cbc8
PX		 322/* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */
323struct VTDInvDescIEC {
4572b22c
TH		 324#if HOST_BIG_ENDIAN
325 uint64_t reserved_2:16;
326 uint64_t index:16; /* Start index to invalidate */
327 uint64_t index_mask:5; /* 2^N for continuous int invalidation */
328 uint64_t resved_1:22;
329 uint64_t granularity:1; /* If set, it's global IR invalidation */
330 uint64_t type:4; /* Should always be 0x4 */
331#else
02a2cbc8
PX		 332 uint32_t type:4; /* Should always be 0x4 */
333 uint32_t granularity:1; /* If set, it's global IR invalidation */
334 uint32_t resved_1:22;
335 uint32_t index_mask:5; /* 2^N for continuous int invalidation */
336 uint32_t index:16; /* Start index to invalidate */
337 uint32_t reserved_2:16;
4572b22c 338#endif
02a2cbc8
PX		 339};
340typedef struct VTDInvDescIEC VTDInvDescIEC;
341
ed7b8fbc 342/* Queued Invalidation Descriptor */
02a2cbc8
PX		 343union VTDInvDesc {
344 struct {
345 uint64_t lo;
346 uint64_t hi;
347 };
c0c1d351
LY		 348 struct {
349 uint64_t val[4];
350 };
02a2cbc8
PX		 351 union {
352 VTDInvDescIEC iec;
353 };
ed7b8fbc 354};
02a2cbc8 355typedef union VTDInvDesc VTDInvDesc;
ed7b8fbc
LT		 356
357/* Masks for struct VTDInvDesc */
358#define VTD_INV_DESC_TYPE 0xf
359#define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */
360#define VTD_INV_DESC_IOTLB 0x2
554f5e16 361#define VTD_INV_DESC_DEVICE 0x3
b7910472
PX		 362#define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache
363 Invalidate Descriptor */
ed7b8fbc 364#define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */
4a4f219e
YS		 365#define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalidate Desc */
366#define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc */
ed7b8fbc
LT		 367#define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */
368
369/* Masks for Invalidation Wait Descriptor*/
370#define VTD_INV_DESC_WAIT_SW (1ULL << 5)
371#define VTD_INV_DESC_WAIT_IF (1ULL << 4)
372#define VTD_INV_DESC_WAIT_FN (1ULL << 6)
373#define VTD_INV_DESC_WAIT_DATA_SHIFT 32
374#define VTD_INV_DESC_WAIT_RSVD_LO 0Xffffff80ULL
375#define VTD_INV_DESC_WAIT_RSVD_HI 3ULL
1da12ec4 376
d92fa2dc
LT		 377/* Masks for Context-cache Invalidation Descriptor */
378#define VTD_INV_DESC_CC_G (3ULL << 4)
379#define VTD_INV_DESC_CC_GLOBAL (1ULL << 4)
380#define VTD_INV_DESC_CC_DOMAIN (2ULL << 4)
381#define VTD_INV_DESC_CC_DEVICE (3ULL << 4)
382#define VTD_INV_DESC_CC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
383#define VTD_INV_DESC_CC_SID(val) (((val) >> 32) & 0xffffUL)
384#define VTD_INV_DESC_CC_FM(val) (((val) >> 48) & 3UL)
385#define VTD_INV_DESC_CC_RSVD 0xfffc00000000ffc0ULL
386
b5a280c0
LT		 387/* Masks for IOTLB Invalidate Descriptor */
388#define VTD_INV_DESC_IOTLB_G (3ULL << 4)
389#define VTD_INV_DESC_IOTLB_GLOBAL (1ULL << 4)
390#define VTD_INV_DESC_IOTLB_DOMAIN (2ULL << 4)
391#define VTD_INV_DESC_IOTLB_PAGE (3ULL << 4)
392#define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
37f51384 393#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL)
b5a280c0
LT		 394#define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
395#define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000ff00ULL
396#define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL
1b2b1237
JW		 397#define VTD_INV_DESC_IOTLB_PASID_PASID (2ULL << 4)
398#define VTD_INV_DESC_IOTLB_PASID_PAGE (3ULL << 4)
399#define VTD_INV_DESC_IOTLB_PASID(val) (((val) >> 32) & VTD_PASID_ID_MASK)
400#define VTD_INV_DESC_IOTLB_PASID_RSVD_LO 0xfff00000000001c0ULL
401#define VTD_INV_DESC_IOTLB_PASID_RSVD_HI 0xf80ULL
b5a280c0 402
554f5e16
JW		 403/* Mask for Device IOTLB Invalidate Descriptor */
404#define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
405#define VTD_INV_DESC_DEVICE_IOTLB_SIZE(val) ((val) & 0x1)
406#define VTD_INV_DESC_DEVICE_IOTLB_SID(val) (((val) >> 32) & 0xFFFFULL)
407#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL
408#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
409
92e5d85e 410/* Rsvd field masks for spte */
0192d667
JW		 411#define VTD_SPTE_SNP 0x800ULL
412
e48929c7
QY		 413#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
414 dt_supported ? \
415 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
92e5d85e
PS		 416 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
417#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
418 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
419#define VTD_SPTE_PAGE_L3_RSVD_MASK(aw) \
420 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
421#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
422 (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
ce586f3b 423
e48929c7
QY		 424#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
425 dt_supported ? \
426 (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
92e5d85e 427 (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
e48929c7
QY		 428#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
429 dt_supported ? \
430 (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
92e5d85e 431 (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
92e5d85e 432
b5a280c0
LT		 433/* Information about page-selective IOTLB invalidate */
434struct VTDIOTLBPageInvInfo {
435 uint16_t domain_id;
1b2b1237 436 uint32_t pasid;
d66b969b 437 uint64_t addr;
b5a280c0
LT		 438 uint8_t mask;
439};
440typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
441
1da12ec4
LT		 442/* Pagesize of VTD paging structures, including root and context tables */
443#define VTD_PAGE_SHIFT 12
444#define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT)
445
446#define VTD_PAGE_SHIFT_4K 12
447#define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
448#define VTD_PAGE_SHIFT_2M 21
449#define VTD_PAGE_MASK_2M (~((1ULL << VTD_PAGE_SHIFT_2M) - 1))
450#define VTD_PAGE_SHIFT_1G 30
451#define VTD_PAGE_MASK_1G (~((1ULL << VTD_PAGE_SHIFT_1G) - 1))
452
453struct VTDRootEntry {
fb43cf73
LY		 454 uint64_t lo;
455 uint64_t hi;
1da12ec4
LT		 456};
457typedef struct VTDRootEntry VTDRootEntry;
458
459/* Masks for struct VTDRootEntry */
460#define VTD_ROOT_ENTRY_P 1ULL
461#define VTD_ROOT_ENTRY_CTP (~0xfffULL)
462
463#define VTD_ROOT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDRootEntry))
92e5d85e 464#define VTD_ROOT_ENTRY_RSVD(aw) (0xffeULL | ~VTD_HAW_MASK(aw))
1da12ec4 465
fb43cf73
LY		 466#define VTD_DEVFN_CHECK_MASK 0x80
467
1da12ec4
LT		 468/* Masks for struct VTDContextEntry */
469/* lo */
470#define VTD_CONTEXT_ENTRY_P (1ULL << 0)
471#define VTD_CONTEXT_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */
472#define VTD_CONTEXT_ENTRY_TT (3ULL << 2) /* Translation Type */
473#define VTD_CONTEXT_TT_MULTI_LEVEL 0
554f5e16
JW		 474#define VTD_CONTEXT_TT_DEV_IOTLB (1ULL << 2)
475#define VTD_CONTEXT_TT_PASS_THROUGH (2ULL << 2)
1da12ec4
LT		 476/* Second Level Page Translation Pointer*/
477#define VTD_CONTEXT_ENTRY_SLPTPTR (~0xfffULL)
92e5d85e 478#define VTD_CONTEXT_ENTRY_RSVD_LO(aw) (0xff0ULL | ~VTD_HAW_MASK(aw))
1da12ec4
LT		 479/* hi */
480#define VTD_CONTEXT_ENTRY_AW 7ULL /* Adjusted guest-address-width */
b5a280c0 481#define VTD_CONTEXT_ENTRY_DID(val) (((val) >> 8) & VTD_DOMAIN_ID_MASK)
1da12ec4
LT		 482#define VTD_CONTEXT_ENTRY_RSVD_HI 0xffffffffff000080ULL
483
484#define VTD_CONTEXT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDContextEntry))
485
fb43cf73
LY		 486#define VTD_CTX_ENTRY_LEGACY_SIZE 16
487#define VTD_CTX_ENTRY_SCALABLE_SIZE 32
488
489#define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff
490#define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw))
491#define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL
492
493/* PASID Table Related Definitions */
494#define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL)
495#define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL)
496#define VTD_PASID_DIR_ENTRY_SIZE 8
497#define VTD_PASID_ENTRY_SIZE 64
498#define VTD_PASID_DIR_BITS_MASK (0x3fffULL)
499#define VTD_PASID_DIR_INDEX(pasid) (((pasid) >> 6) & VTD_PASID_DIR_BITS_MASK)
500#define VTD_PASID_DIR_FPD (1ULL << 1) /* Fault Processing Disable */
501#define VTD_PASID_TABLE_BITS_MASK (0x3fULL)
502#define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK)
503#define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */
504
505/* PASID Granular Translation Type Mask */
56fc1e6a 506#define VTD_PASID_ENTRY_P 1ULL
fb43cf73
LY		 507#define VTD_SM_PASID_ENTRY_PGTT (7ULL << 6)
508#define VTD_SM_PASID_ENTRY_FLT (1ULL << 6)
509#define VTD_SM_PASID_ENTRY_SLT (2ULL << 6)
510#define VTD_SM_PASID_ENTRY_NESTED (3ULL << 6)
511#define VTD_SM_PASID_ENTRY_PT (4ULL << 6)
512
513#define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-width */
514#define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK)
515
516/* Second Level Page Translation Pointer*/
517#define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL)
518
1da12ec4
LT		 519/* Paging Structure common */
520#define VTD_SL_PT_PAGE_SIZE_MASK (1ULL << 7)
521/* Bits to decide the offset for each level */
522#define VTD_SL_LEVEL_BITS 9
523
524/* Second Level Paging Structure */
525#define VTD_SL_PML4_LEVEL 4
526#define VTD_SL_PDP_LEVEL 3
527#define VTD_SL_PD_LEVEL 2
528#define VTD_SL_PT_LEVEL 1
529#define VTD_SL_PT_ENTRY_NR 512
530
531/* Masks for Second Level Paging Entry */
532#define VTD_SL_RW_MASK 3ULL
533#define VTD_SL_R 1ULL
534#define VTD_SL_W (1ULL << 1)
92e5d85e 535#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
1da12ec4 536#define VTD_SL_IGN_COM 0xbff0000000000000ULL
e48929c7 537#define VTD_SL_TM (1ULL << 62)
1da12ec4
LT		 538
539#endif
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