struct tb_desc desc;
uint32_t h;
- desc.env = cpu->env_ptr;
+ desc.env = cpu_env(cpu);
desc.cs_base = cs_base;
desc.flags = flags;
desc.cflags = cflags;
static inline TranslationBlock * QEMU_DISABLE_CFI
cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
uintptr_t ret;
TranslationBlock *last_tb;
const void *tb_ptr = itb->tc.ptr;
void cpu_exec_step_atomic(CPUState *cpu)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
TranslationBlock *tb;
vaddr pc;
uint64_t cs_base;
uint64_t cs_base;
uint32_t flags, cflags;
- cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags);
+ cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags);
/*
* When requested, use an exact setting for cflags for the next
void tlb_init(CPUState *cpu)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
int64_t now = get_clock_realtime();
int i;
void tlb_destroy(CPUState *cpu)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
int i;
qemu_spin_destroy(&env_tlb(env)->c.lock);
size_t full = 0, part = 0, elide = 0;
CPU_FOREACH(cpu) {
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
full += qatomic_read(&env_tlb(env)->c.full_flush_count);
part += qatomic_read(&env_tlb(env)->c.part_flush_count);
static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
uint16_t asked = data.host_int;
uint16_t all_dirty, work, to_clean;
int64_t now = get_clock_realtime();
vaddr addr,
uint16_t idxmap)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
int mmu_idx;
assert_cpu_is_self(cpu);
static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
TLBFlushRangeData d)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
int mmu_idx;
assert_cpu_is_self(cpu);
int mmu_idx;
- env = cpu->env_ptr;
+ env = cpu_env(cpu);
qemu_spin_lock(&env_tlb(env)->c.lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
unsigned int i;
so that it is no longer dirty */
void tlb_set_dirty(CPUState *cpu, vaddr addr)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
int mmu_idx;
assert_cpu_is_self(cpu);
void tlb_set_page_full(CPUState *cpu, int mmu_idx,
vaddr addr, CPUTLBEntryFull *full)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
CPUTLB *tlb = env_tlb(env);
CPUTLBDesc *desc = &tlb->d[mmu_idx];
MemoryRegionSection *section;
bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx,
bool is_store, struct qemu_plugin_hwaddr *data)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr);
uintptr_t index = tlb_index(env, mmu_idx, addr);
MMUAccessType access_type = is_store ? MMU_DATA_STORE : MMU_DATA_LOAD;
} else {
if (ptb->vaddr2 == -1) {
ptb->vaddr2 = TARGET_PAGE_ALIGN(db->pc_first);
- get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->haddr2);
+ get_page_addr_code_hostp(cpu_env(cpu), ptb->vaddr2, &ptb->haddr2);
}
pinsn->haddr = ptb->haddr2 + pinsn->vaddr - ptb->vaddr2;
}
vaddr pc, uint64_t cs_base,
uint32_t flags, int cflags)
{
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
TranslationBlock *tb, *existing_tb;
tb_page_addr_t phys_pc, phys_p2;
tcg_insn_unit *gen_code_buf;
} else {
/* The exception probably happened in a helper. The CPU state should
have been saved before calling it. Fetch the PC from there. */
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
vaddr pc;
uint64_t cs_base;
tb_page_addr_t addr;
ac->init_machine(NULL);
}
cpu = cpu_create(cpu_type);
- env = cpu->env_ptr;
+ env = cpu_env(cpu);
cpu_reset(cpu);
thread_cpu = cpu;
static G_NORETURN
void dump_core_and_abort(int target_sig)
{
- CPUArchState *env = thread_cpu->env_ptr;
- CPUState *cpu = env_cpu(env);
+ CPUState *cpu = thread_cpu;
+ CPUArchState *env = cpu_env(cpu);
TaskState *ts = cpu->opaque;
int core_dumped = 0;
int host_sig;
void force_sig_fault(int sig, int code, abi_ulong addr)
{
CPUState *cpu = thread_cpu;
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
target_siginfo_t info = {};
info.si_signo = sig;
static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
{
- CPUArchState *env = thread_cpu->env_ptr;
- CPUState *cpu = env_cpu(env);
+ CPUState *cpu = thread_cpu;
TaskState *ts = cpu->opaque;
target_siginfo_t tinfo;
ucontext_t *uc = puc;
static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
uint64_t mode = get_param(params, 2)->val_ull;
#ifdef CONFIG_LINUX
- int fd = do_guest_openat(gdbserver_state.g_cpu->env_ptr, 0, filename,
+ int fd = do_guest_openat(cpu_env(gdbserver_state.g_cpu), 0, filename,
flags, mode, false);
#else
int fd = open(filename, flags, mode);
static uint64_t kvmclock_current_nsec(KVMClockState *s)
{
CPUState *cpu = first_cpu;
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
hwaddr kvmclock_struct_pa;
uint64_t migration_tsc = env->tsc;
struct pvclock_vcpu_time_info time;
/* Register the env for all VPs with the GIC */
for (i = 0; i < s->num_vps; i++) {
if (cs != NULL) {
- s->vps[i].env = cs->env_ptr;
+ s->vps[i].env = cpu_env(cs);
cs = CPU_NEXT(cs);
} else {
error_setg(errp,
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
CPUState *cpu = cpu_by_arch_id(hartid);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
"aclint-mtimer: invalid hartid: %zu", hartid);
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
CPUState *cpu = cpu_by_arch_id(hartid);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
"aclint-mtimer: invalid hartid: %zu", hartid);
/* Check if timer interrupt is triggered for each hart. */
for (i = 0; i < mtimer->num_harts; i++) {
CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
if (!env) {
continue;
}
for (i = 0; i < num_harts; i++) {
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
riscv_aclint_mtimer_callback *cb =
g_new0(riscv_aclint_mtimer_callback, 1);
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
CPUState *cpu = cpu_by_arch_id(hartid);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
"aclint-swi: invalid hartid: %zu", hartid);
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
CPUState *cpu = cpu_by_arch_id(hartid);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
"aclint-swi: invalid hartid: %zu", hartid);
RISCVIMSICState *imsic = RISCV_IMSIC(dev);
RISCVCPU *rcpu = RISCV_CPU(cpu_by_arch_id(imsic->hartid));
CPUState *cpu = cpu_by_arch_id(imsic->hartid);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
if (!kvm_irqchip_in_kernel()) {
imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
MachineState *machine = MACHINE(pms);
unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
- CPUPPCState *env = first_cpu->env_ptr;
+ CPUPPCState *env = cpu_env(first_cpu);
int ret = -1;
uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
int fdt_size;
if (cpu == NULL) {
continue;
}
- env = cpu->env_ptr;
+ env = cpu_env(cpu);
cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
qemu_fdt_add_subnode(fdt, cpu_name);
* Older KVM versions with older guest kernels were broken
* with the magic page, don't allow the guest to map it.
*/
- if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
+ if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall,
sizeof(hypercall))) {
_FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
hypercall, sizeof(hypercall)));
*/
static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
{
- cpu->parent_obj.env_ptr = &cpu->env;
}
/* Validate correct placement of CPUArchState. */
* @num_ases: number of CPUAddressSpaces in @cpu_ases
* @as: Pointer to the first AddressSpace, for the convenience of targets which
* only have a single AddressSpace
- * @env_ptr: Pointer to subclass-specific CPUArchState field.
* @gdb_regs: Additional GDB registers.
* @gdb_num_regs: Number of total registers accessible to GDB.
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
AddressSpace *as;
MemoryRegion *memory;
- CPUArchState *env_ptr;
-
CPUJumpCache *tb_jmp_cache;
struct GDBRegisterState *gdb_regs;
QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
+static inline CPUArchState *cpu_env(CPUState *cpu)
+{
+ /* We validate that CPUArchState follows CPUState in cpu-all.h. */
+ return (CPUArchState *)(cpu + 1);
+}
+
typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
extern CPUTailQ cpus;
static const char *get_elf_platform(void)
{
- CPUARMState *env = thread_cpu->env_ptr;
+ CPUARMState *env = cpu_env(thread_cpu);
#if TARGET_BIG_ENDIAN
# define END "b"
if (cpu == thread_cpu) {
continue;
}
- fill_thread_info(info, cpu->env_ptr);
+ fill_thread_info(info, cpu_env(cpu));
}
}
static void target_cpu_free(void *obj)
{
- CPUArchState *env = ((CPUState *)obj)->env_ptr;
+ CPUArchState *env = cpu_env(obj);
target_munmap(env->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES);
g_free(obj);
}
{
CPUState *cpu = env_cpu(env);
CPUState *new_cpu = cpu_create(cpu_type);
- CPUArchState *new_env = new_cpu->env_ptr;
+ CPUArchState *new_env = cpu_env(new_cpu);
CPUBreakpoint *bp;
/* Reset non arch specific state */
ac->init_machine(NULL);
}
cpu = cpu_create(cpu_type);
- env = cpu->env_ptr;
+ env = cpu_env(cpu);
cpu_reset(cpu);
thread_cpu = cpu;
void force_sig(int sig)
{
CPUState *cpu = thread_cpu;
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
target_siginfo_t info = {};
info.si_signo = sig;
void force_sig_fault(int sig, int code, abi_ulong addr)
{
CPUState *cpu = thread_cpu;
- CPUArchState *env = cpu->env_ptr;
+ CPUArchState *env = cpu_env(cpu);
target_siginfo_t info = {};
info.si_signo = sig;
/* abort execution with signal */
static G_NORETURN
-void dump_core_and_abort(CPUArchState *cpu_env, int target_sig)
+void dump_core_and_abort(CPUArchState *env, int target_sig)
{
- CPUState *cpu = thread_cpu;
- CPUArchState *env = cpu->env_ptr;
+ CPUState *cpu = env_cpu(env);
TaskState *ts = (TaskState *)cpu->opaque;
int host_sig, core_dumped = 0;
struct sigaction act;
target_sig, strsignal(host_sig), "core dumped" );
}
- preexit_cleanup(cpu_env, 128 + target_sig);
+ preexit_cleanup(env, 128 + target_sig);
/* The proper exit code for dying from an uncaught signal is
* -<signal>. The kernel doesn't allow exit() or _exit() to pass
static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
{
- CPUArchState *env = thread_cpu->env_ptr;
- CPUState *cpu = env_cpu(env);
+ CPUState *cpu = thread_cpu;
+ CPUArchState *env = cpu_env(cpu);
TaskState *ts = cpu->opaque;
target_siginfo_t tinfo;
host_sigcontext *uc = puc;
{
CPUState *cs = mon_get_cpu(mon);
- return cs ? cs->env_ptr : NULL;
+ return cs ? cpu_env(cs) : NULL;
}
int monitor_get_cpu_index(Monitor *mon)
static void common_semi_rw_cb(CPUState *cs, uint64_t ret, int err)
{
/* Recover the original length from the third argument. */
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
target_ulong args = common_semi_arg(cs, 1);
target_ulong arg2;
GET_ARG(2);
common_semi_readc_cb(CPUState *cs, uint64_t ret, int err)
{
if (!err) {
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
uint8_t ch;
if (get_user_u8(ch, common_semi_stack_bottom(cs) - 1)) {
*/
void do_common_semihosting(CPUState *cs)
{
- CPUArchState *env = cs->env_ptr;
+ CPUArchState *env = cpu_env(cs);
target_ulong args;
target_ulong arg0, arg1, arg2, arg3;
target_ulong ul_ret;
*/
static int validate_strlen(CPUState *cs, target_ulong str, target_ulong tlen)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char c;
if (tlen == 0) {
target_ulong tstr, target_ulong tlen)
{
int ret = validate_strlen(cs, tstr, tlen);
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char *str = NULL;
if (ret > 0) {
static int copy_stat_to_user(CPUState *cs, target_ulong addr,
const struct stat *s)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
struct gdb_stat *p;
if (s->st_dev != (uint32_t)s->st_dev ||
target_ulong fname, target_ulong fname_len,
int gdb_flags, int mode)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char *p;
int ret, host_flags = O_BINARY;
static void host_read(CPUState *cs, gdb_syscall_complete_cb complete,
GuestFD *gf, target_ulong buf, target_ulong len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
void *ptr = lock_user(VERIFY_WRITE, buf, len, 0);
ssize_t ret;
static void host_write(CPUState *cs, gdb_syscall_complete_cb complete,
GuestFD *gf, target_ulong buf, target_ulong len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
void *ptr = lock_user(VERIFY_READ, buf, len, 1);
ssize_t ret;
target_ulong fname, target_ulong fname_len,
target_ulong addr)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
struct stat buf;
char *name;
int ret, err;
static void host_remove(CPUState *cs, gdb_syscall_complete_cb complete,
target_ulong fname, target_ulong fname_len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char *p;
int ret;
target_ulong oname, target_ulong oname_len,
target_ulong nname, target_ulong nname_len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char *ostr, *nstr;
int ret;
static void host_system(CPUState *cs, gdb_syscall_complete_cb complete,
target_ulong cmd, target_ulong cmd_len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char *p;
int ret;
static void host_gettimeofday(CPUState *cs, gdb_syscall_complete_cb complete,
target_ulong tv_addr, target_ulong tz_addr)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
struct gdb_timeval *p;
int64_t rt;
static void staticfile_read(CPUState *cs, gdb_syscall_complete_cb complete,
GuestFD *gf, target_ulong buf, target_ulong len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
target_ulong rest = gf->staticfile.len - gf->staticfile.off;
void *ptr;
static void console_read(CPUState *cs, gdb_syscall_complete_cb complete,
GuestFD *gf, target_ulong buf, target_ulong len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char *ptr;
int ret;
static void console_write(CPUState *cs, gdb_syscall_complete_cb complete,
GuestFD *gf, target_ulong buf, target_ulong len)
{
- CPUArchState *env G_GNUC_UNUSED = cs->env_ptr;
+ CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
char *ptr = lock_user(VERIFY_READ, buf, len, 1);
int ret;
static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAlphaState *env = cpu->env_ptr;
+ CPUAlphaState *env = cpu_env(cpu);
int64_t bound;
ctx->tbflags = ctx->base.tb->flags;
static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAlphaState *env = cpu->env_ptr;
+ CPUAlphaState *env = cpu_env(cpu);
uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
ctx->base.pc_next += 4;
static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
{
- return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
+ return nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cpu_env(cs));
}
static inline bool is_64bit_semihosting(CPUArchState *env)
{
/* The program counter is always up to date with CF_PCREL. */
if (!(tb_cflags(tb) & CF_PCREL)) {
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
/*
* It's OK to look at env for the current mode here, because it's
* never possible for an AArch64 TB to chain to an AArch32 TB.
const TranslationBlock *tb,
const uint64_t *data)
{
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
if (is_a64(env)) {
if (tb_cflags(tb) & CF_PCREL) {
unsigned int cur_el, bool secure,
uint64_t hcr_el2)
{
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
bool pstate_unmasked;
bool unmasked = false;
static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
uint32_t cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure)
{
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
bool rw;
bool scr;
bool hcr;
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
ARMCPU *arm_cpu = env_archcpu(env);
CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb);
int bound, core_mmu_idx;
static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *s = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
uint64_t pc = s->base.pc_next;
uint32_t insn;
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
ARMCPU *cpu = env_archcpu(env);
CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb);
uint32_t condexec, core_mmu_idx;
static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
uint32_t pc = dc->base.pc_next;
unsigned int insn;
static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
uint32_t pc = dc->base.pc_next;
uint32_t insn;
bool is_16bit;
static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAVRState *env = cs->env_ptr;
+ CPUAVRState *env = cpu_env(cs);
uint32_t tb_flags = ctx->base.tb->flags;
ctx->cs = cs;
static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUCRISState *env = cs->env_ptr;
+ CPUCRISState *env = cpu_env(cs);
uint32_t tb_flags = dc->base.tb->flags;
uint32_t pc_start;
static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUCRISState *env = cs->env_ptr;
+ CPUCRISState *env = cpu_env(cs);
unsigned int insn_len;
/* Pretty disas. */
CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- HexagonCPU *hex_cpu = env_archcpu(cs->env_ptr);
+ HexagonCPU *hex_cpu = env_archcpu(cpu_env(cs));
uint32_t hex_flags = dcbase->tb->flags;
ctx->mem_idx = MMU_USER_IDX;
static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUHexagonState *env = cpu->env_ptr;
+ CPUHexagonState *env = cpu_env(cpu);
decode_and_translate_packet(env, ctx);
synchronous across all processors. */
static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
{
- CPUHPPAState *env = cpu->env_ptr;
+ CPUHPPAState *env = cpu_env(cpu);
target_ulong addr = (target_ulong) data.target_ptr;
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
#ifndef CONFIG_USER_ONLY
if (ctx->tb_flags & PSW_C) {
- CPUHPPAState *env = ctx->cs->env_ptr;
+ CPUHPPAState *env = cpu_env(ctx->cs);
int type = hppa_artype_for_page(env, ctx->base.pc_next);
/* If we could not find a TLB entry, then we need to generate an
ITLB miss exception so the kernel will provide it.
static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUHPPAState *env = cs->env_ptr;
+ CPUHPPAState *env = cpu_env(cs);
DisasJumpType ret;
int i, n;
static void
nvmm_set_registers(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
static void
nvmm_get_registers(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
static bool
nvmm_can_take_int(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
struct nvmm_machine *mach = get_nvmm_mach();
static void
nvmm_vcpu_pre_run(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit)
{
AccelCPUState *qcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
uint64_t tpr;
env->eflags = exit->exitstate.rflags;
nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu,
struct nvmm_vcpu_exit *exit)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
int ret = 0;
qemu_mutex_lock_iothread();
static int
nvmm_vcpu_loop(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
struct nvmm_vcpu_exit *exit = vcpu->exit;
int ret;
*/
static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
bool first = true;
X86DecodedInsn decode;
X86DecodeFunc decode_func = decode_root;
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- CPUX86State *env = cs->env_ptr;
+ CPUX86State *env = cpu_env(cs);
TranslateResult out;
TranslateFault err;
{
/* The instruction pointer is always up to date with CF_PCREL. */
if (!(tb_cflags(tb) & CF_PCREL)) {
- CPUX86State *env = cs->env_ptr;
+ CPUX86State *env = cpu_env(cs);
env->eip = tb->pc - tb->cs_base;
}
}
be stopped. Return the next pc value */
static bool disas_insn(DisasContext *s, CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
int b, prefixes;
int shift;
MemOp ot, aflag, dflag;
static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
uint32_t flags = dc->base.tb->flags;
uint32_t cflags = tb_cflags(dc->base.tb);
int cpl = (flags >> HF_CPL_SHIFT) & 3;
/* X64 Extended Control Registers */
static void whpx_set_xcrs(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
WHV_REGISTER_VALUE xcr0;
static int whpx_set_tsc(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
{
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
struct whpx_register_set vcxt;
HRESULT hr;
int idx;
static int whpx_get_tsc(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
/* X64 Extended Control Registers */
static void whpx_get_xcrs(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
WHV_REGISTER_VALUE xcr0;
{
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
struct whpx_register_set vcxt;
uint64_t tpr, apic_base;
HRESULT hr;
{
if (cpu->vcpu_dirty) {
/* The CPU registers have been modified by other parts of QEMU. */
- CPUArchState *env = (CPUArchState *)(cpu->env_ptr);
+ CPUArchState *env = cpu_env(cpu);
return env->eip;
} else if (exit_context_valid) {
/*
static int whpx_handle_halt(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
int ret = 0;
qemu_mutex_lock_iothread();
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
int irq;
uint8_t tpr;
WHV_X64_PENDING_INTERRUPTION_REGISTER new_int;
static void whpx_vcpu_post_run(CPUState *cpu)
{
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
env->eflags = vcpu->exit_ctx.VpContext.Rflags;
static void whpx_vcpu_process_async_events(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
AccelCPUState *vcpu = cpu->accel;
if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = NULL;
Error *local_error = NULL;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
UINT64 freq = 0;
int ret;
cpu->vcpu_dirty = true;
cpu->accel = vcpu;
max_vcpu_index = max(max_vcpu_index, cpu->cpu_index);
- qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr);
+ qemu_add_vm_change_state_handler(whpx_cpu_update_state, env);
return 0;
CPUState *cs)
{
int64_t bound;
- CPULoongArchState *env = cs->env_ptr;
+ CPULoongArchState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPULoongArchState *env = cs->env_ptr;
+ CPULoongArchState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUM68KState *env = cpu->env_ptr;
+ CPUM68KState *env = cpu_env(cpu);
dc->env = env;
dc->pc = dc->base.pc_first;
static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUM68KState *env = cpu->env_ptr;
+ CPUM68KState *env = cpu_env(cpu);
uint16_t insn = read_im16(env, dc);
opcode_table[insn](env, dc, insn);
static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
- CPUMBState *env = cs->env_ptr;
+ CPUMBState *env = cpu_env(cs);
uint32_t ir;
/* TODO: This should raise an exception, not terminate qemu. */
static void uhi_cb(CPUState *cs, uint64_t ret, int err)
{
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
#define E(N) case E##N: err = UHI_E##N; break
QEMU_BUILD_BUG_ON(sizeof(UHIStat) < sizeof(struct gdb_stat));
if (!err) {
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
target_ulong addr = env->active_tc.gpr[5];
UHIStat *dst = lock_user(VERIFY_WRITE, addr, sizeof(UHIStat), 1);
struct gdb_stat s;
static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
ctx->saved_pc = -1;
static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
int insn_bytes;
int is_slot;
static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUNios2State *env = cs->env_ptr;
+ CPUNios2State *env = cpu_env(cs);
Nios2CPU *cpu = env_archcpu(env);
int page_insns;
static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUNios2State *env = cs->env_ptr;
+ CPUNios2State *env = cpu_env(cs);
const Nios2Instruction *instr;
uint32_t code, pc;
uint8_t op;
static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
- CPUOpenRISCState *env = cs->env_ptr;
+ CPUOpenRISCState *env = cpu_env(cs);
int bound;
dc->mem_idx = cpu_mmu_index(env, false);
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
uint32_t insn;
/* Restore state and reload the insn we executed, for filling in DSISR. */
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
switch (env->excp_model) {
#if defined(TARGET_PPC64)
void ppc_cpu_debug_excp_handler(CPUState *cs)
{
#if defined(TARGET_PPC64)
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
if (env->insns_flags2 & PPC2_ISA207S) {
if (cs->watchpoint_hit) {
bool ppc_cpu_debug_check_breakpoint(CPUState *cs)
{
#if defined(TARGET_PPC64)
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
if (env->insns_flags2 & PPC2_ISA207S) {
target_ulong priv;
bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
{
#if defined(TARGET_PPC64)
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
if (env->insns_flags2 & PPC2_ISA207S) {
if (wp == env->dawr0_watchpoint) {
static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
uint32_t hflags = ctx->base.tb->flags;
ctx->spr_cb = env->spr_cb;
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
target_ulong pc;
uint32_t insn;
bool ok;
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUState *cpu = ctx->cs;
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cpu_env(cpu);
return cpu_ldl_code(env, pc);
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cs->env_ptr;
+ CPURISCVState *env = cpu_env(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t tb_flags = ctx->base.tb->flags;
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cpu_env(cpu);
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
ctx->ol = ctx->xl;
static void rx_cpu_init(Object *obj)
{
- CPUState *cs = CPU(obj);
RXCPU *cpu = RX_CPU(obj);
- CPURXState *env = &cpu->env;
cpu_set_cpustate_pointers(cpu);
- cs->env_ptr = env;
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
- CPURXState *env = cs->env_ptr;
+ CPURXState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->env = env;
ctx->tb_flags = ctx->base.tb->flags;
static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPUS390XState *env = cs->env_ptr;
+ CPUS390XState *env = cpu_env(cs);
DisasContext *dc = container_of(dcbase, DisasContext, base);
dc->base.is_jmp = translate_one(env, dc);
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- CPUSH4State *env = cs->env_ptr;
+ CPUSH4State *env = cpu_env(cs);
env->tea = addr;
switch (access_type) {
static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUSH4State *env = cs->env_ptr;
+ CPUSH4State *env = cpu_env(cs);
uint32_t tbflags;
int bound;
static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPUSH4State *env = cs->env_ptr;
+ CPUSH4State *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
#ifdef CONFIG_USER_ONLY
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUSPARCState *env = cs->env_ptr;
+ CPUSPARCState *env = cpu_env(cs);
int bound;
dc->pc = dc->base.pc_first;
static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUSPARCState *env = cs->env_ptr;
+ CPUSPARCState *env = cpu_env(cs);
unsigned int insn;
insn = translator_ldl(env, &dc->base, dc->pc);
CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUTriCoreState *env = cs->env_ptr;
+ CPUTriCoreState *env = cpu_env(cs);
ctx->mem_idx = cpu_mmu_index(env, false);
uint32_t tb_flags = (uint32_t)ctx->base.tb->flags;
static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUTriCoreState *env = cpu->env_ptr;
+ CPUTriCoreState *env = cpu_env(cpu);
uint16_t insn_lo;
bool is_16bit;
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
uint32_t tb_flags = dc->base.tb->flags;
dc->config = env->config;
static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
target_ulong page_start;
/* These two conditions only apply to the first insn in the TB,