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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
b6a0aa05 | 24 | #include "qemu/osdep.h" |
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a PB |
26 | #include "hw/i386/pc.h" |
27 | #include "hw/char/serial.h" | |
28 | #include "hw/i386/apic.h" | |
54a40293 EH |
29 | #include "hw/i386/topology.h" |
30 | #include "sysemu/cpus.h" | |
0d09e41a | 31 | #include "hw/block/fdc.h" |
83c9f4ca PB |
32 | #include "hw/ide.h" |
33 | #include "hw/pci/pci.h" | |
2118196b | 34 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
35 | #include "hw/nvram/fw_cfg.h" |
36 | #include "hw/timer/hpet.h" | |
60d8f328 | 37 | #include "hw/smbios/smbios.h" |
83c9f4ca | 38 | #include "hw/loader.h" |
ca20cf32 | 39 | #include "elf.h" |
47b43a1f | 40 | #include "multiboot.h" |
0d09e41a PB |
41 | #include "hw/timer/mc146818rtc.h" |
42 | #include "hw/timer/i8254.h" | |
43 | #include "hw/audio/pcspk.h" | |
83c9f4ca PB |
44 | #include "hw/pci/msi.h" |
45 | #include "hw/sysbus.h" | |
9c17d615 | 46 | #include "sysemu/sysemu.h" |
e35704ba | 47 | #include "sysemu/numa.h" |
9c17d615 | 48 | #include "sysemu/kvm.h" |
b1c12027 | 49 | #include "sysemu/qtest.h" |
1d31f66b | 50 | #include "kvm_i386.h" |
0d09e41a | 51 | #include "hw/xen/xen.h" |
4be74634 | 52 | #include "sysemu/block-backend.h" |
0d09e41a | 53 | #include "hw/block/block.h" |
a19cbfb3 | 54 | #include "ui/qemu-spice.h" |
022c62cb PB |
55 | #include "exec/memory.h" |
56 | #include "exec/address-spaces.h" | |
9c17d615 | 57 | #include "sysemu/arch_init.h" |
1de7afc9 | 58 | #include "qemu/bitmap.h" |
0c764a9d | 59 | #include "qemu/config-file.h" |
d49b6836 | 60 | #include "qemu/error-report.h" |
0445259b | 61 | #include "hw/acpi/acpi.h" |
5ff020b7 | 62 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 63 | #include "hw/boards.h" |
39848901 | 64 | #include "hw/pci/pci_host.h" |
72c194f7 | 65 | #include "acpi-build.h" |
95bee274 | 66 | #include "hw/mem/pc-dimm.h" |
bf1e8939 | 67 | #include "qapi/visitor.h" |
d1048bef | 68 | #include "qapi-visit.h" |
15eafc2e | 69 | #include "qom/cpu.h" |
1255166b | 70 | #include "hw/nmi.h" |
80cabfad | 71 | |
471fd342 BS |
72 | /* debug PC/ISA interrupts */ |
73 | //#define DEBUG_IRQ | |
74 | ||
75 | #ifdef DEBUG_IRQ | |
76 | #define DPRINTF(fmt, ...) \ | |
77 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
78 | #else | |
79 | #define DPRINTF(fmt, ...) | |
80 | #endif | |
81 | ||
8a92ea2f | 82 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 83 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 84 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 85 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 86 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 87 | |
4c5b10b7 JS |
88 | #define E820_NR_ENTRIES 16 |
89 | ||
90 | struct e820_entry { | |
91 | uint64_t address; | |
92 | uint64_t length; | |
93 | uint32_t type; | |
541dc0d4 | 94 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
95 | |
96 | struct e820_table { | |
97 | uint32_t count; | |
98 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 99 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 | 100 | |
7d67110f GH |
101 | static struct e820_table e820_reserve; |
102 | static struct e820_entry *e820_table; | |
103 | static unsigned e820_entries; | |
dd703b99 | 104 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 105 | |
b881fbe9 | 106 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 107 | { |
b881fbe9 | 108 | GSIState *s = opaque; |
1452411b | 109 | |
b881fbe9 JK |
110 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
111 | if (n < ISA_NUM_IRQS) { | |
112 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 113 | } |
b881fbe9 | 114 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 115 | } |
1452411b | 116 | |
258711c6 JG |
117 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
118 | unsigned size) | |
80cabfad FB |
119 | { |
120 | } | |
121 | ||
c02e1eac JG |
122 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
123 | { | |
a6fc23e5 | 124 | return 0xffffffffffffffffULL; |
c02e1eac JG |
125 | } |
126 | ||
f929aad6 | 127 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 128 | static qemu_irq ferr_irq; |
8e78eb28 IY |
129 | |
130 | void pc_register_ferr_irq(qemu_irq irq) | |
131 | { | |
132 | ferr_irq = irq; | |
133 | } | |
134 | ||
f929aad6 FB |
135 | /* XXX: add IGNNE support */ |
136 | void cpu_set_ferr(CPUX86State *s) | |
137 | { | |
d537cf6c | 138 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
139 | } |
140 | ||
258711c6 JG |
141 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
142 | unsigned size) | |
f929aad6 | 143 | { |
d537cf6c | 144 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
145 | } |
146 | ||
c02e1eac JG |
147 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
148 | { | |
a6fc23e5 | 149 | return 0xffffffffffffffffULL; |
c02e1eac JG |
150 | } |
151 | ||
28ab0e2e | 152 | /* TSC handling */ |
28ab0e2e FB |
153 | uint64_t cpu_get_tsc(CPUX86State *env) |
154 | { | |
4a1418e0 | 155 | return cpu_get_ticks(); |
28ab0e2e FB |
156 | } |
157 | ||
3de388f6 | 158 | /* IRQ handling */ |
4a8fa5dc | 159 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 160 | { |
02e51483 | 161 | X86CPU *cpu = x86_env_get_cpu(env); |
3de388f6 FB |
162 | int intno; |
163 | ||
02e51483 | 164 | intno = apic_get_interrupt(cpu->apic_state); |
3de388f6 | 165 | if (intno >= 0) { |
3de388f6 FB |
166 | return intno; |
167 | } | |
3de388f6 | 168 | /* read the irq from the PIC */ |
02e51483 | 169 | if (!apic_accept_pic_intr(cpu->apic_state)) { |
0e21e12b | 170 | return -1; |
cf6d64bf | 171 | } |
0e21e12b | 172 | |
3de388f6 FB |
173 | intno = pic_read_irq(isa_pic); |
174 | return intno; | |
175 | } | |
176 | ||
d537cf6c | 177 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 178 | { |
182735ef AF |
179 | CPUState *cs = first_cpu; |
180 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 181 | |
471fd342 | 182 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
02e51483 | 183 | if (cpu->apic_state) { |
bdc44640 | 184 | CPU_FOREACH(cs) { |
182735ef | 185 | cpu = X86_CPU(cs); |
02e51483 CF |
186 | if (apic_accept_pic_intr(cpu->apic_state)) { |
187 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 188 | } |
d5529471 AJ |
189 | } |
190 | } else { | |
d8ed887b | 191 | if (level) { |
c3affe56 | 192 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
193 | } else { |
194 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
195 | } | |
a5b38b51 | 196 | } |
3de388f6 FB |
197 | } |
198 | ||
b0a21b53 FB |
199 | /* PC cmos mappings */ |
200 | ||
80cabfad FB |
201 | #define REG_EQUIPMENT_BYTE 0x14 |
202 | ||
bda05509 | 203 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
204 | { |
205 | int val; | |
206 | ||
207 | switch (fd0) { | |
2da44dd0 | 208 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
209 | /* 1.44 Mb 3"5 drive */ |
210 | val = 4; | |
211 | break; | |
2da44dd0 | 212 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
213 | /* 2.88 Mb 3"5 drive */ |
214 | val = 5; | |
215 | break; | |
2da44dd0 | 216 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
217 | /* 1.2 Mb 5"5 drive */ |
218 | val = 2; | |
219 | break; | |
2da44dd0 | 220 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
221 | default: |
222 | val = 0; | |
223 | break; | |
224 | } | |
225 | return val; | |
226 | } | |
227 | ||
9139046c MA |
228 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
229 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 230 | { |
ba6c2377 FB |
231 | rtc_set_memory(s, type_ofs, 47); |
232 | rtc_set_memory(s, info_ofs, cylinders); | |
233 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
234 | rtc_set_memory(s, info_ofs + 2, heads); | |
235 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
236 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
237 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
238 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
239 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
240 | rtc_set_memory(s, info_ofs + 8, sectors); | |
241 | } | |
242 | ||
6ac0e82d AZ |
243 | /* convert boot_device letter to something recognizable by the bios */ |
244 | static int boot_device2nibble(char boot_device) | |
245 | { | |
246 | switch(boot_device) { | |
247 | case 'a': | |
248 | case 'b': | |
249 | return 0x01; /* floppy boot */ | |
250 | case 'c': | |
251 | return 0x02; /* hard drive boot */ | |
252 | case 'd': | |
253 | return 0x03; /* CD-ROM boot */ | |
254 | case 'n': | |
255 | return 0x04; /* Network boot */ | |
256 | } | |
257 | return 0; | |
258 | } | |
259 | ||
ddcd5531 | 260 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
261 | { |
262 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
263 | int nbds, bds[3] = { 0, }; |
264 | int i; | |
265 | ||
266 | nbds = strlen(boot_device); | |
267 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
268 | error_setg(errp, "Too many boot devices for PC"); |
269 | return; | |
0ecdffbb AJ |
270 | } |
271 | for (i = 0; i < nbds; i++) { | |
272 | bds[i] = boot_device2nibble(boot_device[i]); | |
273 | if (bds[i] == 0) { | |
ddcd5531 GA |
274 | error_setg(errp, "Invalid boot device for PC: '%c'", |
275 | boot_device[i]); | |
276 | return; | |
0ecdffbb AJ |
277 | } |
278 | } | |
279 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 280 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
281 | } |
282 | ||
ddcd5531 | 283 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 284 | { |
ddcd5531 | 285 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
286 | } |
287 | ||
7444ca4e LE |
288 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
289 | { | |
290 | int val, nb, i; | |
2da44dd0 JS |
291 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
292 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
293 | |
294 | /* floppy type */ | |
295 | if (floppy) { | |
296 | for (i = 0; i < 2; i++) { | |
297 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
298 | } | |
299 | } | |
300 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
301 | cmos_get_fd_drive_type(fd_type[1]); | |
302 | rtc_set_memory(rtc_state, 0x10, val); | |
303 | ||
304 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
305 | nb = 0; | |
2da44dd0 | 306 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
307 | nb++; |
308 | } | |
2da44dd0 | 309 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
310 | nb++; |
311 | } | |
312 | switch (nb) { | |
313 | case 0: | |
314 | break; | |
315 | case 1: | |
316 | val |= 0x01; /* 1 drive, ready for boot */ | |
317 | break; | |
318 | case 2: | |
319 | val |= 0x41; /* 2 drives, ready for boot */ | |
320 | break; | |
321 | } | |
322 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
323 | } | |
324 | ||
c0897e0c MA |
325 | typedef struct pc_cmos_init_late_arg { |
326 | ISADevice *rtc_state; | |
9139046c | 327 | BusState *idebus[2]; |
c0897e0c MA |
328 | } pc_cmos_init_late_arg; |
329 | ||
b86f4613 LE |
330 | typedef struct check_fdc_state { |
331 | ISADevice *floppy; | |
332 | bool multiple; | |
333 | } CheckFdcState; | |
334 | ||
335 | static int check_fdc(Object *obj, void *opaque) | |
336 | { | |
337 | CheckFdcState *state = opaque; | |
338 | Object *fdc; | |
339 | uint32_t iobase; | |
340 | Error *local_err = NULL; | |
341 | ||
342 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
343 | if (!fdc) { | |
344 | return 0; | |
345 | } | |
346 | ||
347 | iobase = object_property_get_int(obj, "iobase", &local_err); | |
348 | if (local_err || iobase != 0x3f0) { | |
349 | error_free(local_err); | |
350 | return 0; | |
351 | } | |
352 | ||
353 | if (state->floppy) { | |
354 | state->multiple = true; | |
355 | } else { | |
356 | state->floppy = ISA_DEVICE(obj); | |
357 | } | |
358 | return 0; | |
359 | } | |
360 | ||
361 | static const char * const fdc_container_path[] = { | |
362 | "/unattached", "/peripheral", "/peripheral-anon" | |
363 | }; | |
364 | ||
424e4a87 RK |
365 | /* |
366 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
367 | * and ACPI objects. | |
368 | */ | |
369 | ISADevice *pc_find_fdc0(void) | |
370 | { | |
371 | int i; | |
372 | Object *container; | |
373 | CheckFdcState state = { 0 }; | |
374 | ||
375 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
376 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
377 | object_child_foreach(container, check_fdc, &state); | |
378 | } | |
379 | ||
380 | if (state.multiple) { | |
381 | error_report("warning: multiple floppy disk controllers with " | |
433672b0 MA |
382 | "iobase=0x3f0 have been found"); |
383 | error_printf("the one being picked for CMOS setup might not reflect " | |
424e4a87 RK |
384 | "your intent"); |
385 | } | |
386 | ||
387 | return state.floppy; | |
388 | } | |
389 | ||
c0897e0c MA |
390 | static void pc_cmos_init_late(void *opaque) |
391 | { | |
392 | pc_cmos_init_late_arg *arg = opaque; | |
393 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
394 | int16_t cylinders; |
395 | int8_t heads, sectors; | |
c0897e0c | 396 | int val; |
2adc99b2 | 397 | int i, trans; |
c0897e0c | 398 | |
9139046c MA |
399 | val = 0; |
400 | if (ide_get_geometry(arg->idebus[0], 0, | |
401 | &cylinders, &heads, §ors) >= 0) { | |
402 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
403 | val |= 0xf0; | |
404 | } | |
405 | if (ide_get_geometry(arg->idebus[0], 1, | |
406 | &cylinders, &heads, §ors) >= 0) { | |
407 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
408 | val |= 0x0f; | |
409 | } | |
410 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
411 | |
412 | val = 0; | |
413 | for (i = 0; i < 4; i++) { | |
9139046c MA |
414 | /* NOTE: ide_get_geometry() returns the physical |
415 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
416 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
417 | geometry can be different if a translation is done. */ | |
418 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
419 | &cylinders, &heads, §ors) >= 0) { | |
2adc99b2 MA |
420 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
421 | assert((trans & ~3) == 0); | |
422 | val |= trans << (i * 2); | |
c0897e0c MA |
423 | } |
424 | } | |
425 | rtc_set_memory(s, 0x39, val); | |
426 | ||
424e4a87 | 427 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 428 | |
c0897e0c MA |
429 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
430 | } | |
431 | ||
23d30407 | 432 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 433 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 434 | ISADevice *s) |
80cabfad | 435 | { |
7444ca4e | 436 | int val; |
c0897e0c | 437 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 438 | |
b0a21b53 | 439 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
440 | |
441 | /* memory size */ | |
e89001f7 | 442 | /* base memory (first MiB) */ |
88076854 | 443 | val = MIN(pcms->below_4g_mem_size / 1024, 640); |
333190eb FB |
444 | rtc_set_memory(s, 0x15, val); |
445 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 446 | /* extended memory (next 64MiB) */ |
88076854 EH |
447 | if (pcms->below_4g_mem_size > 1024 * 1024) { |
448 | val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; | |
e89001f7 MA |
449 | } else { |
450 | val = 0; | |
451 | } | |
80cabfad FB |
452 | if (val > 65535) |
453 | val = 65535; | |
b0a21b53 FB |
454 | rtc_set_memory(s, 0x17, val); |
455 | rtc_set_memory(s, 0x18, val >> 8); | |
456 | rtc_set_memory(s, 0x30, val); | |
457 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 458 | /* memory between 16MiB and 4GiB */ |
88076854 EH |
459 | if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { |
460 | val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; | |
e89001f7 | 461 | } else { |
9da98861 | 462 | val = 0; |
e89001f7 | 463 | } |
80cabfad FB |
464 | if (val > 65535) |
465 | val = 65535; | |
b0a21b53 FB |
466 | rtc_set_memory(s, 0x34, val); |
467 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 468 | /* memory above 4GiB */ |
88076854 | 469 | val = pcms->above_4g_mem_size / 65536; |
e89001f7 MA |
470 | rtc_set_memory(s, 0x5b, val); |
471 | rtc_set_memory(s, 0x5c, val >> 8); | |
472 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 473 | |
298e01b6 AJ |
474 | /* set the number of CPU */ |
475 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
2d996150 | 476 | |
23d30407 | 477 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 478 | TYPE_ISA_DEVICE, |
ec68007a | 479 | (Object **)&pcms->rtc, |
2d996150 GZ |
480 | object_property_allow_set_link, |
481 | OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | |
23d30407 | 482 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 483 | "rtc_state", &error_abort); |
298e01b6 | 484 | |
007b0657 | 485 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 486 | |
b0a21b53 | 487 | val = 0; |
b0a21b53 FB |
488 | val |= 0x02; /* FPU is there */ |
489 | val |= 0x04; /* PS/2 mouse installed */ | |
490 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
491 | ||
b86f4613 | 492 | /* hard drives and FDC */ |
c0897e0c | 493 | arg.rtc_state = s; |
9139046c MA |
494 | arg.idebus[0] = idebus0; |
495 | arg.idebus[1] = idebus1; | |
c0897e0c | 496 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
497 | } |
498 | ||
a0881c64 AF |
499 | #define TYPE_PORT92 "port92" |
500 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
501 | ||
4b78a802 BS |
502 | /* port 92 stuff: could be split off */ |
503 | typedef struct Port92State { | |
a0881c64 AF |
504 | ISADevice parent_obj; |
505 | ||
23af670e | 506 | MemoryRegion io; |
4b78a802 BS |
507 | uint8_t outport; |
508 | qemu_irq *a20_out; | |
509 | } Port92State; | |
510 | ||
93ef4192 AG |
511 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
512 | unsigned size) | |
4b78a802 BS |
513 | { |
514 | Port92State *s = opaque; | |
4700a316 | 515 | int oldval = s->outport; |
4b78a802 | 516 | |
c5539cb4 | 517 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 BS |
518 | s->outport = val; |
519 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
4700a316 | 520 | if ((val & 1) && !(oldval & 1)) { |
4b78a802 BS |
521 | qemu_system_reset_request(); |
522 | } | |
523 | } | |
524 | ||
93ef4192 AG |
525 | static uint64_t port92_read(void *opaque, hwaddr addr, |
526 | unsigned size) | |
4b78a802 BS |
527 | { |
528 | Port92State *s = opaque; | |
529 | uint32_t ret; | |
530 | ||
531 | ret = s->outport; | |
532 | DPRINTF("port92: read 0x%02x\n", ret); | |
533 | return ret; | |
534 | } | |
535 | ||
536 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
537 | { | |
a0881c64 | 538 | Port92State *s = PORT92(dev); |
4b78a802 BS |
539 | |
540 | s->a20_out = a20_out; | |
541 | } | |
542 | ||
543 | static const VMStateDescription vmstate_port92_isa = { | |
544 | .name = "port92", | |
545 | .version_id = 1, | |
546 | .minimum_version_id = 1, | |
d49805ae | 547 | .fields = (VMStateField[]) { |
4b78a802 BS |
548 | VMSTATE_UINT8(outport, Port92State), |
549 | VMSTATE_END_OF_LIST() | |
550 | } | |
551 | }; | |
552 | ||
553 | static void port92_reset(DeviceState *d) | |
554 | { | |
a0881c64 | 555 | Port92State *s = PORT92(d); |
4b78a802 BS |
556 | |
557 | s->outport &= ~1; | |
558 | } | |
559 | ||
23af670e | 560 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
561 | .read = port92_read, |
562 | .write = port92_write, | |
563 | .impl = { | |
564 | .min_access_size = 1, | |
565 | .max_access_size = 1, | |
566 | }, | |
567 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
568 | }; |
569 | ||
db895a1e | 570 | static void port92_initfn(Object *obj) |
4b78a802 | 571 | { |
db895a1e | 572 | Port92State *s = PORT92(obj); |
4b78a802 | 573 | |
1437c94b | 574 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 575 | |
4b78a802 | 576 | s->outport = 0; |
db895a1e AF |
577 | } |
578 | ||
579 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
580 | { | |
581 | ISADevice *isadev = ISA_DEVICE(dev); | |
582 | Port92State *s = PORT92(dev); | |
583 | ||
584 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
585 | } |
586 | ||
8f04ee08 AL |
587 | static void port92_class_initfn(ObjectClass *klass, void *data) |
588 | { | |
39bffca2 | 589 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 590 | |
db895a1e | 591 | dc->realize = port92_realizefn; |
39bffca2 AL |
592 | dc->reset = port92_reset; |
593 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
594 | /* |
595 | * Reason: unlike ordinary ISA devices, this one needs additional | |
596 | * wiring: its A20 output line needs to be wired up by | |
597 | * port92_init(). | |
598 | */ | |
599 | dc->cannot_instantiate_with_device_add_yet = true; | |
8f04ee08 AL |
600 | } |
601 | ||
8c43a6f0 | 602 | static const TypeInfo port92_info = { |
a0881c64 | 603 | .name = TYPE_PORT92, |
39bffca2 AL |
604 | .parent = TYPE_ISA_DEVICE, |
605 | .instance_size = sizeof(Port92State), | |
db895a1e | 606 | .instance_init = port92_initfn, |
39bffca2 | 607 | .class_init = port92_class_initfn, |
4b78a802 BS |
608 | }; |
609 | ||
83f7d43a | 610 | static void port92_register_types(void) |
4b78a802 | 611 | { |
39bffca2 | 612 | type_register_static(&port92_info); |
4b78a802 | 613 | } |
83f7d43a AF |
614 | |
615 | type_init(port92_register_types) | |
4b78a802 | 616 | |
956a3e6b | 617 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 618 | { |
cc36a7a2 | 619 | X86CPU *cpu = opaque; |
e1a23744 | 620 | |
956a3e6b | 621 | /* XXX: send to all CPUs ? */ |
4b78a802 | 622 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 623 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
624 | } |
625 | ||
4c5b10b7 JS |
626 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
627 | { | |
7d67110f | 628 | int index = le32_to_cpu(e820_reserve.count); |
4c5b10b7 JS |
629 | struct e820_entry *entry; |
630 | ||
7d67110f GH |
631 | if (type != E820_RAM) { |
632 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
633 | if (index >= E820_NR_ENTRIES) { | |
634 | return -EBUSY; | |
635 | } | |
636 | entry = &e820_reserve.entry[index++]; | |
637 | ||
638 | entry->address = cpu_to_le64(address); | |
639 | entry->length = cpu_to_le64(length); | |
640 | entry->type = cpu_to_le32(type); | |
641 | ||
642 | e820_reserve.count = cpu_to_le32(index); | |
643 | } | |
4c5b10b7 | 644 | |
7d67110f | 645 | /* new "etc/e820" file -- include ram too */ |
ab3ad07f | 646 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); |
7d67110f GH |
647 | e820_table[e820_entries].address = cpu_to_le64(address); |
648 | e820_table[e820_entries].length = cpu_to_le64(length); | |
649 | e820_table[e820_entries].type = cpu_to_le32(type); | |
650 | e820_entries++; | |
4c5b10b7 | 651 | |
7d67110f | 652 | return e820_entries; |
4c5b10b7 JS |
653 | } |
654 | ||
7bf8ef19 GS |
655 | int e820_get_num_entries(void) |
656 | { | |
657 | return e820_entries; | |
658 | } | |
659 | ||
660 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
661 | { | |
662 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
663 | *address = le64_to_cpu(e820_table[idx].address); | |
664 | *length = le64_to_cpu(e820_table[idx].length); | |
665 | return true; | |
666 | } | |
667 | return false; | |
668 | } | |
669 | ||
54a40293 EH |
670 | /* Enables contiguous-apic-ID mode, for compatibility */ |
671 | static bool compat_apic_id_mode; | |
672 | ||
673 | void enable_compat_apic_id_mode(void) | |
674 | { | |
675 | compat_apic_id_mode = true; | |
676 | } | |
677 | ||
678 | /* Calculates initial APIC ID for a specific CPU index | |
679 | * | |
680 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
681 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
682 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
683 | * all CPUs up to max_cpus. | |
684 | */ | |
685 | static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
686 | { | |
687 | uint32_t correct_id; | |
688 | static bool warned; | |
689 | ||
690 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
691 | if (compat_apic_id_mode) { | |
b1c12027 | 692 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { |
54a40293 EH |
693 | error_report("APIC IDs set in compatibility mode, " |
694 | "CPU topology won't match the configuration"); | |
695 | warned = true; | |
696 | } | |
697 | return cpu_index; | |
698 | } else { | |
699 | return correct_id; | |
700 | } | |
701 | } | |
702 | ||
5fd0a9d4 | 703 | static void pc_build_smbios(FWCfgState *fw_cfg) |
80cabfad | 704 | { |
c97294ec GS |
705 | uint8_t *smbios_tables, *smbios_anchor; |
706 | size_t smbios_tables_len, smbios_anchor_len; | |
89cc4a27 WH |
707 | struct smbios_phys_mem_area *mem_array; |
708 | unsigned i, array_count; | |
5fd0a9d4 WH |
709 | |
710 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); | |
711 | if (smbios_tables) { | |
712 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
713 | smbios_tables, smbios_tables_len); | |
714 | } | |
715 | ||
89cc4a27 WH |
716 | /* build the array of physical mem area from e820 table */ |
717 | mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); | |
718 | for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { | |
719 | uint64_t addr, len; | |
720 | ||
721 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { | |
722 | mem_array[array_count].address = addr; | |
723 | mem_array[array_count].length = len; | |
724 | array_count++; | |
725 | } | |
726 | } | |
727 | smbios_get_tables(mem_array, array_count, | |
728 | &smbios_tables, &smbios_tables_len, | |
5fd0a9d4 | 729 | &smbios_anchor, &smbios_anchor_len); |
89cc4a27 WH |
730 | g_free(mem_array); |
731 | ||
5fd0a9d4 WH |
732 | if (smbios_anchor) { |
733 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
734 | smbios_tables, smbios_tables_len); | |
735 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
736 | smbios_anchor, smbios_anchor_len); | |
737 | } | |
738 | } | |
739 | ||
ebde2465 | 740 | static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) |
5fd0a9d4 WH |
741 | { |
742 | FWCfgState *fw_cfg; | |
11c2fd3e AL |
743 | uint64_t *numa_fw_cfg; |
744 | int i, j; | |
3cce6243 | 745 | |
305ae888 | 746 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); |
c886fc4c | 747 | |
1d934e89 EH |
748 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
749 | * | |
750 | * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug | |
751 | * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC | |
752 | * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the | |
753 | * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS | |
754 | * may see". | |
755 | * | |
756 | * So, this means we must not use max_cpus, here, but the maximum possible | |
757 | * APIC ID value, plus one. | |
758 | * | |
759 | * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is | |
760 | * the APIC ID, not the "CPU index" | |
761 | */ | |
ebde2465 | 762 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); |
905fdcb5 | 763 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
764 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
765 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 766 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 | 767 | |
5fd0a9d4 | 768 | pc_build_smbios(fw_cfg); |
c97294ec | 769 | |
089da572 | 770 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
7d67110f GH |
771 | &e820_reserve, sizeof(e820_reserve)); |
772 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
773 | sizeof(struct e820_entry) * e820_entries); | |
11c2fd3e | 774 | |
089da572 | 775 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
776 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
777 | * of nodes, one word for each VCPU->node and one word for each node to | |
778 | * hold the amount of memory. | |
779 | */ | |
ebde2465 | 780 | numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); |
11c2fd3e | 781 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 782 | for (i = 0; i < max_cpus; i++) { |
1d934e89 | 783 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); |
ebde2465 | 784 | assert(apic_id < pcms->apic_id_limit); |
11c2fd3e | 785 | for (j = 0; j < nb_numa_nodes; j++) { |
8c85901e | 786 | if (test_bit(i, numa_info[j].node_cpu)) { |
1d934e89 | 787 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); |
11c2fd3e AL |
788 | break; |
789 | } | |
790 | } | |
791 | } | |
792 | for (i = 0; i < nb_numa_nodes; i++) { | |
ebde2465 IM |
793 | numa_fw_cfg[pcms->apic_id_limit + 1 + i] = |
794 | cpu_to_le64(numa_info[i].node_mem); | |
11c2fd3e | 795 | } |
089da572 | 796 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
ebde2465 | 797 | (1 + pcms->apic_id_limit + nb_numa_nodes) * |
1d934e89 | 798 | sizeof(*numa_fw_cfg)); |
bf483392 AG |
799 | |
800 | return fw_cfg; | |
80cabfad FB |
801 | } |
802 | ||
642a4f96 TS |
803 | static long get_file_size(FILE *f) |
804 | { | |
805 | long where, size; | |
806 | ||
807 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
808 | ||
809 | where = ftell(f); | |
810 | fseek(f, 0, SEEK_END); | |
811 | size = ftell(f); | |
812 | fseek(f, where, SEEK_SET); | |
813 | ||
814 | return size; | |
815 | } | |
816 | ||
df1f79fd EH |
817 | static void load_linux(PCMachineState *pcms, |
818 | FWCfgState *fw_cfg) | |
642a4f96 TS |
819 | { |
820 | uint16_t protocol; | |
5cea8590 | 821 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 822 | uint32_t initrd_max; |
57a46d05 | 823 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 824 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 825 | FILE *f; |
bf4e5d92 | 826 | char *vmode; |
df1f79fd | 827 | MachineState *machine = MACHINE(pcms); |
cd4040ec | 828 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
df1f79fd EH |
829 | const char *kernel_filename = machine->kernel_filename; |
830 | const char *initrd_filename = machine->initrd_filename; | |
831 | const char *kernel_cmdline = machine->kernel_cmdline; | |
642a4f96 TS |
832 | |
833 | /* Align to 16 bytes as a paranoia measure */ | |
834 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
835 | ||
836 | /* load the kernel header */ | |
837 | f = fopen(kernel_filename, "rb"); | |
838 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 LG |
839 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
840 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
841 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
842 | kernel_filename, strerror(errno)); | |
843 | exit(1); | |
642a4f96 TS |
844 | } |
845 | ||
846 | /* kernel protocol version */ | |
bc4edd79 | 847 | #if 0 |
642a4f96 | 848 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 849 | #endif |
0f9d76e5 LG |
850 | if (ldl_p(header+0x202) == 0x53726448) { |
851 | protocol = lduw_p(header+0x206); | |
852 | } else { | |
853 | /* This looks like a multiboot kernel. If it is, let's stop | |
854 | treating it like a Linux kernel. */ | |
52001445 | 855 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 856 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 857 | return; |
0f9d76e5 LG |
858 | } |
859 | protocol = 0; | |
f16408df | 860 | } |
642a4f96 TS |
861 | |
862 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 LG |
863 | /* Low kernel */ |
864 | real_addr = 0x90000; | |
865 | cmdline_addr = 0x9a000 - cmdline_size; | |
866 | prot_addr = 0x10000; | |
642a4f96 | 867 | } else if (protocol < 0x202) { |
0f9d76e5 LG |
868 | /* High but ancient kernel */ |
869 | real_addr = 0x90000; | |
870 | cmdline_addr = 0x9a000 - cmdline_size; | |
871 | prot_addr = 0x100000; | |
642a4f96 | 872 | } else { |
0f9d76e5 LG |
873 | /* High and recent kernel */ |
874 | real_addr = 0x10000; | |
875 | cmdline_addr = 0x20000; | |
876 | prot_addr = 0x100000; | |
642a4f96 TS |
877 | } |
878 | ||
bc4edd79 | 879 | #if 0 |
642a4f96 | 880 | fprintf(stderr, |
0f9d76e5 LG |
881 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
882 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
883 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
884 | real_addr, | |
885 | cmdline_addr, | |
886 | prot_addr); | |
bc4edd79 | 887 | #endif |
642a4f96 TS |
888 | |
889 | /* highest address for loading the initrd */ | |
0f9d76e5 LG |
890 | if (protocol >= 0x203) { |
891 | initrd_max = ldl_p(header+0x22c); | |
892 | } else { | |
893 | initrd_max = 0x37ffffff; | |
894 | } | |
642a4f96 | 895 | |
cd4040ec EH |
896 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { |
897 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
927766c7 | 898 | } |
642a4f96 | 899 | |
57a46d05 AG |
900 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
901 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 902 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
903 | |
904 | if (protocol >= 0x202) { | |
0f9d76e5 | 905 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 906 | } else { |
0f9d76e5 LG |
907 | stw_p(header+0x20, 0xA33F); |
908 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
909 | } |
910 | ||
bf4e5d92 PT |
911 | /* handle vga= parameter */ |
912 | vmode = strstr(kernel_cmdline, "vga="); | |
913 | if (vmode) { | |
914 | unsigned int video_mode; | |
915 | /* skip "vga=" */ | |
916 | vmode += 4; | |
917 | if (!strncmp(vmode, "normal", 6)) { | |
918 | video_mode = 0xffff; | |
919 | } else if (!strncmp(vmode, "ext", 3)) { | |
920 | video_mode = 0xfffe; | |
921 | } else if (!strncmp(vmode, "ask", 3)) { | |
922 | video_mode = 0xfffd; | |
923 | } else { | |
924 | video_mode = strtol(vmode, NULL, 0); | |
925 | } | |
926 | stw_p(header+0x1fa, video_mode); | |
927 | } | |
928 | ||
642a4f96 | 929 | /* loader type */ |
5cbdb3a3 | 930 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
931 | If this code is substantially changed, you may want to consider |
932 | incrementing the revision. */ | |
0f9d76e5 LG |
933 | if (protocol >= 0x200) { |
934 | header[0x210] = 0xB0; | |
935 | } | |
642a4f96 TS |
936 | /* heap */ |
937 | if (protocol >= 0x201) { | |
0f9d76e5 LG |
938 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
939 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
940 | } |
941 | ||
942 | /* load initrd */ | |
943 | if (initrd_filename) { | |
0f9d76e5 LG |
944 | if (protocol < 0x200) { |
945 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
946 | exit(1); | |
947 | } | |
642a4f96 | 948 | |
0f9d76e5 | 949 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 | 950 | if (initrd_size < 0) { |
7454e51d MT |
951 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", |
952 | initrd_filename, strerror(errno)); | |
d6fa4b77 MK |
953 | exit(1); |
954 | } | |
955 | ||
45a50b16 | 956 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 957 | |
7267c094 | 958 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
959 | load_image(initrd_filename, initrd_data); |
960 | ||
961 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
962 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
963 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 964 | |
0f9d76e5 LG |
965 | stl_p(header+0x218, initrd_addr); |
966 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
967 | } |
968 | ||
45a50b16 | 969 | /* load kernel and setup */ |
642a4f96 | 970 | setup_size = header[0x1f1]; |
0f9d76e5 LG |
971 | if (setup_size == 0) { |
972 | setup_size = 4; | |
973 | } | |
642a4f96 | 974 | setup_size = (setup_size+1)*512; |
ec5fd402 PB |
975 | if (setup_size > kernel_size) { |
976 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
977 | exit(1); | |
978 | } | |
45a50b16 | 979 | kernel_size -= setup_size; |
642a4f96 | 980 | |
7267c094 AL |
981 | setup = g_malloc(setup_size); |
982 | kernel = g_malloc(kernel_size); | |
45a50b16 | 983 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
984 | if (fread(setup, 1, setup_size, f) != setup_size) { |
985 | fprintf(stderr, "fread() failed\n"); | |
986 | exit(1); | |
987 | } | |
988 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
989 | fprintf(stderr, "fread() failed\n"); | |
990 | exit(1); | |
991 | } | |
642a4f96 | 992 | fclose(f); |
45a50b16 | 993 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
994 | |
995 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
996 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
997 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
998 | ||
999 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1000 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1001 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1002 | ||
2e55e842 GN |
1003 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
1004 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 1005 | nb_option_roms++; |
642a4f96 TS |
1006 | } |
1007 | ||
b41a2cd1 FB |
1008 | #define NE2000_NB_MAX 6 |
1009 | ||
675d6f82 BS |
1010 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
1011 | 0x280, 0x380 }; | |
1012 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 1013 | |
48a18b3c | 1014 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
1015 | { |
1016 | static int nb_ne2k = 0; | |
1017 | ||
1018 | if (nb_ne2k == NE2000_NB_MAX) | |
1019 | return; | |
48a18b3c | 1020 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 1021 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
1022 | nb_ne2k++; |
1023 | } | |
1024 | ||
92a16d7a | 1025 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 1026 | { |
4917cf44 AF |
1027 | if (current_cpu) { |
1028 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 1029 | return cpu->apic_state; |
0e26b7b8 BS |
1030 | } else { |
1031 | return NULL; | |
1032 | } | |
1033 | } | |
1034 | ||
845773ab | 1035 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 1036 | { |
c3affe56 | 1037 | X86CPU *cpu = opaque; |
53b67b30 BS |
1038 | |
1039 | if (level) { | |
c3affe56 | 1040 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
1041 | } |
1042 | } | |
1043 | ||
62fc403f | 1044 | static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, |
46232aaa | 1045 | Error **errp) |
31050930 | 1046 | { |
e1570d00 | 1047 | X86CPU *cpu = NULL; |
31050930 IM |
1048 | Error *local_err = NULL; |
1049 | ||
e1570d00 | 1050 | cpu = cpu_x86_create(cpu_model, &local_err); |
cd7b87ff | 1051 | if (local_err != NULL) { |
e1570d00 | 1052 | goto out; |
31050930 IM |
1053 | } |
1054 | ||
1055 | object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); | |
1056 | object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); | |
1057 | ||
e1570d00 | 1058 | out: |
31050930 | 1059 | if (local_err) { |
31050930 | 1060 | error_propagate(errp, local_err); |
cd7b87ff AF |
1061 | object_unref(OBJECT(cpu)); |
1062 | cpu = NULL; | |
31050930 IM |
1063 | } |
1064 | return cpu; | |
1065 | } | |
1066 | ||
c649983b IM |
1067 | void pc_hot_add_cpu(const int64_t id, Error **errp) |
1068 | { | |
0e3bd562 | 1069 | X86CPU *cpu; |
4884b7bf | 1070 | MachineState *machine = MACHINE(qdev_get_machine()); |
c649983b | 1071 | int64_t apic_id = x86_cpu_apic_id_from_index(id); |
0e3bd562 | 1072 | Error *local_err = NULL; |
c649983b | 1073 | |
8de433cb IM |
1074 | if (id < 0) { |
1075 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1076 | return; | |
1077 | } | |
1078 | ||
c649983b IM |
1079 | if (cpu_exists(apic_id)) { |
1080 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1081 | ", it already exists", id); | |
1082 | return; | |
1083 | } | |
1084 | ||
1085 | if (id >= max_cpus) { | |
1086 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1087 | ", max allowed: %d", id, max_cpus - 1); | |
1088 | return; | |
1089 | } | |
1090 | ||
5ff020b7 EH |
1091 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1092 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1093 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1094 | id, apic_id); | |
1095 | return; | |
1096 | } | |
1097 | ||
4884b7bf | 1098 | cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); |
0e3bd562 AF |
1099 | if (local_err) { |
1100 | error_propagate(errp, local_err); | |
1101 | return; | |
1102 | } | |
1103 | object_unref(OBJECT(cpu)); | |
c649983b IM |
1104 | } |
1105 | ||
4884b7bf | 1106 | void pc_cpus_init(PCMachineState *pcms) |
70166477 IY |
1107 | { |
1108 | int i; | |
53a89e26 | 1109 | X86CPU *cpu = NULL; |
4884b7bf | 1110 | MachineState *machine = MACHINE(pcms); |
70166477 IY |
1111 | |
1112 | /* init CPUs */ | |
4884b7bf | 1113 | if (machine->cpu_model == NULL) { |
70166477 | 1114 | #ifdef TARGET_X86_64 |
4884b7bf | 1115 | machine->cpu_model = "qemu64"; |
70166477 | 1116 | #else |
4884b7bf | 1117 | machine->cpu_model = "qemu32"; |
70166477 IY |
1118 | #endif |
1119 | } | |
1120 | ||
ebde2465 IM |
1121 | /* Calculates the limit to CPU APIC ID values |
1122 | * | |
1123 | * Limit for the APIC ID value, so that all | |
1124 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1125 | * | |
1126 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
1127 | */ | |
1128 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
1129 | if (pcms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { | |
1130 | error_report("max_cpus is too large. APIC ID of last CPU is %u", | |
1131 | pcms->apic_id_limit - 1); | |
f03bd716 EH |
1132 | exit(1); |
1133 | } | |
1134 | ||
3811ef14 IM |
1135 | pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
1136 | sizeof(CPUArchId) * max_cpus); | |
1137 | for (i = 0; i < max_cpus; i++) { | |
1138 | pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); | |
1139 | pcms->possible_cpus->len++; | |
1140 | if (i < smp_cpus) { | |
1141 | cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), | |
1142 | &error_fatal); | |
1143 | pcms->possible_cpus->cpus[i].cpu = CPU(cpu); | |
1144 | object_unref(OBJECT(cpu)); | |
1145 | } | |
70166477 | 1146 | } |
53a89e26 | 1147 | |
c97294ec GS |
1148 | /* tell smbios about cpuid version and features */ |
1149 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
70166477 IY |
1150 | } |
1151 | ||
f8c457b8 MT |
1152 | /* pci-info ROM file. Little endian format */ |
1153 | typedef struct PcRomPciInfo { | |
1154 | uint64_t w32_min; | |
1155 | uint64_t w32_max; | |
1156 | uint64_t w64_min; | |
1157 | uint64_t w64_max; | |
1158 | } PcRomPciInfo; | |
1159 | ||
3459a625 | 1160 | static |
9ebeed0c | 1161 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1162 | { |
9ebeed0c EH |
1163 | PCMachineState *pcms = container_of(notifier, |
1164 | PCMachineState, machine_done); | |
1165 | PCIBus *bus = pcms->bus; | |
2118196b MA |
1166 | |
1167 | if (bus) { | |
1168 | int extra_hosts = 0; | |
1169 | ||
1170 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1171 | /* look for expander root buses */ | |
1172 | if (pci_bus_is_root(bus)) { | |
1173 | extra_hosts++; | |
1174 | } | |
1175 | } | |
f264d360 | 1176 | if (extra_hosts && pcms->fw_cfg) { |
2118196b MA |
1177 | uint64_t *val = g_malloc(sizeof(*val)); |
1178 | *val = cpu_to_le64(extra_hosts); | |
f264d360 | 1179 | fw_cfg_add_file(pcms->fw_cfg, |
2118196b MA |
1180 | "etc/extra-pci-roots", val, sizeof(*val)); |
1181 | } | |
1182 | } | |
1183 | ||
bb292f5a | 1184 | acpi_setup(); |
3459a625 MT |
1185 | } |
1186 | ||
e4e8ba04 | 1187 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1188 | { |
b20c9bd5 MT |
1189 | int i, j; |
1190 | ||
dd4c2f01 EH |
1191 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); |
1192 | pcms->numa_nodes = nb_numa_nodes; | |
1193 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1194 | sizeof *pcms->node_mem); | |
8c85901e | 1195 | for (i = 0; i < nb_numa_nodes; i++) { |
dd4c2f01 | 1196 | pcms->node_mem[i] = numa_info[i].node_mem; |
8c85901e WG |
1197 | } |
1198 | ||
dd4c2f01 EH |
1199 | pcms->node_cpu = g_malloc0(pcms->apic_id_limit * |
1200 | sizeof *pcms->node_cpu); | |
b20c9bd5 MT |
1201 | |
1202 | for (i = 0; i < max_cpus; i++) { | |
1203 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); | |
dd4c2f01 | 1204 | assert(apic_id < pcms->apic_id_limit); |
b20c9bd5 | 1205 | for (j = 0; j < nb_numa_nodes; j++) { |
8c85901e | 1206 | if (test_bit(i, numa_info[j].node_cpu)) { |
dd4c2f01 | 1207 | pcms->node_cpu[apic_id] = j; |
b20c9bd5 MT |
1208 | break; |
1209 | } | |
1210 | } | |
1211 | } | |
3459a625 | 1212 | |
9ebeed0c EH |
1213 | pcms->machine_done.notify = pc_machine_done; |
1214 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1215 | } |
1216 | ||
83d08f26 MT |
1217 | /* setup pci memory address space mapping into system address space */ |
1218 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1219 | MemoryRegion *pci_address_space) | |
39848901 | 1220 | { |
83d08f26 MT |
1221 | /* Set to lower priority than RAM */ |
1222 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1223 | pci_address_space, -1); | |
39848901 IM |
1224 | } |
1225 | ||
f7e4dd6c GH |
1226 | void pc_acpi_init(const char *default_dsdt) |
1227 | { | |
c5a98cf3 | 1228 | char *filename; |
f7e4dd6c GH |
1229 | |
1230 | if (acpi_tables != NULL) { | |
1231 | /* manually set via -acpitable, leave it alone */ | |
1232 | return; | |
1233 | } | |
1234 | ||
1235 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1236 | if (filename == NULL) { | |
1237 | fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); | |
c5a98cf3 | 1238 | } else { |
5bdb59a2 MA |
1239 | QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, |
1240 | &error_abort); | |
c5a98cf3 | 1241 | Error *err = NULL; |
f7e4dd6c | 1242 | |
5bdb59a2 | 1243 | qemu_opt_set(opts, "file", filename, &error_abort); |
0c764a9d | 1244 | |
1a4b2666 | 1245 | acpi_table_add_builtin(opts, &err); |
c5a98cf3 | 1246 | if (err) { |
c29b77f9 MA |
1247 | error_reportf_err(err, "WARNING: failed to load %s: ", |
1248 | filename); | |
c5a98cf3 | 1249 | } |
c5a98cf3 | 1250 | g_free(filename); |
f7e4dd6c | 1251 | } |
f7e4dd6c GH |
1252 | } |
1253 | ||
7bc35e0f | 1254 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1255 | { |
1256 | int i; | |
1257 | FWCfgState *fw_cfg; | |
1258 | ||
df1f79fd | 1259 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1260 | |
305ae888 | 1261 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
b33a5bbf CL |
1262 | rom_set_fw(fw_cfg); |
1263 | ||
df1f79fd | 1264 | load_linux(pcms, fw_cfg); |
b33a5bbf CL |
1265 | for (i = 0; i < nb_option_roms; i++) { |
1266 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
1267 | !strcmp(option_rom[i].name, "multiboot.bin")); | |
1268 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1269 | } | |
f264d360 | 1270 | pcms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1271 | } |
1272 | ||
5934e216 EH |
1273 | void pc_memory_init(PCMachineState *pcms, |
1274 | MemoryRegion *system_memory, | |
1275 | MemoryRegion *rom_memory, | |
1276 | MemoryRegion **ram_memory) | |
80cabfad | 1277 | { |
cbc5b5f3 JJ |
1278 | int linux_boot, i; |
1279 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1280 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1281 | FWCfgState *fw_cfg; |
62b160c0 | 1282 | MachineState *machine = MACHINE(pcms); |
16a9e8a5 | 1283 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
d592d303 | 1284 | |
c8d163bc EH |
1285 | assert(machine->ram_size == pcms->below_4g_mem_size + |
1286 | pcms->above_4g_mem_size); | |
9521d42b PB |
1287 | |
1288 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1289 | |
00cb2a99 | 1290 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1291 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1292 | * with older qemus that used qemu_ram_alloc(). |
1293 | */ | |
7267c094 | 1294 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1295 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1296 | machine->ram_size); | |
ae0a5466 | 1297 | *ram_memory = ram; |
7267c094 | 1298 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1299 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
c8d163bc | 1300 | 0, pcms->below_4g_mem_size); |
00cb2a99 | 1301 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
c8d163bc EH |
1302 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); |
1303 | if (pcms->above_4g_mem_size > 0) { | |
7267c094 | 1304 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1305 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
c8d163bc EH |
1306 | pcms->below_4g_mem_size, |
1307 | pcms->above_4g_mem_size); | |
00cb2a99 AK |
1308 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1309 | ram_above_4g); | |
c8d163bc | 1310 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1311 | } |
82b36dc3 | 1312 | |
bb292f5a | 1313 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1314 | (machine->ram_slots || |
9521d42b | 1315 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1316 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1317 | ||
1318 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1319 | mc->name); | |
1320 | exit(EXIT_FAILURE); | |
1321 | } | |
1322 | ||
619d11e4 | 1323 | /* initialize hotplug memory address space */ |
bb292f5a | 1324 | if (pcmc->has_reserved_memory && |
9521d42b | 1325 | (machine->ram_size < machine->maxram_size)) { |
619d11e4 | 1326 | ram_addr_t hotplug_mem_size = |
9521d42b | 1327 | machine->maxram_size - machine->ram_size; |
619d11e4 | 1328 | |
a0cc8856 IM |
1329 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1330 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1331 | machine->ram_slots); | |
1332 | exit(EXIT_FAILURE); | |
1333 | } | |
1334 | ||
f2c38522 PK |
1335 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1336 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1337 | error_report("maximum memory size must by aligned to multiple of " | |
1338 | "%d bytes", TARGET_PAGE_SIZE); | |
1339 | exit(EXIT_FAILURE); | |
1340 | } | |
1341 | ||
a7d69ff1 | 1342 | pcms->hotplug_memory.base = |
c8d163bc | 1343 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); |
619d11e4 | 1344 | |
16a9e8a5 | 1345 | if (pcmc->enforce_aligned_dimm) { |
085f8e88 IM |
1346 | /* size hotplug region assuming 1G page max alignment per slot */ |
1347 | hotplug_mem_size += (1ULL << 30) * machine->ram_slots; | |
1348 | } | |
1349 | ||
a7d69ff1 | 1350 | if ((pcms->hotplug_memory.base + hotplug_mem_size) < |
619d11e4 IM |
1351 | hotplug_mem_size) { |
1352 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1353 | machine->maxram_size); | |
1354 | exit(EXIT_FAILURE); | |
1355 | } | |
1356 | ||
a7d69ff1 | 1357 | memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), |
619d11e4 | 1358 | "hotplug-memory", hotplug_mem_size); |
a7d69ff1 BR |
1359 | memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, |
1360 | &pcms->hotplug_memory.mr); | |
619d11e4 | 1361 | } |
cbc5b5f3 JJ |
1362 | |
1363 | /* Initialize PC system firmware */ | |
5db3f0de | 1364 | pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); |
00cb2a99 | 1365 | |
7267c094 | 1366 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
49946538 | 1367 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1368 | &error_fatal); |
c5705a77 | 1369 | vmstate_register_ram_global(option_rom_mr); |
4463aee6 | 1370 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1371 | PC_ROM_MIN_VGA, |
1372 | option_rom_mr, | |
1373 | 1); | |
f753ff16 | 1374 | |
ebde2465 | 1375 | fw_cfg = bochs_bios_init(&address_space_memory, pcms); |
c886fc4c | 1376 | |
8832cb80 | 1377 | rom_set_fw(fw_cfg); |
1d108d97 | 1378 | |
bb292f5a | 1379 | if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { |
de268e13 | 1380 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 IM |
1381 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
1382 | uint64_t res_mem_end = pcms->hotplug_memory.base; | |
1383 | ||
1384 | if (!pcmc->broken_reserved_end) { | |
1385 | res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); | |
1386 | } | |
3385e8e2 | 1387 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); |
de268e13 IM |
1388 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1389 | } | |
1390 | ||
f753ff16 | 1391 | if (linux_boot) { |
df1f79fd | 1392 | load_linux(pcms, fw_cfg); |
f753ff16 PB |
1393 | } |
1394 | ||
1395 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1396 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1397 | } |
f264d360 | 1398 | pcms->fw_cfg = fw_cfg; |
3d53f5c3 IY |
1399 | } |
1400 | ||
0b0cc076 | 1401 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1402 | { |
0b0cc076 | 1403 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1404 | } |
1405 | ||
48a18b3c | 1406 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1407 | { |
ad6d45fa AL |
1408 | DeviceState *dev = NULL; |
1409 | ||
bab47d9a | 1410 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1411 | if (pci_bus) { |
1412 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1413 | dev = pcidev ? &pcidev->qdev : NULL; | |
1414 | } else if (isa_bus) { | |
1415 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1416 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1417 | } |
bab47d9a | 1418 | rom_reset_order_override(); |
ad6d45fa | 1419 | return dev; |
765d7908 IY |
1420 | } |
1421 | ||
258711c6 JG |
1422 | static const MemoryRegionOps ioport80_io_ops = { |
1423 | .write = ioport80_write, | |
c02e1eac | 1424 | .read = ioport80_read, |
258711c6 JG |
1425 | .endianness = DEVICE_NATIVE_ENDIAN, |
1426 | .impl = { | |
1427 | .min_access_size = 1, | |
1428 | .max_access_size = 1, | |
1429 | }, | |
1430 | }; | |
1431 | ||
1432 | static const MemoryRegionOps ioportF0_io_ops = { | |
1433 | .write = ioportF0_write, | |
c02e1eac | 1434 | .read = ioportF0_read, |
258711c6 JG |
1435 | .endianness = DEVICE_NATIVE_ENDIAN, |
1436 | .impl = { | |
1437 | .min_access_size = 1, | |
1438 | .max_access_size = 1, | |
1439 | }, | |
1440 | }; | |
1441 | ||
48a18b3c | 1442 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1443 | ISADevice **rtc_state, |
fd53c87c | 1444 | bool create_fdctrl, |
7a10ef51 | 1445 | bool no_vmport, |
3a87d009 | 1446 | uint32_t hpet_irqs) |
ffe513da IY |
1447 | { |
1448 | int i; | |
1449 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1450 | DeviceState *hpet = NULL; |
1451 | int pit_isa_irq = 0; | |
1452 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1453 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1454 | qemu_irq *a20_line; |
c2d8d311 | 1455 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
258711c6 JG |
1456 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1457 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1458 | |
2c9b15ca | 1459 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1460 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1461 | |
2c9b15ca | 1462 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1463 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1464 | |
5d17c0d2 JK |
1465 | /* |
1466 | * Check if an HPET shall be created. | |
1467 | * | |
1468 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1469 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1470 | */ | |
1471 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1472 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1473 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1474 | if (hpet) { |
7a10ef51 LPF |
1475 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1476 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1477 | * IRQ8 and IRQ2. | |
1478 | */ | |
1479 | uint8_t compat = object_property_get_int(OBJECT(hpet), | |
1480 | HPET_INTCAP, NULL); | |
1481 | if (!compat) { | |
1482 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1483 | } | |
1484 | qdev_init_nofail(hpet); | |
1485 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1486 | ||
b881fbe9 | 1487 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1488 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1489 | } |
ce967e2f JK |
1490 | pit_isa_irq = -1; |
1491 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1492 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1493 | } |
ffe513da | 1494 | } |
48a18b3c | 1495 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1496 | |
1497 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1498 | ||
c2d8d311 | 1499 | if (!xen_enabled()) { |
15eafc2e | 1500 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1501 | pit = kvm_pit_init(isa_bus, 0x40); |
1502 | } else { | |
1503 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1504 | } | |
1505 | if (hpet) { | |
1506 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1507 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1508 | } |
1509 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1510 | } |
ffe513da | 1511 | |
b6607a1a | 1512 | serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); |
07dc7880 | 1513 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
ffe513da | 1514 | |
182735ef | 1515 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1516 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1517 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1518 | if (!no_vmport) { |
48a18b3c HP |
1519 | vmport_init(isa_bus); |
1520 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1521 | } else { |
1522 | vmmouse = NULL; | |
1523 | } | |
86d86414 | 1524 | if (vmmouse) { |
4a17cc4f AF |
1525 | DeviceState *dev = DEVICE(vmmouse); |
1526 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1527 | qdev_init_nofail(dev); | |
86d86414 | 1528 | } |
48a18b3c | 1529 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1530 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1531 | |
57146941 | 1532 | DMA_init(isa_bus, 0); |
ffe513da IY |
1533 | |
1534 | for(i = 0; i < MAX_FD; i++) { | |
1535 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
936a7c1c | 1536 | create_fdctrl |= !!fd[i]; |
ffe513da | 1537 | } |
220a8846 LE |
1538 | if (create_fdctrl) { |
1539 | fdctrl_init_isa(isa_bus, fd); | |
1540 | } | |
ffe513da IY |
1541 | } |
1542 | ||
9011a1a7 IY |
1543 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1544 | { | |
1545 | int i; | |
1546 | ||
bab47d9a | 1547 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1548 | for (i = 0; i < nb_nics; i++) { |
1549 | NICInfo *nd = &nd_table[i]; | |
1550 | ||
1551 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1552 | pc_init_ne2k_isa(isa_bus, nd); | |
1553 | } else { | |
29b358f9 | 1554 | pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); |
9011a1a7 IY |
1555 | } |
1556 | } | |
bab47d9a | 1557 | rom_reset_order_override(); |
9011a1a7 IY |
1558 | } |
1559 | ||
845773ab | 1560 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1561 | { |
1562 | int max_bus; | |
1563 | int bus; | |
1564 | ||
1565 | max_bus = drive_get_max_bus(IF_SCSI); | |
1566 | for (bus = 0; bus <= max_bus; bus++) { | |
1567 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1568 | } | |
1569 | } | |
a39e3564 JB |
1570 | |
1571 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1572 | { | |
1573 | DeviceState *dev; | |
1574 | SysBusDevice *d; | |
1575 | unsigned int i; | |
1576 | ||
15eafc2e | 1577 | if (kvm_ioapic_in_kernel()) { |
a39e3564 JB |
1578 | dev = qdev_create(NULL, "kvm-ioapic"); |
1579 | } else { | |
1580 | dev = qdev_create(NULL, "ioapic"); | |
1581 | } | |
1582 | if (parent_name) { | |
1583 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1584 | "ioapic", OBJECT(dev), NULL); | |
1585 | } | |
1586 | qdev_init_nofail(dev); | |
1356b98d | 1587 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1588 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1589 | |
1590 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1591 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1592 | } | |
1593 | } | |
d5747cac | 1594 | |
95bee274 IM |
1595 | static void pc_dimm_plug(HotplugHandler *hotplug_dev, |
1596 | DeviceState *dev, Error **errp) | |
1597 | { | |
3fbcdc27 | 1598 | HotplugHandlerClass *hhc; |
95bee274 IM |
1599 | Error *local_err = NULL; |
1600 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
16a9e8a5 | 1601 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
95bee274 IM |
1602 | PCDIMMDevice *dimm = PC_DIMM(dev); |
1603 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1604 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
92a37a04 | 1605 | uint64_t align = TARGET_PAGE_SIZE; |
95bee274 | 1606 | |
16a9e8a5 | 1607 | if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { |
91aa70ab IM |
1608 | align = memory_region_get_alignment(mr); |
1609 | } | |
1610 | ||
3fbcdc27 IM |
1611 | if (!pcms->acpi_dev) { |
1612 | error_setg(&local_err, | |
1613 | "memory hotplug is not enabled: missing acpi device"); | |
1614 | goto out; | |
1615 | } | |
1616 | ||
d6a9b0b8 | 1617 | pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); |
43bbb49e | 1618 | if (local_err) { |
b8865591 IM |
1619 | goto out; |
1620 | } | |
1621 | ||
3fbcdc27 | 1622 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
8e23184b | 1623 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1624 | out: |
1625 | error_propagate(errp, local_err); | |
1626 | } | |
1627 | ||
64fec58e TC |
1628 | static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, |
1629 | DeviceState *dev, Error **errp) | |
1630 | { | |
1631 | HotplugHandlerClass *hhc; | |
1632 | Error *local_err = NULL; | |
1633 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1634 | ||
1635 | if (!pcms->acpi_dev) { | |
1636 | error_setg(&local_err, | |
1637 | "memory hotplug is not enabled: missing acpi device"); | |
1638 | goto out; | |
1639 | } | |
1640 | ||
1641 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1642 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1643 | ||
1644 | out: | |
1645 | error_propagate(errp, local_err); | |
1646 | } | |
1647 | ||
f7d3e29d TC |
1648 | static void pc_dimm_unplug(HotplugHandler *hotplug_dev, |
1649 | DeviceState *dev, Error **errp) | |
1650 | { | |
1651 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1652 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
1653 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1654 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
1655 | HotplugHandlerClass *hhc; | |
1656 | Error *local_err = NULL; | |
1657 | ||
1658 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1659 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1660 | ||
1661 | if (local_err) { | |
1662 | goto out; | |
1663 | } | |
1664 | ||
43bbb49e | 1665 | pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); |
f7d3e29d TC |
1666 | object_unparent(OBJECT(dev)); |
1667 | ||
1668 | out: | |
1669 | error_propagate(errp, local_err); | |
1670 | } | |
1671 | ||
3811ef14 IM |
1672 | static int pc_apic_cmp(const void *a, const void *b) |
1673 | { | |
1674 | CPUArchId *apic_a = (CPUArchId *)a; | |
1675 | CPUArchId *apic_b = (CPUArchId *)b; | |
1676 | ||
1677 | return apic_a->arch_id - apic_b->arch_id; | |
1678 | } | |
1679 | ||
5279569e GZ |
1680 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1681 | DeviceState *dev, Error **errp) | |
1682 | { | |
3811ef14 IM |
1683 | CPUClass *cc = CPU_GET_CLASS(dev); |
1684 | CPUArchId apic_id, *found_cpu; | |
5279569e GZ |
1685 | HotplugHandlerClass *hhc; |
1686 | Error *local_err = NULL; | |
1687 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1688 | ||
1689 | if (!dev->hotplugged) { | |
1690 | goto out; | |
1691 | } | |
1692 | ||
1693 | if (!pcms->acpi_dev) { | |
1694 | error_setg(&local_err, | |
1695 | "cpu hotplug is not enabled: missing acpi device"); | |
1696 | goto out; | |
1697 | } | |
1698 | ||
1699 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1700 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2d996150 GZ |
1701 | if (local_err) { |
1702 | goto out; | |
1703 | } | |
1704 | ||
1705 | /* increment the number of CPUs */ | |
1706 | rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); | |
3811ef14 IM |
1707 | |
1708 | apic_id.arch_id = cc->get_arch_id(CPU(dev)); | |
1709 | found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, | |
1710 | pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), | |
1711 | pc_apic_cmp); | |
1712 | assert(found_cpu); | |
1713 | found_cpu->cpu = CPU(dev); | |
5279569e GZ |
1714 | out: |
1715 | error_propagate(errp, local_err); | |
1716 | } | |
1717 | ||
95bee274 IM |
1718 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1719 | DeviceState *dev, Error **errp) | |
1720 | { | |
1721 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1722 | pc_dimm_plug(hotplug_dev, dev, errp); | |
5279569e GZ |
1723 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1724 | pc_cpu_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1725 | } |
1726 | } | |
1727 | ||
d9c5c5b8 TC |
1728 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1729 | DeviceState *dev, Error **errp) | |
1730 | { | |
64fec58e TC |
1731 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1732 | pc_dimm_unplug_request(hotplug_dev, dev, errp); | |
1733 | } else { | |
1734 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1735 | " type: %s", object_get_typename(OBJECT(dev))); | |
1736 | } | |
d9c5c5b8 TC |
1737 | } |
1738 | ||
232391c1 TC |
1739 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1740 | DeviceState *dev, Error **errp) | |
1741 | { | |
f7d3e29d TC |
1742 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1743 | pc_dimm_unplug(hotplug_dev, dev, errp); | |
1744 | } else { | |
1745 | error_setg(errp, "acpi: device unplug for not supported device" | |
1746 | " type: %s", object_get_typename(OBJECT(dev))); | |
1747 | } | |
232391c1 TC |
1748 | } |
1749 | ||
95bee274 IM |
1750 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, |
1751 | DeviceState *dev) | |
1752 | { | |
1753 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); | |
1754 | ||
5279569e GZ |
1755 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
1756 | object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
95bee274 IM |
1757 | return HOTPLUG_HANDLER(machine); |
1758 | } | |
1759 | ||
1760 | return pcmc->get_hotplug_handler ? | |
1761 | pcmc->get_hotplug_handler(machine, dev) : NULL; | |
1762 | } | |
1763 | ||
bf1e8939 | 1764 | static void |
d7bce999 EB |
1765 | pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, |
1766 | const char *name, void *opaque, | |
1767 | Error **errp) | |
bf1e8939 IM |
1768 | { |
1769 | PCMachineState *pcms = PC_MACHINE(obj); | |
a7d69ff1 | 1770 | int64_t value = memory_region_size(&pcms->hotplug_memory.mr); |
bf1e8939 | 1771 | |
51e72bc1 | 1772 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
1773 | } |
1774 | ||
c87b1520 | 1775 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
d7bce999 EB |
1776 | const char *name, void *opaque, |
1777 | Error **errp) | |
c87b1520 DS |
1778 | { |
1779 | PCMachineState *pcms = PC_MACHINE(obj); | |
1780 | uint64_t value = pcms->max_ram_below_4g; | |
1781 | ||
51e72bc1 | 1782 | visit_type_size(v, name, &value, errp); |
c87b1520 DS |
1783 | } |
1784 | ||
1785 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
d7bce999 EB |
1786 | const char *name, void *opaque, |
1787 | Error **errp) | |
c87b1520 DS |
1788 | { |
1789 | PCMachineState *pcms = PC_MACHINE(obj); | |
1790 | Error *error = NULL; | |
1791 | uint64_t value; | |
1792 | ||
51e72bc1 | 1793 | visit_type_size(v, name, &value, &error); |
c87b1520 DS |
1794 | if (error) { |
1795 | error_propagate(errp, error); | |
1796 | return; | |
1797 | } | |
1798 | if (value > (1ULL << 32)) { | |
455b0fde EB |
1799 | error_setg(&error, |
1800 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
1801 | "' expects size less than or equal to 4G", value); | |
c87b1520 DS |
1802 | error_propagate(errp, error); |
1803 | return; | |
1804 | } | |
1805 | ||
1806 | if (value < (1ULL << 20)) { | |
1807 | error_report("Warning: small max_ram_below_4g(%"PRIu64 | |
1808 | ") less than 1M. BIOS may not work..", | |
1809 | value); | |
1810 | } | |
1811 | ||
1812 | pcms->max_ram_below_4g = value; | |
1813 | } | |
1814 | ||
d7bce999 EB |
1815 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
1816 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1817 | { |
1818 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 1819 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 1820 | |
51e72bc1 | 1821 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
1822 | } |
1823 | ||
d7bce999 EB |
1824 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
1825 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1826 | { |
1827 | PCMachineState *pcms = PC_MACHINE(obj); | |
1828 | ||
51e72bc1 | 1829 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
1830 | } |
1831 | ||
355023f2 PB |
1832 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) |
1833 | { | |
1834 | bool smm_available = false; | |
1835 | ||
1836 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
1837 | return false; | |
1838 | } | |
1839 | ||
1840 | if (tcg_enabled() || qtest_enabled()) { | |
1841 | smm_available = true; | |
1842 | } else if (kvm_enabled()) { | |
1843 | smm_available = kvm_has_smm(); | |
1844 | } | |
1845 | ||
1846 | if (smm_available) { | |
1847 | return true; | |
1848 | } | |
1849 | ||
1850 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
1851 | error_report("System Management Mode not supported by this hypervisor."); | |
1852 | exit(1); | |
1853 | } | |
1854 | return false; | |
1855 | } | |
1856 | ||
d7bce999 EB |
1857 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, |
1858 | void *opaque, Error **errp) | |
355023f2 PB |
1859 | { |
1860 | PCMachineState *pcms = PC_MACHINE(obj); | |
1861 | OnOffAuto smm = pcms->smm; | |
1862 | ||
51e72bc1 | 1863 | visit_type_OnOffAuto(v, name, &smm, errp); |
355023f2 PB |
1864 | } |
1865 | ||
d7bce999 EB |
1866 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, |
1867 | void *opaque, Error **errp) | |
355023f2 PB |
1868 | { |
1869 | PCMachineState *pcms = PC_MACHINE(obj); | |
1870 | ||
51e72bc1 | 1871 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); |
355023f2 PB |
1872 | } |
1873 | ||
87252e1b XG |
1874 | static bool pc_machine_get_nvdimm(Object *obj, Error **errp) |
1875 | { | |
1876 | PCMachineState *pcms = PC_MACHINE(obj); | |
1877 | ||
5fe79386 | 1878 | return pcms->acpi_nvdimm_state.is_enabled; |
87252e1b XG |
1879 | } |
1880 | ||
1881 | static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
1882 | { | |
1883 | PCMachineState *pcms = PC_MACHINE(obj); | |
1884 | ||
5fe79386 | 1885 | pcms->acpi_nvdimm_state.is_enabled = value; |
87252e1b XG |
1886 | } |
1887 | ||
bf1e8939 IM |
1888 | static void pc_machine_initfn(Object *obj) |
1889 | { | |
c87b1520 DS |
1890 | PCMachineState *pcms = PC_MACHINE(obj); |
1891 | ||
bf1e8939 IM |
1892 | object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", |
1893 | pc_machine_get_hotplug_memory_region_size, | |
dda65c7c | 1894 | NULL, NULL, NULL, &error_abort); |
49d2e648 | 1895 | |
c87b1520 DS |
1896 | pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ |
1897 | object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
1898 | pc_machine_get_max_ram_below_4g, | |
1899 | pc_machine_set_max_ram_below_4g, | |
dda65c7c | 1900 | NULL, NULL, &error_abort); |
49d2e648 MA |
1901 | object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, |
1902 | "Maximum ram below the 4G boundary (32bit boundary)", | |
dda65c7c | 1903 | &error_abort); |
91aa70ab | 1904 | |
355023f2 PB |
1905 | pcms->smm = ON_OFF_AUTO_AUTO; |
1906 | object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", | |
1907 | pc_machine_get_smm, | |
1908 | pc_machine_set_smm, | |
dda65c7c | 1909 | NULL, NULL, &error_abort); |
355023f2 PB |
1910 | object_property_set_description(obj, PC_MACHINE_SMM, |
1911 | "Enable SMM (pc & q35)", | |
dda65c7c | 1912 | &error_abort); |
355023f2 | 1913 | |
d1048bef DS |
1914 | pcms->vmport = ON_OFF_AUTO_AUTO; |
1915 | object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", | |
1916 | pc_machine_get_vmport, | |
1917 | pc_machine_set_vmport, | |
dda65c7c | 1918 | NULL, NULL, &error_abort); |
49d2e648 MA |
1919 | object_property_set_description(obj, PC_MACHINE_VMPORT, |
1920 | "Enable vmport (pc & q35)", | |
dda65c7c | 1921 | &error_abort); |
87252e1b XG |
1922 | |
1923 | /* nvdimm is disabled on default. */ | |
5fe79386 | 1924 | pcms->acpi_nvdimm_state.is_enabled = false; |
87252e1b XG |
1925 | object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, |
1926 | pc_machine_set_nvdimm, &error_abort); | |
bf1e8939 IM |
1927 | } |
1928 | ||
ae50c55a ZG |
1929 | static void pc_machine_reset(void) |
1930 | { | |
1931 | CPUState *cs; | |
1932 | X86CPU *cpu; | |
1933 | ||
1934 | qemu_devices_reset(); | |
1935 | ||
1936 | /* Reset APIC after devices have been reset to cancel | |
1937 | * any changes that qemu_devices_reset() might have done. | |
1938 | */ | |
1939 | CPU_FOREACH(cs) { | |
1940 | cpu = X86_CPU(cs); | |
1941 | ||
1942 | if (cpu->apic_state) { | |
1943 | device_reset(cpu->apic_state); | |
1944 | } | |
1945 | } | |
1946 | } | |
1947 | ||
fb43b73b IM |
1948 | static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) |
1949 | { | |
ed256144 | 1950 | X86CPUTopoInfo topo; |
fb43b73b | 1951 | x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, |
ed256144 CF |
1952 | &topo); |
1953 | return topo.pkg_id; | |
fb43b73b IM |
1954 | } |
1955 | ||
3811ef14 IM |
1956 | static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine) |
1957 | { | |
1958 | PCMachineState *pcms = PC_MACHINE(machine); | |
1959 | int len = sizeof(CPUArchIdList) + | |
1960 | sizeof(CPUArchId) * (pcms->possible_cpus->len); | |
1961 | CPUArchIdList *list = g_malloc(len); | |
1962 | ||
1963 | memcpy(list, pcms->possible_cpus, len); | |
1964 | return list; | |
1965 | } | |
1966 | ||
1255166b BD |
1967 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) |
1968 | { | |
1969 | /* cpu index isn't used */ | |
1970 | CPUState *cs; | |
1971 | ||
1972 | CPU_FOREACH(cs) { | |
1973 | X86CPU *cpu = X86_CPU(cs); | |
1974 | ||
1975 | if (!cpu->apic_state) { | |
1976 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
1977 | } else { | |
1978 | apic_deliver_nmi(cpu->apic_state); | |
1979 | } | |
1980 | } | |
1981 | } | |
1982 | ||
95bee274 IM |
1983 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
1984 | { | |
1985 | MachineClass *mc = MACHINE_CLASS(oc); | |
1986 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
1987 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1255166b | 1988 | NMIClass *nc = NMI_CLASS(oc); |
95bee274 IM |
1989 | |
1990 | pcmc->get_hotplug_handler = mc->get_hotplug_handler; | |
7102fa70 EH |
1991 | pcmc->pci_enabled = true; |
1992 | pcmc->has_acpi_build = true; | |
1993 | pcmc->rsdp_in_ram = true; | |
1994 | pcmc->smbios_defaults = true; | |
1995 | pcmc->smbios_uuid_encoded = true; | |
1996 | pcmc->gigabyte_align = true; | |
1997 | pcmc->has_reserved_memory = true; | |
1998 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 1999 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2000 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2001 | * to be used at the moment, 32K should be enough for a while. */ | |
2002 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
36f96c4b | 2003 | pcmc->save_tsc_khz = true; |
95bee274 | 2004 | mc->get_hotplug_handler = pc_get_hotpug_handler; |
fb43b73b | 2005 | mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; |
3811ef14 | 2006 | mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; |
41742767 | 2007 | mc->default_boot_order = "cad"; |
4458fb3a EH |
2008 | mc->hot_add_cpu = pc_hot_add_cpu; |
2009 | mc->max_cpus = 255; | |
ae50c55a | 2010 | mc->reset = pc_machine_reset; |
95bee274 | 2011 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2012 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2013 | hc->unplug = pc_machine_device_unplug_cb; |
1255166b | 2014 | nc->nmi_monitor_handler = x86_nmi; |
95bee274 IM |
2015 | } |
2016 | ||
d5747cac IM |
2017 | static const TypeInfo pc_machine_info = { |
2018 | .name = TYPE_PC_MACHINE, | |
2019 | .parent = TYPE_MACHINE, | |
2020 | .abstract = true, | |
2021 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2022 | .instance_init = pc_machine_initfn, |
d5747cac | 2023 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2024 | .class_init = pc_machine_class_init, |
2025 | .interfaces = (InterfaceInfo[]) { | |
2026 | { TYPE_HOTPLUG_HANDLER }, | |
1255166b | 2027 | { TYPE_NMI }, |
95bee274 IM |
2028 | { } |
2029 | }, | |
d5747cac IM |
2030 | }; |
2031 | ||
2032 | static void pc_machine_register_types(void) | |
2033 | { | |
2034 | type_register_static(&pc_machine_info); | |
2035 | } | |
2036 | ||
2037 | type_init(pc_machine_register_types) |