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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
0d09e41a PB |
25 | #include "hw/i386/pc.h" |
26 | #include "hw/char/serial.h" | |
27 | #include "hw/i386/apic.h" | |
54a40293 EH |
28 | #include "hw/i386/topology.h" |
29 | #include "sysemu/cpus.h" | |
0d09e41a | 30 | #include "hw/block/fdc.h" |
83c9f4ca PB |
31 | #include "hw/ide.h" |
32 | #include "hw/pci/pci.h" | |
83c9089e | 33 | #include "monitor/monitor.h" |
0d09e41a PB |
34 | #include "hw/nvram/fw_cfg.h" |
35 | #include "hw/timer/hpet.h" | |
36 | #include "hw/i386/smbios.h" | |
83c9f4ca | 37 | #include "hw/loader.h" |
ca20cf32 | 38 | #include "elf.h" |
47b43a1f | 39 | #include "multiboot.h" |
0d09e41a PB |
40 | #include "hw/timer/mc146818rtc.h" |
41 | #include "hw/timer/i8254.h" | |
42 | #include "hw/audio/pcspk.h" | |
83c9f4ca PB |
43 | #include "hw/pci/msi.h" |
44 | #include "hw/sysbus.h" | |
9c17d615 | 45 | #include "sysemu/sysemu.h" |
e35704ba | 46 | #include "sysemu/numa.h" |
9c17d615 | 47 | #include "sysemu/kvm.h" |
b1c12027 | 48 | #include "sysemu/qtest.h" |
1d31f66b | 49 | #include "kvm_i386.h" |
0d09e41a | 50 | #include "hw/xen/xen.h" |
4be74634 | 51 | #include "sysemu/block-backend.h" |
0d09e41a | 52 | #include "hw/block/block.h" |
a19cbfb3 | 53 | #include "ui/qemu-spice.h" |
022c62cb PB |
54 | #include "exec/memory.h" |
55 | #include "exec/address-spaces.h" | |
9c17d615 | 56 | #include "sysemu/arch_init.h" |
1de7afc9 | 57 | #include "qemu/bitmap.h" |
0c764a9d | 58 | #include "qemu/config-file.h" |
0445259b | 59 | #include "hw/acpi/acpi.h" |
5ff020b7 | 60 | #include "hw/acpi/cpu_hotplug.h" |
53a89e26 | 61 | #include "hw/cpu/icc_bus.h" |
c649983b | 62 | #include "hw/boards.h" |
39848901 | 63 | #include "hw/pci/pci_host.h" |
72c194f7 | 64 | #include "acpi-build.h" |
95bee274 | 65 | #include "hw/mem/pc-dimm.h" |
2e1ac493 | 66 | #include "trace.h" |
bf1e8939 | 67 | #include "qapi/visitor.h" |
d1048bef | 68 | #include "qapi-visit.h" |
80cabfad | 69 | |
471fd342 BS |
70 | /* debug PC/ISA interrupts */ |
71 | //#define DEBUG_IRQ | |
72 | ||
73 | #ifdef DEBUG_IRQ | |
74 | #define DPRINTF(fmt, ...) \ | |
75 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
76 | #else | |
77 | #define DPRINTF(fmt, ...) | |
78 | #endif | |
79 | ||
438f92ee MT |
80 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables |
81 | * (128K) and other BIOS datastructures (less than 4K reported to be used at | |
82 | * the moment, 32K should be enough for a while). */ | |
e0bcc42e | 83 | static unsigned acpi_data_size = 0x20000 + 0x8000; |
927766c7 MT |
84 | void pc_set_legacy_acpi_data_size(void) |
85 | { | |
86 | acpi_data_size = 0x10000; | |
87 | } | |
88 | ||
3cce6243 | 89 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 90 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 91 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 92 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 93 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 94 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 95 | |
4c5b10b7 JS |
96 | #define E820_NR_ENTRIES 16 |
97 | ||
98 | struct e820_entry { | |
99 | uint64_t address; | |
100 | uint64_t length; | |
101 | uint32_t type; | |
541dc0d4 | 102 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
103 | |
104 | struct e820_table { | |
105 | uint32_t count; | |
106 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 107 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 | 108 | |
7d67110f GH |
109 | static struct e820_table e820_reserve; |
110 | static struct e820_entry *e820_table; | |
111 | static unsigned e820_entries; | |
dd703b99 | 112 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 113 | |
b881fbe9 | 114 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 115 | { |
b881fbe9 | 116 | GSIState *s = opaque; |
1452411b | 117 | |
b881fbe9 JK |
118 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
119 | if (n < ISA_NUM_IRQS) { | |
120 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 121 | } |
b881fbe9 | 122 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 123 | } |
1452411b | 124 | |
258711c6 JG |
125 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
126 | unsigned size) | |
80cabfad FB |
127 | { |
128 | } | |
129 | ||
c02e1eac JG |
130 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
131 | { | |
a6fc23e5 | 132 | return 0xffffffffffffffffULL; |
c02e1eac JG |
133 | } |
134 | ||
f929aad6 | 135 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 136 | static qemu_irq ferr_irq; |
8e78eb28 IY |
137 | |
138 | void pc_register_ferr_irq(qemu_irq irq) | |
139 | { | |
140 | ferr_irq = irq; | |
141 | } | |
142 | ||
f929aad6 FB |
143 | /* XXX: add IGNNE support */ |
144 | void cpu_set_ferr(CPUX86State *s) | |
145 | { | |
d537cf6c | 146 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
147 | } |
148 | ||
258711c6 JG |
149 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
150 | unsigned size) | |
f929aad6 | 151 | { |
d537cf6c | 152 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
153 | } |
154 | ||
c02e1eac JG |
155 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
156 | { | |
a6fc23e5 | 157 | return 0xffffffffffffffffULL; |
c02e1eac JG |
158 | } |
159 | ||
28ab0e2e | 160 | /* TSC handling */ |
28ab0e2e FB |
161 | uint64_t cpu_get_tsc(CPUX86State *env) |
162 | { | |
4a1418e0 | 163 | return cpu_get_ticks(); |
28ab0e2e FB |
164 | } |
165 | ||
a5954d5c | 166 | /* SMM support */ |
f885f1ea IY |
167 | |
168 | static cpu_set_smm_t smm_set; | |
169 | static void *smm_arg; | |
170 | ||
171 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
172 | { | |
173 | assert(smm_set == NULL); | |
174 | assert(smm_arg == NULL); | |
175 | smm_set = callback; | |
176 | smm_arg = arg; | |
177 | } | |
178 | ||
4a8fa5dc | 179 | void cpu_smm_update(CPUX86State *env) |
a5954d5c | 180 | { |
182735ef | 181 | if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { |
f885f1ea | 182 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); |
182735ef | 183 | } |
a5954d5c FB |
184 | } |
185 | ||
186 | ||
3de388f6 | 187 | /* IRQ handling */ |
4a8fa5dc | 188 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 189 | { |
02e51483 | 190 | X86CPU *cpu = x86_env_get_cpu(env); |
3de388f6 FB |
191 | int intno; |
192 | ||
02e51483 | 193 | intno = apic_get_interrupt(cpu->apic_state); |
3de388f6 | 194 | if (intno >= 0) { |
3de388f6 FB |
195 | return intno; |
196 | } | |
3de388f6 | 197 | /* read the irq from the PIC */ |
02e51483 | 198 | if (!apic_accept_pic_intr(cpu->apic_state)) { |
0e21e12b | 199 | return -1; |
cf6d64bf | 200 | } |
0e21e12b | 201 | |
3de388f6 FB |
202 | intno = pic_read_irq(isa_pic); |
203 | return intno; | |
204 | } | |
205 | ||
d537cf6c | 206 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 207 | { |
182735ef AF |
208 | CPUState *cs = first_cpu; |
209 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 210 | |
471fd342 | 211 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
02e51483 | 212 | if (cpu->apic_state) { |
bdc44640 | 213 | CPU_FOREACH(cs) { |
182735ef | 214 | cpu = X86_CPU(cs); |
02e51483 CF |
215 | if (apic_accept_pic_intr(cpu->apic_state)) { |
216 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 217 | } |
d5529471 AJ |
218 | } |
219 | } else { | |
d8ed887b | 220 | if (level) { |
c3affe56 | 221 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
222 | } else { |
223 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
224 | } | |
a5b38b51 | 225 | } |
3de388f6 FB |
226 | } |
227 | ||
b0a21b53 FB |
228 | /* PC cmos mappings */ |
229 | ||
80cabfad FB |
230 | #define REG_EQUIPMENT_BYTE 0x14 |
231 | ||
d288c7ba | 232 | static int cmos_get_fd_drive_type(FDriveType fd0) |
777428f2 FB |
233 | { |
234 | int val; | |
235 | ||
236 | switch (fd0) { | |
d288c7ba | 237 | case FDRIVE_DRV_144: |
777428f2 FB |
238 | /* 1.44 Mb 3"5 drive */ |
239 | val = 4; | |
240 | break; | |
d288c7ba | 241 | case FDRIVE_DRV_288: |
777428f2 FB |
242 | /* 2.88 Mb 3"5 drive */ |
243 | val = 5; | |
244 | break; | |
d288c7ba | 245 | case FDRIVE_DRV_120: |
777428f2 FB |
246 | /* 1.2 Mb 5"5 drive */ |
247 | val = 2; | |
248 | break; | |
d288c7ba | 249 | case FDRIVE_DRV_NONE: |
777428f2 FB |
250 | default: |
251 | val = 0; | |
252 | break; | |
253 | } | |
254 | return val; | |
255 | } | |
256 | ||
9139046c MA |
257 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
258 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 259 | { |
ba6c2377 FB |
260 | rtc_set_memory(s, type_ofs, 47); |
261 | rtc_set_memory(s, info_ofs, cylinders); | |
262 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
263 | rtc_set_memory(s, info_ofs + 2, heads); | |
264 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
265 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
266 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
267 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
268 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
269 | rtc_set_memory(s, info_ofs + 8, sectors); | |
270 | } | |
271 | ||
6ac0e82d AZ |
272 | /* convert boot_device letter to something recognizable by the bios */ |
273 | static int boot_device2nibble(char boot_device) | |
274 | { | |
275 | switch(boot_device) { | |
276 | case 'a': | |
277 | case 'b': | |
278 | return 0x01; /* floppy boot */ | |
279 | case 'c': | |
280 | return 0x02; /* hard drive boot */ | |
281 | case 'd': | |
282 | return 0x03; /* CD-ROM boot */ | |
283 | case 'n': | |
284 | return 0x04; /* Network boot */ | |
285 | } | |
286 | return 0; | |
287 | } | |
288 | ||
ddcd5531 | 289 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
290 | { |
291 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
292 | int nbds, bds[3] = { 0, }; |
293 | int i; | |
294 | ||
295 | nbds = strlen(boot_device); | |
296 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
297 | error_setg(errp, "Too many boot devices for PC"); |
298 | return; | |
0ecdffbb AJ |
299 | } |
300 | for (i = 0; i < nbds; i++) { | |
301 | bds[i] = boot_device2nibble(boot_device[i]); | |
302 | if (bds[i] == 0) { | |
ddcd5531 GA |
303 | error_setg(errp, "Invalid boot device for PC: '%c'", |
304 | boot_device[i]); | |
305 | return; | |
0ecdffbb AJ |
306 | } |
307 | } | |
308 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 309 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
310 | } |
311 | ||
ddcd5531 | 312 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 313 | { |
ddcd5531 | 314 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
315 | } |
316 | ||
c0897e0c MA |
317 | typedef struct pc_cmos_init_late_arg { |
318 | ISADevice *rtc_state; | |
9139046c | 319 | BusState *idebus[2]; |
c0897e0c MA |
320 | } pc_cmos_init_late_arg; |
321 | ||
322 | static void pc_cmos_init_late(void *opaque) | |
323 | { | |
324 | pc_cmos_init_late_arg *arg = opaque; | |
325 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
326 | int16_t cylinders; |
327 | int8_t heads, sectors; | |
c0897e0c | 328 | int val; |
2adc99b2 | 329 | int i, trans; |
c0897e0c | 330 | |
9139046c MA |
331 | val = 0; |
332 | if (ide_get_geometry(arg->idebus[0], 0, | |
333 | &cylinders, &heads, §ors) >= 0) { | |
334 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
335 | val |= 0xf0; | |
336 | } | |
337 | if (ide_get_geometry(arg->idebus[0], 1, | |
338 | &cylinders, &heads, §ors) >= 0) { | |
339 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
340 | val |= 0x0f; | |
341 | } | |
342 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
343 | |
344 | val = 0; | |
345 | for (i = 0; i < 4; i++) { | |
9139046c MA |
346 | /* NOTE: ide_get_geometry() returns the physical |
347 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
348 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
349 | geometry can be different if a translation is done. */ | |
350 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
351 | &cylinders, &heads, §ors) >= 0) { | |
2adc99b2 MA |
352 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
353 | assert((trans & ~3) == 0); | |
354 | val |= trans << (i * 2); | |
c0897e0c MA |
355 | } |
356 | } | |
357 | rtc_set_memory(s, 0x39, val); | |
358 | ||
359 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
360 | } | |
361 | ||
845773ab | 362 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
2d996150 | 363 | const char *boot_device, MachineState *machine, |
34d4260e | 364 | ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
63ffb564 | 365 | ISADevice *s) |
80cabfad | 366 | { |
61a8d649 | 367 | int val, nb, i; |
980bda8b | 368 | FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; |
c0897e0c | 369 | static pc_cmos_init_late_arg arg; |
2d996150 | 370 | PCMachineState *pc_machine = PC_MACHINE(machine); |
ddcd5531 | 371 | Error *local_err = NULL; |
b0a21b53 | 372 | |
b0a21b53 | 373 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
374 | |
375 | /* memory size */ | |
e89001f7 MA |
376 | /* base memory (first MiB) */ |
377 | val = MIN(ram_size / 1024, 640); | |
333190eb FB |
378 | rtc_set_memory(s, 0x15, val); |
379 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 MA |
380 | /* extended memory (next 64MiB) */ |
381 | if (ram_size > 1024 * 1024) { | |
382 | val = (ram_size - 1024 * 1024) / 1024; | |
383 | } else { | |
384 | val = 0; | |
385 | } | |
80cabfad FB |
386 | if (val > 65535) |
387 | val = 65535; | |
b0a21b53 FB |
388 | rtc_set_memory(s, 0x17, val); |
389 | rtc_set_memory(s, 0x18, val >> 8); | |
390 | rtc_set_memory(s, 0x30, val); | |
391 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 MA |
392 | /* memory between 16MiB and 4GiB */ |
393 | if (ram_size > 16 * 1024 * 1024) { | |
394 | val = (ram_size - 16 * 1024 * 1024) / 65536; | |
395 | } else { | |
9da98861 | 396 | val = 0; |
e89001f7 | 397 | } |
80cabfad FB |
398 | if (val > 65535) |
399 | val = 65535; | |
b0a21b53 FB |
400 | rtc_set_memory(s, 0x34, val); |
401 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 MA |
402 | /* memory above 4GiB */ |
403 | val = above_4g_mem_size / 65536; | |
404 | rtc_set_memory(s, 0x5b, val); | |
405 | rtc_set_memory(s, 0x5c, val >> 8); | |
406 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 407 | |
298e01b6 AJ |
408 | /* set the number of CPU */ |
409 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
2d996150 GZ |
410 | |
411 | object_property_add_link(OBJECT(machine), "rtc_state", | |
412 | TYPE_ISA_DEVICE, | |
413 | (Object **)&pc_machine->rtc, | |
414 | object_property_allow_set_link, | |
415 | OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | |
416 | object_property_set_link(OBJECT(machine), OBJECT(s), | |
417 | "rtc_state", &error_abort); | |
298e01b6 | 418 | |
ddcd5531 GA |
419 | set_boot_dev(s, boot_device, &local_err); |
420 | if (local_err) { | |
565f65d2 | 421 | error_report_err(local_err); |
28c5af54 JM |
422 | exit(1); |
423 | } | |
80cabfad | 424 | |
b41a2cd1 | 425 | /* floppy type */ |
34d4260e | 426 | if (floppy) { |
34d4260e | 427 | for (i = 0; i < 2; i++) { |
61a8d649 | 428 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); |
63ffb564 BS |
429 | } |
430 | } | |
431 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
432 | cmos_get_fd_drive_type(fd_type[1]); | |
b0a21b53 | 433 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 434 | |
b0a21b53 | 435 | val = 0; |
b41a2cd1 | 436 | nb = 0; |
63ffb564 | 437 | if (fd_type[0] < FDRIVE_DRV_NONE) { |
80cabfad | 438 | nb++; |
d288c7ba | 439 | } |
63ffb564 | 440 | if (fd_type[1] < FDRIVE_DRV_NONE) { |
80cabfad | 441 | nb++; |
d288c7ba | 442 | } |
80cabfad FB |
443 | switch (nb) { |
444 | case 0: | |
445 | break; | |
446 | case 1: | |
b0a21b53 | 447 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
448 | break; |
449 | case 2: | |
b0a21b53 | 450 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
451 | break; |
452 | } | |
b0a21b53 FB |
453 | val |= 0x02; /* FPU is there */ |
454 | val |= 0x04; /* PS/2 mouse installed */ | |
455 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
456 | ||
ba6c2377 | 457 | /* hard drives */ |
c0897e0c | 458 | arg.rtc_state = s; |
9139046c MA |
459 | arg.idebus[0] = idebus0; |
460 | arg.idebus[1] = idebus1; | |
c0897e0c | 461 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
462 | } |
463 | ||
a0881c64 AF |
464 | #define TYPE_PORT92 "port92" |
465 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
466 | ||
4b78a802 BS |
467 | /* port 92 stuff: could be split off */ |
468 | typedef struct Port92State { | |
a0881c64 AF |
469 | ISADevice parent_obj; |
470 | ||
23af670e | 471 | MemoryRegion io; |
4b78a802 BS |
472 | uint8_t outport; |
473 | qemu_irq *a20_out; | |
474 | } Port92State; | |
475 | ||
93ef4192 AG |
476 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
477 | unsigned size) | |
4b78a802 BS |
478 | { |
479 | Port92State *s = opaque; | |
4700a316 | 480 | int oldval = s->outport; |
4b78a802 | 481 | |
c5539cb4 | 482 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 BS |
483 | s->outport = val; |
484 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
4700a316 | 485 | if ((val & 1) && !(oldval & 1)) { |
4b78a802 BS |
486 | qemu_system_reset_request(); |
487 | } | |
488 | } | |
489 | ||
93ef4192 AG |
490 | static uint64_t port92_read(void *opaque, hwaddr addr, |
491 | unsigned size) | |
4b78a802 BS |
492 | { |
493 | Port92State *s = opaque; | |
494 | uint32_t ret; | |
495 | ||
496 | ret = s->outport; | |
497 | DPRINTF("port92: read 0x%02x\n", ret); | |
498 | return ret; | |
499 | } | |
500 | ||
501 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
502 | { | |
a0881c64 | 503 | Port92State *s = PORT92(dev); |
4b78a802 BS |
504 | |
505 | s->a20_out = a20_out; | |
506 | } | |
507 | ||
508 | static const VMStateDescription vmstate_port92_isa = { | |
509 | .name = "port92", | |
510 | .version_id = 1, | |
511 | .minimum_version_id = 1, | |
d49805ae | 512 | .fields = (VMStateField[]) { |
4b78a802 BS |
513 | VMSTATE_UINT8(outport, Port92State), |
514 | VMSTATE_END_OF_LIST() | |
515 | } | |
516 | }; | |
517 | ||
518 | static void port92_reset(DeviceState *d) | |
519 | { | |
a0881c64 | 520 | Port92State *s = PORT92(d); |
4b78a802 BS |
521 | |
522 | s->outport &= ~1; | |
523 | } | |
524 | ||
23af670e | 525 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
526 | .read = port92_read, |
527 | .write = port92_write, | |
528 | .impl = { | |
529 | .min_access_size = 1, | |
530 | .max_access_size = 1, | |
531 | }, | |
532 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
533 | }; |
534 | ||
db895a1e | 535 | static void port92_initfn(Object *obj) |
4b78a802 | 536 | { |
db895a1e | 537 | Port92State *s = PORT92(obj); |
4b78a802 | 538 | |
1437c94b | 539 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 540 | |
4b78a802 | 541 | s->outport = 0; |
db895a1e AF |
542 | } |
543 | ||
544 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
545 | { | |
546 | ISADevice *isadev = ISA_DEVICE(dev); | |
547 | Port92State *s = PORT92(dev); | |
548 | ||
549 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
550 | } |
551 | ||
8f04ee08 AL |
552 | static void port92_class_initfn(ObjectClass *klass, void *data) |
553 | { | |
39bffca2 | 554 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 555 | |
db895a1e | 556 | dc->realize = port92_realizefn; |
39bffca2 AL |
557 | dc->reset = port92_reset; |
558 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
559 | /* |
560 | * Reason: unlike ordinary ISA devices, this one needs additional | |
561 | * wiring: its A20 output line needs to be wired up by | |
562 | * port92_init(). | |
563 | */ | |
564 | dc->cannot_instantiate_with_device_add_yet = true; | |
8f04ee08 AL |
565 | } |
566 | ||
8c43a6f0 | 567 | static const TypeInfo port92_info = { |
a0881c64 | 568 | .name = TYPE_PORT92, |
39bffca2 AL |
569 | .parent = TYPE_ISA_DEVICE, |
570 | .instance_size = sizeof(Port92State), | |
db895a1e | 571 | .instance_init = port92_initfn, |
39bffca2 | 572 | .class_init = port92_class_initfn, |
4b78a802 BS |
573 | }; |
574 | ||
83f7d43a | 575 | static void port92_register_types(void) |
4b78a802 | 576 | { |
39bffca2 | 577 | type_register_static(&port92_info); |
4b78a802 | 578 | } |
83f7d43a AF |
579 | |
580 | type_init(port92_register_types) | |
4b78a802 | 581 | |
956a3e6b | 582 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 583 | { |
cc36a7a2 | 584 | X86CPU *cpu = opaque; |
e1a23744 | 585 | |
956a3e6b | 586 | /* XXX: send to all CPUs ? */ |
4b78a802 | 587 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 588 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
589 | } |
590 | ||
4c5b10b7 JS |
591 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
592 | { | |
7d67110f | 593 | int index = le32_to_cpu(e820_reserve.count); |
4c5b10b7 JS |
594 | struct e820_entry *entry; |
595 | ||
7d67110f GH |
596 | if (type != E820_RAM) { |
597 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
598 | if (index >= E820_NR_ENTRIES) { | |
599 | return -EBUSY; | |
600 | } | |
601 | entry = &e820_reserve.entry[index++]; | |
602 | ||
603 | entry->address = cpu_to_le64(address); | |
604 | entry->length = cpu_to_le64(length); | |
605 | entry->type = cpu_to_le32(type); | |
606 | ||
607 | e820_reserve.count = cpu_to_le32(index); | |
608 | } | |
4c5b10b7 | 609 | |
7d67110f | 610 | /* new "etc/e820" file -- include ram too */ |
ab3ad07f | 611 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); |
7d67110f GH |
612 | e820_table[e820_entries].address = cpu_to_le64(address); |
613 | e820_table[e820_entries].length = cpu_to_le64(length); | |
614 | e820_table[e820_entries].type = cpu_to_le32(type); | |
615 | e820_entries++; | |
4c5b10b7 | 616 | |
7d67110f | 617 | return e820_entries; |
4c5b10b7 JS |
618 | } |
619 | ||
7bf8ef19 GS |
620 | int e820_get_num_entries(void) |
621 | { | |
622 | return e820_entries; | |
623 | } | |
624 | ||
625 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
626 | { | |
627 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
628 | *address = le64_to_cpu(e820_table[idx].address); | |
629 | *length = le64_to_cpu(e820_table[idx].length); | |
630 | return true; | |
631 | } | |
632 | return false; | |
633 | } | |
634 | ||
54a40293 EH |
635 | /* Enables contiguous-apic-ID mode, for compatibility */ |
636 | static bool compat_apic_id_mode; | |
637 | ||
638 | void enable_compat_apic_id_mode(void) | |
639 | { | |
640 | compat_apic_id_mode = true; | |
641 | } | |
642 | ||
643 | /* Calculates initial APIC ID for a specific CPU index | |
644 | * | |
645 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
646 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
647 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
648 | * all CPUs up to max_cpus. | |
649 | */ | |
650 | static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
651 | { | |
652 | uint32_t correct_id; | |
653 | static bool warned; | |
654 | ||
655 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
656 | if (compat_apic_id_mode) { | |
b1c12027 | 657 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { |
54a40293 EH |
658 | error_report("APIC IDs set in compatibility mode, " |
659 | "CPU topology won't match the configuration"); | |
660 | warned = true; | |
661 | } | |
662 | return cpu_index; | |
663 | } else { | |
664 | return correct_id; | |
665 | } | |
666 | } | |
667 | ||
1d934e89 EH |
668 | /* Calculates the limit to CPU APIC ID values |
669 | * | |
670 | * This function returns the limit for the APIC ID value, so that all | |
671 | * CPU APIC IDs are < pc_apic_id_limit(). | |
672 | * | |
673 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
674 | */ | |
675 | static unsigned int pc_apic_id_limit(unsigned int max_cpus) | |
676 | { | |
677 | return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
678 | } | |
679 | ||
a88b362c | 680 | static FWCfgState *bochs_bios_init(void) |
80cabfad | 681 | { |
a88b362c | 682 | FWCfgState *fw_cfg; |
c97294ec GS |
683 | uint8_t *smbios_tables, *smbios_anchor; |
684 | size_t smbios_tables_len, smbios_anchor_len; | |
11c2fd3e AL |
685 | uint64_t *numa_fw_cfg; |
686 | int i, j; | |
1d934e89 | 687 | unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); |
3cce6243 | 688 | |
66708822 | 689 | fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); |
1d934e89 EH |
690 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
691 | * | |
692 | * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug | |
693 | * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC | |
694 | * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the | |
695 | * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS | |
696 | * may see". | |
697 | * | |
698 | * So, this means we must not use max_cpus, here, but the maximum possible | |
699 | * APIC ID value, plus one. | |
700 | * | |
701 | * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is | |
702 | * the APIC ID, not the "CPU index" | |
703 | */ | |
704 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); | |
3cce6243 | 705 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 706 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
707 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
708 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 709 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 | 710 | |
c97294ec GS |
711 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); |
712 | if (smbios_tables) { | |
b6f6e3d3 | 713 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
c97294ec GS |
714 | smbios_tables, smbios_tables_len); |
715 | } | |
716 | ||
717 | smbios_get_tables(&smbios_tables, &smbios_tables_len, | |
718 | &smbios_anchor, &smbios_anchor_len); | |
719 | if (smbios_anchor) { | |
720 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
721 | smbios_tables, smbios_tables_len); | |
722 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
723 | smbios_anchor, smbios_anchor_len); | |
724 | } | |
725 | ||
089da572 | 726 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
7d67110f GH |
727 | &e820_reserve, sizeof(e820_reserve)); |
728 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
729 | sizeof(struct e820_entry) * e820_entries); | |
11c2fd3e | 730 | |
089da572 | 731 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
732 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
733 | * of nodes, one word for each VCPU->node and one word for each node to | |
734 | * hold the amount of memory. | |
735 | */ | |
1d934e89 | 736 | numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); |
11c2fd3e | 737 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 738 | for (i = 0; i < max_cpus; i++) { |
1d934e89 EH |
739 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); |
740 | assert(apic_id < apic_id_limit); | |
11c2fd3e | 741 | for (j = 0; j < nb_numa_nodes; j++) { |
8c85901e | 742 | if (test_bit(i, numa_info[j].node_cpu)) { |
1d934e89 | 743 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); |
11c2fd3e AL |
744 | break; |
745 | } | |
746 | } | |
747 | } | |
748 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 749 | numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); |
11c2fd3e | 750 | } |
089da572 | 751 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
1d934e89 EH |
752 | (1 + apic_id_limit + nb_numa_nodes) * |
753 | sizeof(*numa_fw_cfg)); | |
bf483392 AG |
754 | |
755 | return fw_cfg; | |
80cabfad FB |
756 | } |
757 | ||
642a4f96 TS |
758 | static long get_file_size(FILE *f) |
759 | { | |
760 | long where, size; | |
761 | ||
762 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
763 | ||
764 | where = ftell(f); | |
765 | fseek(f, 0, SEEK_END); | |
766 | size = ftell(f); | |
767 | fseek(f, where, SEEK_SET); | |
768 | ||
769 | return size; | |
770 | } | |
771 | ||
a88b362c | 772 | static void load_linux(FWCfgState *fw_cfg, |
4fc9af53 | 773 | const char *kernel_filename, |
0f9d76e5 LG |
774 | const char *initrd_filename, |
775 | const char *kernel_cmdline, | |
a8170e5e | 776 | hwaddr max_ram_size) |
642a4f96 TS |
777 | { |
778 | uint16_t protocol; | |
5cea8590 | 779 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 780 | uint32_t initrd_max; |
57a46d05 | 781 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 782 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 783 | FILE *f; |
bf4e5d92 | 784 | char *vmode; |
642a4f96 TS |
785 | |
786 | /* Align to 16 bytes as a paranoia measure */ | |
787 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
788 | ||
789 | /* load the kernel header */ | |
790 | f = fopen(kernel_filename, "rb"); | |
791 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 LG |
792 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
793 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
794 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
795 | kernel_filename, strerror(errno)); | |
796 | exit(1); | |
642a4f96 TS |
797 | } |
798 | ||
799 | /* kernel protocol version */ | |
bc4edd79 | 800 | #if 0 |
642a4f96 | 801 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 802 | #endif |
0f9d76e5 LG |
803 | if (ldl_p(header+0x202) == 0x53726448) { |
804 | protocol = lduw_p(header+0x206); | |
805 | } else { | |
806 | /* This looks like a multiboot kernel. If it is, let's stop | |
807 | treating it like a Linux kernel. */ | |
52001445 | 808 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 809 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 810 | return; |
0f9d76e5 LG |
811 | } |
812 | protocol = 0; | |
f16408df | 813 | } |
642a4f96 TS |
814 | |
815 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 LG |
816 | /* Low kernel */ |
817 | real_addr = 0x90000; | |
818 | cmdline_addr = 0x9a000 - cmdline_size; | |
819 | prot_addr = 0x10000; | |
642a4f96 | 820 | } else if (protocol < 0x202) { |
0f9d76e5 LG |
821 | /* High but ancient kernel */ |
822 | real_addr = 0x90000; | |
823 | cmdline_addr = 0x9a000 - cmdline_size; | |
824 | prot_addr = 0x100000; | |
642a4f96 | 825 | } else { |
0f9d76e5 LG |
826 | /* High and recent kernel */ |
827 | real_addr = 0x10000; | |
828 | cmdline_addr = 0x20000; | |
829 | prot_addr = 0x100000; | |
642a4f96 TS |
830 | } |
831 | ||
bc4edd79 | 832 | #if 0 |
642a4f96 | 833 | fprintf(stderr, |
0f9d76e5 LG |
834 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
835 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
836 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
837 | real_addr, | |
838 | cmdline_addr, | |
839 | prot_addr); | |
bc4edd79 | 840 | #endif |
642a4f96 TS |
841 | |
842 | /* highest address for loading the initrd */ | |
0f9d76e5 LG |
843 | if (protocol >= 0x203) { |
844 | initrd_max = ldl_p(header+0x22c); | |
845 | } else { | |
846 | initrd_max = 0x37ffffff; | |
847 | } | |
642a4f96 | 848 | |
927766c7 MT |
849 | if (initrd_max >= max_ram_size - acpi_data_size) { |
850 | initrd_max = max_ram_size - acpi_data_size - 1; | |
851 | } | |
642a4f96 | 852 | |
57a46d05 AG |
853 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
854 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 855 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
856 | |
857 | if (protocol >= 0x202) { | |
0f9d76e5 | 858 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 859 | } else { |
0f9d76e5 LG |
860 | stw_p(header+0x20, 0xA33F); |
861 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
862 | } |
863 | ||
bf4e5d92 PT |
864 | /* handle vga= parameter */ |
865 | vmode = strstr(kernel_cmdline, "vga="); | |
866 | if (vmode) { | |
867 | unsigned int video_mode; | |
868 | /* skip "vga=" */ | |
869 | vmode += 4; | |
870 | if (!strncmp(vmode, "normal", 6)) { | |
871 | video_mode = 0xffff; | |
872 | } else if (!strncmp(vmode, "ext", 3)) { | |
873 | video_mode = 0xfffe; | |
874 | } else if (!strncmp(vmode, "ask", 3)) { | |
875 | video_mode = 0xfffd; | |
876 | } else { | |
877 | video_mode = strtol(vmode, NULL, 0); | |
878 | } | |
879 | stw_p(header+0x1fa, video_mode); | |
880 | } | |
881 | ||
642a4f96 | 882 | /* loader type */ |
5cbdb3a3 | 883 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
884 | If this code is substantially changed, you may want to consider |
885 | incrementing the revision. */ | |
0f9d76e5 LG |
886 | if (protocol >= 0x200) { |
887 | header[0x210] = 0xB0; | |
888 | } | |
642a4f96 TS |
889 | /* heap */ |
890 | if (protocol >= 0x201) { | |
0f9d76e5 LG |
891 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
892 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
893 | } |
894 | ||
895 | /* load initrd */ | |
896 | if (initrd_filename) { | |
0f9d76e5 LG |
897 | if (protocol < 0x200) { |
898 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
899 | exit(1); | |
900 | } | |
642a4f96 | 901 | |
0f9d76e5 | 902 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 | 903 | if (initrd_size < 0) { |
7454e51d MT |
904 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", |
905 | initrd_filename, strerror(errno)); | |
d6fa4b77 MK |
906 | exit(1); |
907 | } | |
908 | ||
45a50b16 | 909 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 910 | |
7267c094 | 911 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
912 | load_image(initrd_filename, initrd_data); |
913 | ||
914 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
915 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
916 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 917 | |
0f9d76e5 LG |
918 | stl_p(header+0x218, initrd_addr); |
919 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
920 | } |
921 | ||
45a50b16 | 922 | /* load kernel and setup */ |
642a4f96 | 923 | setup_size = header[0x1f1]; |
0f9d76e5 LG |
924 | if (setup_size == 0) { |
925 | setup_size = 4; | |
926 | } | |
642a4f96 | 927 | setup_size = (setup_size+1)*512; |
45a50b16 | 928 | kernel_size -= setup_size; |
642a4f96 | 929 | |
7267c094 AL |
930 | setup = g_malloc(setup_size); |
931 | kernel = g_malloc(kernel_size); | |
45a50b16 | 932 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
933 | if (fread(setup, 1, setup_size, f) != setup_size) { |
934 | fprintf(stderr, "fread() failed\n"); | |
935 | exit(1); | |
936 | } | |
937 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
938 | fprintf(stderr, "fread() failed\n"); | |
939 | exit(1); | |
940 | } | |
642a4f96 | 941 | fclose(f); |
45a50b16 | 942 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
943 | |
944 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
945 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
946 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
947 | ||
948 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
949 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
950 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
951 | ||
2e55e842 GN |
952 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
953 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 954 | nb_option_roms++; |
642a4f96 TS |
955 | } |
956 | ||
b41a2cd1 FB |
957 | #define NE2000_NB_MAX 6 |
958 | ||
675d6f82 BS |
959 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
960 | 0x280, 0x380 }; | |
961 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 962 | |
48a18b3c | 963 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
964 | { |
965 | static int nb_ne2k = 0; | |
966 | ||
967 | if (nb_ne2k == NE2000_NB_MAX) | |
968 | return; | |
48a18b3c | 969 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 970 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
971 | nb_ne2k++; |
972 | } | |
973 | ||
92a16d7a | 974 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 975 | { |
4917cf44 AF |
976 | if (current_cpu) { |
977 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 978 | return cpu->apic_state; |
0e26b7b8 BS |
979 | } else { |
980 | return NULL; | |
981 | } | |
982 | } | |
983 | ||
845773ab | 984 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 985 | { |
c3affe56 | 986 | X86CPU *cpu = opaque; |
53b67b30 BS |
987 | |
988 | if (level) { | |
c3affe56 | 989 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
990 | } |
991 | } | |
992 | ||
62fc403f IM |
993 | static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, |
994 | DeviceState *icc_bridge, Error **errp) | |
31050930 | 995 | { |
e1570d00 | 996 | X86CPU *cpu = NULL; |
31050930 IM |
997 | Error *local_err = NULL; |
998 | ||
e1570d00 EH |
999 | if (icc_bridge == NULL) { |
1000 | error_setg(&local_err, "Invalid icc-bridge value"); | |
1001 | goto out; | |
1002 | } | |
1003 | ||
1004 | cpu = cpu_x86_create(cpu_model, &local_err); | |
cd7b87ff | 1005 | if (local_err != NULL) { |
e1570d00 | 1006 | goto out; |
31050930 IM |
1007 | } |
1008 | ||
e1570d00 EH |
1009 | qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); |
1010 | object_unref(OBJECT(cpu)); | |
1011 | ||
31050930 IM |
1012 | object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); |
1013 | object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); | |
1014 | ||
e1570d00 | 1015 | out: |
31050930 | 1016 | if (local_err) { |
31050930 | 1017 | error_propagate(errp, local_err); |
cd7b87ff AF |
1018 | object_unref(OBJECT(cpu)); |
1019 | cpu = NULL; | |
31050930 IM |
1020 | } |
1021 | return cpu; | |
1022 | } | |
1023 | ||
c649983b IM |
1024 | static const char *current_cpu_model; |
1025 | ||
1026 | void pc_hot_add_cpu(const int64_t id, Error **errp) | |
1027 | { | |
1028 | DeviceState *icc_bridge; | |
1029 | int64_t apic_id = x86_cpu_apic_id_from_index(id); | |
1030 | ||
8de433cb IM |
1031 | if (id < 0) { |
1032 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1033 | return; | |
1034 | } | |
1035 | ||
c649983b IM |
1036 | if (cpu_exists(apic_id)) { |
1037 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1038 | ", it already exists", id); | |
1039 | return; | |
1040 | } | |
1041 | ||
1042 | if (id >= max_cpus) { | |
1043 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1044 | ", max allowed: %d", id, max_cpus - 1); | |
1045 | return; | |
1046 | } | |
1047 | ||
5ff020b7 EH |
1048 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1049 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1050 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1051 | id, apic_id); | |
1052 | return; | |
1053 | } | |
1054 | ||
c649983b IM |
1055 | icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", |
1056 | TYPE_ICC_BRIDGE, NULL)); | |
1057 | pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); | |
1058 | } | |
1059 | ||
62fc403f | 1060 | void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) |
70166477 IY |
1061 | { |
1062 | int i; | |
53a89e26 | 1063 | X86CPU *cpu = NULL; |
31050930 | 1064 | Error *error = NULL; |
f03bd716 | 1065 | unsigned long apic_id_limit; |
70166477 IY |
1066 | |
1067 | /* init CPUs */ | |
1068 | if (cpu_model == NULL) { | |
1069 | #ifdef TARGET_X86_64 | |
1070 | cpu_model = "qemu64"; | |
1071 | #else | |
1072 | cpu_model = "qemu32"; | |
1073 | #endif | |
1074 | } | |
c649983b | 1075 | current_cpu_model = cpu_model; |
70166477 | 1076 | |
f03bd716 EH |
1077 | apic_id_limit = pc_apic_id_limit(max_cpus); |
1078 | if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { | |
1079 | error_report("max_cpus is too large. APIC ID of last CPU is %lu", | |
1080 | apic_id_limit - 1); | |
1081 | exit(1); | |
1082 | } | |
1083 | ||
bdeec802 | 1084 | for (i = 0; i < smp_cpus; i++) { |
53a89e26 IM |
1085 | cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), |
1086 | icc_bridge, &error); | |
31050930 | 1087 | if (error) { |
565f65d2 | 1088 | error_report_err(error); |
bdeec802 IM |
1089 | exit(1); |
1090 | } | |
70166477 | 1091 | } |
53a89e26 IM |
1092 | |
1093 | /* map APIC MMIO area if CPU has APIC */ | |
02e51483 | 1094 | if (cpu && cpu->apic_state) { |
53a89e26 IM |
1095 | /* XXX: what if the base changes? */ |
1096 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, | |
1097 | APIC_DEFAULT_ADDRESS, 0x1000); | |
1098 | } | |
c97294ec GS |
1099 | |
1100 | /* tell smbios about cpuid version and features */ | |
1101 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
70166477 IY |
1102 | } |
1103 | ||
f8c457b8 MT |
1104 | /* pci-info ROM file. Little endian format */ |
1105 | typedef struct PcRomPciInfo { | |
1106 | uint64_t w32_min; | |
1107 | uint64_t w32_max; | |
1108 | uint64_t w64_min; | |
1109 | uint64_t w64_max; | |
1110 | } PcRomPciInfo; | |
1111 | ||
3459a625 MT |
1112 | typedef struct PcGuestInfoState { |
1113 | PcGuestInfo info; | |
1114 | Notifier machine_done; | |
1115 | } PcGuestInfoState; | |
1116 | ||
1117 | static | |
1118 | void pc_guest_info_machine_done(Notifier *notifier, void *data) | |
1119 | { | |
1120 | PcGuestInfoState *guest_info_state = container_of(notifier, | |
1121 | PcGuestInfoState, | |
1122 | machine_done); | |
72c194f7 | 1123 | acpi_setup(&guest_info_state->info); |
3459a625 MT |
1124 | } |
1125 | ||
1126 | PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, | |
1127 | ram_addr_t above_4g_mem_size) | |
1128 | { | |
1129 | PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); | |
1130 | PcGuestInfo *guest_info = &guest_info_state->info; | |
b20c9bd5 MT |
1131 | int i, j; |
1132 | ||
f30ee8a9 | 1133 | guest_info->ram_size_below_4g = below_4g_mem_size; |
b20c9bd5 MT |
1134 | guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; |
1135 | guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); | |
1136 | guest_info->apic_xrupt_override = kvm_allows_irq0_override(); | |
1137 | guest_info->numa_nodes = nb_numa_nodes; | |
8c85901e | 1138 | guest_info->node_mem = g_malloc0(guest_info->numa_nodes * |
b20c9bd5 | 1139 | sizeof *guest_info->node_mem); |
8c85901e WG |
1140 | for (i = 0; i < nb_numa_nodes; i++) { |
1141 | guest_info->node_mem[i] = numa_info[i].node_mem; | |
1142 | } | |
1143 | ||
b20c9bd5 MT |
1144 | guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * |
1145 | sizeof *guest_info->node_cpu); | |
1146 | ||
1147 | for (i = 0; i < max_cpus; i++) { | |
1148 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); | |
1149 | assert(apic_id < guest_info->apic_id_limit); | |
1150 | for (j = 0; j < nb_numa_nodes; j++) { | |
8c85901e | 1151 | if (test_bit(i, numa_info[j].node_cpu)) { |
b20c9bd5 MT |
1152 | guest_info->node_cpu[apic_id] = j; |
1153 | break; | |
1154 | } | |
1155 | } | |
1156 | } | |
3459a625 | 1157 | |
3459a625 MT |
1158 | guest_info_state->machine_done.notify = pc_guest_info_machine_done; |
1159 | qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); | |
1160 | return guest_info; | |
1161 | } | |
1162 | ||
83d08f26 MT |
1163 | /* setup pci memory address space mapping into system address space */ |
1164 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1165 | MemoryRegion *pci_address_space) | |
39848901 | 1166 | { |
83d08f26 MT |
1167 | /* Set to lower priority than RAM */ |
1168 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1169 | pci_address_space, -1); | |
39848901 IM |
1170 | } |
1171 | ||
f7e4dd6c GH |
1172 | void pc_acpi_init(const char *default_dsdt) |
1173 | { | |
c5a98cf3 | 1174 | char *filename; |
f7e4dd6c GH |
1175 | |
1176 | if (acpi_tables != NULL) { | |
1177 | /* manually set via -acpitable, leave it alone */ | |
1178 | return; | |
1179 | } | |
1180 | ||
1181 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1182 | if (filename == NULL) { | |
1183 | fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); | |
c5a98cf3 | 1184 | } else { |
5bdb59a2 MA |
1185 | QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, |
1186 | &error_abort); | |
c5a98cf3 | 1187 | Error *err = NULL; |
f7e4dd6c | 1188 | |
5bdb59a2 | 1189 | qemu_opt_set(opts, "file", filename, &error_abort); |
0c764a9d | 1190 | |
1a4b2666 | 1191 | acpi_table_add_builtin(opts, &err); |
c5a98cf3 | 1192 | if (err) { |
4a44d85e SA |
1193 | error_report("WARNING: failed to load %s: %s", filename, |
1194 | error_get_pretty(err)); | |
c5a98cf3 LE |
1195 | error_free(err); |
1196 | } | |
c5a98cf3 | 1197 | g_free(filename); |
f7e4dd6c | 1198 | } |
f7e4dd6c GH |
1199 | } |
1200 | ||
b33a5bbf CL |
1201 | FWCfgState *xen_load_linux(const char *kernel_filename, |
1202 | const char *kernel_cmdline, | |
1203 | const char *initrd_filename, | |
1204 | ram_addr_t below_4g_mem_size, | |
1205 | PcGuestInfo *guest_info) | |
1206 | { | |
1207 | int i; | |
1208 | FWCfgState *fw_cfg; | |
1209 | ||
1210 | assert(kernel_filename != NULL); | |
1211 | ||
66708822 | 1212 | fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); |
b33a5bbf CL |
1213 | rom_set_fw(fw_cfg); |
1214 | ||
1215 | load_linux(fw_cfg, kernel_filename, initrd_filename, | |
1216 | kernel_cmdline, below_4g_mem_size); | |
1217 | for (i = 0; i < nb_option_roms; i++) { | |
1218 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
1219 | !strcmp(option_rom[i].name, "multiboot.bin")); | |
1220 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1221 | } | |
1222 | guest_info->fw_cfg = fw_cfg; | |
1223 | return fw_cfg; | |
1224 | } | |
1225 | ||
9521d42b PB |
1226 | FWCfgState *pc_memory_init(MachineState *machine, |
1227 | MemoryRegion *system_memory, | |
a88b362c LE |
1228 | ram_addr_t below_4g_mem_size, |
1229 | ram_addr_t above_4g_mem_size, | |
1230 | MemoryRegion *rom_memory, | |
3459a625 MT |
1231 | MemoryRegion **ram_memory, |
1232 | PcGuestInfo *guest_info) | |
80cabfad | 1233 | { |
cbc5b5f3 JJ |
1234 | int linux_boot, i; |
1235 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1236 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1237 | FWCfgState *fw_cfg; |
619d11e4 | 1238 | PCMachineState *pcms = PC_MACHINE(machine); |
d592d303 | 1239 | |
9521d42b PB |
1240 | assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); |
1241 | ||
1242 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1243 | |
00cb2a99 | 1244 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1245 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1246 | * with older qemus that used qemu_ram_alloc(). |
1247 | */ | |
7267c094 | 1248 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1249 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1250 | machine->ram_size); | |
ae0a5466 | 1251 | *ram_memory = ram; |
7267c094 | 1252 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1253 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
00cb2a99 AK |
1254 | 0, below_4g_mem_size); |
1255 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
7db16f24 | 1256 | e820_add_entry(0, below_4g_mem_size, E820_RAM); |
bbe80adf | 1257 | if (above_4g_mem_size > 0) { |
7267c094 | 1258 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1259 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
00cb2a99 AK |
1260 | below_4g_mem_size, above_4g_mem_size); |
1261 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1262 | ram_above_4g); | |
0624c7f9 | 1263 | e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); |
bbe80adf | 1264 | } |
82b36dc3 | 1265 | |
ca8336f3 IM |
1266 | if (!guest_info->has_reserved_memory && |
1267 | (machine->ram_slots || | |
9521d42b | 1268 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1269 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1270 | ||
1271 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1272 | mc->name); | |
1273 | exit(EXIT_FAILURE); | |
1274 | } | |
1275 | ||
619d11e4 | 1276 | /* initialize hotplug memory address space */ |
de268e13 | 1277 | if (guest_info->has_reserved_memory && |
9521d42b | 1278 | (machine->ram_size < machine->maxram_size)) { |
619d11e4 | 1279 | ram_addr_t hotplug_mem_size = |
9521d42b | 1280 | machine->maxram_size - machine->ram_size; |
619d11e4 | 1281 | |
a0cc8856 IM |
1282 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1283 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1284 | machine->ram_slots); | |
1285 | exit(EXIT_FAILURE); | |
1286 | } | |
1287 | ||
f2c38522 PK |
1288 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1289 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1290 | error_report("maximum memory size must by aligned to multiple of " | |
1291 | "%d bytes", TARGET_PAGE_SIZE); | |
1292 | exit(EXIT_FAILURE); | |
1293 | } | |
1294 | ||
619d11e4 IM |
1295 | pcms->hotplug_memory_base = |
1296 | ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); | |
1297 | ||
085f8e88 IM |
1298 | if (pcms->enforce_aligned_dimm) { |
1299 | /* size hotplug region assuming 1G page max alignment per slot */ | |
1300 | hotplug_mem_size += (1ULL << 30) * machine->ram_slots; | |
1301 | } | |
1302 | ||
619d11e4 IM |
1303 | if ((pcms->hotplug_memory_base + hotplug_mem_size) < |
1304 | hotplug_mem_size) { | |
1305 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1306 | machine->maxram_size); | |
1307 | exit(EXIT_FAILURE); | |
1308 | } | |
1309 | ||
1310 | memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), | |
1311 | "hotplug-memory", hotplug_mem_size); | |
1312 | memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, | |
1313 | &pcms->hotplug_memory); | |
1314 | } | |
cbc5b5f3 JJ |
1315 | |
1316 | /* Initialize PC system firmware */ | |
6dd2a5c9 | 1317 | pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); |
00cb2a99 | 1318 | |
7267c094 | 1319 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
49946538 HT |
1320 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
1321 | &error_abort); | |
c5705a77 | 1322 | vmstate_register_ram_global(option_rom_mr); |
4463aee6 | 1323 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1324 | PC_ROM_MIN_VGA, |
1325 | option_rom_mr, | |
1326 | 1); | |
f753ff16 | 1327 | |
bf483392 | 1328 | fw_cfg = bochs_bios_init(); |
8832cb80 | 1329 | rom_set_fw(fw_cfg); |
1d108d97 | 1330 | |
de268e13 IM |
1331 | if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { |
1332 | uint64_t *val = g_malloc(sizeof(*val)); | |
1333 | *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); | |
1334 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); | |
1335 | } | |
1336 | ||
f753ff16 | 1337 | if (linux_boot) { |
9521d42b PB |
1338 | load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, |
1339 | machine->kernel_cmdline, below_4g_mem_size); | |
f753ff16 PB |
1340 | } |
1341 | ||
1342 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1343 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1344 | } |
3459a625 | 1345 | guest_info->fw_cfg = fw_cfg; |
459ae5ea | 1346 | return fw_cfg; |
3d53f5c3 IY |
1347 | } |
1348 | ||
845773ab IY |
1349 | qemu_irq *pc_allocate_cpu_irq(void) |
1350 | { | |
1351 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
1352 | } | |
1353 | ||
48a18b3c | 1354 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1355 | { |
ad6d45fa AL |
1356 | DeviceState *dev = NULL; |
1357 | ||
16094b75 AJ |
1358 | if (pci_bus) { |
1359 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1360 | dev = pcidev ? &pcidev->qdev : NULL; | |
1361 | } else if (isa_bus) { | |
1362 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1363 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1364 | } |
ad6d45fa | 1365 | return dev; |
765d7908 IY |
1366 | } |
1367 | ||
4556bd8b BS |
1368 | static void cpu_request_exit(void *opaque, int irq, int level) |
1369 | { | |
4917cf44 | 1370 | CPUState *cpu = current_cpu; |
4556bd8b | 1371 | |
4917cf44 AF |
1372 | if (cpu && level) { |
1373 | cpu_exit(cpu); | |
4556bd8b BS |
1374 | } |
1375 | } | |
1376 | ||
258711c6 JG |
1377 | static const MemoryRegionOps ioport80_io_ops = { |
1378 | .write = ioport80_write, | |
c02e1eac | 1379 | .read = ioport80_read, |
258711c6 JG |
1380 | .endianness = DEVICE_NATIVE_ENDIAN, |
1381 | .impl = { | |
1382 | .min_access_size = 1, | |
1383 | .max_access_size = 1, | |
1384 | }, | |
1385 | }; | |
1386 | ||
1387 | static const MemoryRegionOps ioportF0_io_ops = { | |
1388 | .write = ioportF0_write, | |
c02e1eac | 1389 | .read = ioportF0_read, |
258711c6 JG |
1390 | .endianness = DEVICE_NATIVE_ENDIAN, |
1391 | .impl = { | |
1392 | .min_access_size = 1, | |
1393 | .max_access_size = 1, | |
1394 | }, | |
1395 | }; | |
1396 | ||
48a18b3c | 1397 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1398 | ISADevice **rtc_state, |
34d4260e | 1399 | ISADevice **floppy, |
7a10ef51 LPF |
1400 | bool no_vmport, |
1401 | uint32 hpet_irqs) | |
ffe513da IY |
1402 | { |
1403 | int i; | |
1404 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1405 | DeviceState *hpet = NULL; |
1406 | int pit_isa_irq = 0; | |
1407 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1408 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1409 | qemu_irq *a20_line; |
c2d8d311 | 1410 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
4556bd8b | 1411 | qemu_irq *cpu_exit_irq; |
258711c6 JG |
1412 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1413 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1414 | |
2c9b15ca | 1415 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1416 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1417 | |
2c9b15ca | 1418 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1419 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1420 | |
5d17c0d2 JK |
1421 | /* |
1422 | * Check if an HPET shall be created. | |
1423 | * | |
1424 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1425 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1426 | */ | |
1427 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1428 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1429 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1430 | if (hpet) { |
7a10ef51 LPF |
1431 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1432 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1433 | * IRQ8 and IRQ2. | |
1434 | */ | |
1435 | uint8_t compat = object_property_get_int(OBJECT(hpet), | |
1436 | HPET_INTCAP, NULL); | |
1437 | if (!compat) { | |
1438 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1439 | } | |
1440 | qdev_init_nofail(hpet); | |
1441 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1442 | ||
b881fbe9 | 1443 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1444 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1445 | } |
ce967e2f JK |
1446 | pit_isa_irq = -1; |
1447 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1448 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1449 | } |
ffe513da | 1450 | } |
48a18b3c | 1451 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1452 | |
1453 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1454 | ||
c2d8d311 SS |
1455 | if (!xen_enabled()) { |
1456 | if (kvm_irqchip_in_kernel()) { | |
1457 | pit = kvm_pit_init(isa_bus, 0x40); | |
1458 | } else { | |
1459 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1460 | } | |
1461 | if (hpet) { | |
1462 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1463 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1464 | } |
1465 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1466 | } |
ffe513da | 1467 | |
b6607a1a | 1468 | serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); |
07dc7880 | 1469 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
ffe513da | 1470 | |
182735ef | 1471 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1472 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1473 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1474 | if (!no_vmport) { |
48a18b3c HP |
1475 | vmport_init(isa_bus); |
1476 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1477 | } else { |
1478 | vmmouse = NULL; | |
1479 | } | |
86d86414 | 1480 | if (vmmouse) { |
4a17cc4f AF |
1481 | DeviceState *dev = DEVICE(vmmouse); |
1482 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1483 | qdev_init_nofail(dev); | |
86d86414 | 1484 | } |
48a18b3c | 1485 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1486 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1487 | |
4556bd8b BS |
1488 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1489 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1490 | |
1491 | for(i = 0; i < MAX_FD; i++) { | |
1492 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1493 | } | |
48a18b3c | 1494 | *floppy = fdctrl_init_isa(isa_bus, fd); |
ffe513da IY |
1495 | } |
1496 | ||
9011a1a7 IY |
1497 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1498 | { | |
1499 | int i; | |
1500 | ||
1501 | for (i = 0; i < nb_nics; i++) { | |
1502 | NICInfo *nd = &nd_table[i]; | |
1503 | ||
1504 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1505 | pc_init_ne2k_isa(isa_bus, nd); | |
1506 | } else { | |
29b358f9 | 1507 | pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); |
9011a1a7 IY |
1508 | } |
1509 | } | |
1510 | } | |
1511 | ||
845773ab | 1512 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1513 | { |
1514 | int max_bus; | |
1515 | int bus; | |
1516 | ||
1517 | max_bus = drive_get_max_bus(IF_SCSI); | |
1518 | for (bus = 0; bus <= max_bus; bus++) { | |
1519 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1520 | } | |
1521 | } | |
a39e3564 JB |
1522 | |
1523 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1524 | { | |
1525 | DeviceState *dev; | |
1526 | SysBusDevice *d; | |
1527 | unsigned int i; | |
1528 | ||
1529 | if (kvm_irqchip_in_kernel()) { | |
1530 | dev = qdev_create(NULL, "kvm-ioapic"); | |
1531 | } else { | |
1532 | dev = qdev_create(NULL, "ioapic"); | |
1533 | } | |
1534 | if (parent_name) { | |
1535 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1536 | "ioapic", OBJECT(dev), NULL); | |
1537 | } | |
1538 | qdev_init_nofail(dev); | |
1356b98d | 1539 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1540 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1541 | |
1542 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1543 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1544 | } | |
1545 | } | |
d5747cac IM |
1546 | |
1547 | static void pc_generic_machine_class_init(ObjectClass *oc, void *data) | |
1548 | { | |
1549 | MachineClass *mc = MACHINE_CLASS(oc); | |
1550 | QEMUMachine *qm = data; | |
1551 | ||
2709f263 | 1552 | mc->family = qm->family; |
d5747cac IM |
1553 | mc->name = qm->name; |
1554 | mc->alias = qm->alias; | |
1555 | mc->desc = qm->desc; | |
1556 | mc->init = qm->init; | |
1557 | mc->reset = qm->reset; | |
1558 | mc->hot_add_cpu = qm->hot_add_cpu; | |
1559 | mc->kvm_type = qm->kvm_type; | |
1560 | mc->block_default_type = qm->block_default_type; | |
16026518 | 1561 | mc->units_per_default_bus = qm->units_per_default_bus; |
d5747cac IM |
1562 | mc->max_cpus = qm->max_cpus; |
1563 | mc->no_serial = qm->no_serial; | |
1564 | mc->no_parallel = qm->no_parallel; | |
1565 | mc->use_virtcon = qm->use_virtcon; | |
1566 | mc->use_sclp = qm->use_sclp; | |
1567 | mc->no_floppy = qm->no_floppy; | |
1568 | mc->no_cdrom = qm->no_cdrom; | |
1569 | mc->no_sdcard = qm->no_sdcard; | |
1570 | mc->is_default = qm->is_default; | |
1571 | mc->default_machine_opts = qm->default_machine_opts; | |
1572 | mc->default_boot_order = qm->default_boot_order; | |
6f00494a | 1573 | mc->default_display = qm->default_display; |
d5747cac IM |
1574 | mc->compat_props = qm->compat_props; |
1575 | mc->hw_version = qm->hw_version; | |
1576 | } | |
1577 | ||
1578 | void qemu_register_pc_machine(QEMUMachine *m) | |
1579 | { | |
1580 | char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); | |
1581 | TypeInfo ti = { | |
1582 | .name = name, | |
1583 | .parent = TYPE_PC_MACHINE, | |
1584 | .class_init = pc_generic_machine_class_init, | |
1585 | .class_data = (void *)m, | |
1586 | }; | |
1587 | ||
1588 | type_register(&ti); | |
1589 | g_free(name); | |
1590 | } | |
1591 | ||
95bee274 IM |
1592 | static void pc_dimm_plug(HotplugHandler *hotplug_dev, |
1593 | DeviceState *dev, Error **errp) | |
1594 | { | |
0cd03d89 | 1595 | int slot; |
3fbcdc27 | 1596 | HotplugHandlerClass *hhc; |
95bee274 IM |
1597 | Error *local_err = NULL; |
1598 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
0cd03d89 | 1599 | MachineState *machine = MACHINE(hotplug_dev); |
95bee274 IM |
1600 | PCDIMMDevice *dimm = PC_DIMM(dev); |
1601 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1602 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
b03541fa | 1603 | uint64_t existing_dimms_capacity = 0; |
92a37a04 | 1604 | uint64_t align = TARGET_PAGE_SIZE; |
34dde136 IM |
1605 | uint64_t addr; |
1606 | ||
1607 | addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); | |
95bee274 IM |
1608 | if (local_err) { |
1609 | goto out; | |
1610 | } | |
1611 | ||
91aa70ab IM |
1612 | if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { |
1613 | align = memory_region_get_alignment(mr); | |
1614 | } | |
1615 | ||
0b312571 IM |
1616 | addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, |
1617 | memory_region_size(&pcms->hotplug_memory), | |
92a37a04 | 1618 | !addr ? NULL : &addr, align, |
0b312571 IM |
1619 | memory_region_size(mr), &local_err); |
1620 | if (local_err) { | |
1621 | goto out; | |
1622 | } | |
0cd03d89 | 1623 | |
37153450 BR |
1624 | existing_dimms_capacity = pc_existing_dimms_capacity(&local_err); |
1625 | if (local_err) { | |
b03541fa IM |
1626 | goto out; |
1627 | } | |
1628 | ||
1629 | if (existing_dimms_capacity + memory_region_size(mr) > | |
1630 | machine->maxram_size - machine->ram_size) { | |
1631 | error_setg(&local_err, "not enough space, currently 0x%" PRIx64 | |
759048ac BR |
1632 | " in use of total hot pluggable 0x" RAM_ADDR_FMT, |
1633 | existing_dimms_capacity, | |
1634 | machine->maxram_size - machine->ram_size); | |
b03541fa IM |
1635 | goto out; |
1636 | } | |
1637 | ||
0b312571 | 1638 | object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); |
0cd03d89 IM |
1639 | if (local_err) { |
1640 | goto out; | |
1641 | } | |
2e1ac493 | 1642 | trace_mhp_pc_dimm_assigned_address(addr); |
0cd03d89 IM |
1643 | |
1644 | slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); | |
1645 | if (local_err) { | |
1646 | goto out; | |
1647 | } | |
1648 | ||
1649 | slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, | |
1650 | machine->ram_slots, &local_err); | |
1651 | if (local_err) { | |
1652 | goto out; | |
1653 | } | |
1654 | object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); | |
1655 | if (local_err) { | |
1656 | goto out; | |
1657 | } | |
2e1ac493 | 1658 | trace_mhp_pc_dimm_assigned_slot(slot); |
0b312571 | 1659 | |
3fbcdc27 IM |
1660 | if (!pcms->acpi_dev) { |
1661 | error_setg(&local_err, | |
1662 | "memory hotplug is not enabled: missing acpi device"); | |
1663 | goto out; | |
1664 | } | |
1665 | ||
b8865591 IM |
1666 | if (kvm_enabled() && !kvm_has_free_slot(machine)) { |
1667 | error_setg(&local_err, "hypervisor has no free memory slots left"); | |
1668 | goto out; | |
1669 | } | |
1670 | ||
95bee274 IM |
1671 | memory_region_add_subregion(&pcms->hotplug_memory, |
1672 | addr - pcms->hotplug_memory_base, mr); | |
1673 | vmstate_register_ram(mr, dev); | |
3fbcdc27 IM |
1674 | |
1675 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1676 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
95bee274 IM |
1677 | out: |
1678 | error_propagate(errp, local_err); | |
1679 | } | |
1680 | ||
5279569e GZ |
1681 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1682 | DeviceState *dev, Error **errp) | |
1683 | { | |
1684 | HotplugHandlerClass *hhc; | |
1685 | Error *local_err = NULL; | |
1686 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1687 | ||
1688 | if (!dev->hotplugged) { | |
1689 | goto out; | |
1690 | } | |
1691 | ||
1692 | if (!pcms->acpi_dev) { | |
1693 | error_setg(&local_err, | |
1694 | "cpu hotplug is not enabled: missing acpi device"); | |
1695 | goto out; | |
1696 | } | |
1697 | ||
1698 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1699 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2d996150 GZ |
1700 | if (local_err) { |
1701 | goto out; | |
1702 | } | |
1703 | ||
1704 | /* increment the number of CPUs */ | |
1705 | rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); | |
5279569e GZ |
1706 | out: |
1707 | error_propagate(errp, local_err); | |
1708 | } | |
1709 | ||
95bee274 IM |
1710 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1711 | DeviceState *dev, Error **errp) | |
1712 | { | |
1713 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1714 | pc_dimm_plug(hotplug_dev, dev, errp); | |
5279569e GZ |
1715 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1716 | pc_cpu_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1717 | } |
1718 | } | |
1719 | ||
d9c5c5b8 TC |
1720 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1721 | DeviceState *dev, Error **errp) | |
1722 | { | |
1723 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1724 | " type: %s", object_get_typename(OBJECT(dev))); | |
1725 | } | |
1726 | ||
232391c1 TC |
1727 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1728 | DeviceState *dev, Error **errp) | |
1729 | { | |
1730 | error_setg(errp, "acpi: device unplug for not supported device" | |
1731 | " type: %s", object_get_typename(OBJECT(dev))); | |
1732 | } | |
1733 | ||
95bee274 IM |
1734 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, |
1735 | DeviceState *dev) | |
1736 | { | |
1737 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); | |
1738 | ||
5279569e GZ |
1739 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
1740 | object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
95bee274 IM |
1741 | return HOTPLUG_HANDLER(machine); |
1742 | } | |
1743 | ||
1744 | return pcmc->get_hotplug_handler ? | |
1745 | pcmc->get_hotplug_handler(machine, dev) : NULL; | |
1746 | } | |
1747 | ||
bf1e8939 IM |
1748 | static void |
1749 | pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, | |
1750 | const char *name, Error **errp) | |
1751 | { | |
1752 | PCMachineState *pcms = PC_MACHINE(obj); | |
1753 | int64_t value = memory_region_size(&pcms->hotplug_memory); | |
1754 | ||
1755 | visit_type_int(v, &value, name, errp); | |
1756 | } | |
1757 | ||
c87b1520 DS |
1758 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
1759 | void *opaque, const char *name, | |
1760 | Error **errp) | |
1761 | { | |
1762 | PCMachineState *pcms = PC_MACHINE(obj); | |
1763 | uint64_t value = pcms->max_ram_below_4g; | |
1764 | ||
1765 | visit_type_size(v, &value, name, errp); | |
1766 | } | |
1767 | ||
1768 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
1769 | void *opaque, const char *name, | |
1770 | Error **errp) | |
1771 | { | |
1772 | PCMachineState *pcms = PC_MACHINE(obj); | |
1773 | Error *error = NULL; | |
1774 | uint64_t value; | |
1775 | ||
1776 | visit_type_size(v, &value, name, &error); | |
1777 | if (error) { | |
1778 | error_propagate(errp, error); | |
1779 | return; | |
1780 | } | |
1781 | if (value > (1ULL << 32)) { | |
1782 | error_set(&error, ERROR_CLASS_GENERIC_ERROR, | |
1783 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
1784 | "' expects size less than or equal to 4G", value); | |
1785 | error_propagate(errp, error); | |
1786 | return; | |
1787 | } | |
1788 | ||
1789 | if (value < (1ULL << 20)) { | |
1790 | error_report("Warning: small max_ram_below_4g(%"PRIu64 | |
1791 | ") less than 1M. BIOS may not work..", | |
1792 | value); | |
1793 | } | |
1794 | ||
1795 | pcms->max_ram_below_4g = value; | |
1796 | } | |
1797 | ||
d1048bef DS |
1798 | static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, |
1799 | const char *name, Error **errp) | |
9b23cfb7 DDAG |
1800 | { |
1801 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 1802 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 1803 | |
d1048bef | 1804 | visit_type_OnOffAuto(v, &vmport, name, errp); |
9b23cfb7 DDAG |
1805 | } |
1806 | ||
d1048bef DS |
1807 | static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, |
1808 | const char *name, Error **errp) | |
9b23cfb7 DDAG |
1809 | { |
1810 | PCMachineState *pcms = PC_MACHINE(obj); | |
1811 | ||
d1048bef | 1812 | visit_type_OnOffAuto(v, &pcms->vmport, name, errp); |
9b23cfb7 DDAG |
1813 | } |
1814 | ||
91aa70ab IM |
1815 | static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) |
1816 | { | |
1817 | PCMachineState *pcms = PC_MACHINE(obj); | |
1818 | ||
1819 | return pcms->enforce_aligned_dimm; | |
1820 | } | |
1821 | ||
bf1e8939 IM |
1822 | static void pc_machine_initfn(Object *obj) |
1823 | { | |
c87b1520 DS |
1824 | PCMachineState *pcms = PC_MACHINE(obj); |
1825 | ||
bf1e8939 IM |
1826 | object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", |
1827 | pc_machine_get_hotplug_memory_region_size, | |
1828 | NULL, NULL, NULL, NULL); | |
49d2e648 | 1829 | |
c87b1520 DS |
1830 | pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ |
1831 | object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
1832 | pc_machine_get_max_ram_below_4g, | |
1833 | pc_machine_set_max_ram_below_4g, | |
1834 | NULL, NULL, NULL); | |
49d2e648 MA |
1835 | object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, |
1836 | "Maximum ram below the 4G boundary (32bit boundary)", | |
1837 | NULL); | |
91aa70ab | 1838 | |
d1048bef DS |
1839 | pcms->vmport = ON_OFF_AUTO_AUTO; |
1840 | object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", | |
1841 | pc_machine_get_vmport, | |
1842 | pc_machine_set_vmport, | |
1843 | NULL, NULL, NULL); | |
49d2e648 MA |
1844 | object_property_set_description(obj, PC_MACHINE_VMPORT, |
1845 | "Enable vmport (pc & q35)", | |
1846 | NULL); | |
91aa70ab IM |
1847 | |
1848 | pcms->enforce_aligned_dimm = true; | |
1849 | object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, | |
1850 | pc_machine_get_aligned_dimm, | |
1851 | NULL, NULL); | |
bf1e8939 IM |
1852 | } |
1853 | ||
95bee274 IM |
1854 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
1855 | { | |
1856 | MachineClass *mc = MACHINE_CLASS(oc); | |
1857 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
1858 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1859 | ||
1860 | pcmc->get_hotplug_handler = mc->get_hotplug_handler; | |
1861 | mc->get_hotplug_handler = pc_get_hotpug_handler; | |
1862 | hc->plug = pc_machine_device_plug_cb; | |
d9c5c5b8 | 1863 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 1864 | hc->unplug = pc_machine_device_unplug_cb; |
95bee274 IM |
1865 | } |
1866 | ||
d5747cac IM |
1867 | static const TypeInfo pc_machine_info = { |
1868 | .name = TYPE_PC_MACHINE, | |
1869 | .parent = TYPE_MACHINE, | |
1870 | .abstract = true, | |
1871 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 1872 | .instance_init = pc_machine_initfn, |
d5747cac | 1873 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
1874 | .class_init = pc_machine_class_init, |
1875 | .interfaces = (InterfaceInfo[]) { | |
1876 | { TYPE_HOTPLUG_HANDLER }, | |
1877 | { } | |
1878 | }, | |
d5747cac IM |
1879 | }; |
1880 | ||
1881 | static void pc_machine_register_types(void) | |
1882 | { | |
1883 | type_register_static(&pc_machine_info); | |
1884 | } | |
1885 | ||
1886 | type_init(pc_machine_register_types) |