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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
0d09e41a PB |
25 | #include "hw/i386/pc.h" |
26 | #include "hw/char/serial.h" | |
27 | #include "hw/i386/apic.h" | |
28 | #include "hw/block/fdc.h" | |
83c9f4ca PB |
29 | #include "hw/ide.h" |
30 | #include "hw/pci/pci.h" | |
83c9089e | 31 | #include "monitor/monitor.h" |
0d09e41a PB |
32 | #include "hw/nvram/fw_cfg.h" |
33 | #include "hw/timer/hpet.h" | |
34 | #include "hw/i386/smbios.h" | |
83c9f4ca | 35 | #include "hw/loader.h" |
ca20cf32 | 36 | #include "elf.h" |
47b43a1f | 37 | #include "multiboot.h" |
0d09e41a PB |
38 | #include "hw/timer/mc146818rtc.h" |
39 | #include "hw/timer/i8254.h" | |
40 | #include "hw/audio/pcspk.h" | |
83c9f4ca PB |
41 | #include "hw/pci/msi.h" |
42 | #include "hw/sysbus.h" | |
9c17d615 PB |
43 | #include "sysemu/sysemu.h" |
44 | #include "sysemu/kvm.h" | |
1d31f66b | 45 | #include "kvm_i386.h" |
0d09e41a | 46 | #include "hw/xen/xen.h" |
9c17d615 | 47 | #include "sysemu/blockdev.h" |
0d09e41a | 48 | #include "hw/block/block.h" |
a19cbfb3 | 49 | #include "ui/qemu-spice.h" |
022c62cb PB |
50 | #include "exec/memory.h" |
51 | #include "exec/address-spaces.h" | |
9c17d615 | 52 | #include "sysemu/arch_init.h" |
1de7afc9 | 53 | #include "qemu/bitmap.h" |
0c764a9d | 54 | #include "qemu/config-file.h" |
0445259b | 55 | #include "hw/acpi/acpi.h" |
53a89e26 | 56 | #include "hw/cpu/icc_bus.h" |
c649983b | 57 | #include "hw/boards.h" |
80cabfad | 58 | |
471fd342 BS |
59 | /* debug PC/ISA interrupts */ |
60 | //#define DEBUG_IRQ | |
61 | ||
62 | #ifdef DEBUG_IRQ | |
63 | #define DPRINTF(fmt, ...) \ | |
64 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
65 | #else | |
66 | #define DPRINTF(fmt, ...) | |
67 | #endif | |
68 | ||
a80274c3 PB |
69 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
70 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 71 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 72 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 73 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 74 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 75 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 76 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 77 | |
3a4a4697 LE |
78 | #define IO_APIC_DEFAULT_ADDRESS 0xfec00000 |
79 | ||
4c5b10b7 JS |
80 | #define E820_NR_ENTRIES 16 |
81 | ||
82 | struct e820_entry { | |
83 | uint64_t address; | |
84 | uint64_t length; | |
85 | uint32_t type; | |
541dc0d4 | 86 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
87 | |
88 | struct e820_table { | |
89 | uint32_t count; | |
90 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 91 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
92 | |
93 | static struct e820_table e820_table; | |
dd703b99 | 94 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 95 | |
b881fbe9 | 96 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 97 | { |
b881fbe9 | 98 | GSIState *s = opaque; |
1452411b | 99 | |
b881fbe9 JK |
100 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
101 | if (n < ISA_NUM_IRQS) { | |
102 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 103 | } |
b881fbe9 | 104 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 105 | } |
1452411b | 106 | |
258711c6 JG |
107 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
108 | unsigned size) | |
80cabfad FB |
109 | { |
110 | } | |
111 | ||
c02e1eac JG |
112 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
113 | { | |
a6fc23e5 | 114 | return 0xffffffffffffffffULL; |
c02e1eac JG |
115 | } |
116 | ||
f929aad6 | 117 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 118 | static qemu_irq ferr_irq; |
8e78eb28 IY |
119 | |
120 | void pc_register_ferr_irq(qemu_irq irq) | |
121 | { | |
122 | ferr_irq = irq; | |
123 | } | |
124 | ||
f929aad6 FB |
125 | /* XXX: add IGNNE support */ |
126 | void cpu_set_ferr(CPUX86State *s) | |
127 | { | |
d537cf6c | 128 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
129 | } |
130 | ||
258711c6 JG |
131 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
132 | unsigned size) | |
f929aad6 | 133 | { |
d537cf6c | 134 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
135 | } |
136 | ||
c02e1eac JG |
137 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
138 | { | |
a6fc23e5 | 139 | return 0xffffffffffffffffULL; |
c02e1eac JG |
140 | } |
141 | ||
28ab0e2e | 142 | /* TSC handling */ |
28ab0e2e FB |
143 | uint64_t cpu_get_tsc(CPUX86State *env) |
144 | { | |
4a1418e0 | 145 | return cpu_get_ticks(); |
28ab0e2e FB |
146 | } |
147 | ||
a5954d5c | 148 | /* SMM support */ |
f885f1ea IY |
149 | |
150 | static cpu_set_smm_t smm_set; | |
151 | static void *smm_arg; | |
152 | ||
153 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
154 | { | |
155 | assert(smm_set == NULL); | |
156 | assert(smm_arg == NULL); | |
157 | smm_set = callback; | |
158 | smm_arg = arg; | |
159 | } | |
160 | ||
4a8fa5dc | 161 | void cpu_smm_update(CPUX86State *env) |
a5954d5c | 162 | { |
f885f1ea IY |
163 | if (smm_set && smm_arg && env == first_cpu) |
164 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
165 | } |
166 | ||
167 | ||
3de388f6 | 168 | /* IRQ handling */ |
4a8fa5dc | 169 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 FB |
170 | { |
171 | int intno; | |
172 | ||
cf6d64bf | 173 | intno = apic_get_interrupt(env->apic_state); |
3de388f6 | 174 | if (intno >= 0) { |
3de388f6 FB |
175 | return intno; |
176 | } | |
3de388f6 | 177 | /* read the irq from the PIC */ |
cf6d64bf | 178 | if (!apic_accept_pic_intr(env->apic_state)) { |
0e21e12b | 179 | return -1; |
cf6d64bf | 180 | } |
0e21e12b | 181 | |
3de388f6 FB |
182 | intno = pic_read_irq(isa_pic); |
183 | return intno; | |
184 | } | |
185 | ||
d537cf6c | 186 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 187 | { |
4a8fa5dc | 188 | CPUX86State *env = first_cpu; |
a5b38b51 | 189 | |
471fd342 | 190 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
d5529471 AJ |
191 | if (env->apic_state) { |
192 | while (env) { | |
cf6d64bf BS |
193 | if (apic_accept_pic_intr(env->apic_state)) { |
194 | apic_deliver_pic_intr(env->apic_state, level); | |
195 | } | |
d5529471 AJ |
196 | env = env->next_cpu; |
197 | } | |
198 | } else { | |
d8ed887b AF |
199 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
200 | if (level) { | |
c3affe56 | 201 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
202 | } else { |
203 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
204 | } | |
a5b38b51 | 205 | } |
3de388f6 FB |
206 | } |
207 | ||
b0a21b53 FB |
208 | /* PC cmos mappings */ |
209 | ||
80cabfad FB |
210 | #define REG_EQUIPMENT_BYTE 0x14 |
211 | ||
d288c7ba | 212 | static int cmos_get_fd_drive_type(FDriveType fd0) |
777428f2 FB |
213 | { |
214 | int val; | |
215 | ||
216 | switch (fd0) { | |
d288c7ba | 217 | case FDRIVE_DRV_144: |
777428f2 FB |
218 | /* 1.44 Mb 3"5 drive */ |
219 | val = 4; | |
220 | break; | |
d288c7ba | 221 | case FDRIVE_DRV_288: |
777428f2 FB |
222 | /* 2.88 Mb 3"5 drive */ |
223 | val = 5; | |
224 | break; | |
d288c7ba | 225 | case FDRIVE_DRV_120: |
777428f2 FB |
226 | /* 1.2 Mb 5"5 drive */ |
227 | val = 2; | |
228 | break; | |
d288c7ba | 229 | case FDRIVE_DRV_NONE: |
777428f2 FB |
230 | default: |
231 | val = 0; | |
232 | break; | |
233 | } | |
234 | return val; | |
235 | } | |
236 | ||
9139046c MA |
237 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
238 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 239 | { |
ba6c2377 FB |
240 | rtc_set_memory(s, type_ofs, 47); |
241 | rtc_set_memory(s, info_ofs, cylinders); | |
242 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
243 | rtc_set_memory(s, info_ofs + 2, heads); | |
244 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
245 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
246 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
247 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
248 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
249 | rtc_set_memory(s, info_ofs + 8, sectors); | |
250 | } | |
251 | ||
6ac0e82d AZ |
252 | /* convert boot_device letter to something recognizable by the bios */ |
253 | static int boot_device2nibble(char boot_device) | |
254 | { | |
255 | switch(boot_device) { | |
256 | case 'a': | |
257 | case 'b': | |
258 | return 0x01; /* floppy boot */ | |
259 | case 'c': | |
260 | return 0x02; /* hard drive boot */ | |
261 | case 'd': | |
262 | return 0x03; /* CD-ROM boot */ | |
263 | case 'n': | |
264 | return 0x04; /* Network boot */ | |
265 | } | |
266 | return 0; | |
267 | } | |
268 | ||
1d914fa0 | 269 | static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
270 | { |
271 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
272 | int nbds, bds[3] = { 0, }; |
273 | int i; | |
274 | ||
275 | nbds = strlen(boot_device); | |
276 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 277 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
278 | return(1); |
279 | } | |
280 | for (i = 0; i < nbds; i++) { | |
281 | bds[i] = boot_device2nibble(boot_device[i]); | |
282 | if (bds[i] == 0) { | |
1ecda02b MA |
283 | error_report("Invalid boot device for PC: '%c'", |
284 | boot_device[i]); | |
0ecdffbb AJ |
285 | return(1); |
286 | } | |
287 | } | |
288 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 289 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
290 | return(0); |
291 | } | |
292 | ||
d9346e81 MA |
293 | static int pc_boot_set(void *opaque, const char *boot_device) |
294 | { | |
295 | return set_boot_dev(opaque, boot_device, 0); | |
296 | } | |
297 | ||
c0897e0c MA |
298 | typedef struct pc_cmos_init_late_arg { |
299 | ISADevice *rtc_state; | |
9139046c | 300 | BusState *idebus[2]; |
c0897e0c MA |
301 | } pc_cmos_init_late_arg; |
302 | ||
303 | static void pc_cmos_init_late(void *opaque) | |
304 | { | |
305 | pc_cmos_init_late_arg *arg = opaque; | |
306 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
307 | int16_t cylinders; |
308 | int8_t heads, sectors; | |
c0897e0c | 309 | int val; |
2adc99b2 | 310 | int i, trans; |
c0897e0c | 311 | |
9139046c MA |
312 | val = 0; |
313 | if (ide_get_geometry(arg->idebus[0], 0, | |
314 | &cylinders, &heads, §ors) >= 0) { | |
315 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
316 | val |= 0xf0; | |
317 | } | |
318 | if (ide_get_geometry(arg->idebus[0], 1, | |
319 | &cylinders, &heads, §ors) >= 0) { | |
320 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
321 | val |= 0x0f; | |
322 | } | |
323 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
324 | |
325 | val = 0; | |
326 | for (i = 0; i < 4; i++) { | |
9139046c MA |
327 | /* NOTE: ide_get_geometry() returns the physical |
328 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
329 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
330 | geometry can be different if a translation is done. */ | |
331 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
332 | &cylinders, &heads, §ors) >= 0) { | |
2adc99b2 MA |
333 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
334 | assert((trans & ~3) == 0); | |
335 | val |= trans << (i * 2); | |
c0897e0c MA |
336 | } |
337 | } | |
338 | rtc_set_memory(s, 0x39, val); | |
339 | ||
340 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
341 | } | |
342 | ||
b8b7456d IM |
343 | typedef struct RTCCPUHotplugArg { |
344 | Notifier cpu_added_notifier; | |
345 | ISADevice *rtc_state; | |
346 | } RTCCPUHotplugArg; | |
347 | ||
348 | static void rtc_notify_cpu_added(Notifier *notifier, void *data) | |
349 | { | |
350 | RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, | |
351 | cpu_added_notifier); | |
352 | ISADevice *s = arg->rtc_state; | |
353 | ||
354 | /* increment the number of CPUs */ | |
355 | rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); | |
356 | } | |
357 | ||
845773ab | 358 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
c0897e0c | 359 | const char *boot_device, |
34d4260e | 360 | ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
63ffb564 | 361 | ISADevice *s) |
80cabfad | 362 | { |
61a8d649 | 363 | int val, nb, i; |
980bda8b | 364 | FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; |
c0897e0c | 365 | static pc_cmos_init_late_arg arg; |
b8b7456d | 366 | static RTCCPUHotplugArg cpu_hotplug_cb; |
b0a21b53 | 367 | |
b0a21b53 | 368 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
369 | |
370 | /* memory size */ | |
e89001f7 MA |
371 | /* base memory (first MiB) */ |
372 | val = MIN(ram_size / 1024, 640); | |
333190eb FB |
373 | rtc_set_memory(s, 0x15, val); |
374 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 MA |
375 | /* extended memory (next 64MiB) */ |
376 | if (ram_size > 1024 * 1024) { | |
377 | val = (ram_size - 1024 * 1024) / 1024; | |
378 | } else { | |
379 | val = 0; | |
380 | } | |
80cabfad FB |
381 | if (val > 65535) |
382 | val = 65535; | |
b0a21b53 FB |
383 | rtc_set_memory(s, 0x17, val); |
384 | rtc_set_memory(s, 0x18, val >> 8); | |
385 | rtc_set_memory(s, 0x30, val); | |
386 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 MA |
387 | /* memory between 16MiB and 4GiB */ |
388 | if (ram_size > 16 * 1024 * 1024) { | |
389 | val = (ram_size - 16 * 1024 * 1024) / 65536; | |
390 | } else { | |
9da98861 | 391 | val = 0; |
e89001f7 | 392 | } |
80cabfad FB |
393 | if (val > 65535) |
394 | val = 65535; | |
b0a21b53 FB |
395 | rtc_set_memory(s, 0x34, val); |
396 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 MA |
397 | /* memory above 4GiB */ |
398 | val = above_4g_mem_size / 65536; | |
399 | rtc_set_memory(s, 0x5b, val); | |
400 | rtc_set_memory(s, 0x5c, val >> 8); | |
401 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 402 | |
298e01b6 AJ |
403 | /* set the number of CPU */ |
404 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
b8b7456d IM |
405 | /* init CPU hotplug notifier */ |
406 | cpu_hotplug_cb.rtc_state = s; | |
407 | cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; | |
408 | qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); | |
298e01b6 | 409 | |
6ac0e82d | 410 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 411 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
412 | exit(1); |
413 | } | |
80cabfad | 414 | |
b41a2cd1 | 415 | /* floppy type */ |
34d4260e | 416 | if (floppy) { |
34d4260e | 417 | for (i = 0; i < 2; i++) { |
61a8d649 | 418 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); |
63ffb564 BS |
419 | } |
420 | } | |
421 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
422 | cmos_get_fd_drive_type(fd_type[1]); | |
b0a21b53 | 423 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 424 | |
b0a21b53 | 425 | val = 0; |
b41a2cd1 | 426 | nb = 0; |
63ffb564 | 427 | if (fd_type[0] < FDRIVE_DRV_NONE) { |
80cabfad | 428 | nb++; |
d288c7ba | 429 | } |
63ffb564 | 430 | if (fd_type[1] < FDRIVE_DRV_NONE) { |
80cabfad | 431 | nb++; |
d288c7ba | 432 | } |
80cabfad FB |
433 | switch (nb) { |
434 | case 0: | |
435 | break; | |
436 | case 1: | |
b0a21b53 | 437 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
438 | break; |
439 | case 2: | |
b0a21b53 | 440 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
441 | break; |
442 | } | |
b0a21b53 FB |
443 | val |= 0x02; /* FPU is there */ |
444 | val |= 0x04; /* PS/2 mouse installed */ | |
445 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
446 | ||
ba6c2377 | 447 | /* hard drives */ |
c0897e0c | 448 | arg.rtc_state = s; |
9139046c MA |
449 | arg.idebus[0] = idebus0; |
450 | arg.idebus[1] = idebus1; | |
c0897e0c | 451 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
452 | } |
453 | ||
a0881c64 AF |
454 | #define TYPE_PORT92 "port92" |
455 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
456 | ||
4b78a802 BS |
457 | /* port 92 stuff: could be split off */ |
458 | typedef struct Port92State { | |
a0881c64 AF |
459 | ISADevice parent_obj; |
460 | ||
23af670e | 461 | MemoryRegion io; |
4b78a802 BS |
462 | uint8_t outport; |
463 | qemu_irq *a20_out; | |
464 | } Port92State; | |
465 | ||
93ef4192 AG |
466 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
467 | unsigned size) | |
4b78a802 BS |
468 | { |
469 | Port92State *s = opaque; | |
470 | ||
471 | DPRINTF("port92: write 0x%02x\n", val); | |
472 | s->outport = val; | |
473 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
474 | if (val & 1) { | |
475 | qemu_system_reset_request(); | |
476 | } | |
477 | } | |
478 | ||
93ef4192 AG |
479 | static uint64_t port92_read(void *opaque, hwaddr addr, |
480 | unsigned size) | |
4b78a802 BS |
481 | { |
482 | Port92State *s = opaque; | |
483 | uint32_t ret; | |
484 | ||
485 | ret = s->outport; | |
486 | DPRINTF("port92: read 0x%02x\n", ret); | |
487 | return ret; | |
488 | } | |
489 | ||
490 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
491 | { | |
a0881c64 | 492 | Port92State *s = PORT92(dev); |
4b78a802 BS |
493 | |
494 | s->a20_out = a20_out; | |
495 | } | |
496 | ||
497 | static const VMStateDescription vmstate_port92_isa = { | |
498 | .name = "port92", | |
499 | .version_id = 1, | |
500 | .minimum_version_id = 1, | |
501 | .minimum_version_id_old = 1, | |
502 | .fields = (VMStateField []) { | |
503 | VMSTATE_UINT8(outport, Port92State), | |
504 | VMSTATE_END_OF_LIST() | |
505 | } | |
506 | }; | |
507 | ||
508 | static void port92_reset(DeviceState *d) | |
509 | { | |
a0881c64 | 510 | Port92State *s = PORT92(d); |
4b78a802 BS |
511 | |
512 | s->outport &= ~1; | |
513 | } | |
514 | ||
23af670e | 515 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
516 | .read = port92_read, |
517 | .write = port92_write, | |
518 | .impl = { | |
519 | .min_access_size = 1, | |
520 | .max_access_size = 1, | |
521 | }, | |
522 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
523 | }; |
524 | ||
4b78a802 BS |
525 | static int port92_initfn(ISADevice *dev) |
526 | { | |
a0881c64 | 527 | Port92State *s = PORT92(dev); |
4b78a802 | 528 | |
23af670e RH |
529 | memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); |
530 | isa_register_ioport(dev, &s->io, 0x92); | |
531 | ||
4b78a802 BS |
532 | s->outport = 0; |
533 | return 0; | |
534 | } | |
535 | ||
8f04ee08 AL |
536 | static void port92_class_initfn(ObjectClass *klass, void *data) |
537 | { | |
39bffca2 | 538 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
539 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
540 | ic->init = port92_initfn; | |
39bffca2 AL |
541 | dc->no_user = 1; |
542 | dc->reset = port92_reset; | |
543 | dc->vmsd = &vmstate_port92_isa; | |
8f04ee08 AL |
544 | } |
545 | ||
8c43a6f0 | 546 | static const TypeInfo port92_info = { |
a0881c64 | 547 | .name = TYPE_PORT92, |
39bffca2 AL |
548 | .parent = TYPE_ISA_DEVICE, |
549 | .instance_size = sizeof(Port92State), | |
550 | .class_init = port92_class_initfn, | |
4b78a802 BS |
551 | }; |
552 | ||
83f7d43a | 553 | static void port92_register_types(void) |
4b78a802 | 554 | { |
39bffca2 | 555 | type_register_static(&port92_info); |
4b78a802 | 556 | } |
83f7d43a AF |
557 | |
558 | type_init(port92_register_types) | |
4b78a802 | 559 | |
956a3e6b | 560 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 561 | { |
cc36a7a2 | 562 | X86CPU *cpu = opaque; |
e1a23744 | 563 | |
956a3e6b | 564 | /* XXX: send to all CPUs ? */ |
4b78a802 | 565 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 566 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
567 | } |
568 | ||
4c5b10b7 JS |
569 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
570 | { | |
8ca209ad | 571 | int index = le32_to_cpu(e820_table.count); |
4c5b10b7 JS |
572 | struct e820_entry *entry; |
573 | ||
574 | if (index >= E820_NR_ENTRIES) | |
575 | return -EBUSY; | |
8ca209ad | 576 | entry = &e820_table.entry[index++]; |
4c5b10b7 | 577 | |
8ca209ad AW |
578 | entry->address = cpu_to_le64(address); |
579 | entry->length = cpu_to_le64(length); | |
580 | entry->type = cpu_to_le32(type); | |
4c5b10b7 | 581 | |
8ca209ad AW |
582 | e820_table.count = cpu_to_le32(index); |
583 | return index; | |
4c5b10b7 JS |
584 | } |
585 | ||
1d934e89 EH |
586 | /* Calculates the limit to CPU APIC ID values |
587 | * | |
588 | * This function returns the limit for the APIC ID value, so that all | |
589 | * CPU APIC IDs are < pc_apic_id_limit(). | |
590 | * | |
591 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
592 | */ | |
593 | static unsigned int pc_apic_id_limit(unsigned int max_cpus) | |
594 | { | |
595 | return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
596 | } | |
597 | ||
bf483392 | 598 | static void *bochs_bios_init(void) |
80cabfad | 599 | { |
3cce6243 | 600 | void *fw_cfg; |
b6f6e3d3 AL |
601 | uint8_t *smbios_table; |
602 | size_t smbios_len; | |
11c2fd3e AL |
603 | uint64_t *numa_fw_cfg; |
604 | int i, j; | |
1d934e89 | 605 | unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); |
3cce6243 BS |
606 | |
607 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
1d934e89 EH |
608 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
609 | * | |
610 | * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug | |
611 | * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC | |
612 | * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the | |
613 | * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS | |
614 | * may see". | |
615 | * | |
616 | * So, this means we must not use max_cpus, here, but the maximum possible | |
617 | * APIC ID value, plus one. | |
618 | * | |
619 | * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is | |
620 | * the APIC ID, not the "CPU index" | |
621 | */ | |
622 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); | |
3cce6243 | 623 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 624 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
625 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
626 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 627 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 AL |
628 | |
629 | smbios_table = smbios_get_table(&smbios_len); | |
630 | if (smbios_table) | |
631 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
632 | smbios_table, smbios_len); | |
089da572 MA |
633 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
634 | &e820_table, sizeof(e820_table)); | |
11c2fd3e | 635 | |
089da572 | 636 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
637 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
638 | * of nodes, one word for each VCPU->node and one word for each node to | |
639 | * hold the amount of memory. | |
640 | */ | |
1d934e89 | 641 | numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); |
11c2fd3e | 642 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 643 | for (i = 0; i < max_cpus; i++) { |
1d934e89 EH |
644 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); |
645 | assert(apic_id < apic_id_limit); | |
11c2fd3e | 646 | for (j = 0; j < nb_numa_nodes; j++) { |
ee785fed | 647 | if (test_bit(i, node_cpumask[j])) { |
1d934e89 | 648 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); |
11c2fd3e AL |
649 | break; |
650 | } | |
651 | } | |
652 | } | |
653 | for (i = 0; i < nb_numa_nodes; i++) { | |
1d934e89 | 654 | numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]); |
11c2fd3e | 655 | } |
089da572 | 656 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
1d934e89 EH |
657 | (1 + apic_id_limit + nb_numa_nodes) * |
658 | sizeof(*numa_fw_cfg)); | |
bf483392 AG |
659 | |
660 | return fw_cfg; | |
80cabfad FB |
661 | } |
662 | ||
642a4f96 TS |
663 | static long get_file_size(FILE *f) |
664 | { | |
665 | long where, size; | |
666 | ||
667 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
668 | ||
669 | where = ftell(f); | |
670 | fseek(f, 0, SEEK_END); | |
671 | size = ftell(f); | |
672 | fseek(f, where, SEEK_SET); | |
673 | ||
674 | return size; | |
675 | } | |
676 | ||
f16408df | 677 | static void load_linux(void *fw_cfg, |
4fc9af53 | 678 | const char *kernel_filename, |
0f9d76e5 | 679 | const char *initrd_filename, |
680 | const char *kernel_cmdline, | |
a8170e5e | 681 | hwaddr max_ram_size) |
642a4f96 TS |
682 | { |
683 | uint16_t protocol; | |
5cea8590 | 684 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 685 | uint32_t initrd_max; |
57a46d05 | 686 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 687 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 688 | FILE *f; |
bf4e5d92 | 689 | char *vmode; |
642a4f96 TS |
690 | |
691 | /* Align to 16 bytes as a paranoia measure */ | |
692 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
693 | ||
694 | /* load the kernel header */ | |
695 | f = fopen(kernel_filename, "rb"); | |
696 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 | 697 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
698 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
699 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
700 | kernel_filename, strerror(errno)); | |
701 | exit(1); | |
642a4f96 TS |
702 | } |
703 | ||
704 | /* kernel protocol version */ | |
bc4edd79 | 705 | #if 0 |
642a4f96 | 706 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 707 | #endif |
0f9d76e5 | 708 | if (ldl_p(header+0x202) == 0x53726448) { |
709 | protocol = lduw_p(header+0x206); | |
710 | } else { | |
711 | /* This looks like a multiboot kernel. If it is, let's stop | |
712 | treating it like a Linux kernel. */ | |
52001445 | 713 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 714 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 715 | return; |
0f9d76e5 | 716 | } |
717 | protocol = 0; | |
f16408df | 718 | } |
642a4f96 TS |
719 | |
720 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 | 721 | /* Low kernel */ |
722 | real_addr = 0x90000; | |
723 | cmdline_addr = 0x9a000 - cmdline_size; | |
724 | prot_addr = 0x10000; | |
642a4f96 | 725 | } else if (protocol < 0x202) { |
0f9d76e5 | 726 | /* High but ancient kernel */ |
727 | real_addr = 0x90000; | |
728 | cmdline_addr = 0x9a000 - cmdline_size; | |
729 | prot_addr = 0x100000; | |
642a4f96 | 730 | } else { |
0f9d76e5 | 731 | /* High and recent kernel */ |
732 | real_addr = 0x10000; | |
733 | cmdline_addr = 0x20000; | |
734 | prot_addr = 0x100000; | |
642a4f96 TS |
735 | } |
736 | ||
bc4edd79 | 737 | #if 0 |
642a4f96 | 738 | fprintf(stderr, |
0f9d76e5 | 739 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
740 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
741 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
742 | real_addr, | |
743 | cmdline_addr, | |
744 | prot_addr); | |
bc4edd79 | 745 | #endif |
642a4f96 TS |
746 | |
747 | /* highest address for loading the initrd */ | |
0f9d76e5 | 748 | if (protocol >= 0x203) { |
749 | initrd_max = ldl_p(header+0x22c); | |
750 | } else { | |
751 | initrd_max = 0x37ffffff; | |
752 | } | |
642a4f96 | 753 | |
e6ade764 GC |
754 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
755 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 756 | |
57a46d05 AG |
757 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
758 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 759 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
760 | |
761 | if (protocol >= 0x202) { | |
0f9d76e5 | 762 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 763 | } else { |
0f9d76e5 | 764 | stw_p(header+0x20, 0xA33F); |
765 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
766 | } |
767 | ||
bf4e5d92 PT |
768 | /* handle vga= parameter */ |
769 | vmode = strstr(kernel_cmdline, "vga="); | |
770 | if (vmode) { | |
771 | unsigned int video_mode; | |
772 | /* skip "vga=" */ | |
773 | vmode += 4; | |
774 | if (!strncmp(vmode, "normal", 6)) { | |
775 | video_mode = 0xffff; | |
776 | } else if (!strncmp(vmode, "ext", 3)) { | |
777 | video_mode = 0xfffe; | |
778 | } else if (!strncmp(vmode, "ask", 3)) { | |
779 | video_mode = 0xfffd; | |
780 | } else { | |
781 | video_mode = strtol(vmode, NULL, 0); | |
782 | } | |
783 | stw_p(header+0x1fa, video_mode); | |
784 | } | |
785 | ||
642a4f96 | 786 | /* loader type */ |
5cbdb3a3 | 787 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
788 | If this code is substantially changed, you may want to consider |
789 | incrementing the revision. */ | |
0f9d76e5 | 790 | if (protocol >= 0x200) { |
791 | header[0x210] = 0xB0; | |
792 | } | |
642a4f96 TS |
793 | /* heap */ |
794 | if (protocol >= 0x201) { | |
0f9d76e5 | 795 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
796 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
797 | } |
798 | ||
799 | /* load initrd */ | |
800 | if (initrd_filename) { | |
0f9d76e5 | 801 | if (protocol < 0x200) { |
802 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
803 | exit(1); | |
804 | } | |
642a4f96 | 805 | |
0f9d76e5 | 806 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
807 | if (initrd_size < 0) { |
808 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
809 | initrd_filename); | |
810 | exit(1); | |
811 | } | |
812 | ||
45a50b16 | 813 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 814 | |
7267c094 | 815 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
816 | load_image(initrd_filename, initrd_data); |
817 | ||
818 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
819 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
820 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 821 | |
0f9d76e5 | 822 | stl_p(header+0x218, initrd_addr); |
823 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
824 | } |
825 | ||
45a50b16 | 826 | /* load kernel and setup */ |
642a4f96 | 827 | setup_size = header[0x1f1]; |
0f9d76e5 | 828 | if (setup_size == 0) { |
829 | setup_size = 4; | |
830 | } | |
642a4f96 | 831 | setup_size = (setup_size+1)*512; |
45a50b16 | 832 | kernel_size -= setup_size; |
642a4f96 | 833 | |
7267c094 AL |
834 | setup = g_malloc(setup_size); |
835 | kernel = g_malloc(kernel_size); | |
45a50b16 | 836 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
837 | if (fread(setup, 1, setup_size, f) != setup_size) { |
838 | fprintf(stderr, "fread() failed\n"); | |
839 | exit(1); | |
840 | } | |
841 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
842 | fprintf(stderr, "fread() failed\n"); | |
843 | exit(1); | |
844 | } | |
642a4f96 | 845 | fclose(f); |
45a50b16 | 846 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
847 | |
848 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
849 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
850 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
851 | ||
852 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
853 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
854 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
855 | ||
2e55e842 GN |
856 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
857 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 858 | nb_option_roms++; |
642a4f96 TS |
859 | } |
860 | ||
b41a2cd1 FB |
861 | #define NE2000_NB_MAX 6 |
862 | ||
675d6f82 BS |
863 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
864 | 0x280, 0x380 }; | |
865 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 866 | |
675d6f82 BS |
867 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
868 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 869 | |
48a18b3c | 870 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
871 | { |
872 | static int nb_ne2k = 0; | |
873 | ||
874 | if (nb_ne2k == NE2000_NB_MAX) | |
875 | return; | |
48a18b3c | 876 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 877 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
878 | nb_ne2k++; |
879 | } | |
880 | ||
92a16d7a | 881 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 BS |
882 | { |
883 | if (cpu_single_env) { | |
884 | return cpu_single_env->apic_state; | |
885 | } else { | |
886 | return NULL; | |
887 | } | |
888 | } | |
889 | ||
845773ab | 890 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 891 | { |
c3affe56 | 892 | X86CPU *cpu = opaque; |
53b67b30 BS |
893 | |
894 | if (level) { | |
c3affe56 | 895 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
896 | } |
897 | } | |
898 | ||
62fc403f IM |
899 | static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, |
900 | DeviceState *icc_bridge, Error **errp) | |
31050930 IM |
901 | { |
902 | X86CPU *cpu; | |
903 | Error *local_err = NULL; | |
904 | ||
62fc403f | 905 | cpu = cpu_x86_create(cpu_model, icc_bridge, errp); |
31050930 IM |
906 | if (!cpu) { |
907 | return cpu; | |
908 | } | |
909 | ||
910 | object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); | |
911 | object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); | |
912 | ||
913 | if (local_err) { | |
914 | if (cpu != NULL) { | |
915 | object_unref(OBJECT(cpu)); | |
916 | cpu = NULL; | |
917 | } | |
918 | error_propagate(errp, local_err); | |
919 | } | |
920 | return cpu; | |
921 | } | |
922 | ||
c649983b IM |
923 | static const char *current_cpu_model; |
924 | ||
925 | void pc_hot_add_cpu(const int64_t id, Error **errp) | |
926 | { | |
927 | DeviceState *icc_bridge; | |
928 | int64_t apic_id = x86_cpu_apic_id_from_index(id); | |
929 | ||
75e4aa94 IM |
930 | if (id < 0) { |
931 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
932 | return; | |
933 | } | |
934 | ||
c649983b IM |
935 | if (cpu_exists(apic_id)) { |
936 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
937 | ", it already exists", id); | |
938 | return; | |
939 | } | |
940 | ||
941 | if (id >= max_cpus) { | |
942 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
943 | ", max allowed: %d", id, max_cpus - 1); | |
944 | return; | |
945 | } | |
946 | ||
947 | icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", | |
948 | TYPE_ICC_BRIDGE, NULL)); | |
949 | pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); | |
950 | } | |
951 | ||
62fc403f | 952 | void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) |
70166477 IY |
953 | { |
954 | int i; | |
53a89e26 | 955 | X86CPU *cpu = NULL; |
31050930 | 956 | Error *error = NULL; |
70166477 IY |
957 | |
958 | /* init CPUs */ | |
959 | if (cpu_model == NULL) { | |
960 | #ifdef TARGET_X86_64 | |
961 | cpu_model = "qemu64"; | |
962 | #else | |
963 | cpu_model = "qemu32"; | |
964 | #endif | |
965 | } | |
c649983b | 966 | current_cpu_model = cpu_model; |
70166477 | 967 | |
bdeec802 | 968 | for (i = 0; i < smp_cpus; i++) { |
53a89e26 IM |
969 | cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), |
970 | icc_bridge, &error); | |
31050930 IM |
971 | if (error) { |
972 | fprintf(stderr, "%s\n", error_get_pretty(error)); | |
973 | error_free(error); | |
bdeec802 IM |
974 | exit(1); |
975 | } | |
70166477 | 976 | } |
53a89e26 IM |
977 | |
978 | /* map APIC MMIO area if CPU has APIC */ | |
979 | if (cpu && cpu->env.apic_state) { | |
980 | /* XXX: what if the base changes? */ | |
981 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, | |
982 | APIC_DEFAULT_ADDRESS, 0x1000); | |
983 | } | |
70166477 IY |
984 | } |
985 | ||
f7e4dd6c GH |
986 | void pc_acpi_init(const char *default_dsdt) |
987 | { | |
c5a98cf3 | 988 | char *filename; |
f7e4dd6c GH |
989 | |
990 | if (acpi_tables != NULL) { | |
991 | /* manually set via -acpitable, leave it alone */ | |
992 | return; | |
993 | } | |
994 | ||
995 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
996 | if (filename == NULL) { | |
997 | fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); | |
c5a98cf3 LE |
998 | } else { |
999 | char *arg; | |
1000 | QemuOpts *opts; | |
1001 | Error *err = NULL; | |
f7e4dd6c | 1002 | |
c5a98cf3 | 1003 | arg = g_strdup_printf("file=%s", filename); |
0c764a9d | 1004 | |
c5a98cf3 LE |
1005 | /* creates a deep copy of "arg" */ |
1006 | opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); | |
1007 | g_assert(opts != NULL); | |
0c764a9d | 1008 | |
c5a98cf3 LE |
1009 | acpi_table_add(opts, &err); |
1010 | if (err) { | |
1011 | fprintf(stderr, "WARNING: failed to load %s: %s\n", filename, | |
1012 | error_get_pretty(err)); | |
1013 | error_free(err); | |
1014 | } | |
1015 | g_free(arg); | |
1016 | g_free(filename); | |
f7e4dd6c | 1017 | } |
f7e4dd6c GH |
1018 | } |
1019 | ||
459ae5ea | 1020 | void *pc_memory_init(MemoryRegion *system_memory, |
4aa63af1 | 1021 | const char *kernel_filename, |
845773ab IY |
1022 | const char *kernel_cmdline, |
1023 | const char *initrd_filename, | |
e0e7e67b | 1024 | ram_addr_t below_4g_mem_size, |
ae0a5466 | 1025 | ram_addr_t above_4g_mem_size, |
4463aee6 | 1026 | MemoryRegion *rom_memory, |
ae0a5466 | 1027 | MemoryRegion **ram_memory) |
80cabfad | 1028 | { |
cbc5b5f3 JJ |
1029 | int linux_boot, i; |
1030 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1031 | MemoryRegion *ram_below_4g, *ram_above_4g; |
81a204e4 | 1032 | void *fw_cfg; |
d592d303 | 1033 | |
80cabfad FB |
1034 | linux_boot = (kernel_filename != NULL); |
1035 | ||
00cb2a99 | 1036 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1037 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1038 | * with older qemus that used qemu_ram_alloc(). |
1039 | */ | |
7267c094 | 1040 | ram = g_malloc(sizeof(*ram)); |
c5705a77 | 1041 | memory_region_init_ram(ram, "pc.ram", |
00cb2a99 | 1042 | below_4g_mem_size + above_4g_mem_size); |
c5705a77 | 1043 | vmstate_register_ram_global(ram); |
ae0a5466 | 1044 | *ram_memory = ram; |
7267c094 | 1045 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
00cb2a99 AK |
1046 | memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, |
1047 | 0, below_4g_mem_size); | |
1048 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
bbe80adf | 1049 | if (above_4g_mem_size > 0) { |
7267c094 | 1050 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
00cb2a99 AK |
1051 | memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, |
1052 | below_4g_mem_size, above_4g_mem_size); | |
1053 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1054 | ram_above_4g); | |
bbe80adf | 1055 | } |
82b36dc3 | 1056 | |
cbc5b5f3 JJ |
1057 | |
1058 | /* Initialize PC system firmware */ | |
1059 | pc_system_firmware_init(rom_memory); | |
00cb2a99 | 1060 | |
7267c094 | 1061 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
c5705a77 AK |
1062 | memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE); |
1063 | vmstate_register_ram_global(option_rom_mr); | |
4463aee6 | 1064 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1065 | PC_ROM_MIN_VGA, |
1066 | option_rom_mr, | |
1067 | 1); | |
f753ff16 | 1068 | |
bf483392 | 1069 | fw_cfg = bochs_bios_init(); |
8832cb80 | 1070 | rom_set_fw(fw_cfg); |
1d108d97 | 1071 | |
f753ff16 | 1072 | if (linux_boot) { |
81a204e4 | 1073 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
1074 | } |
1075 | ||
1076 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1077 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1078 | } |
459ae5ea | 1079 | return fw_cfg; |
3d53f5c3 IY |
1080 | } |
1081 | ||
845773ab IY |
1082 | qemu_irq *pc_allocate_cpu_irq(void) |
1083 | { | |
1084 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
1085 | } | |
1086 | ||
48a18b3c | 1087 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1088 | { |
ad6d45fa AL |
1089 | DeviceState *dev = NULL; |
1090 | ||
16094b75 AJ |
1091 | if (pci_bus) { |
1092 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1093 | dev = pcidev ? &pcidev->qdev : NULL; | |
1094 | } else if (isa_bus) { | |
1095 | ISADevice *isadev = isa_vga_init(isa_bus); | |
1096 | dev = isadev ? &isadev->qdev : NULL; | |
765d7908 | 1097 | } |
ad6d45fa | 1098 | return dev; |
765d7908 IY |
1099 | } |
1100 | ||
4556bd8b BS |
1101 | static void cpu_request_exit(void *opaque, int irq, int level) |
1102 | { | |
4a8fa5dc | 1103 | CPUX86State *env = cpu_single_env; |
4556bd8b BS |
1104 | |
1105 | if (env && level) { | |
1106 | cpu_exit(env); | |
1107 | } | |
1108 | } | |
1109 | ||
258711c6 JG |
1110 | static const MemoryRegionOps ioport80_io_ops = { |
1111 | .write = ioport80_write, | |
c02e1eac | 1112 | .read = ioport80_read, |
258711c6 JG |
1113 | .endianness = DEVICE_NATIVE_ENDIAN, |
1114 | .impl = { | |
1115 | .min_access_size = 1, | |
1116 | .max_access_size = 1, | |
1117 | }, | |
1118 | }; | |
1119 | ||
1120 | static const MemoryRegionOps ioportF0_io_ops = { | |
1121 | .write = ioportF0_write, | |
c02e1eac | 1122 | .read = ioportF0_read, |
258711c6 JG |
1123 | .endianness = DEVICE_NATIVE_ENDIAN, |
1124 | .impl = { | |
1125 | .min_access_size = 1, | |
1126 | .max_access_size = 1, | |
1127 | }, | |
1128 | }; | |
1129 | ||
48a18b3c | 1130 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1131 | ISADevice **rtc_state, |
34d4260e | 1132 | ISADevice **floppy, |
1611977c | 1133 | bool no_vmport) |
ffe513da IY |
1134 | { |
1135 | int i; | |
1136 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1137 | DeviceState *hpet = NULL; |
1138 | int pit_isa_irq = 0; | |
1139 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1140 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1141 | qemu_irq *a20_line; |
c2d8d311 | 1142 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
4556bd8b | 1143 | qemu_irq *cpu_exit_irq; |
258711c6 JG |
1144 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1145 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1146 | |
258711c6 JG |
1147 | memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1); |
1148 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); | |
ffe513da | 1149 | |
258711c6 JG |
1150 | memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1); |
1151 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); | |
ffe513da | 1152 | |
5d17c0d2 JK |
1153 | /* |
1154 | * Check if an HPET shall be created. | |
1155 | * | |
1156 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1157 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1158 | */ | |
1159 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
ce967e2f | 1160 | hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); |
822557eb | 1161 | |
dd703b99 | 1162 | if (hpet) { |
b881fbe9 | 1163 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1164 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1165 | } |
ce967e2f JK |
1166 | pit_isa_irq = -1; |
1167 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1168 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1169 | } |
ffe513da | 1170 | } |
48a18b3c | 1171 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1172 | |
1173 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1174 | ||
c2d8d311 SS |
1175 | if (!xen_enabled()) { |
1176 | if (kvm_irqchip_in_kernel()) { | |
1177 | pit = kvm_pit_init(isa_bus, 0x40); | |
1178 | } else { | |
1179 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1180 | } | |
1181 | if (hpet) { | |
1182 | /* connect PIT to output control line of the HPET */ | |
1183 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); | |
1184 | } | |
1185 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1186 | } |
ffe513da IY |
1187 | |
1188 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1189 | if (serial_hds[i]) { | |
48a18b3c | 1190 | serial_isa_init(isa_bus, i, serial_hds[i]); |
ffe513da IY |
1191 | } |
1192 | } | |
1193 | ||
1194 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1195 | if (parallel_hds[i]) { | |
48a18b3c | 1196 | parallel_init(isa_bus, i, parallel_hds[i]); |
ffe513da IY |
1197 | } |
1198 | } | |
1199 | ||
cc36a7a2 AF |
1200 | a20_line = qemu_allocate_irqs(handle_a20_line_change, |
1201 | x86_env_get_cpu(first_cpu), 2); | |
48a18b3c | 1202 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1203 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1204 | if (!no_vmport) { |
48a18b3c HP |
1205 | vmport_init(isa_bus); |
1206 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1207 | } else { |
1208 | vmmouse = NULL; | |
1209 | } | |
86d86414 BS |
1210 | if (vmmouse) { |
1211 | qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042); | |
43f20196 | 1212 | qdev_init_nofail(&vmmouse->qdev); |
86d86414 | 1213 | } |
48a18b3c | 1214 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1215 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1216 | |
4556bd8b BS |
1217 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1218 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1219 | |
1220 | for(i = 0; i < MAX_FD; i++) { | |
1221 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1222 | } | |
48a18b3c | 1223 | *floppy = fdctrl_init_isa(isa_bus, fd); |
ffe513da IY |
1224 | } |
1225 | ||
9011a1a7 IY |
1226 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1227 | { | |
1228 | int i; | |
1229 | ||
1230 | for (i = 0; i < nb_nics; i++) { | |
1231 | NICInfo *nd = &nd_table[i]; | |
1232 | ||
1233 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1234 | pc_init_ne2k_isa(isa_bus, nd); | |
1235 | } else { | |
1236 | pci_nic_init_nofail(nd, "e1000", NULL); | |
1237 | } | |
1238 | } | |
1239 | } | |
1240 | ||
845773ab | 1241 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1242 | { |
1243 | int max_bus; | |
1244 | int bus; | |
1245 | ||
1246 | max_bus = drive_get_max_bus(IF_SCSI); | |
1247 | for (bus = 0; bus <= max_bus; bus++) { | |
1248 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1249 | } | |
1250 | } | |
a39e3564 JB |
1251 | |
1252 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1253 | { | |
1254 | DeviceState *dev; | |
1255 | SysBusDevice *d; | |
1256 | unsigned int i; | |
1257 | ||
1258 | if (kvm_irqchip_in_kernel()) { | |
1259 | dev = qdev_create(NULL, "kvm-ioapic"); | |
1260 | } else { | |
1261 | dev = qdev_create(NULL, "ioapic"); | |
1262 | } | |
1263 | if (parent_name) { | |
1264 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1265 | "ioapic", OBJECT(dev), NULL); | |
1266 | } | |
1267 | qdev_init_nofail(dev); | |
1356b98d | 1268 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1269 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1270 | |
1271 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1272 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1273 | } | |
1274 | } |