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hw/ide/ahci: Expose AHCIPCIState structure
[mirror_qemu.git] / hw / i386 / pc_q35.c
CommitLineData
df2d8b3e
IY		 1/*
2 * Q35 chipset based pc system emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on pc.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
e688df6b 30
b6a0aa05 31#include "qemu/osdep.h"
d471bf3e 32#include "qemu/units.h"
9cc44d9b 33#include "hw/char/parallel-isa.h"
04920fc0 34#include "hw/loader.h"
93198b6c 35#include "hw/i2c/smbus_eeprom.h"
bcdb9064 36#include "hw/rtc/mc146818rtc.h"
e44d989a 37#include "sysemu/tcg.h"
9c17d615 38#include "sysemu/kvm.h"
a09ef8ff 39#include "hw/i386/kvm/clock.h"
0d09e41a 40#include "hw/pci-host/q35.h"
3f3cbbb2 41#include "hw/pci/pcie_port.h"
a27bd6c7 42#include "hw/qdev-properties.h"
549e984e 43#include "hw/i386/x86.h"
b094f2e0 44#include "hw/i386/pc.h"
ef18310d
EH		 45#include "hw/i386/amd_iommu.h"
46#include "hw/i386/intel_iommu.h"
94692dcd 47#include "hw/display/ramfb.h"
a2eb5c0c 48#include "hw/firmware/smbios.h"
df2d8b3e 49#include "hw/ide/pci.h"
d407be08 50#include "hw/ide/ahci-pci.h"
7f54640b 51#include "hw/intc/ioapic.h"
1a6981bb 52#include "hw/southbridge/ich9.h"
df2d8b3e 53#include "hw/usb.h"
f0712099 54#include "hw/usb/hcd-uhci.h"
e688df6b 55#include "qapi/error.h"
c87b1520 56#include "qemu/error-report.h"
3bfe5716 57#include "sysemu/numa.h"
cab78e7c 58#include "hw/hyperv/vmbus-bridge.h"
4b997690 59#include "hw/mem/nvdimm.h"
5c94b826 60#include "hw/i386/acpi-build.h"
d1aa2f50 61#include "target/i386/cpu.h"
df2d8b3e
IY		 62
63/* ICH9 AHCI has 6 ports */
64#define MAX_SATA_PORTS 6
65
efce3175
PB		 66struct ehci_companions {
67 const char *name;
68 int func;
69 int port;
70};
71
72static const struct ehci_companions ich9_1d[] = {
f0712099
BB		 73 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 },
74 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 },
75 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 },
efce3175
PB		 76};
77
78static const struct ehci_companions ich9_1a[] = {
f0712099
BB		 79 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 },
80 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 },
81 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 },
efce3175
PB		 82};
83
84static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
85{
86 const struct ehci_companions *comp;
87 PCIDevice *ehci, *uhci;
88 BusState *usbbus;
89 const char *name;
90 int i;
91
92 switch (slot) {
93 case 0x1d:
94 name = "ich9-usb-ehci1";
95 comp = ich9_1d;
96 break;
97 case 0x1a:
98 name = "ich9-usb-ehci2";
99 comp = ich9_1a;
100 break;
101 default:
102 return -1;
103 }
104
c925f40a 105 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name);
9307d06d 106 pci_realize_and_unref(ehci, bus, &error_fatal);
efce3175
PB		 107 usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
108
109 for (i = 0; i < 3; i++) {
c925f40a 110 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func),
9307d06d 111 comp[i].name);
efce3175
PB		 112 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
113 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
9307d06d 114 pci_realize_and_unref(uhci, bus, &error_fatal);
efce3175
PB		 115 }
116 return 0;
117}
118
df2d8b3e 119/* PC hardware initialisation */
3ef96221 120static void pc_q35_init(MachineState *machine)
df2d8b3e 121{
ec68007a 122 PCMachineState *pcms = PC_MACHINE(machine);
7102fa70 123 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 124 X86MachineState *x86ms = X86_MACHINE(machine);
00f52e77 125 Object *phb;
df2d8b3e
IY		 126 PCIBus *host_bus;
127 PCIDevice *lpc;
f999c0de 128 DeviceState *lpc_dev;
df2d8b3e
IY		 129 BusState *idebus[MAX_SATA_PORTS];
130 ISADevice *rtc_state;
8631743c 131 MemoryRegion *system_memory = get_system_memory();
5fe79386 132 MemoryRegion *system_io = get_system_io();
88ad980c 133 MemoryRegion *pci_memory = g_new(MemoryRegion, 1);
df2d8b3e
IY		 134 GSIState *gsi_state;
135 ISABus *isa_bus;
df2d8b3e 136 int i;
df2d8b3e 137 PCIDevice *ahci;
c87b1520 138 ram_addr_t lowmem;
d93162e1 139 DriveInfo *hd[MAX_SATA_PORTS];
6cd2234c 140 MachineClass *mc = MACHINE_GET_CLASS(machine);
3f3cbbb2 141 bool acpi_pcihp;
c318bef7 142 bool keep_pci_slot_hpc;
c48eb7a4 143 uint64_t pci_hole64_size = 0;
f0513d2c 144
88ad980c
PMD		 145 assert(pcmc->pci_enabled);
146
4e17997d
MT		 147 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
148 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
149 * also known as MMCFG).
150 * If it doesn't, we need to split it in chunks below and above 4G.
151 * In any case, try to make sure that guest addresses aligned at
152 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
4e17997d 153 */
3ef96221 154 if (machine->ram_size >= 0xb0000000) {
533e8bbb 155 lowmem = 0x80000000;
c87b1520
DS		 156 } else {
157 lowmem = 0xb0000000;
158 }
159
a9dd38db 160 /* Handle the machine opt max-ram-below-4g. It is basically doing
c87b1520
DS		 161 * min(qemu limit, user limit).
162 */
9a45729d
GH		 163 if (!pcms->max_ram_below_4g) {
164 pcms->max_ram_below_4g = 4 * GiB;
5ec7d098 165 }
9a45729d
GH		 166 if (lowmem > pcms->max_ram_below_4g) {
167 lowmem = pcms->max_ram_below_4g;
c87b1520 168 if (machine->ram_size - lowmem > lowmem &&
d471bf3e 169 lowmem & (1 * GiB - 1)) {
9e5d2c52
AF		 170 warn_report("There is possibly poor performance as the ram size "
171 " (0x%" PRIx64 ") is more then twice the size of"
172 " max-ram-below-4g (%"PRIu64") and"
173 " max-ram-below-4g is not a multiple of 1G.",
9a45729d 174 (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
c87b1520
DS		 175 }
176 }
177
178 if (machine->ram_size >= lowmem) {
f0bb276b
PB		 179 x86ms->above_4g_mem_size = machine->ram_size - lowmem;
180 x86ms->below_4g_mem_size = lowmem;
df2d8b3e 181 } else {
f0bb276b
PB		 182 x86ms->above_4g_mem_size = 0;
183 x86ms->below_4g_mem_size = machine->ram_size;
df2d8b3e
IY		 184 }
185
97488c63 186 pc_machine_init_sgx_epc(pcms);
703a548a 187 x86_cpus_init(x86ms, pcmc->default_cpu_version);
3c2a9669 188
b797c98d
PMD		 189 if (kvm_enabled()) {
190 kvmclock_create(pcmc->kvmclock_create_always);
191 }
3c2a9669 192
5db3f0de 193 pc_guest_info_init(pcms);
07fb6176 194
7102fa70 195 if (pcmc->smbios_defaults) {
b29ad07e 196 /* These values are guest ABI, do not change */
1e366da0 197 smbios_set_defaults("QEMU", mc->desc,
7102fa70
EH		 198 mc->name, pcmc->smbios_legacy_mode,
199 pcmc->smbios_uuid_encoded,
0e4edb3b 200 pcms->smbios_entry_point_type);
b29ad07e
MA		 201 }
202
df2d8b3e 203 /* create pci host bus */
00f52e77 204 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE));
df2d8b3e 205
88ad980c
PMD		 206 pci_hole64_size = object_property_get_uint(phb,
207 PCI_HOST_PROP_PCI_HOLE64_SIZE,
208 &error_abort);
c48eb7a4 209
48767787 210 /* allocate ram and load rom/bios */
88ad980c
PMD		 211 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
212 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size);
48767787 213
00f52e77 214 object_property_add_child(OBJECT(machine), "q35", phb);
3d664a9a 215 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
f9fddaf7 216 OBJECT(machine->ram), NULL);
3d664a9a 217 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM,
5325cc34 218 OBJECT(pci_memory), NULL);
3d664a9a 219 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM,
8631743c 220 OBJECT(system_memory), NULL);
3d664a9a 221 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM,
5325cc34 222 OBJECT(system_io), NULL);
00f52e77 223 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
5325cc34 224 x86ms->below_4g_mem_size, NULL);
00f52e77 225 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE,
5325cc34 226 x86ms->above_4g_mem_size, NULL);
e36102cb
BB		 227 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU,
228 pcms->default_bus_bypass_iommu, NULL);
06a492bd 229 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
00f52e77 230
df2d8b3e 231 /* pci */
00f52e77 232 host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
06a492bd
BB		 233 pcms->bus = host_bus;
234
29538512 235 /* irq lines */
88ad980c 236 gsi_state = pc_gsi_create(&x86ms->gsi, true);
29538512 237
df2d8b3e 238 /* create ISA bus */
c925f40a 239 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
ecf403cb 240 TYPE_ICH9_LPC_DEVICE);
29538512 241 lpc_dev = DEVICE(lpc);
fc11ca08
PMD		 242 qdev_prop_set_bit(lpc_dev, "smm-enabled",
243 x86_machine_is_smm_enabled(x86ms));
244 pci_realize_and_unref(lpc, host_bus, &error_fatal);
29538512
BB		 245 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
246 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
247 }
781bbd6b 248
f0bc6bf7
BB		 249 rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
250
781bbd6b
IM		 251 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
252 TYPE_HOTPLUG_HANDLER,
50aef131 253 (Object **)&x86ms->acpi_dev,
781bbd6b 254 object_property_allow_set_link,
d2623129 255 OBJ_PROP_LINK_STRONG);
5325cc34
MA		 256 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
257 OBJECT(lpc), &error_abort);
781bbd6b 258
3f3cbbb2 259 acpi_pcihp = object_property_get_bool(OBJECT(lpc),
aa29466b 260 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
3f3cbbb2
JS		 261 NULL);
262
c318bef7
JS		 263 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc),
264 "x-keep-pci-slot-hpc",
265 NULL);
266
267 if (!keep_pci_slot_hpc && acpi_pcihp) {
1d77e157
IM		 268 object_register_sugar_prop(TYPE_PCIE_SLOT,
269 "x-do-not-expose-native-hotplug-cap",
270 "true", true);
3f3cbbb2
JS		 271 }
272
958f8182 273 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
df2d8b3e 274
c300bbe8
XL		 275 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
276 pc_i8259_create(isa_bus, gsi_state->i8259_irq);
277 }
8197e24c 278
88ad980c 279 ioapic_init_gsi(gsi_state, "q35");
df2d8b3e 280
6f529b75
PB		 281 if (tcg_enabled()) {
282 x86_register_ferr_irq(x86ms->gsi[13]);
283 }
df2d8b3e 284
7fb1cf16 285 assert(pcms->vmport != ON_OFF_AUTO__MAX);
ec68007a 286 if (pcms->vmport == ON_OFF_AUTO_AUTO) {
b2a3b8d7 287 pcms->vmport = ON_OFF_AUTO_ON;
d1048bef
DS		 288 }
289
df2d8b3e 290 /* init basic PC hardware */
87af48a4 291 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy,
feddd2fd 292 0xff0104);
df2d8b3e 293
f5878b03 294 if (pcms->sata_enabled) {
272f0428
CP		 295 /* ahci and SATA device, for q35 1 ahci controller is built-in */
296 ahci = pci_create_simple_multifunction(host_bus,
297 PCI_DEVFN(ICH9_SATA1_DEV,
298 ICH9_SATA1_FUNC),
e052944a 299 "ich9-ahci");
1a8e2f58
PMD		 300 idebus[0] = qdev_get_child_bus(DEVICE(ahci), "ide.0");
301 idebus[1] = qdev_get_child_bus(DEVICE(ahci), "ide.1");
bbe3179a
JS		 302 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
303 ide_drive_get(hd, ahci_get_num_ports(ahci));
272f0428
CP		 304 ahci_ide_create_devs(ahci, hd);
305 } else {
306 idebus[0] = idebus[1] = NULL;
307 }
df2d8b3e 308
4bcbe0b6 309 if (machine_usb(machine)) {
df2d8b3e
IY		 310 /* Should we create 6 UHCI according to ich9 spec? */
311 ehci_create_ich9_with_companions(host_bus, 0x1d);
312 }
313
f5878b03 314 if (pcms->smbus_enabled) {
07981e8f
BB		 315 PCIDevice *smb;
316
be232eb0 317 /* TODO: Populate SPD eeprom data. */
07981e8f
BB		 318 smb = pci_create_simple_multifunction(host_bus,
319 PCI_DEVFN(ICH9_SMB_DEV,
320 ICH9_SMB_FUNC),
e052944a 321 TYPE_ICH9_SMB_DEVICE);
07981e8f
BB		 322 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c"));
323
ebe15582 324 smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
be232eb0 325 }
df2d8b3e 326
88076854 327 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
df2d8b3e
IY		 328
329 /* the rest devices to which pci devfn is automatically assigned */
330 pc_vga_init(isa_bus, host_bus);
7d6eff13 331 pc_nic_init(pcmc, isa_bus, host_bus);
5fe79386 332
f6a0d06b
EA		 333 if (machine->nvdimms_state->is_enabled) {
334 nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
5c94b826 335 x86_nvdimm_acpi_dsmio,
f0bb276b 336 x86ms->fw_cfg, OBJECT(pcms));
5fe79386 337 }
df2d8b3e
IY		 338}
339
99fbeafe
EH		 340#define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
341 static void pc_init_##suffix(MachineState *machine) \
342 { \
343 void (*compat)(MachineState *m) = (compatfn); \
344 if (compat) { \
345 compat(machine); \
346 } \
347 pc_q35_init(machine); \
348 } \
349 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
3458b2b0 350
9953f882 351
865906f7 352static void pc_q35_machine_options(MachineClass *m)
fddd179a 353{
4b9c264b 354 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
0a343a5a 355 pcmc->pci_root_uid = 0;
5719a179 356 pcmc->default_cpu_version = 1;
4b9c264b 357
fddd179a
EH		 358 m->family = "pc_q35";
359 m->desc = "Standard PC (Q35 + ICH9, 2009)";
fddd179a 360 m->units_per_default_bus = 1;
0b7783a7
EH		 361 m->default_machine_opts = "firmware=bios-256k.bin";
362 m->default_display = "std";
01ecdaa4 363 m->default_nic = "e1000e";
c87759ce 364 m->default_kernel_irqchip_split = false;
0b7783a7 365 m->no_floppy = 1;
e0001297 366 m->max_cpus = 1024;
545d8574 367 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
ef18310d
EH		 368 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
369 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
94692dcd 370 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
cab78e7c 371 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
fddd179a
EH		 372}
373
2b10a676 374static void pc_q35_9_0_machine_options(MachineClass *m)
87e896ab
EH		 375{
376 pc_q35_machine_options(m);
377 m->alias = "q35";
a6fd5b0e
MA		 378}
379
2b10a676
CH		 380DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL,
381 pc_q35_9_0_machine_options);
382
383static void pc_q35_8_2_machine_options(MachineClass *m)
384{
385 pc_q35_9_0_machine_options(m);
386 m->alias = NULL;
387 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len);
388 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len);
389}
390
95f5c89e
CH		 391DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL,
392 pc_q35_8_2_machine_options);
393
394static void pc_q35_8_1_machine_options(MachineClass *m)
395{
cf038650 396 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
95f5c89e
CH		 397 pc_q35_8_2_machine_options(m);
398 m->alias = NULL;
cf038650 399 pcmc->broken_32bit_mem_addr_check = true;
95f5c89e
CH		 400 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len);
401 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len);
402}
403
f9be4771
CH		 404DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL,
405 pc_q35_8_1_machine_options);
406
407static void pc_q35_8_0_machine_options(MachineClass *m)
408{
bf376f30
SS		 409 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
410
f9be4771 411 pc_q35_8_1_machine_options(m);
f9be4771
CH		 412 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
413 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
bf376f30
SS		 414
415 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */
416 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
e0001297 417 m->max_cpus = 288;
f9be4771
CH		 418}
419
db723c80
CH		 420DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL,
421 pc_q35_8_0_machine_options);
422
423static void pc_q35_7_2_machine_options(MachineClass *m)
424{
425 pc_q35_8_0_machine_options(m);
db723c80
CH		 426 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len);
427 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len);
428}
429
f514e147
CH		 430DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL,
431 pc_q35_7_2_machine_options);
432
433static void pc_q35_7_1_machine_options(MachineClass *m)
434{
435 pc_q35_7_2_machine_options(m);
f514e147
CH		 436 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len);
437 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len);
438}
439
0ca70366
CH		 440DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
441 pc_q35_7_1_machine_options);
442
443static void pc_q35_7_0_machine_options(MachineClass *m)
444{
67f7e426 445 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
0ca70366 446 pc_q35_7_1_machine_options(m);
b3e6982b 447 pcmc->enforce_amd_1tb_hole = false;
0ca70366
CH		 448 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
449 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
450}
451
01854af2
CH		 452DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL,
453 pc_q35_7_0_machine_options);
454
455static void pc_q35_6_2_machine_options(MachineClass *m)
456{
457 pc_q35_7_0_machine_options(m);
01854af2
CH		 458 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len);
459 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
460}
461
52e64f5b
YW		 462DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL,
463 pc_q35_6_2_machine_options);
464
465static void pc_q35_6_1_machine_options(MachineClass *m)
466{
467 pc_q35_6_2_machine_options(m);
52e64f5b
YW		 468 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
469 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
2b526199 470 m->smp_props.prefer_sockets = true;
52e64f5b
YW		 471}
472
da7e13c0
CH		 473DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
474 pc_q35_6_1_machine_options);
475
476static void pc_q35_6_0_machine_options(MachineClass *m)
477{
478 pc_q35_6_1_machine_options(m);
da7e13c0
CH		 479 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
480 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
481}
482
576a00bd
CH		 483DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
484 pc_q35_6_0_machine_options);
485
486static void pc_q35_5_2_machine_options(MachineClass *m)
487{
488 pc_q35_6_0_machine_options(m);
576a00bd
CH		 489 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
490 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
491}
492
3ff3c5d3
CH		 493DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
494 pc_q35_5_2_machine_options);
495
496static void pc_q35_5_1_machine_options(MachineClass *m)
497{
8700a984
VK		 498 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
499
3ff3c5d3 500 pc_q35_5_2_machine_options(m);
3ff3c5d3
CH		 501 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
502 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
8700a984 503 pcmc->kvmclock_create_always = false;
0a343a5a 504 pcmc->pci_root_uid = 1;
3ff3c5d3
CH		 505}
506
541aaa1d
CH		 507DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
508 pc_q35_5_1_machine_options);
509
510static void pc_q35_5_0_machine_options(MachineClass *m)
511{
512 pc_q35_5_1_machine_options(m);
32a354dc 513 m->numa_mem_supported = true;
541aaa1d
CH		 514 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
515 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
d110b6b4 516 m->auto_enable_numa_with_memdev = false;
541aaa1d
CH		 517}
518
3eb74d20
CH		 519DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
520 pc_q35_5_0_machine_options);
521
522static void pc_q35_4_2_machine_options(MachineClass *m)
523{
524 pc_q35_5_0_machine_options(m);
3eb74d20
CH		 525 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
526 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
527}
528
9aec2e52
CH		 529DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
530 pc_q35_4_2_machine_options);
531
532static void pc_q35_4_1_machine_options(MachineClass *m)
533{
534 pc_q35_4_2_machine_options(m);
9aec2e52
CH		 535 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
536 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
537}
538
9bf2650b
CH		 539DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
540 pc_q35_4_1_machine_options);
541
c87759ce 542static void pc_q35_4_0_1_machine_options(MachineClass *m)
9bf2650b 543{
0788a56b 544 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
9bf2650b 545 pc_q35_4_1_machine_options(m);
0788a56b 546 pcmc->default_cpu_version = CPU_VERSION_LEGACY;
8e8cbed0
GK		 547 /*
548 * This is the default machine for the 4.0-stable branch. It is basically
549 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
550 * 4.0 compat props.
551 */
552 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
553 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
c87759ce
AW		 554}
555
556DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
557 pc_q35_4_0_1_machine_options);
558
559static void pc_q35_4_0_machine_options(MachineClass *m)
560{
561 pc_q35_4_0_1_machine_options(m);
562 m->default_kernel_irqchip_split = true;
8e8cbed0 563 /* Compat props are applied by the 4.0.1 machine */
9bf2650b
CH		 564}
565
84e060bf
AW		 566DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
567 pc_q35_4_0_machine_options);
568
569static void pc_q35_3_1_machine_options(MachineClass *m)
570{
fda672b5
SG		 571 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
572
84e060bf 573 pc_q35_4_0_machine_options(m);
b2fc91db 574 m->default_kernel_irqchip_split = false;
7fccf2a0 575 m->smbus_no_migration_support = true;
fda672b5 576 pcmc->pvh_enabled = false;
abd93cc7
MAL		 577 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
578 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
84e060bf
AW		 579}
580
4a93722f
MAL		 581DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
582 pc_q35_3_1_machine_options);
583
584static void pc_q35_3_0_machine_options(MachineClass *m)
585{
586 pc_q35_3_1_machine_options(m);
ddb3235d
MAL		 587 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
588 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
4a93722f
MAL		 589}
590
aa78a16d
PM		 591DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
592 pc_q35_3_0_machine_options);
968ee4ad
BM		 593
594static void pc_q35_2_12_machine_options(MachineClass *m)
595{
aa78a16d 596 pc_q35_3_0_machine_options(m);
0d47310b
MAL		 597 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
598 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
968ee4ad
BM		 599}
600
df47ce8a
HZ		 601DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
602 pc_q35_2_12_machine_options);
603
604static void pc_q35_2_11_machine_options(MachineClass *m)
605{
606 pc_q35_2_12_machine_options(m);
01ecdaa4 607 m->default_nic = "e1000";
43df70a9
MAL		 608 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
609 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
df47ce8a
HZ		 610}
611
a6fd5b0e
MA		 612DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
613 pc_q35_2_11_machine_options);
614
615static void pc_q35_2_10_machine_options(MachineClass *m)
616{
617 pc_q35_2_11_machine_options(m);
503224f4
MAL		 618 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
619 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
7b8be49d 620 m->auto_enable_numa_with_memhp = false;
87e896ab
EH		 621}
622
465238d9
PX		 623DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
624 pc_q35_2_10_machine_options);
625
626static void pc_q35_2_9_machine_options(MachineClass *m)
627{
628 pc_q35_2_10_machine_options(m);
3e803152
MAL		 629 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
630 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
465238d9
PX		 631}
632
d580bd4b
EH		 633DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
634 pc_q35_2_9_machine_options);
635
636static void pc_q35_2_8_machine_options(MachineClass *m)
637{
638 pc_q35_2_9_machine_options(m);
edc24ccd
MAL		 639 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
640 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
d580bd4b
EH		 641}
642
a4d3c834
LM		 643DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
644 pc_q35_2_8_machine_options);
645
646static void pc_q35_2_7_machine_options(MachineClass *m)
647{
648 pc_q35_2_8_machine_options(m);
00d0f9fd 649 m->max_cpus = 255;
5a995064
MAL		 650 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
651 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
a4d3c834
LM		 652}
653
d86c1451
IM		 654DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
655 pc_q35_2_7_machine_options);
656
657static void pc_q35_2_6_machine_options(MachineClass *m)
658{
f014c974 659 X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
679dd1a9 660 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
88cbe073 661
d86c1451 662 pc_q35_2_7_machine_options(m);
679dd1a9 663 pcmc->legacy_cpu_hotplug = true;
f014c974 664 x86mc->fwcfg_dma_enabled = false;
ff8f261f
MAL		 665 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
666 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
d86c1451
IM		 667}
668
240240d5
EH		 669DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
670 pc_q35_2_6_machine_options);
671
672static void pc_q35_2_5_machine_options(MachineClass *m)
673{
2f34ebf2 674 X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
88cbe073 675
240240d5 676 pc_q35_2_6_machine_options(m);
2f34ebf2 677 x86mc->save_tsc_khz = false;
bab47d9a 678 m->legacy_fw_cfg_order = 1;
fe759610
MAL		 679 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
680 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
240240d5
EH		 681}
682
87e896ab
EH		 683DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
684 pc_q35_2_5_machine_options);
685
865906f7 686static void pc_q35_2_4_machine_options(MachineClass *m)
fddd179a 687{
2f8b5008 688 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
88cbe073 689
87e896ab 690 pc_q35_2_5_machine_options(m);
de796d93 691 m->hw_version = "2.4.0";
2f8b5008 692 pcmc->broken_reserved_end = true;
2f99b9c2
MAL		 693 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
694 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
fddd179a 695}
aeca6e8d 696
99fbeafe
EH		 697DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
698 pc_q35_2_4_machine_options);
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