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df2d8b3e IY |
1 | /* |
2 | * Q35 chipset based pc system emulator | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2009, 2010 | |
6 | * Isaku Yamahata <yamahata at valinux co jp> | |
7 | * VA Linux Systems Japan K.K. | |
8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
9 | * | |
10 | * This is based on pc.c, but heavily modified. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
13 | * of this software and associated documentation files (the "Software"), to deal | |
14 | * in the Software without restriction, including without limitation the rights | |
15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
16 | * copies of the Software, and to permit persons to whom the Software is | |
17 | * furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice shall be included in | |
20 | * all copies or substantial portions of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
28 | * THE SOFTWARE. | |
29 | */ | |
83c9f4ca | 30 | #include "hw/hw.h" |
04920fc0 | 31 | #include "hw/loader.h" |
9c17d615 | 32 | #include "sysemu/arch_init.h" |
0d09e41a | 33 | #include "hw/i2c/smbus.h" |
83c9f4ca | 34 | #include "hw/boards.h" |
0d09e41a PB |
35 | #include "hw/timer/mc146818rtc.h" |
36 | #include "hw/xen/xen.h" | |
9c17d615 | 37 | #include "sysemu/kvm.h" |
83c9f4ca | 38 | #include "hw/kvm/clock.h" |
0d09e41a | 39 | #include "hw/pci-host/q35.h" |
022c62cb | 40 | #include "exec/address-spaces.h" |
0d09e41a | 41 | #include "hw/i386/ich9.h" |
df2d8b3e IY |
42 | #include "hw/ide/pci.h" |
43 | #include "hw/ide/ahci.h" | |
44 | #include "hw/usb.h" | |
f0513d2c | 45 | #include "hw/cpu/icc_bus.h" |
df2d8b3e IY |
46 | |
47 | /* ICH9 AHCI has 6 ports */ | |
48 | #define MAX_SATA_PORTS 6 | |
49 | ||
7f1bb742 | 50 | static bool has_pci_info; |
72c194f7 | 51 | static bool has_acpi_build = true; |
3ab135f3 | 52 | |
df2d8b3e IY |
53 | /* PC hardware initialisation */ |
54 | static void pc_q35_init(QEMUMachineInitArgs *args) | |
55 | { | |
df2d8b3e IY |
56 | ram_addr_t below_4g_mem_size, above_4g_mem_size; |
57 | Q35PCIHost *q35_host; | |
ce88812f | 58 | PCIHostState *phb; |
df2d8b3e IY |
59 | PCIBus *host_bus; |
60 | PCIDevice *lpc; | |
61 | BusState *idebus[MAX_SATA_PORTS]; | |
62 | ISADevice *rtc_state; | |
63 | ISADevice *floppy; | |
64 | MemoryRegion *pci_memory; | |
65 | MemoryRegion *rom_memory; | |
66 | MemoryRegion *ram_memory; | |
67 | GSIState *gsi_state; | |
68 | ISABus *isa_bus; | |
69 | int pci_enabled = 1; | |
70 | qemu_irq *cpu_irq; | |
71 | qemu_irq *gsi; | |
72 | qemu_irq *i8259; | |
73 | int i; | |
74 | ICH9LPCState *ich9_lpc; | |
75 | PCIDevice *ahci; | |
f0513d2c | 76 | DeviceState *icc_bridge; |
3459a625 | 77 | PcGuestInfo *guest_info; |
f0513d2c | 78 | |
254c1282 AP |
79 | if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) { |
80 | fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); | |
81 | exit(1); | |
82 | } | |
83 | ||
f0513d2c IM |
84 | icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); |
85 | object_property_add_child(qdev_get_machine(), "icc-bridge", | |
86 | OBJECT(icc_bridge), NULL); | |
df2d8b3e | 87 | |
3b6fb9ca | 88 | pc_cpus_init(args->cpu_model, icc_bridge); |
f7e4dd6c | 89 | pc_acpi_init("q35-acpi-dsdt.aml"); |
df2d8b3e | 90 | |
21022c92 JK |
91 | kvmclock_create(); |
92 | ||
3b6fb9ca MA |
93 | if (args->ram_size >= 0xb0000000) { |
94 | above_4g_mem_size = args->ram_size - 0xb0000000; | |
df2d8b3e IY |
95 | below_4g_mem_size = 0xb0000000; |
96 | } else { | |
97 | above_4g_mem_size = 0; | |
3b6fb9ca | 98 | below_4g_mem_size = args->ram_size; |
df2d8b3e IY |
99 | } |
100 | ||
101 | /* pci enabled */ | |
102 | if (pci_enabled) { | |
103 | pci_memory = g_new(MemoryRegion, 1); | |
2c9b15ca | 104 | memory_region_init(pci_memory, NULL, "pci", INT64_MAX); |
df2d8b3e IY |
105 | rom_memory = pci_memory; |
106 | } else { | |
107 | pci_memory = NULL; | |
108 | rom_memory = get_system_memory(); | |
109 | } | |
110 | ||
3459a625 | 111 | guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); |
f8c457b8 | 112 | guest_info->has_pci_info = has_pci_info; |
6dd2a5c9 | 113 | guest_info->isapc_ram_fw = false; |
72c194f7 | 114 | guest_info->has_acpi_build = has_acpi_build; |
3459a625 | 115 | |
df2d8b3e IY |
116 | /* allocate ram and load rom/bios */ |
117 | if (!xen_enabled()) { | |
3b6fb9ca MA |
118 | pc_memory_init(get_system_memory(), |
119 | args->kernel_filename, args->kernel_cmdline, | |
120 | args->initrd_filename, | |
121 | below_4g_mem_size, above_4g_mem_size, | |
3459a625 | 122 | rom_memory, &ram_memory, guest_info); |
df2d8b3e IY |
123 | } |
124 | ||
125 | /* irq lines */ | |
126 | gsi_state = g_malloc0(sizeof(*gsi_state)); | |
127 | if (kvm_irqchip_in_kernel()) { | |
128 | kvm_pc_setup_irq_routing(pci_enabled); | |
129 | gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, | |
130 | GSI_NUM_PINS); | |
131 | } else { | |
132 | gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); | |
133 | } | |
134 | ||
135 | /* create pci host bus */ | |
136 | q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); | |
137 | ||
c52dc697 | 138 | object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); |
df2d8b3e IY |
139 | q35_host->mch.ram_memory = ram_memory; |
140 | q35_host->mch.pci_address_space = pci_memory; | |
141 | q35_host->mch.system_memory = get_system_memory(); | |
c7e775e4 | 142 | q35_host->mch.address_space_io = get_system_io(); |
df2d8b3e IY |
143 | q35_host->mch.below_4g_mem_size = below_4g_mem_size; |
144 | q35_host->mch.above_4g_mem_size = above_4g_mem_size; | |
3459a625 | 145 | q35_host->mch.guest_info = guest_info; |
df2d8b3e IY |
146 | /* pci */ |
147 | qdev_init_nofail(DEVICE(q35_host)); | |
ce88812f HT |
148 | phb = PCI_HOST_BRIDGE(q35_host); |
149 | host_bus = phb->bus; | |
df2d8b3e IY |
150 | /* create ISA bus */ |
151 | lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, | |
152 | ICH9_LPC_FUNC), true, | |
153 | TYPE_ICH9_LPC_DEVICE); | |
154 | ich9_lpc = ICH9_LPC_DEVICE(lpc); | |
155 | ich9_lpc->pic = gsi; | |
156 | ich9_lpc->ioapic = gsi_state->ioapic_irq; | |
157 | pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, | |
158 | ICH9_LPC_NB_PIRQS); | |
91c3f2f0 | 159 | pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); |
df2d8b3e IY |
160 | isa_bus = ich9_lpc->isa_bus; |
161 | ||
162 | /*end early*/ | |
163 | isa_bus_irqs(isa_bus, gsi); | |
164 | ||
165 | if (kvm_irqchip_in_kernel()) { | |
166 | i8259 = kvm_i8259_init(isa_bus); | |
167 | } else if (xen_enabled()) { | |
168 | i8259 = xen_interrupt_controller_init(); | |
169 | } else { | |
170 | cpu_irq = pc_allocate_cpu_irq(); | |
171 | i8259 = i8259_init(isa_bus, cpu_irq[0]); | |
172 | } | |
173 | ||
174 | for (i = 0; i < ISA_NUM_IRQS; i++) { | |
175 | gsi_state->i8259_irq[i] = i8259[i]; | |
176 | } | |
177 | if (pci_enabled) { | |
178 | ioapic_init_gsi(gsi_state, NULL); | |
179 | } | |
f0513d2c | 180 | qdev_init_nofail(icc_bridge); |
df2d8b3e IY |
181 | |
182 | pc_register_ferr_irq(gsi[13]); | |
183 | ||
184 | /* init basic PC hardware */ | |
185 | pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); | |
186 | ||
187 | /* connect pm stuff to lpc */ | |
a3ac6b53 | 188 | ich9_lpc_pm_init(lpc); |
df2d8b3e IY |
189 | |
190 | /* ahci and SATA device, for q35 1 ahci controller is built-in */ | |
191 | ahci = pci_create_simple_multifunction(host_bus, | |
192 | PCI_DEVFN(ICH9_SATA1_DEV, | |
193 | ICH9_SATA1_FUNC), | |
194 | true, "ich9-ahci"); | |
195 | idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); | |
196 | idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); | |
197 | ||
198 | if (usb_enabled(false)) { | |
199 | /* Should we create 6 UHCI according to ich9 spec? */ | |
200 | ehci_create_ich9_with_companions(host_bus, 0x1d); | |
201 | } | |
202 | ||
203 | /* TODO: Populate SPD eeprom data. */ | |
204 | smbus_eeprom_init(ich9_smb_init(host_bus, | |
205 | PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), | |
206 | 0xb100), | |
207 | 8, NULL, 0); | |
208 | ||
c1654732 | 209 | pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order, |
df2d8b3e IY |
210 | floppy, idebus[0], idebus[1], rtc_state); |
211 | ||
212 | /* the rest devices to which pci devfn is automatically assigned */ | |
213 | pc_vga_init(isa_bus, host_bus); | |
df2d8b3e IY |
214 | pc_nic_init(isa_bus, host_bus); |
215 | if (pci_enabled) { | |
216 | pc_pci_device_init(host_bus); | |
217 | } | |
218 | } | |
219 | ||
89b439f3 | 220 | static void pc_compat_1_6(QEMUMachineInitArgs *args) |
f8c457b8 MT |
221 | { |
222 | has_pci_info = false; | |
04920fc0 | 223 | rom_file_in_ram = false; |
72c194f7 | 224 | has_acpi_build = false; |
f8c457b8 MT |
225 | } |
226 | ||
89b439f3 | 227 | static void pc_compat_1_5(QEMUMachineInitArgs *args) |
9604f70f | 228 | { |
89b439f3 | 229 | pc_compat_1_6(args); |
9604f70f MT |
230 | } |
231 | ||
89b439f3 | 232 | static void pc_compat_1_4(QEMUMachineInitArgs *args) |
9953f882 | 233 | { |
396f79f4 | 234 | pc_compat_1_5(args); |
4458c236 | 235 | x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); |
56383703 | 236 | x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); |
89b439f3 EH |
237 | } |
238 | ||
239 | static void pc_q35_init_1_6(QEMUMachineInitArgs *args) | |
240 | { | |
241 | pc_compat_1_6(args); | |
242 | pc_q35_init(args); | |
243 | } | |
244 | ||
245 | static void pc_q35_init_1_5(QEMUMachineInitArgs *args) | |
246 | { | |
247 | pc_compat_1_5(args); | |
248 | pc_q35_init(args); | |
249 | } | |
250 | ||
251 | static void pc_q35_init_1_4(QEMUMachineInitArgs *args) | |
252 | { | |
253 | pc_compat_1_4(args); | |
254 | pc_q35_init(args); | |
9953f882 MA |
255 | } |
256 | ||
a0dba644 MT |
257 | #define PC_Q35_MACHINE_OPTIONS \ |
258 | PC_DEFAULT_MACHINE_OPTIONS, \ | |
259 | .desc = "Standard PC (Q35 + ICH9, 2009)", \ | |
260 | .hot_add_cpu = pc_hot_add_cpu | |
261 | ||
e9845f09 VM |
262 | #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS |
263 | ||
264 | static QEMUMachine pc_q35_machine_v1_7 = { | |
265 | PC_Q35_1_7_MACHINE_OPTIONS, | |
266 | .name = "pc-q35-1.7", | |
267 | .alias = "q35", | |
268 | .init = pc_q35_init, | |
269 | }; | |
270 | ||
a0dba644 MT |
271 | #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS |
272 | ||
45053fde | 273 | static QEMUMachine pc_q35_machine_v1_6 = { |
a0dba644 | 274 | PC_Q35_1_6_MACHINE_OPTIONS, |
45053fde | 275 | .name = "pc-q35-1.6", |
9604f70f | 276 | .init = pc_q35_init_1_6, |
e9845f09 VM |
277 | .compat_props = (GlobalProperty[]) { |
278 | PC_COMPAT_1_6, | |
279 | { /* end of list */ } | |
280 | }, | |
45053fde EH |
281 | }; |
282 | ||
bf3caa3d | 283 | static QEMUMachine pc_q35_machine_v1_5 = { |
a0dba644 | 284 | PC_Q35_1_6_MACHINE_OPTIONS, |
bf3caa3d | 285 | .name = "pc-q35-1.5", |
f8c457b8 | 286 | .init = pc_q35_init_1_5, |
ffce9ebb EH |
287 | .compat_props = (GlobalProperty[]) { |
288 | PC_COMPAT_1_5, | |
289 | { /* end of list */ } | |
290 | }, | |
df2d8b3e IY |
291 | }; |
292 | ||
a0dba644 MT |
293 | #define PC_Q35_1_4_MACHINE_OPTIONS \ |
294 | PC_Q35_1_6_MACHINE_OPTIONS, \ | |
295 | .hot_add_cpu = NULL | |
296 | ||
bf3caa3d | 297 | static QEMUMachine pc_q35_machine_v1_4 = { |
a0dba644 | 298 | PC_Q35_1_4_MACHINE_OPTIONS, |
bf3caa3d | 299 | .name = "pc-q35-1.4", |
9953f882 | 300 | .init = pc_q35_init_1_4, |
bf3caa3d PB |
301 | .compat_props = (GlobalProperty[]) { |
302 | PC_COMPAT_1_4, | |
303 | { /* end of list */ } | |
304 | }, | |
bf3caa3d PB |
305 | }; |
306 | ||
df2d8b3e IY |
307 | static void pc_q35_machine_init(void) |
308 | { | |
e9845f09 | 309 | qemu_register_machine(&pc_q35_machine_v1_7); |
45053fde | 310 | qemu_register_machine(&pc_q35_machine_v1_6); |
bf3caa3d PB |
311 | qemu_register_machine(&pc_q35_machine_v1_5); |
312 | qemu_register_machine(&pc_q35_machine_v1_4); | |
df2d8b3e IY |
313 | } |
314 | ||
315 | machine_init(pc_q35_machine_init); |