[qemu.git] / hw / i8259.c

/*
 * QEMU 8259 interrupt controller emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pc.h"
#include "isa.h"
#include "monitor.h"
#include "qemu-timer.h"

/* debug PIC */
//#define DEBUG_PIC

#ifdef DEBUG_PIC
#define DPRINTF(fmt, ...)                                       \
    do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

//#define DEBUG_IRQ_LATENCY
//#define DEBUG_IRQ_COUNT

typedef struct PicState {
    uint8_t last_irr; /* edge detection */
    uint8_t irr; /* interrupt request register */
    uint8_t imr; /* interrupt mask register */
    uint8_t isr; /* interrupt service register */
    uint8_t priority_add; /* highest irq priority */
    uint8_t irq_base;
    uint8_t read_reg_select;
    uint8_t poll;
    uint8_t special_mask;
    uint8_t init_state;
    uint8_t auto_eoi;
    uint8_t rotate_on_auto_eoi;
    uint8_t special_fully_nested_mode;
    uint8_t init4; /* true if 4 byte init */
    uint8_t single_mode; /* true if slave pic is not initialized */
    uint8_t elcr; /* PIIX edge/trigger selection*/
    uint8_t elcr_mask;
    PicState2 *pics_state;
} PicState;

struct PicState2 {
    /* 0 is master pic, 1 is slave pic */
    /* XXX: better separation between the two pics */
    PicState pics[2];
    qemu_irq parent_irq;
    void *irq_request_opaque;
};

#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
static int irq_level[16];
#endif
#ifdef DEBUG_IRQ_COUNT
static uint64_t irq_count[16];
#endif
PicState2 *isa_pic;

/* set irq level. If an edge is detected, then the IRR is set to 1 */
static inline void pic_set_irq1(PicState *s, int irq, int level)
{
    int mask;
    mask = 1 << irq;
    if (s->elcr & mask) {
        /* level triggered */
        if (level) {
            s->irr |= mask;
            s->last_irr |= mask;
        } else {
            s->irr &= ~mask;
            s->last_irr &= ~mask;
        }
    } else {
        /* edge triggered */
        if (level) {
            if ((s->last_irr & mask) == 0)
                s->irr |= mask;
            s->last_irr |= mask;
        } else {
            s->last_irr &= ~mask;
        }
    }
}

/* return the highest priority found in mask (highest = smallest
   number). Return 8 if no irq */
static inline int get_priority(PicState *s, int mask)
{
    int priority;
    if (mask == 0)
        return 8;
    priority = 0;
    while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
        priority++;
    return priority;
}

/* return the pic wanted interrupt. return -1 if none */
static int pic_get_irq(PicState *s)
{
    int mask, cur_priority, priority;

    mask = s->irr & ~s->imr;
    priority = get_priority(s, mask);
    if (priority == 8)
        return -1;
    /* compute current priority. If special fully nested mode on the
       master, the IRQ coming from the slave is not taken into account
       for the priority computation. */
    mask = s->isr;
    if (s->special_mask)
        mask &= ~s->imr;
    if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
        mask &= ~(1 << 2);
    cur_priority = get_priority(s, mask);
    if (priority < cur_priority) {
        /* higher priority found: an irq should be generated */
        return (priority + s->priority_add) & 7;
    } else {
        return -1;
    }
}

/* raise irq to CPU if necessary. must be called every time the active
   irq may change */
/* XXX: should not export it, but it is needed for an APIC kludge */
void pic_update_irq(PicState2 *s)
{
    int irq2, irq;

    /* first look at slave pic */
    irq2 = pic_get_irq(&s->pics[1]);
    if (irq2 >= 0) {
        /* if irq request by slave pic, signal master PIC */
        pic_set_irq1(&s->pics[0], 2, 1);
        pic_set_irq1(&s->pics[0], 2, 0);
    }
    /* look at requested irq */
    irq = pic_get_irq(&s->pics[0]);
    if (irq >= 0) {
#if defined(DEBUG_PIC)
        {
            int i;
            for(i = 0; i < 2; i++) {
                printf("pic%d: imr=%x irr=%x padd=%d\n",
                       i, s->pics[i].imr, s->pics[i].irr,
                       s->pics[i].priority_add);

            }
        }
        printf("pic: cpu_interrupt\n");
#endif
        qemu_irq_raise(s->parent_irq);
    }

/* all targets should do this rather than acking the IRQ in the cpu */
#if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
    else {
        qemu_irq_lower(s->parent_irq);
    }
#endif
}

#ifdef DEBUG_IRQ_LATENCY
int64_t irq_time[16];
#endif

static void i8259_set_irq(void *opaque, int irq, int level)
{
    PicState2 *s = opaque;

#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
    if (level != irq_level[irq]) {
        DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
        irq_level[irq] = level;
#ifdef DEBUG_IRQ_COUNT
	if (level == 1)
	    irq_count[irq]++;
#endif
    }
#endif
#ifdef DEBUG_IRQ_LATENCY
    if (level) {
        irq_time[irq] = qemu_get_clock_ns(vm_clock);
    }
#endif
    pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
    pic_update_irq(s);
}

/* acknowledge interrupt 'irq' */
static inline void pic_intack(PicState *s, int irq)
{
    if (s->auto_eoi) {
        if (s->rotate_on_auto_eoi)
            s->priority_add = (irq + 1) & 7;
    } else {
        s->isr |= (1 << irq);
    }
    /* We don't clear a level sensitive interrupt here */
    if (!(s->elcr & (1 << irq)))
        s->irr &= ~(1 << irq);
}

int pic_read_irq(PicState2 *s)
{
    int irq, irq2, intno;

    irq = pic_get_irq(&s->pics[0]);
    if (irq >= 0) {
        pic_intack(&s->pics[0], irq);
        if (irq == 2) {
            irq2 = pic_get_irq(&s->pics[1]);
            if (irq2 >= 0) {
                pic_intack(&s->pics[1], irq2);
            } else {
                /* spurious IRQ on slave controller */
                irq2 = 7;
            }
            intno = s->pics[1].irq_base + irq2;
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
            irq = irq2 + 8;
#endif
        } else {
            intno = s->pics[0].irq_base + irq;
        }
    } else {
        /* spurious IRQ on host controller */
        irq = 7;
        intno = s->pics[0].irq_base + irq;
    }
    pic_update_irq(s);

#ifdef DEBUG_IRQ_LATENCY
    printf("IRQ%d latency=%0.3fus\n",
           irq,
           (double)(qemu_get_clock_ns(vm_clock) -
                    irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
#endif
    DPRINTF("pic_interrupt: irq=%d\n", irq);
    return intno;
}

static void pic_reset(void *opaque)
{
    PicState *s = opaque;

    s->last_irr = 0;
    s->irr = 0;
    s->imr = 0;
    s->isr = 0;
    s->priority_add = 0;
    s->irq_base = 0;
    s->read_reg_select = 0;
    s->poll = 0;
    s->special_mask = 0;
    s->init_state = 0;
    s->auto_eoi = 0;
    s->rotate_on_auto_eoi = 0;
    s->special_fully_nested_mode = 0;
    s->init4 = 0;
    s->single_mode = 0;
    /* Note: ELCR is not reset */
}

static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    PicState *s = opaque;
    int priority, cmd, irq;

    DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
    addr &= 1;
    if (addr == 0) {
        if (val & 0x10) {
            /* init */
            pic_reset(s);
            /* deassert a pending interrupt */
            qemu_irq_lower(s->pics_state->parent_irq);
            s->init_state = 1;
            s->init4 = val & 1;
            s->single_mode = val & 2;
            if (val & 0x08)
                hw_error("level sensitive irq not supported");
        } else if (val & 0x08) {
            if (val & 0x04)
                s->poll = 1;
            if (val & 0x02)
                s->read_reg_select = val & 1;
            if (val & 0x40)
                s->special_mask = (val >> 5) & 1;
        } else {
            cmd = val >> 5;
            switch(cmd) {
            case 0:
            case 4:
                s->rotate_on_auto_eoi = cmd >> 2;
                break;
            case 1: /* end of interrupt */
            case 5:
                priority = get_priority(s, s->isr);
                if (priority != 8) {
                    irq = (priority + s->priority_add) & 7;
                    s->isr &= ~(1 << irq);
                    if (cmd == 5)
                        s->priority_add = (irq + 1) & 7;
                    pic_update_irq(s->pics_state);
                }
                break;
            case 3:
                irq = val & 7;
                s->isr &= ~(1 << irq);
                pic_update_irq(s->pics_state);
                break;
            case 6:
                s->priority_add = (val + 1) & 7;
                pic_update_irq(s->pics_state);
                break;
            case 7:
                irq = val & 7;
                s->isr &= ~(1 << irq);
                s->priority_add = (irq + 1) & 7;
                pic_update_irq(s->pics_state);
                break;
            default:
                /* no operation */
                break;
            }
        }
    } else {
        switch(s->init_state) {
        case 0:
            /* normal mode */
            s->imr = val;
            pic_update_irq(s->pics_state);
            break;
        case 1:
            s->irq_base = val & 0xf8;
            s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
            break;
        case 2:
            if (s->init4) {
                s->init_state = 3;
            } else {
                s->init_state = 0;
            }
            break;
        case 3:
            s->special_fully_nested_mode = (val >> 4) & 1;
            s->auto_eoi = (val >> 1) & 1;
            s->init_state = 0;
            break;
        }
    }
}

static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
{
    int ret;

    ret = pic_get_irq(s);
    if (ret >= 0) {
        if (addr1 >> 7) {
            s->pics_state->pics[0].isr &= ~(1 << 2);
            s->pics_state->pics[0].irr &= ~(1 << 2);
        }
        s->irr &= ~(1 << ret);
        s->isr &= ~(1 << ret);
        if (addr1 >> 7 || ret != 2)
            pic_update_irq(s->pics_state);
    } else {
        ret = 0x07;
        pic_update_irq(s->pics_state);
    }

    return ret;
}

static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
{
    PicState *s = opaque;
    unsigned int addr;
    int ret;

    addr = addr1;
    addr &= 1;
    if (s->poll) {
        ret = pic_poll_read(s, addr1);
        s->poll = 0;
    } else {
        if (addr == 0) {
            if (s->read_reg_select)
                ret = s->isr;
            else
                ret = s->irr;
        } else {
            ret = s->imr;
        }
    }
    DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret);
    return ret;
}

/* memory mapped interrupt status */
/* XXX: may be the same than pic_read_irq() */
uint32_t pic_intack_read(PicState2 *s)
{
    int ret;

    ret = pic_poll_read(&s->pics[0], 0x00);
    if (ret == 2)
        ret = pic_poll_read(&s->pics[1], 0x80) + 8;
    /* Prepare for ISR read */
    s->pics[0].read_reg_select = 1;

    return ret;
}

static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    PicState *s = opaque;
    s->elcr = val & s->elcr_mask;
}

static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
{
    PicState *s = opaque;
    return s->elcr;
}

static const VMStateDescription vmstate_pic = {
    .name = "i8259",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(last_irr, PicState),
        VMSTATE_UINT8(irr, PicState),
        VMSTATE_UINT8(imr, PicState),
        VMSTATE_UINT8(isr, PicState),
        VMSTATE_UINT8(priority_add, PicState),
        VMSTATE_UINT8(irq_base, PicState),
        VMSTATE_UINT8(read_reg_select, PicState),
        VMSTATE_UINT8(poll, PicState),
        VMSTATE_UINT8(special_mask, PicState),
        VMSTATE_UINT8(init_state, PicState),
        VMSTATE_UINT8(auto_eoi, PicState),
        VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
        VMSTATE_UINT8(special_fully_nested_mode, PicState),
        VMSTATE_UINT8(init4, PicState),
        VMSTATE_UINT8(single_mode, PicState),
        VMSTATE_UINT8(elcr, PicState),
        VMSTATE_END_OF_LIST()
    }
};

/* XXX: add generic master/slave system */
static void pic_init1(int io_addr, int elcr_addr, PicState *s)
{
    register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
    register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
    if (elcr_addr >= 0) {
        register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
        register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
    }
    vmstate_register(NULL, io_addr, &vmstate_pic, s);
    qemu_register_reset(pic_reset, s);
}

void pic_info(Monitor *mon)
{
    int i;
    PicState *s;

    if (!isa_pic)
        return;

    for(i=0;i<2;i++) {
        s = &isa_pic->pics[i];
        monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
                       "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
                       i, s->irr, s->imr, s->isr, s->priority_add,
                       s->irq_base, s->read_reg_select, s->elcr,
                       s->special_fully_nested_mode);
    }
}

void irq_info(Monitor *mon)
{
#ifndef DEBUG_IRQ_COUNT
    monitor_printf(mon, "irq statistic code not compiled.\n");
#else
    int i;
    int64_t count;

    monitor_printf(mon, "IRQ statistics:\n");
    for (i = 0; i < 16; i++) {
        count = irq_count[i];
        if (count > 0)
            monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
    }
#endif
}

qemu_irq *i8259_init(qemu_irq parent_irq)
{
    PicState2 *s;

    s = qemu_mallocz(sizeof(PicState2));
    pic_init1(0x20, 0x4d0, &s->pics[0]);
    pic_init1(0xa0, 0x4d1, &s->pics[1]);
    s->pics[0].elcr_mask = 0xf8;
    s->pics[1].elcr_mask = 0xde;
    s->parent_irq = parent_irq;
    s->pics[0].pics_state = s;
    s->pics[1].pics_state = s;
    isa_pic = s;
    return qemu_allocate_irqs(i8259_set_irq, s, 16);
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 8259 interrupt controller emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "pc.h"
	26	#include "isa.h"
376253ec	27	#include "monitor.h"
0bf9e31a	28	#include "qemu-timer.h"
80cabfad FB	29
	30	/* debug PIC */
	31	//#define DEBUG_PIC
	32
8ac02ff8 BS	33	#ifdef DEBUG_PIC
	34	#define DPRINTF(fmt, ...) \
	35	do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
	36	#else
	37	#define DPRINTF(fmt, ...)
	38	#endif
	39
b41a2cd1	40	//#define DEBUG_IRQ_LATENCY
4a0fb71e	41	//#define DEBUG_IRQ_COUNT
b41a2cd1	42
80cabfad FB	43	typedef struct PicState {
	44	uint8_t last_irr; /* edge detection */
	45	uint8_t irr; /* interrupt request register */
	46	uint8_t imr; /* interrupt mask register */
	47	uint8_t isr; /* interrupt service register */
	48	uint8_t priority_add; /* highest irq priority */
	49	uint8_t irq_base;
	50	uint8_t read_reg_select;
	51	uint8_t poll;
	52	uint8_t special_mask;
	53	uint8_t init_state;
	54	uint8_t auto_eoi;
	55	uint8_t rotate_on_auto_eoi;
	56	uint8_t special_fully_nested_mode;
	57	uint8_t init4; /* true if 4 byte init */
2053152b	58	uint8_t single_mode; /* true if slave pic is not initialized */
660de336 FB	59	uint8_t elcr; /* PIIX edge/trigger selection*/
660de336 FB	60	uint8_t elcr_mask;
3de388f6	61	PicState2 *pics_state;
80cabfad FB	62	} PicState;
80cabfad FB	63
3de388f6 FB	64	struct PicState2 {
	65	/* 0 is master pic, 1 is slave pic */
	66	/* XXX: better separation between the two pics */
	67	PicState pics[2];
d537cf6c	68	qemu_irq parent_irq;
3de388f6 FB	69	void *irq_request_opaque;
3de388f6 FB	70	};
80cabfad	71
4a0fb71e FB	72	#if defined(DEBUG_PIC) \|\| defined (DEBUG_IRQ_COUNT)
	73	static int irq_level[16];
	74	#endif
	75	#ifdef DEBUG_IRQ_COUNT
	76	static uint64_t irq_count[16];
	77	#endif
fbe3288d	78	PicState2 *isa_pic;
4a0fb71e	79
80cabfad FB	80	/* set irq level. If an edge is detected, then the IRR is set to 1 */
	81	static inline void pic_set_irq1(PicState *s, int irq, int level)
	82	{
	83	int mask;
	84	mask = 1 << irq;
660de336 FB	85	if (s->elcr & mask) {
	86	/* level triggered */
	87	if (level) {
80cabfad	88	s->irr \|= mask;
660de336 FB	89	s->last_irr \|= mask;
	90	} else {
	91	s->irr &= ~mask;
	92	s->last_irr &= ~mask;
	93	}
80cabfad	94	} else {
660de336 FB	95	/* edge triggered */
	96	if (level) {
	97	if ((s->last_irr & mask) == 0)
	98	s->irr \|= mask;
	99	s->last_irr \|= mask;
	100	} else {
	101	s->last_irr &= ~mask;
	102	}
80cabfad FB	103	}
	104	}
	105
	106	/* return the highest priority found in mask (highest = smallest
	107	number). Return 8 if no irq */
	108	static inline int get_priority(PicState *s, int mask)
	109	{
	110	int priority;
	111	if (mask == 0)
	112	return 8;
	113	priority = 0;
	114	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
	115	priority++;
	116	return priority;
	117	}
	118
	119	/* return the pic wanted interrupt. return -1 if none */
	120	static int pic_get_irq(PicState *s)
	121	{
	122	int mask, cur_priority, priority;
	123
	124	mask = s->irr & ~s->imr;
	125	priority = get_priority(s, mask);
	126	if (priority == 8)
	127	return -1;
	128	/* compute current priority. If special fully nested mode on the
	129	master, the IRQ coming from the slave is not taken into account
	130	for the priority computation. */
	131	mask = s->isr;
84678711 AZ	132	if (s->special_mask)
84678711 AZ	133	mask &= ~s->imr;
3de388f6	134	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
80cabfad FB	135	mask &= ~(1 << 2);
	136	cur_priority = get_priority(s, mask);
	137	if (priority < cur_priority) {
	138	/* higher priority found: an irq should be generated */
	139	return (priority + s->priority_add) & 7;
	140	} else {
	141	return -1;
	142	}
	143	}
	144
	145	/* raise irq to CPU if necessary. must be called every time the active
	146	irq may change */
3de388f6 FB	147	/* XXX: should not export it, but it is needed for an APIC kludge */
3de388f6 FB	148	void pic_update_irq(PicState2 *s)
80cabfad FB	149	{
	150	int irq2, irq;
	151
	152	/* first look at slave pic */
3de388f6	153	irq2 = pic_get_irq(&s->pics[1]);
80cabfad FB	154	if (irq2 >= 0) {
80cabfad FB	155	/* if irq request by slave pic, signal master PIC */
3de388f6 FB	156	pic_set_irq1(&s->pics[0], 2, 1);
3de388f6 FB	157	pic_set_irq1(&s->pics[0], 2, 0);
80cabfad FB	158	}
80cabfad FB	159	/* look at requested irq */
3de388f6	160	irq = pic_get_irq(&s->pics[0]);
80cabfad	161	if (irq >= 0) {
80cabfad FB	162	#if defined(DEBUG_PIC)
	163	{
	164	int i;
	165	for(i = 0; i < 2; i++) {
5fafdf24 TS	166	printf("pic%d: imr=%x irr=%x padd=%d\n",
5fafdf24 TS	167	i, s->pics[i].imr, s->pics[i].irr,
3de388f6	168	s->pics[i].priority_add);
3b46e624	169
80cabfad FB	170	}
80cabfad FB	171	}
2444ca41	172	printf("pic: cpu_interrupt\n");
80cabfad	173	#endif
d537cf6c	174	qemu_irq_raise(s->parent_irq);
80cabfad	175	}
4de9b249 TS	176
4de9b249 TS	177	/* all targets should do this rather than acking the IRQ in the cpu */
29463b24	178	#if defined(TARGET_MIPS) \|\| defined(TARGET_PPC) \|\| defined(TARGET_ALPHA)
4de9b249	179	else {
d537cf6c	180	qemu_irq_lower(s->parent_irq);
4de9b249 TS	181	}
4de9b249 TS	182	#endif
80cabfad FB	183	}
	184
	185	#ifdef DEBUG_IRQ_LATENCY
	186	int64_t irq_time[16];
80cabfad	187	#endif
80cabfad	188
9596ebb7	189	static void i8259_set_irq(void *opaque, int irq, int level)
80cabfad	190	{
3de388f6 FB	191	PicState2 *s = opaque;
3de388f6 FB	192
4a0fb71e	193	#if defined(DEBUG_PIC) \|\| defined(DEBUG_IRQ_COUNT)
80cabfad	194	if (level != irq_level[irq]) {
8ac02ff8	195	DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
80cabfad	196	irq_level[irq] = level;
4a0fb71e FB	197	#ifdef DEBUG_IRQ_COUNT
	198	if (level == 1)
	199	irq_count[irq]++;
	200	#endif
80cabfad FB	201	}
	202	#endif
	203	#ifdef DEBUG_IRQ_LATENCY
	204	if (level) {
74475455	205	irq_time[irq] = qemu_get_clock_ns(vm_clock);
80cabfad FB	206	}
80cabfad FB	207	#endif
3de388f6 FB	208	pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
3de388f6 FB	209	pic_update_irq(s);
80cabfad FB	210	}
	211
	212	/* acknowledge interrupt 'irq' */
	213	static inline void pic_intack(PicState *s, int irq)
	214	{
	215	if (s->auto_eoi) {
	216	if (s->rotate_on_auto_eoi)
	217	s->priority_add = (irq + 1) & 7;
	218	} else {
	219	s->isr \|= (1 << irq);
	220	}
0ecf89aa FB	221	/* We don't clear a level sensitive interrupt here */
	222	if (!(s->elcr & (1 << irq)))
	223	s->irr &= ~(1 << irq);
80cabfad FB	224	}
80cabfad FB	225
3de388f6	226	int pic_read_irq(PicState2 *s)
80cabfad FB	227	{
	228	int irq, irq2, intno;
	229
3de388f6	230	irq = pic_get_irq(&s->pics[0]);
15aeac38	231	if (irq >= 0) {
3de388f6	232	pic_intack(&s->pics[0], irq);
15aeac38	233	if (irq == 2) {
3de388f6	234	irq2 = pic_get_irq(&s->pics[1]);
15aeac38	235	if (irq2 >= 0) {
3de388f6	236	pic_intack(&s->pics[1], irq2);
15aeac38 FB	237	} else {
	238	/* spurious IRQ on slave controller */
	239	irq2 = 7;
	240	}
3de388f6	241	intno = s->pics[1].irq_base + irq2;
7f5b7d3e	242	#if defined(DEBUG_PIC) \|\| defined(DEBUG_IRQ_LATENCY)
15aeac38	243	irq = irq2 + 8;
7f5b7d3e	244	#endif
15aeac38	245	} else {
3de388f6	246	intno = s->pics[0].irq_base + irq;
15aeac38 FB	247	}
	248	} else {
	249	/* spurious IRQ on host controller */
	250	irq = 7;
3de388f6	251	intno = s->pics[0].irq_base + irq;
15aeac38	252	}
3de388f6	253	pic_update_irq(s);
3b46e624	254
80cabfad	255	#ifdef DEBUG_IRQ_LATENCY
5fafdf24 TS	256	printf("IRQ%d latency=%0.3fus\n",
5fafdf24 TS	257	irq,
74475455	258	(double)(qemu_get_clock_ns(vm_clock) -
6ee093c9	259	irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
80cabfad	260	#endif
8ac02ff8	261	DPRINTF("pic_interrupt: irq=%d\n", irq);
80cabfad FB	262	return intno;
	263	}
	264
d7d02e3c FB	265	static void pic_reset(void *opaque)
	266	{
	267	PicState *s = opaque;
d7d02e3c	268
3de388f6 FB	269	s->last_irr = 0;
	270	s->irr = 0;
	271	s->imr = 0;
	272	s->isr = 0;
	273	s->priority_add = 0;
	274	s->irq_base = 0;
	275	s->read_reg_select = 0;
	276	s->poll = 0;
	277	s->special_mask = 0;
	278	s->init_state = 0;
	279	s->auto_eoi = 0;
	280	s->rotate_on_auto_eoi = 0;
	281	s->special_fully_nested_mode = 0;
	282	s->init4 = 0;
2053152b	283	s->single_mode = 0;
4dbe19e1	284	/* Note: ELCR is not reset */
d7d02e3c FB	285	}
d7d02e3c FB	286
b41a2cd1	287	static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	288	{
b41a2cd1	289	PicState *s = opaque;
d7d02e3c	290	int priority, cmd, irq;
80cabfad	291
8ac02ff8	292	DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
80cabfad FB	293	addr &= 1;
	294	if (addr == 0) {
	295	if (val & 0x10) {
	296	/* init */
d7d02e3c	297	pic_reset(s);
b54ad049	298	/* deassert a pending interrupt */
d537cf6c	299	qemu_irq_lower(s->pics_state->parent_irq);
80cabfad FB	300	s->init_state = 1;
80cabfad FB	301	s->init4 = val & 1;
2053152b	302	s->single_mode = val & 2;
80cabfad FB	303	if (val & 0x08)
	304	hw_error("level sensitive irq not supported");
	305	} else if (val & 0x08) {
	306	if (val & 0x04)
	307	s->poll = 1;
	308	if (val & 0x02)
	309	s->read_reg_select = val & 1;
	310	if (val & 0x40)
	311	s->special_mask = (val >> 5) & 1;
	312	} else {
	313	cmd = val >> 5;
	314	switch(cmd) {
	315	case 0:
	316	case 4:
	317	s->rotate_on_auto_eoi = cmd >> 2;
	318	break;
	319	case 1: /* end of interrupt */
	320	case 5:
	321	priority = get_priority(s, s->isr);
	322	if (priority != 8) {
	323	irq = (priority + s->priority_add) & 7;
	324	s->isr &= ~(1 << irq);
	325	if (cmd == 5)
	326	s->priority_add = (irq + 1) & 7;
3de388f6	327	pic_update_irq(s->pics_state);
80cabfad FB	328	}
	329	break;
	330	case 3:
	331	irq = val & 7;
	332	s->isr &= ~(1 << irq);
3de388f6	333	pic_update_irq(s->pics_state);
80cabfad FB	334	break;
	335	case 6:
	336	s->priority_add = (val + 1) & 7;
3de388f6	337	pic_update_irq(s->pics_state);
80cabfad FB	338	break;
	339	case 7:
	340	irq = val & 7;
	341	s->isr &= ~(1 << irq);
	342	s->priority_add = (irq + 1) & 7;
3de388f6	343	pic_update_irq(s->pics_state);
80cabfad FB	344	break;
	345	default:
	346	/* no operation */
	347	break;
	348	}
	349	}
	350	} else {
	351	switch(s->init_state) {
	352	case 0:
	353	/* normal mode */
	354	s->imr = val;
3de388f6	355	pic_update_irq(s->pics_state);
80cabfad FB	356	break;
	357	case 1:
	358	s->irq_base = val & 0xf8;
2bb081f7	359	s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
80cabfad FB	360	break;
	361	case 2:
	362	if (s->init4) {
	363	s->init_state = 3;
	364	} else {
	365	s->init_state = 0;
	366	}
	367	break;
	368	case 3:
	369	s->special_fully_nested_mode = (val >> 4) & 1;
	370	s->auto_eoi = (val >> 1) & 1;
	371	s->init_state = 0;
	372	break;
	373	}
	374	}
	375	}
	376
	377	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
	378	{
	379	int ret;
	380
	381	ret = pic_get_irq(s);
	382	if (ret >= 0) {
	383	if (addr1 >> 7) {
3de388f6 FB	384	s->pics_state->pics[0].isr &= ~(1 << 2);
3de388f6 FB	385	s->pics_state->pics[0].irr &= ~(1 << 2);
80cabfad FB	386	}
	387	s->irr &= ~(1 << ret);
	388	s->isr &= ~(1 << ret);
	389	if (addr1 >> 7 \|\| ret != 2)
3de388f6	390	pic_update_irq(s->pics_state);
80cabfad FB	391	} else {
80cabfad FB	392	ret = 0x07;
3de388f6	393	pic_update_irq(s->pics_state);
80cabfad FB	394	}
	395
	396	return ret;
	397	}
	398
b41a2cd1	399	static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
80cabfad	400	{
b41a2cd1	401	PicState *s = opaque;
80cabfad FB	402	unsigned int addr;
	403	int ret;
	404
	405	addr = addr1;
80cabfad FB	406	addr &= 1;
	407	if (s->poll) {
	408	ret = pic_poll_read(s, addr1);
	409	s->poll = 0;
	410	} else {
	411	if (addr == 0) {
	412	if (s->read_reg_select)
	413	ret = s->isr;
	414	else
	415	ret = s->irr;
	416	} else {
	417	ret = s->imr;
	418	}
	419	}
8ac02ff8	420	DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret);
80cabfad FB	421	return ret;
	422	}
	423
	424	/* memory mapped interrupt status */
3de388f6 FB	425	/* XXX: may be the same than pic_read_irq() */
3de388f6 FB	426	uint32_t pic_intack_read(PicState2 *s)
80cabfad FB	427	{
	428	int ret;
	429
3de388f6	430	ret = pic_poll_read(&s->pics[0], 0x00);
80cabfad	431	if (ret == 2)
3de388f6	432	ret = pic_poll_read(&s->pics[1], 0x80) + 8;
80cabfad	433	/* Prepare for ISR read */
3de388f6	434	s->pics[0].read_reg_select = 1;
3b46e624	435
80cabfad FB	436	return ret;
	437	}
	438
660de336 FB	439	static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	440	{
	441	PicState *s = opaque;
	442	s->elcr = val & s->elcr_mask;
	443	}
	444
	445	static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
	446	{
	447	PicState *s = opaque;
	448	return s->elcr;
	449	}
	450
77eea838 JQ	451	static const VMStateDescription vmstate_pic = {
	452	.name = "i8259",
	453	.version_id = 1,
	454	.minimum_version_id = 1,
	455	.minimum_version_id_old = 1,
	456	.fields = (VMStateField []) {
	457	VMSTATE_UINT8(last_irr, PicState),
	458	VMSTATE_UINT8(irr, PicState),
	459	VMSTATE_UINT8(imr, PicState),
	460	VMSTATE_UINT8(isr, PicState),
	461	VMSTATE_UINT8(priority_add, PicState),
	462	VMSTATE_UINT8(irq_base, PicState),
	463	VMSTATE_UINT8(read_reg_select, PicState),
	464	VMSTATE_UINT8(poll, PicState),
	465	VMSTATE_UINT8(special_mask, PicState),
	466	VMSTATE_UINT8(init_state, PicState),
	467	VMSTATE_UINT8(auto_eoi, PicState),
	468	VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
	469	VMSTATE_UINT8(special_fully_nested_mode, PicState),
	470	VMSTATE_UINT8(init4, PicState),
	471	VMSTATE_UINT8(single_mode, PicState),
	472	VMSTATE_UINT8(elcr, PicState),
	473	VMSTATE_END_OF_LIST()
	474	}
	475	};
b0a21b53 FB	476
b0a21b53 FB	477	/* XXX: add generic master/slave system */
660de336	478	static void pic_init1(int io_addr, int elcr_addr, PicState *s)
b0a21b53 FB	479	{
	480	register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
	481	register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
660de336 FB	482	if (elcr_addr >= 0) {
	483	register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
	484	register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
	485	}
0be71e32	486	vmstate_register(NULL, io_addr, &vmstate_pic, s);
a08d4367	487	qemu_register_reset(pic_reset, s);
b0a21b53 FB	488	}
b0a21b53 FB	489
376253ec	490	void pic_info(Monitor *mon)
ba91cd80 FB	491	{
	492	int i;
	493	PicState *s;
3b46e624	494
3de388f6 FB	495	if (!isa_pic)
3de388f6 FB	496	return;
ba91cd80 FB	497
ba91cd80 FB	498	for(i=0;i<2;i++) {
3de388f6	499	s = &isa_pic->pics[i];
376253ec AL	500	monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
	501	"irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
	502	i, s->irr, s->imr, s->isr, s->priority_add,
	503	s->irq_base, s->read_reg_select, s->elcr,
	504	s->special_fully_nested_mode);
ba91cd80 FB	505	}
	506	}
	507
376253ec	508	void irq_info(Monitor *mon)
4a0fb71e FB	509	{
4a0fb71e FB	510	#ifndef DEBUG_IRQ_COUNT
376253ec	511	monitor_printf(mon, "irq statistic code not compiled.\n");
4a0fb71e FB	512	#else
	513	int i;
	514	int64_t count;
	515
376253ec	516	monitor_printf(mon, "IRQ statistics:\n");
4a0fb71e FB	517	for (i = 0; i < 16; i++) {
	518	count = irq_count[i];
	519	if (count > 0)
376253ec	520	monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
4a0fb71e FB	521	}
	522	#endif
	523	}
ba91cd80	524
d537cf6c	525	qemu_irq *i8259_init(qemu_irq parent_irq)
80cabfad	526	{
3de388f6	527	PicState2 *s;
d537cf6c	528
3de388f6	529	s = qemu_mallocz(sizeof(PicState2));
3de388f6 FB	530	pic_init1(0x20, 0x4d0, &s->pics[0]);
	531	pic_init1(0xa0, 0x4d1, &s->pics[1]);
	532	s->pics[0].elcr_mask = 0xf8;
	533	s->pics[1].elcr_mask = 0xde;
d537cf6c	534	s->parent_irq = parent_irq;
3de388f6 FB	535	s->pics[0].pics_state = s;
3de388f6 FB	536	s->pics[1].pics_state = s;
d537cf6c PB	537	isa_pic = s;
d537cf6c PB	538	return qemu_allocate_irqs(i8259_set_irq, s, 16);
80cabfad	539	}