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80cabfad FB |
1 | /* |
2 | * QEMU 8259 interrupt controller emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
80cabfad FB |
24 | #include "vl.h" |
25 | ||
26 | /* debug PIC */ | |
27 | //#define DEBUG_PIC | |
28 | ||
b41a2cd1 FB |
29 | //#define DEBUG_IRQ_LATENCY |
30 | ||
80cabfad FB |
31 | typedef struct PicState { |
32 | uint8_t last_irr; /* edge detection */ | |
33 | uint8_t irr; /* interrupt request register */ | |
34 | uint8_t imr; /* interrupt mask register */ | |
35 | uint8_t isr; /* interrupt service register */ | |
36 | uint8_t priority_add; /* highest irq priority */ | |
37 | uint8_t irq_base; | |
38 | uint8_t read_reg_select; | |
39 | uint8_t poll; | |
40 | uint8_t special_mask; | |
41 | uint8_t init_state; | |
42 | uint8_t auto_eoi; | |
43 | uint8_t rotate_on_auto_eoi; | |
44 | uint8_t special_fully_nested_mode; | |
45 | uint8_t init4; /* true if 4 byte init */ | |
660de336 FB |
46 | uint8_t elcr; /* PIIX edge/trigger selection*/ |
47 | uint8_t elcr_mask; | |
80cabfad FB |
48 | } PicState; |
49 | ||
50 | /* 0 is master pic, 1 is slave pic */ | |
ba91cd80 | 51 | static PicState pics[2]; |
80cabfad FB |
52 | |
53 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ | |
54 | static inline void pic_set_irq1(PicState *s, int irq, int level) | |
55 | { | |
56 | int mask; | |
57 | mask = 1 << irq; | |
660de336 FB |
58 | if (s->elcr & mask) { |
59 | /* level triggered */ | |
60 | if (level) { | |
80cabfad | 61 | s->irr |= mask; |
660de336 FB |
62 | s->last_irr |= mask; |
63 | } else { | |
64 | s->irr &= ~mask; | |
65 | s->last_irr &= ~mask; | |
66 | } | |
80cabfad | 67 | } else { |
660de336 FB |
68 | /* edge triggered */ |
69 | if (level) { | |
70 | if ((s->last_irr & mask) == 0) | |
71 | s->irr |= mask; | |
72 | s->last_irr |= mask; | |
73 | } else { | |
74 | s->last_irr &= ~mask; | |
75 | } | |
80cabfad FB |
76 | } |
77 | } | |
78 | ||
79 | /* return the highest priority found in mask (highest = smallest | |
80 | number). Return 8 if no irq */ | |
81 | static inline int get_priority(PicState *s, int mask) | |
82 | { | |
83 | int priority; | |
84 | if (mask == 0) | |
85 | return 8; | |
86 | priority = 0; | |
87 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
88 | priority++; | |
89 | return priority; | |
90 | } | |
91 | ||
92 | /* return the pic wanted interrupt. return -1 if none */ | |
93 | static int pic_get_irq(PicState *s) | |
94 | { | |
95 | int mask, cur_priority, priority; | |
96 | ||
97 | mask = s->irr & ~s->imr; | |
98 | priority = get_priority(s, mask); | |
99 | if (priority == 8) | |
100 | return -1; | |
101 | /* compute current priority. If special fully nested mode on the | |
102 | master, the IRQ coming from the slave is not taken into account | |
103 | for the priority computation. */ | |
104 | mask = s->isr; | |
105 | if (s->special_fully_nested_mode && s == &pics[0]) | |
106 | mask &= ~(1 << 2); | |
107 | cur_priority = get_priority(s, mask); | |
108 | if (priority < cur_priority) { | |
109 | /* higher priority found: an irq should be generated */ | |
110 | return (priority + s->priority_add) & 7; | |
111 | } else { | |
112 | return -1; | |
113 | } | |
114 | } | |
115 | ||
116 | /* raise irq to CPU if necessary. must be called every time the active | |
117 | irq may change */ | |
b0a21b53 | 118 | static void pic_update_irq(void) |
80cabfad FB |
119 | { |
120 | int irq2, irq; | |
121 | ||
122 | /* first look at slave pic */ | |
123 | irq2 = pic_get_irq(&pics[1]); | |
124 | if (irq2 >= 0) { | |
125 | /* if irq request by slave pic, signal master PIC */ | |
126 | pic_set_irq1(&pics[0], 2, 1); | |
127 | pic_set_irq1(&pics[0], 2, 0); | |
128 | } | |
129 | /* look at requested irq */ | |
130 | irq = pic_get_irq(&pics[0]); | |
131 | if (irq >= 0) { | |
80cabfad FB |
132 | #if defined(DEBUG_PIC) |
133 | { | |
134 | int i; | |
135 | for(i = 0; i < 2; i++) { | |
136 | printf("pic%d: imr=%x irr=%x padd=%d\n", | |
137 | i, pics[i].imr, pics[i].irr, pics[i].priority_add); | |
138 | ||
139 | } | |
140 | } | |
141 | printf("pic: cpu_interrupt req=%d\n", pic_irq_requested); | |
142 | #endif | |
143 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
144 | } | |
145 | } | |
146 | ||
147 | #ifdef DEBUG_IRQ_LATENCY | |
148 | int64_t irq_time[16]; | |
80cabfad FB |
149 | #endif |
150 | #if defined(DEBUG_PIC) | |
151 | int irq_level[16]; | |
152 | #endif | |
153 | ||
154 | void pic_set_irq(int irq, int level) | |
155 | { | |
156 | #if defined(DEBUG_PIC) | |
157 | if (level != irq_level[irq]) { | |
158 | printf("pic_set_irq: irq=%d level=%d\n", irq, level); | |
159 | irq_level[irq] = level; | |
160 | } | |
161 | #endif | |
162 | #ifdef DEBUG_IRQ_LATENCY | |
163 | if (level) { | |
164 | irq_time[irq] = cpu_get_ticks(); | |
165 | } | |
166 | #endif | |
167 | pic_set_irq1(&pics[irq >> 3], irq & 7, level); | |
168 | pic_update_irq(); | |
169 | } | |
170 | ||
171 | /* acknowledge interrupt 'irq' */ | |
172 | static inline void pic_intack(PicState *s, int irq) | |
173 | { | |
174 | if (s->auto_eoi) { | |
175 | if (s->rotate_on_auto_eoi) | |
176 | s->priority_add = (irq + 1) & 7; | |
177 | } else { | |
178 | s->isr |= (1 << irq); | |
179 | } | |
180 | s->irr &= ~(1 << irq); | |
181 | } | |
182 | ||
a541f297 | 183 | int cpu_get_pic_interrupt(CPUState *env) |
80cabfad FB |
184 | { |
185 | int irq, irq2, intno; | |
186 | ||
15aeac38 FB |
187 | /* read the irq from the PIC */ |
188 | ||
189 | irq = pic_get_irq(&pics[0]); | |
190 | if (irq >= 0) { | |
191 | pic_intack(&pics[0], irq); | |
192 | if (irq == 2) { | |
193 | irq2 = pic_get_irq(&pics[1]); | |
194 | if (irq2 >= 0) { | |
195 | pic_intack(&pics[1], irq2); | |
196 | } else { | |
197 | /* spurious IRQ on slave controller */ | |
198 | irq2 = 7; | |
199 | } | |
200 | intno = pics[1].irq_base + irq2; | |
201 | irq = irq2 + 8; | |
202 | } else { | |
203 | intno = pics[0].irq_base + irq; | |
204 | } | |
205 | } else { | |
206 | /* spurious IRQ on host controller */ | |
207 | irq = 7; | |
208 | intno = pics[0].irq_base + irq; | |
209 | } | |
210 | pic_update_irq(); | |
211 | ||
80cabfad FB |
212 | #ifdef DEBUG_IRQ_LATENCY |
213 | printf("IRQ%d latency=%0.3fus\n", | |
214 | irq, | |
215 | (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec); | |
216 | #endif | |
217 | #if defined(DEBUG_PIC) | |
218 | printf("pic_interrupt: irq=%d\n", irq); | |
219 | #endif | |
80cabfad FB |
220 | return intno; |
221 | } | |
222 | ||
b41a2cd1 | 223 | static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 224 | { |
b41a2cd1 | 225 | PicState *s = opaque; |
660de336 | 226 | int priority, cmd, irq, tmp; |
80cabfad FB |
227 | |
228 | #ifdef DEBUG_PIC | |
229 | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val); | |
230 | #endif | |
80cabfad FB |
231 | addr &= 1; |
232 | if (addr == 0) { | |
233 | if (val & 0x10) { | |
234 | /* init */ | |
660de336 | 235 | tmp = s->elcr_mask; |
80cabfad | 236 | memset(s, 0, sizeof(PicState)); |
660de336 | 237 | s->elcr_mask = tmp; |
b54ad049 FB |
238 | /* deassert a pending interrupt */ |
239 | cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
660de336 | 240 | |
80cabfad FB |
241 | s->init_state = 1; |
242 | s->init4 = val & 1; | |
243 | if (val & 0x02) | |
244 | hw_error("single mode not supported"); | |
245 | if (val & 0x08) | |
246 | hw_error("level sensitive irq not supported"); | |
247 | } else if (val & 0x08) { | |
248 | if (val & 0x04) | |
249 | s->poll = 1; | |
250 | if (val & 0x02) | |
251 | s->read_reg_select = val & 1; | |
252 | if (val & 0x40) | |
253 | s->special_mask = (val >> 5) & 1; | |
254 | } else { | |
255 | cmd = val >> 5; | |
256 | switch(cmd) { | |
257 | case 0: | |
258 | case 4: | |
259 | s->rotate_on_auto_eoi = cmd >> 2; | |
260 | break; | |
261 | case 1: /* end of interrupt */ | |
262 | case 5: | |
263 | priority = get_priority(s, s->isr); | |
264 | if (priority != 8) { | |
265 | irq = (priority + s->priority_add) & 7; | |
266 | s->isr &= ~(1 << irq); | |
267 | if (cmd == 5) | |
268 | s->priority_add = (irq + 1) & 7; | |
269 | pic_update_irq(); | |
270 | } | |
271 | break; | |
272 | case 3: | |
273 | irq = val & 7; | |
274 | s->isr &= ~(1 << irq); | |
275 | pic_update_irq(); | |
276 | break; | |
277 | case 6: | |
278 | s->priority_add = (val + 1) & 7; | |
279 | pic_update_irq(); | |
280 | break; | |
281 | case 7: | |
282 | irq = val & 7; | |
283 | s->isr &= ~(1 << irq); | |
284 | s->priority_add = (irq + 1) & 7; | |
285 | pic_update_irq(); | |
286 | break; | |
287 | default: | |
288 | /* no operation */ | |
289 | break; | |
290 | } | |
291 | } | |
292 | } else { | |
293 | switch(s->init_state) { | |
294 | case 0: | |
295 | /* normal mode */ | |
296 | s->imr = val; | |
297 | pic_update_irq(); | |
298 | break; | |
299 | case 1: | |
300 | s->irq_base = val & 0xf8; | |
301 | s->init_state = 2; | |
302 | break; | |
303 | case 2: | |
304 | if (s->init4) { | |
305 | s->init_state = 3; | |
306 | } else { | |
307 | s->init_state = 0; | |
308 | } | |
309 | break; | |
310 | case 3: | |
311 | s->special_fully_nested_mode = (val >> 4) & 1; | |
312 | s->auto_eoi = (val >> 1) & 1; | |
313 | s->init_state = 0; | |
314 | break; | |
315 | } | |
316 | } | |
317 | } | |
318 | ||
319 | static uint32_t pic_poll_read (PicState *s, uint32_t addr1) | |
320 | { | |
321 | int ret; | |
322 | ||
323 | ret = pic_get_irq(s); | |
324 | if (ret >= 0) { | |
325 | if (addr1 >> 7) { | |
326 | pics[0].isr &= ~(1 << 2); | |
327 | pics[0].irr &= ~(1 << 2); | |
328 | } | |
329 | s->irr &= ~(1 << ret); | |
330 | s->isr &= ~(1 << ret); | |
331 | if (addr1 >> 7 || ret != 2) | |
332 | pic_update_irq(); | |
333 | } else { | |
334 | ret = 0x07; | |
335 | pic_update_irq(); | |
336 | } | |
337 | ||
338 | return ret; | |
339 | } | |
340 | ||
b41a2cd1 | 341 | static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) |
80cabfad | 342 | { |
b41a2cd1 | 343 | PicState *s = opaque; |
80cabfad FB |
344 | unsigned int addr; |
345 | int ret; | |
346 | ||
347 | addr = addr1; | |
80cabfad FB |
348 | addr &= 1; |
349 | if (s->poll) { | |
350 | ret = pic_poll_read(s, addr1); | |
351 | s->poll = 0; | |
352 | } else { | |
353 | if (addr == 0) { | |
354 | if (s->read_reg_select) | |
355 | ret = s->isr; | |
356 | else | |
357 | ret = s->irr; | |
358 | } else { | |
359 | ret = s->imr; | |
360 | } | |
361 | } | |
362 | #ifdef DEBUG_PIC | |
363 | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret); | |
364 | #endif | |
365 | return ret; | |
366 | } | |
367 | ||
368 | /* memory mapped interrupt status */ | |
369 | uint32_t pic_intack_read(CPUState *env) | |
370 | { | |
371 | int ret; | |
372 | ||
373 | ret = pic_poll_read(&pics[0], 0x00); | |
374 | if (ret == 2) | |
375 | ret = pic_poll_read(&pics[1], 0x80) + 8; | |
376 | /* Prepare for ISR read */ | |
377 | pics[0].read_reg_select = 1; | |
378 | ||
379 | return ret; | |
380 | } | |
381 | ||
660de336 FB |
382 | static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
383 | { | |
384 | PicState *s = opaque; | |
385 | s->elcr = val & s->elcr_mask; | |
386 | } | |
387 | ||
388 | static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1) | |
389 | { | |
390 | PicState *s = opaque; | |
391 | return s->elcr; | |
392 | } | |
393 | ||
b0a21b53 FB |
394 | static void pic_save(QEMUFile *f, void *opaque) |
395 | { | |
396 | PicState *s = opaque; | |
397 | ||
398 | qemu_put_8s(f, &s->last_irr); | |
399 | qemu_put_8s(f, &s->irr); | |
400 | qemu_put_8s(f, &s->imr); | |
401 | qemu_put_8s(f, &s->isr); | |
402 | qemu_put_8s(f, &s->priority_add); | |
403 | qemu_put_8s(f, &s->irq_base); | |
404 | qemu_put_8s(f, &s->read_reg_select); | |
405 | qemu_put_8s(f, &s->poll); | |
406 | qemu_put_8s(f, &s->special_mask); | |
407 | qemu_put_8s(f, &s->init_state); | |
408 | qemu_put_8s(f, &s->auto_eoi); | |
409 | qemu_put_8s(f, &s->rotate_on_auto_eoi); | |
410 | qemu_put_8s(f, &s->special_fully_nested_mode); | |
411 | qemu_put_8s(f, &s->init4); | |
660de336 | 412 | qemu_put_8s(f, &s->elcr); |
b0a21b53 FB |
413 | } |
414 | ||
415 | static int pic_load(QEMUFile *f, void *opaque, int version_id) | |
416 | { | |
417 | PicState *s = opaque; | |
418 | ||
419 | if (version_id != 1) | |
420 | return -EINVAL; | |
421 | ||
422 | qemu_get_8s(f, &s->last_irr); | |
423 | qemu_get_8s(f, &s->irr); | |
424 | qemu_get_8s(f, &s->imr); | |
425 | qemu_get_8s(f, &s->isr); | |
426 | qemu_get_8s(f, &s->priority_add); | |
427 | qemu_get_8s(f, &s->irq_base); | |
428 | qemu_get_8s(f, &s->read_reg_select); | |
429 | qemu_get_8s(f, &s->poll); | |
430 | qemu_get_8s(f, &s->special_mask); | |
431 | qemu_get_8s(f, &s->init_state); | |
432 | qemu_get_8s(f, &s->auto_eoi); | |
433 | qemu_get_8s(f, &s->rotate_on_auto_eoi); | |
434 | qemu_get_8s(f, &s->special_fully_nested_mode); | |
435 | qemu_get_8s(f, &s->init4); | |
660de336 | 436 | qemu_get_8s(f, &s->elcr); |
b0a21b53 FB |
437 | return 0; |
438 | } | |
439 | ||
440 | /* XXX: add generic master/slave system */ | |
660de336 | 441 | static void pic_init1(int io_addr, int elcr_addr, PicState *s) |
b0a21b53 FB |
442 | { |
443 | register_ioport_write(io_addr, 2, 1, pic_ioport_write, s); | |
444 | register_ioport_read(io_addr, 2, 1, pic_ioport_read, s); | |
660de336 FB |
445 | if (elcr_addr >= 0) { |
446 | register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s); | |
447 | register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); | |
448 | } | |
b0a21b53 FB |
449 | register_savevm("i8259", io_addr, 1, pic_save, pic_load, s); |
450 | } | |
451 | ||
ba91cd80 FB |
452 | void pic_info(void) |
453 | { | |
454 | int i; | |
455 | PicState *s; | |
456 | ||
457 | for(i=0;i<2;i++) { | |
458 | s = &pics[i]; | |
15aeac38 | 459 | term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", |
660de336 | 460 | i, s->irr, s->imr, s->isr, s->priority_add, |
15aeac38 FB |
461 | s->irq_base, s->read_reg_select, s->elcr, |
462 | s->special_fully_nested_mode); | |
ba91cd80 FB |
463 | } |
464 | } | |
465 | ||
466 | ||
80cabfad FB |
467 | void pic_init(void) |
468 | { | |
660de336 FB |
469 | pic_init1(0x20, 0x4d0, &pics[0]); |
470 | pic_init1(0xa0, 0x4d1, &pics[1]); | |
471 | pics[0].elcr_mask = 0xf8; | |
472 | pics[1].elcr_mask = 0xde; | |
80cabfad FB |
473 | } |
474 |