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f6ad2e32 AG |
1 | /* |
2 | * QEMU AHCI Emulation | |
3 | * | |
4 | * Copyright (c) 2010 qiaochong@loongson.cn | |
5 | * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> | |
6 | * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> | |
7 | * Copyright (c) 2010 Alexander Graf <agraf@suse.de> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
21 | * | |
22 | * | |
23 | * lspci dump of a ICH-9 real device in IDE mode (hopefully close enough): | |
24 | * | |
25 | * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0]) | |
26 | * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] | |
27 | * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ | |
28 | * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- | |
29 | * Latency: 0 | |
30 | * Interrupt: pin B routed to IRQ 222 | |
31 | * Region 0: I/O ports at d000 [size=8] | |
32 | * Region 1: I/O ports at cc00 [size=4] | |
33 | * Region 2: I/O ports at c880 [size=8] | |
34 | * Region 3: I/O ports at c800 [size=4] | |
35 | * Region 4: I/O ports at c480 [size=32] | |
36 | * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K] | |
37 | * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+ | |
38 | * Address: fee0f00c Data: 41d9 | |
39 | * Capabilities: [70] Power Management version 3 | |
40 | * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) | |
41 | * Status: D0 PME-Enable- DSel=0 DScale=0 PME- | |
42 | * Capabilities: [a8] SATA HBA <?> | |
43 | * Capabilities: [b0] Vendor Specific Information <?> | |
44 | * Kernel driver in use: ahci | |
45 | * Kernel modules: ahci | |
46 | * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00 | |
47 | * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00 | |
48 | * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29 | |
49 | * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00 | |
50 | * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 | |
51 | * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
52 | * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
53 | * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 | |
54 | * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00 | |
55 | * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00 | |
56 | * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00 | |
57 | * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 | |
58 | * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
59 | * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
60 | * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
61 | * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 | |
62 | * | |
63 | */ | |
64 | ||
65 | #include <hw/hw.h> | |
66 | #include <hw/msi.h> | |
67 | #include <hw/pc.h> | |
68 | #include <hw/pci.h> | |
69 | ||
70 | #include "monitor.h" | |
71 | #include "dma.h" | |
72 | #include "cpu-common.h" | |
f6ad2e32 AG |
73 | #include "internal.h" |
74 | #include <hw/ide/pci.h> | |
75 | ||
76 | /* #define DEBUG_AHCI */ | |
77 | ||
78 | #ifdef DEBUG_AHCI | |
79 | #define DPRINTF(port, fmt, ...) \ | |
80 | do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \ | |
81 | fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
82 | #else | |
83 | #define DPRINTF(port, fmt, ...) do {} while(0) | |
84 | #endif | |
85 | ||
86 | #define AHCI_PCI_BAR 5 | |
87 | #define AHCI_MAX_PORTS 32 | |
88 | #define AHCI_MAX_SG 168 /* hardware max is 64K */ | |
89 | #define AHCI_DMA_BOUNDARY 0xffffffff | |
90 | #define AHCI_USE_CLUSTERING 0 | |
91 | #define AHCI_MAX_CMDS 32 | |
92 | #define AHCI_CMD_SZ 32 | |
93 | #define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ) | |
94 | #define AHCI_RX_FIS_SZ 256 | |
95 | #define AHCI_CMD_TBL_CDB 0x40 | |
96 | #define AHCI_CMD_TBL_HDR_SZ 0x80 | |
97 | #define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16)) | |
98 | #define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS) | |
99 | #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \ | |
100 | AHCI_RX_FIS_SZ) | |
101 | ||
102 | #define AHCI_IRQ_ON_SG (1 << 31) | |
103 | #define AHCI_CMD_ATAPI (1 << 5) | |
104 | #define AHCI_CMD_WRITE (1 << 6) | |
105 | #define AHCI_CMD_PREFETCH (1 << 7) | |
106 | #define AHCI_CMD_RESET (1 << 8) | |
107 | #define AHCI_CMD_CLR_BUSY (1 << 10) | |
108 | ||
109 | #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ | |
110 | #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */ | |
111 | #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */ | |
112 | ||
113 | /* global controller registers */ | |
114 | #define HOST_CAP 0x00 /* host capabilities */ | |
115 | #define HOST_CTL 0x04 /* global host control */ | |
116 | #define HOST_IRQ_STAT 0x08 /* interrupt status */ | |
117 | #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ | |
118 | #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ | |
119 | ||
120 | /* HOST_CTL bits */ | |
121 | #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */ | |
122 | #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */ | |
123 | #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ | |
124 | ||
125 | /* HOST_CAP bits */ | |
126 | #define HOST_CAP_SSC (1 << 14) /* Slumber capable */ | |
127 | #define HOST_CAP_AHCI (1 << 18) /* AHCI only */ | |
128 | #define HOST_CAP_CLO (1 << 24) /* Command List Override support */ | |
129 | #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */ | |
130 | #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ | |
131 | #define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */ | |
132 | ||
133 | /* registers for each SATA port */ | |
134 | #define PORT_LST_ADDR 0x00 /* command list DMA addr */ | |
135 | #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ | |
136 | #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ | |
137 | #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ | |
138 | #define PORT_IRQ_STAT 0x10 /* interrupt status */ | |
139 | #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ | |
140 | #define PORT_CMD 0x18 /* port command */ | |
141 | #define PORT_TFDATA 0x20 /* taskfile data */ | |
142 | #define PORT_SIG 0x24 /* device TF signature */ | |
143 | #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ | |
144 | #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ | |
145 | #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ | |
146 | #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ | |
147 | #define PORT_CMD_ISSUE 0x38 /* command issue */ | |
148 | #define PORT_RESERVED 0x3c /* reserved */ | |
149 | ||
150 | /* PORT_IRQ_{STAT,MASK} bits */ | |
151 | #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ | |
152 | #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ | |
153 | #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ | |
154 | #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ | |
155 | #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ | |
156 | #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ | |
157 | #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ | |
158 | #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ | |
159 | ||
160 | #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ | |
161 | #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ | |
162 | #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ | |
163 | #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ | |
164 | #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ | |
165 | #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ | |
166 | #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ | |
167 | #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ | |
168 | #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ | |
169 | ||
170 | #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \ | |
171 | PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \ | |
172 | PORT_IRQ_UNK_FIS) | |
173 | #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \ | |
174 | PORT_IRQ_HBUS_DATA_ERR) | |
175 | #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \ | |
176 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \ | |
177 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS) | |
178 | ||
179 | /* PORT_CMD bits */ | |
180 | #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ | |
181 | #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ | |
182 | #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ | |
183 | #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ | |
184 | #define PORT_CMD_CLO (1 << 3) /* Command list override */ | |
185 | #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ | |
186 | #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ | |
187 | #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ | |
188 | ||
189 | #define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */ | |
190 | #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ | |
191 | #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ | |
192 | #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ | |
193 | ||
194 | #define PORT_IRQ_STAT_DHRS (1 << 0) /* Device to Host Register FIS */ | |
195 | #define PORT_IRQ_STAT_PSS (1 << 1) /* PIO Setup FIS */ | |
196 | #define PORT_IRQ_STAT_DSS (1 << 2) /* DMA Setup FIS */ | |
197 | #define PORT_IRQ_STAT_SDBS (1 << 3) /* Set Device Bits */ | |
198 | #define PORT_IRQ_STAT_UFS (1 << 4) /* Unknown FIS */ | |
199 | #define PORT_IRQ_STAT_DPS (1 << 5) /* Descriptor Processed */ | |
200 | #define PORT_IRQ_STAT_PCS (1 << 6) /* Port Connect Change Status */ | |
201 | #define PORT_IRQ_STAT_DMPS (1 << 7) /* Device Mechanical Presence | |
202 | Status */ | |
203 | #define PORT_IRQ_STAT_PRCS (1 << 22) /* File Ready Status */ | |
204 | #define PORT_IRQ_STAT_IPMS (1 << 23) /* Incorrect Port Multiplier | |
205 | Status */ | |
206 | #define PORT_IRQ_STAT_OFS (1 << 24) /* Overflow Status */ | |
207 | #define PORT_IRQ_STAT_INFS (1 << 26) /* Interface Non-Fatal Error | |
208 | Status */ | |
209 | #define PORT_IRQ_STAT_IFS (1 << 27) /* Interface Fatal Error */ | |
210 | #define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */ | |
211 | #define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */ | |
212 | #define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */ | |
213 | #define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */ | |
214 | ||
215 | /* ap->flags bits */ | |
216 | #define AHCI_FLAG_NO_NCQ (1 << 24) | |
217 | #define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */ | |
218 | #define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */ | |
219 | #define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */ | |
220 | #define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */ | |
221 | ||
222 | #define ATA_SRST (1 << 2) /* software reset */ | |
223 | ||
224 | #define STATE_RUN 0 | |
225 | #define STATE_RESET 1 | |
226 | ||
227 | #define SATA_SCR_SSTATUS_DET_NODEV 0x0 | |
228 | #define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3 | |
229 | ||
230 | #define SATA_SCR_SSTATUS_SPD_NODEV 0x00 | |
231 | #define SATA_SCR_SSTATUS_SPD_GEN1 0x10 | |
232 | ||
233 | #define SATA_SCR_SSTATUS_IPM_NODEV 0x000 | |
234 | #define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100 | |
235 | ||
236 | #define AHCI_SCR_SCTL_DET 0xf | |
237 | ||
238 | #define SATA_FIS_TYPE_REGISTER_H2D 0x27 | |
239 | #define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80 | |
240 | ||
241 | #define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f | |
242 | #define AHCI_CMD_HDR_PRDT_LEN 16 | |
243 | ||
244 | #define SATA_SIGNATURE_CDROM 0xeb140000 | |
245 | #define SATA_SIGNATURE_DISK 0x00000101 | |
246 | ||
247 | #define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20 | |
248 | /* Shouldn't this be 0x2c? */ | |
249 | ||
250 | #define SATA_PORTS 4 | |
251 | ||
252 | #define AHCI_PORT_REGS_START_ADDR 0x100 | |
253 | #define AHCI_PORT_REGS_END_ADDR (AHCI_PORT_REGS_START_ADDR + SATA_PORTS * 0x80) | |
254 | #define AHCI_PORT_ADDR_OFFSET_MASK 0x7f | |
255 | ||
256 | #define AHCI_NUM_COMMAND_SLOTS 31 | |
257 | #define AHCI_SUPPORTED_SPEED 20 | |
258 | #define AHCI_SUPPORTED_SPEED_GEN1 1 | |
259 | #define AHCI_VERSION_1_0 0x10000 | |
260 | ||
261 | #define AHCI_PROGMODE_MAJOR_REV_1 1 | |
262 | ||
263 | #define AHCI_COMMAND_TABLE_ACMD 0x40 | |
264 | ||
265 | #define IDE_FEATURE_DMA 1 | |
266 | ||
267 | #define READ_FPDMA_QUEUED 0x60 | |
268 | #define WRITE_FPDMA_QUEUED 0x61 | |
269 | ||
270 | #define RES_FIS_DSFIS 0x00 | |
271 | #define RES_FIS_PSFIS 0x20 | |
272 | #define RES_FIS_RFIS 0x40 | |
273 | #define RES_FIS_SDBFIS 0x58 | |
274 | #define RES_FIS_UFIS 0x60 | |
275 | ||
276 | typedef struct AHCIControlRegs { | |
277 | uint32_t cap; | |
278 | uint32_t ghc; | |
279 | uint32_t irqstatus; | |
280 | uint32_t impl; | |
281 | uint32_t version; | |
282 | } AHCIControlRegs; | |
283 | ||
284 | typedef struct AHCIPortRegs { | |
285 | uint32_t lst_addr; | |
286 | uint32_t lst_addr_hi; | |
287 | uint32_t fis_addr; | |
288 | uint32_t fis_addr_hi; | |
289 | uint32_t irq_stat; | |
290 | uint32_t irq_mask; | |
291 | uint32_t cmd; | |
292 | uint32_t unused0; | |
293 | uint32_t tfdata; | |
294 | uint32_t sig; | |
295 | uint32_t scr_stat; | |
296 | uint32_t scr_ctl; | |
297 | uint32_t scr_err; | |
298 | uint32_t scr_act; | |
299 | uint32_t cmd_issue; | |
300 | uint32_t reserved; | |
301 | } AHCIPortRegs; | |
302 | ||
303 | typedef struct AHCICmdHdr { | |
304 | uint32_t opts; | |
305 | uint32_t status; | |
306 | uint64_t tbl_addr; | |
307 | uint32_t reserved[4]; | |
308 | } __attribute__ ((packed)) AHCICmdHdr; | |
309 | ||
310 | typedef struct AHCI_SG { | |
311 | uint64_t addr; | |
312 | uint32_t reserved; | |
313 | uint32_t flags_size; | |
314 | } __attribute__ ((packed)) AHCI_SG; | |
315 | ||
316 | typedef struct AHCIDevice AHCIDevice; | |
317 | ||
318 | typedef struct NCQTransferState { | |
319 | AHCIDevice *drive; | |
320 | BlockDriverAIOCB *aiocb; | |
321 | QEMUSGList sglist; | |
322 | int is_read; | |
323 | uint16_t sector_count; | |
324 | uint64_t lba; | |
325 | uint8_t tag; | |
326 | int slot; | |
327 | int used; | |
328 | } NCQTransferState; | |
329 | ||
330 | struct AHCIDevice { | |
331 | IDEDMA dma; | |
332 | IDEBus port; | |
333 | int port_no; | |
334 | uint32_t port_state; | |
335 | uint32_t finished; | |
336 | AHCIPortRegs port_regs; | |
337 | struct AHCIState *hba; | |
338 | QEMUBH *check_bh; | |
339 | uint8_t *lst; | |
340 | uint8_t *res_fis; | |
341 | int dma_status; | |
342 | int done_atapi_packet; | |
343 | int busy_slot; | |
344 | BlockDriverCompletionFunc *dma_cb; | |
345 | AHCICmdHdr *cur_cmd; | |
346 | NCQTransferState ncq_tfs[AHCI_MAX_CMDS]; | |
347 | }; | |
348 | ||
349 | typedef struct AHCIState { | |
350 | AHCIDevice dev[SATA_PORTS]; | |
351 | AHCIControlRegs control_regs; | |
352 | int mem; | |
353 | qemu_irq irq; | |
354 | } AHCIState; | |
355 | ||
356 | typedef struct AHCIPCIState { | |
357 | PCIDevice card; | |
358 | AHCIState ahci; | |
359 | } AHCIPCIState; | |
360 | ||
361 | typedef struct NCQFrame { | |
362 | uint8_t fis_type; | |
363 | uint8_t c; | |
364 | uint8_t command; | |
365 | uint8_t sector_count_low; | |
366 | uint8_t lba0; | |
367 | uint8_t lba1; | |
368 | uint8_t lba2; | |
369 | uint8_t fua; | |
370 | uint8_t lba3; | |
371 | uint8_t lba4; | |
372 | uint8_t lba5; | |
373 | uint8_t sector_count_high; | |
374 | uint8_t tag; | |
375 | uint8_t reserved5; | |
376 | uint8_t reserved6; | |
377 | uint8_t control; | |
378 | uint8_t reserved7; | |
379 | uint8_t reserved8; | |
380 | uint8_t reserved9; | |
381 | uint8_t reserved10; | |
382 | } __attribute__ ((packed)) NCQFrame; | |
383 | ||
384 | static void check_cmd(AHCIState *s, int port); | |
385 | static int handle_cmd(AHCIState *s,int port,int slot); | |
386 | static void ahci_reset_port(AHCIState *s, int port); | |
387 | static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis); | |
388 | ||
389 | static uint32_t ahci_port_read(AHCIState *s, int port, int offset) | |
390 | { | |
391 | uint32_t val; | |
392 | AHCIPortRegs *pr; | |
393 | pr = &s->dev[port].port_regs; | |
394 | ||
395 | switch (offset) { | |
396 | case PORT_LST_ADDR: | |
397 | val = pr->lst_addr; | |
398 | break; | |
399 | case PORT_LST_ADDR_HI: | |
400 | val = pr->lst_addr_hi; | |
401 | break; | |
402 | case PORT_FIS_ADDR: | |
403 | val = pr->fis_addr; | |
404 | break; | |
405 | case PORT_FIS_ADDR_HI: | |
406 | val = pr->fis_addr_hi; | |
407 | break; | |
408 | case PORT_IRQ_STAT: | |
409 | val = pr->irq_stat; | |
410 | break; | |
411 | case PORT_IRQ_MASK: | |
412 | val = pr->irq_mask; | |
413 | break; | |
414 | case PORT_CMD: | |
415 | val = pr->cmd; | |
416 | break; | |
417 | case PORT_TFDATA: | |
418 | val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | | |
419 | s->dev[port].port.ifs[0].status; | |
420 | break; | |
421 | case PORT_SIG: | |
422 | val = pr->sig; | |
423 | break; | |
424 | case PORT_SCR_STAT: | |
425 | if (s->dev[port].port.ifs[0].bs) { | |
426 | val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | | |
427 | SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; | |
428 | } else { | |
429 | val = SATA_SCR_SSTATUS_DET_NODEV; | |
430 | } | |
431 | break; | |
432 | case PORT_SCR_CTL: | |
433 | val = pr->scr_ctl; | |
434 | break; | |
435 | case PORT_SCR_ERR: | |
436 | val = pr->scr_err; | |
437 | break; | |
438 | case PORT_SCR_ACT: | |
439 | pr->scr_act &= ~s->dev[port].finished; | |
440 | s->dev[port].finished = 0; | |
441 | val = pr->scr_act; | |
442 | break; | |
443 | case PORT_CMD_ISSUE: | |
444 | val = pr->cmd_issue; | |
445 | break; | |
446 | case PORT_RESERVED: | |
447 | default: | |
448 | val = 0; | |
449 | } | |
450 | DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); | |
451 | return val; | |
452 | ||
453 | } | |
454 | ||
455 | static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) | |
456 | { | |
457 | struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); | |
458 | ||
459 | DPRINTF(0, "raise irq\n"); | |
460 | ||
461 | if (msi_enabled(&d->card)) { | |
462 | msi_notify(&d->card, 0); | |
463 | } else { | |
464 | qemu_irq_raise(s->irq); | |
465 | } | |
466 | } | |
467 | ||
468 | static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) | |
469 | { | |
470 | struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); | |
471 | ||
472 | DPRINTF(0, "lower irq\n"); | |
473 | ||
474 | if (!msi_enabled(&d->card)) { | |
475 | qemu_irq_lower(s->irq); | |
476 | } | |
477 | } | |
478 | ||
479 | static void ahci_check_irq(AHCIState *s) | |
480 | { | |
481 | int i; | |
482 | ||
483 | DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); | |
484 | ||
485 | for (i = 0; i < SATA_PORTS; i++) { | |
486 | AHCIPortRegs *pr = &s->dev[i].port_regs; | |
487 | if (pr->irq_stat & pr->irq_mask) { | |
488 | s->control_regs.irqstatus |= (1 << i); | |
489 | } | |
490 | } | |
491 | ||
492 | if (s->control_regs.irqstatus && | |
493 | (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { | |
494 | ahci_irq_raise(s, NULL); | |
495 | } else { | |
496 | ahci_irq_lower(s, NULL); | |
497 | } | |
498 | } | |
499 | ||
500 | static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, | |
501 | int irq_type) | |
502 | { | |
503 | DPRINTF(d->port_no, "trigger irq %#x -> %x\n", | |
504 | irq_type, d->port_regs.irq_mask & irq_type); | |
505 | ||
506 | d->port_regs.irq_stat |= irq_type; | |
507 | ahci_check_irq(s); | |
508 | } | |
509 | ||
510 | static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted) | |
511 | { | |
512 | target_phys_addr_t len = wanted; | |
513 | ||
514 | if (*ptr) { | |
fe6ceac8 | 515 | cpu_physical_memory_unmap(*ptr, len, 1, len); |
f6ad2e32 AG |
516 | } |
517 | ||
518 | *ptr = cpu_physical_memory_map(addr, &len, 1); | |
519 | if (len < wanted) { | |
fe6ceac8 | 520 | cpu_physical_memory_unmap(*ptr, len, 1, len); |
f6ad2e32 AG |
521 | *ptr = NULL; |
522 | } | |
523 | } | |
524 | ||
525 | static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) | |
526 | { | |
527 | AHCIPortRegs *pr = &s->dev[port].port_regs; | |
528 | ||
529 | DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); | |
530 | switch (offset) { | |
531 | case PORT_LST_ADDR: | |
532 | pr->lst_addr = val; | |
533 | map_page(&s->dev[port].lst, | |
534 | ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); | |
535 | s->dev[port].cur_cmd = NULL; | |
536 | break; | |
537 | case PORT_LST_ADDR_HI: | |
538 | pr->lst_addr_hi = val; | |
539 | map_page(&s->dev[port].lst, | |
540 | ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); | |
541 | s->dev[port].cur_cmd = NULL; | |
542 | break; | |
543 | case PORT_FIS_ADDR: | |
544 | pr->fis_addr = val; | |
545 | map_page(&s->dev[port].res_fis, | |
546 | ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); | |
547 | break; | |
548 | case PORT_FIS_ADDR_HI: | |
549 | pr->fis_addr_hi = val; | |
550 | map_page(&s->dev[port].res_fis, | |
551 | ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); | |
552 | break; | |
553 | case PORT_IRQ_STAT: | |
554 | pr->irq_stat &= ~val; | |
555 | break; | |
556 | case PORT_IRQ_MASK: | |
557 | pr->irq_mask = val & 0xfdc000ff; | |
558 | ahci_check_irq(s); | |
559 | break; | |
560 | case PORT_CMD: | |
561 | pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); | |
562 | ||
563 | if (pr->cmd & PORT_CMD_START) { | |
564 | pr->cmd |= PORT_CMD_LIST_ON; | |
565 | } | |
566 | ||
567 | if (pr->cmd & PORT_CMD_FIS_RX) { | |
568 | pr->cmd |= PORT_CMD_FIS_ON; | |
569 | } | |
570 | ||
571 | check_cmd(s, port); | |
572 | break; | |
573 | case PORT_TFDATA: | |
574 | s->dev[port].port.ifs[0].error = (val >> 8) & 0xff; | |
575 | s->dev[port].port.ifs[0].status = val & 0xff; | |
576 | break; | |
577 | case PORT_SIG: | |
578 | pr->sig = val; | |
579 | break; | |
580 | case PORT_SCR_STAT: | |
581 | pr->scr_stat = val; | |
582 | break; | |
583 | case PORT_SCR_CTL: | |
584 | if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && | |
585 | ((val & AHCI_SCR_SCTL_DET) == 0)) { | |
586 | ahci_reset_port(s, port); | |
587 | } | |
588 | pr->scr_ctl = val; | |
589 | break; | |
590 | case PORT_SCR_ERR: | |
591 | pr->scr_err &= ~val; | |
592 | break; | |
593 | case PORT_SCR_ACT: | |
594 | /* RW1 */ | |
595 | pr->scr_act |= val; | |
596 | break; | |
597 | case PORT_CMD_ISSUE: | |
598 | pr->cmd_issue |= val; | |
599 | check_cmd(s, port); | |
600 | break; | |
601 | default: | |
602 | break; | |
603 | } | |
604 | } | |
605 | ||
606 | static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr) | |
607 | { | |
608 | AHCIState *s = ptr; | |
609 | uint32_t val = 0; | |
610 | ||
611 | addr = addr & 0xfff; | |
612 | if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { | |
613 | switch (addr) { | |
614 | case HOST_CAP: | |
615 | val = s->control_regs.cap; | |
616 | break; | |
617 | case HOST_CTL: | |
618 | val = s->control_regs.ghc; | |
619 | break; | |
620 | case HOST_IRQ_STAT: | |
621 | val = s->control_regs.irqstatus; | |
622 | break; | |
623 | case HOST_PORTS_IMPL: | |
624 | val = s->control_regs.impl; | |
625 | break; | |
626 | case HOST_VERSION: | |
627 | val = s->control_regs.version; | |
628 | break; | |
629 | } | |
630 | ||
631 | DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); | |
632 | } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && | |
633 | (addr < AHCI_PORT_REGS_END_ADDR)) { | |
634 | val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, | |
635 | addr & AHCI_PORT_ADDR_OFFSET_MASK); | |
636 | } | |
637 | ||
638 | return val; | |
639 | } | |
640 | ||
641 | ||
642 | ||
643 | static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
644 | { | |
645 | AHCIState *s = ptr; | |
646 | addr = addr & 0xfff; | |
647 | ||
648 | /* Only aligned reads are allowed on AHCI */ | |
649 | if (addr & 3) { | |
650 | fprintf(stderr, "ahci: Mis-aligned write to addr 0x" | |
651 | TARGET_FMT_plx "\n", addr); | |
652 | return; | |
653 | } | |
654 | ||
655 | if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { | |
656 | DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); | |
657 | ||
658 | switch (addr) { | |
659 | case HOST_CAP: /* R/WO, RO */ | |
660 | /* FIXME handle R/WO */ | |
661 | break; | |
662 | case HOST_CTL: /* R/W */ | |
663 | if (val & HOST_CTL_RESET) { | |
664 | DPRINTF(-1, "HBA Reset\n"); | |
665 | /* FIXME reset? */ | |
666 | } else { | |
667 | s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; | |
668 | ahci_check_irq(s); | |
669 | } | |
670 | break; | |
671 | case HOST_IRQ_STAT: /* R/WC, RO */ | |
672 | s->control_regs.irqstatus &= ~val; | |
673 | ahci_check_irq(s); | |
674 | break; | |
675 | case HOST_PORTS_IMPL: /* R/WO, RO */ | |
676 | /* FIXME handle R/WO */ | |
677 | break; | |
678 | case HOST_VERSION: /* RO */ | |
679 | /* FIXME report write? */ | |
680 | break; | |
681 | default: | |
682 | DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); | |
683 | } | |
684 | } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && | |
685 | (addr < AHCI_PORT_REGS_END_ADDR)) { | |
686 | ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, | |
687 | addr & AHCI_PORT_ADDR_OFFSET_MASK, val); | |
688 | } | |
689 | ||
690 | } | |
691 | ||
692 | static CPUReadMemoryFunc * const ahci_readfn[3]={ | |
693 | ahci_mem_readl, | |
694 | ahci_mem_readl, | |
695 | ahci_mem_readl | |
696 | }; | |
697 | ||
698 | static CPUWriteMemoryFunc * const ahci_writefn[3]={ | |
699 | ahci_mem_writel, | |
700 | ahci_mem_writel, | |
701 | ahci_mem_writel | |
702 | }; | |
703 | ||
704 | static void ahci_reg_init(AHCIState *s) | |
705 | { | |
706 | int i; | |
707 | ||
708 | s->control_regs.cap = (SATA_PORTS - 1) | | |
709 | (AHCI_NUM_COMMAND_SLOTS << 8) | | |
710 | (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | | |
711 | HOST_CAP_NCQ | HOST_CAP_AHCI; | |
712 | ||
713 | s->control_regs.impl = (1 << SATA_PORTS) - 1; | |
714 | ||
715 | s->control_regs.version = AHCI_VERSION_1_0; | |
716 | ||
717 | for (i = 0; i < SATA_PORTS; i++) { | |
718 | s->dev[i].port_state = STATE_RUN; | |
719 | } | |
720 | } | |
721 | ||
722 | static uint32_t read_from_sglist(uint8_t *buffer, uint32_t len, | |
723 | QEMUSGList *sglist) | |
724 | { | |
725 | uint32_t i = 0; | |
726 | uint32_t total = 0, once; | |
727 | ScatterGatherEntry *cur_prd; | |
728 | uint32_t sgcount; | |
729 | ||
730 | cur_prd = sglist->sg; | |
731 | sgcount = sglist->nsg; | |
732 | for (i = 0; len && sgcount; i++) { | |
733 | once = MIN(cur_prd->len, len); | |
734 | cpu_physical_memory_read(cur_prd->base, buffer, once); | |
735 | cur_prd++; | |
736 | sgcount--; | |
737 | len -= once; | |
738 | buffer += once; | |
739 | total += once; | |
740 | } | |
741 | ||
742 | return total; | |
743 | } | |
744 | ||
745 | static uint32_t write_to_sglist(uint8_t *buffer, uint32_t len, | |
746 | QEMUSGList *sglist) | |
747 | { | |
748 | uint32_t i = 0; | |
749 | uint32_t total = 0, once; | |
750 | ScatterGatherEntry *cur_prd; | |
751 | uint32_t sgcount; | |
752 | ||
753 | DPRINTF(-1, "total: 0x%x bytes\n", len); | |
754 | ||
755 | cur_prd = sglist->sg; | |
756 | sgcount = sglist->nsg; | |
757 | for (i = 0; len && sgcount; i++) { | |
758 | once = MIN(cur_prd->len, len); | |
759 | DPRINTF(-1, "write 0x%x bytes to 0x%lx\n", once, (long)cur_prd->base); | |
760 | cpu_physical_memory_write(cur_prd->base, buffer, once); | |
761 | cur_prd++; | |
762 | sgcount--; | |
763 | len -= once; | |
764 | buffer += once; | |
765 | total += once; | |
766 | } | |
767 | ||
768 | return total; | |
769 | } | |
770 | ||
771 | static void check_cmd(AHCIState *s, int port) | |
772 | { | |
773 | AHCIPortRegs *pr = &s->dev[port].port_regs; | |
774 | int slot; | |
775 | ||
776 | if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { | |
777 | for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { | |
778 | if ((pr->cmd_issue & (1 << slot)) && | |
779 | !handle_cmd(s, port, slot)) { | |
780 | pr->cmd_issue &= ~(1 << slot); | |
781 | } | |
782 | } | |
783 | } | |
784 | } | |
785 | ||
786 | static void ahci_check_cmd_bh(void *opaque) | |
787 | { | |
788 | AHCIDevice *ad = opaque; | |
789 | ||
790 | qemu_bh_delete(ad->check_bh); | |
791 | ad->check_bh = NULL; | |
792 | ||
793 | if ((ad->busy_slot != -1) && | |
794 | !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { | |
795 | /* no longer busy */ | |
796 | ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); | |
797 | ad->busy_slot = -1; | |
798 | } | |
799 | ||
800 | check_cmd(ad->hba, ad->port_no); | |
801 | } | |
802 | ||
803 | static void ahci_reset_port(AHCIState *s, int port) | |
804 | { | |
805 | AHCIDevice *d = &s->dev[port]; | |
806 | AHCIPortRegs *pr = &d->port_regs; | |
807 | IDEState *ide_state = &d->port.ifs[0]; | |
808 | uint8_t init_fis[0x20]; | |
f6ad2e32 AG |
809 | int i; |
810 | ||
811 | DPRINTF(port, "reset port\n"); | |
812 | ||
813 | ide_bus_reset(&d->port); | |
814 | ide_state->ncq_queues = AHCI_MAX_CMDS; | |
815 | ||
816 | pr->irq_stat = 0; | |
817 | pr->irq_mask = 0; | |
818 | pr->scr_stat = 0; | |
819 | pr->scr_ctl = 0; | |
820 | pr->scr_err = 0; | |
821 | pr->scr_act = 0; | |
822 | d->busy_slot = -1; | |
823 | ||
824 | ide_state = &s->dev[port].port.ifs[0]; | |
825 | if (!ide_state->bs) { | |
826 | return; | |
827 | } | |
828 | ||
829 | /* reset ncq queue */ | |
830 | for (i = 0; i < AHCI_MAX_CMDS; i++) { | |
831 | NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; | |
832 | if (!ncq_tfs->used) { | |
833 | continue; | |
834 | } | |
835 | ||
836 | if (ncq_tfs->aiocb) { | |
837 | bdrv_aio_cancel(ncq_tfs->aiocb); | |
838 | ncq_tfs->aiocb = NULL; | |
839 | } | |
840 | ||
841 | qemu_sglist_destroy(&ncq_tfs->sglist); | |
842 | ncq_tfs->used = 0; | |
843 | } | |
844 | ||
845 | memset(init_fis, 0, sizeof(init_fis)); | |
846 | s->dev[port].port_state = STATE_RUN; | |
847 | if (!ide_state->bs) { | |
848 | s->dev[port].port_regs.sig = 0; | |
cdfe17df | 849 | ide_state->status = SEEK_STAT | WRERR_STAT; |
f6ad2e32 AG |
850 | } else if (ide_state->drive_kind == IDE_CD) { |
851 | s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM; | |
852 | ide_state->lcyl = 0x14; | |
853 | ide_state->hcyl = 0xeb; | |
854 | DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl); | |
855 | init_fis[5] = ide_state->lcyl; | |
856 | init_fis[6] = ide_state->hcyl; | |
857 | ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; | |
858 | } else { | |
859 | s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK; | |
860 | ide_state->status = SEEK_STAT | WRERR_STAT; | |
861 | } | |
862 | ||
863 | ide_state->error = 1; | |
864 | init_fis[4] = 1; | |
865 | init_fis[12] = 1; | |
866 | ahci_write_fis_d2h(d, init_fis); | |
867 | } | |
868 | ||
869 | static void debug_print_fis(uint8_t *fis, int cmd_len) | |
870 | { | |
871 | #ifdef DEBUG_AHCI | |
872 | int i; | |
873 | ||
874 | fprintf(stderr, "fis:"); | |
875 | for (i = 0; i < cmd_len; i++) { | |
876 | if ((i & 0xf) == 0) { | |
877 | fprintf(stderr, "\n%02x:",i); | |
878 | } | |
879 | fprintf(stderr, "%02x ",fis[i]); | |
880 | } | |
881 | fprintf(stderr, "\n"); | |
882 | #endif | |
883 | } | |
884 | ||
885 | static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) | |
886 | { | |
887 | AHCIPortRegs *pr = &s->dev[port].port_regs; | |
888 | IDEState *ide_state; | |
889 | uint8_t *sdb_fis; | |
890 | ||
891 | if (!s->dev[port].res_fis || | |
892 | !(pr->cmd & PORT_CMD_FIS_RX)) { | |
893 | return; | |
894 | } | |
895 | ||
896 | sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS]; | |
897 | ide_state = &s->dev[port].port.ifs[0]; | |
898 | ||
899 | /* clear memory */ | |
900 | *(uint32_t*)sdb_fis = 0; | |
901 | ||
902 | /* write values */ | |
903 | sdb_fis[0] = ide_state->error; | |
904 | sdb_fis[2] = ide_state->status & 0x77; | |
905 | s->dev[port].finished |= finished; | |
906 | *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished); | |
907 | ||
908 | ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS); | |
909 | } | |
910 | ||
911 | static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) | |
912 | { | |
913 | AHCIPortRegs *pr = &ad->port_regs; | |
914 | uint8_t *d2h_fis; | |
915 | int i; | |
916 | target_phys_addr_t cmd_len = 0x80; | |
917 | int cmd_mapped = 0; | |
918 | ||
919 | if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { | |
920 | return; | |
921 | } | |
922 | ||
923 | if (!cmd_fis) { | |
924 | /* map cmd_fis */ | |
925 | uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); | |
926 | cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 0); | |
927 | cmd_mapped = 1; | |
928 | } | |
929 | ||
930 | d2h_fis = &ad->res_fis[RES_FIS_RFIS]; | |
931 | ||
932 | d2h_fis[0] = 0x34; | |
933 | d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); | |
934 | d2h_fis[2] = ad->port.ifs[0].status; | |
935 | d2h_fis[3] = ad->port.ifs[0].error; | |
936 | ||
937 | d2h_fis[4] = cmd_fis[4]; | |
938 | d2h_fis[5] = cmd_fis[5]; | |
939 | d2h_fis[6] = cmd_fis[6]; | |
940 | d2h_fis[7] = cmd_fis[7]; | |
941 | d2h_fis[8] = cmd_fis[8]; | |
942 | d2h_fis[9] = cmd_fis[9]; | |
943 | d2h_fis[10] = cmd_fis[10]; | |
944 | d2h_fis[11] = cmd_fis[11]; | |
945 | d2h_fis[12] = cmd_fis[12]; | |
946 | d2h_fis[13] = cmd_fis[13]; | |
947 | for (i = 14; i < 0x20; i++) { | |
948 | d2h_fis[i] = 0; | |
949 | } | |
950 | ||
951 | if (d2h_fis[2] & ERR_STAT) { | |
952 | ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_TFES); | |
953 | } | |
954 | ||
955 | ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); | |
956 | ||
957 | if (cmd_mapped) { | |
fe6ceac8 | 958 | cpu_physical_memory_unmap(cmd_fis, cmd_len, 0, cmd_len); |
f6ad2e32 AG |
959 | } |
960 | } | |
961 | ||
962 | static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist) | |
963 | { | |
964 | AHCICmdHdr *cmd = ad->cur_cmd; | |
965 | uint32_t opts = le32_to_cpu(cmd->opts); | |
966 | uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; | |
967 | int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; | |
968 | target_phys_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); | |
969 | target_phys_addr_t real_prdt_len = prdt_len; | |
970 | uint8_t *prdt; | |
971 | int i; | |
972 | int r = 0; | |
973 | ||
974 | if (!sglist_alloc_hint) { | |
975 | DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); | |
976 | return -1; | |
977 | } | |
978 | ||
979 | /* map PRDT */ | |
980 | if (!(prdt = cpu_physical_memory_map(prdt_addr, &prdt_len, 0))){ | |
981 | DPRINTF(ad->port_no, "map failed\n"); | |
982 | return -1; | |
983 | } | |
984 | ||
985 | if (prdt_len < real_prdt_len) { | |
986 | DPRINTF(ad->port_no, "mapped less than expected\n"); | |
987 | r = -1; | |
988 | goto out; | |
989 | } | |
990 | ||
991 | /* Get entries in the PRDT, init a qemu sglist accordingly */ | |
992 | if (sglist_alloc_hint > 0) { | |
993 | AHCI_SG *tbl = (AHCI_SG *)prdt; | |
994 | ||
995 | qemu_sglist_init(sglist, sglist_alloc_hint); | |
996 | for (i = 0; i < sglist_alloc_hint; i++) { | |
997 | /* flags_size is zero-based */ | |
998 | qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), | |
999 | le32_to_cpu(tbl[i].flags_size) + 1); | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | out: | |
fe6ceac8 | 1004 | cpu_physical_memory_unmap(prdt, prdt_len, 0, prdt_len); |
f6ad2e32 AG |
1005 | return r; |
1006 | } | |
1007 | ||
1008 | static void ncq_cb(void *opaque, int ret) | |
1009 | { | |
1010 | NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; | |
1011 | IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; | |
1012 | ||
1013 | /* Clear bit for this tag in SActive */ | |
1014 | ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag); | |
1015 | ||
1016 | if (ret < 0) { | |
1017 | /* error */ | |
1018 | ide_state->error = ABRT_ERR; | |
1019 | ide_state->status = READY_STAT | ERR_STAT; | |
1020 | ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); | |
1021 | } else { | |
1022 | ide_state->status = READY_STAT | SEEK_STAT; | |
1023 | } | |
1024 | ||
1025 | ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, | |
1026 | (1 << ncq_tfs->tag)); | |
1027 | ||
1028 | DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", | |
1029 | ncq_tfs->tag); | |
1030 | ||
1031 | qemu_sglist_destroy(&ncq_tfs->sglist); | |
1032 | ncq_tfs->used = 0; | |
1033 | } | |
1034 | ||
1035 | static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, | |
1036 | int slot) | |
1037 | { | |
1038 | NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; | |
1039 | uint8_t tag = ncq_fis->tag >> 3; | |
1040 | NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag]; | |
1041 | ||
1042 | if (ncq_tfs->used) { | |
1043 | /* error - already in use */ | |
1044 | fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); | |
1045 | return; | |
1046 | } | |
1047 | ||
1048 | ncq_tfs->used = 1; | |
1049 | ncq_tfs->drive = &s->dev[port]; | |
1050 | ncq_tfs->slot = slot; | |
1051 | ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | | |
1052 | ((uint64_t)ncq_fis->lba4 << 32) | | |
1053 | ((uint64_t)ncq_fis->lba3 << 24) | | |
1054 | ((uint64_t)ncq_fis->lba2 << 16) | | |
1055 | ((uint64_t)ncq_fis->lba1 << 8) | | |
1056 | (uint64_t)ncq_fis->lba0; | |
1057 | ||
1058 | /* Note: We calculate the sector count, but don't currently rely on it. | |
1059 | * The total size of the DMA buffer tells us the transfer size instead. */ | |
1060 | ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) | | |
1061 | ncq_fis->sector_count_low; | |
1062 | ||
1063 | DPRINTF(port, "NCQ transfer LBA from %ld to %ld, drive max %ld\n", | |
1064 | ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2, | |
1065 | s->dev[port].port.ifs[0].nb_sectors - 1); | |
1066 | ||
1067 | ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist); | |
1068 | ncq_tfs->tag = tag; | |
1069 | ||
1070 | switch(ncq_fis->command) { | |
1071 | case READ_FPDMA_QUEUED: | |
1072 | DPRINTF(port, "NCQ reading %d sectors from LBA %ld, tag %d\n", | |
1073 | ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); | |
1074 | ncq_tfs->is_read = 1; | |
1075 | ||
1076 | DPRINTF(port, "tag %d aio read %ld\n", ncq_tfs->tag, ncq_tfs->lba); | |
1077 | ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, | |
1078 | &ncq_tfs->sglist, ncq_tfs->lba, | |
1079 | ncq_cb, ncq_tfs); | |
1080 | break; | |
1081 | case WRITE_FPDMA_QUEUED: | |
1082 | DPRINTF(port, "NCQ writing %d sectors to LBA %ld, tag %d\n", | |
1083 | ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); | |
1084 | ncq_tfs->is_read = 0; | |
1085 | ||
1086 | DPRINTF(port, "tag %d aio write %ld\n", ncq_tfs->tag, ncq_tfs->lba); | |
1087 | ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, | |
1088 | &ncq_tfs->sglist, ncq_tfs->lba, | |
1089 | ncq_cb, ncq_tfs); | |
1090 | break; | |
1091 | default: | |
1092 | DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n"); | |
1093 | qemu_sglist_destroy(&ncq_tfs->sglist); | |
1094 | break; | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | static int handle_cmd(AHCIState *s, int port, int slot) | |
1099 | { | |
1100 | IDEState *ide_state; | |
f6ad2e32 AG |
1101 | uint32_t opts; |
1102 | uint64_t tbl_addr; | |
1103 | AHCICmdHdr *cmd; | |
1104 | uint8_t *cmd_fis; | |
1105 | target_phys_addr_t cmd_len; | |
1106 | ||
1107 | if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { | |
1108 | /* Engine currently busy, try again later */ | |
1109 | DPRINTF(port, "engine busy\n"); | |
1110 | return -1; | |
1111 | } | |
1112 | ||
f6ad2e32 AG |
1113 | cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot]; |
1114 | ||
1115 | if (!s->dev[port].lst) { | |
1116 | DPRINTF(port, "error: lst not given but cmd handled"); | |
1117 | return -1; | |
1118 | } | |
1119 | ||
1120 | /* remember current slot handle for later */ | |
1121 | s->dev[port].cur_cmd = cmd; | |
1122 | ||
1123 | opts = le32_to_cpu(cmd->opts); | |
1124 | tbl_addr = le64_to_cpu(cmd->tbl_addr); | |
1125 | ||
1126 | cmd_len = 0x80; | |
1127 | cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 1); | |
1128 | ||
1129 | if (!cmd_fis) { | |
1130 | DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); | |
1131 | return -1; | |
1132 | } | |
1133 | ||
1134 | /* The device we are working for */ | |
1135 | ide_state = &s->dev[port].port.ifs[0]; | |
1136 | ||
1137 | if (!ide_state->bs) { | |
1138 | DPRINTF(port, "error: guest accessed unused port"); | |
1139 | goto out; | |
1140 | } | |
1141 | ||
1142 | debug_print_fis(cmd_fis, 0x90); | |
1143 | //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4); | |
1144 | ||
1145 | switch (cmd_fis[0]) { | |
1146 | case SATA_FIS_TYPE_REGISTER_H2D: | |
1147 | break; | |
1148 | default: | |
1149 | DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " | |
1150 | "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], | |
1151 | cmd_fis[2]); | |
1152 | goto out; | |
1153 | break; | |
1154 | } | |
1155 | ||
1156 | switch (cmd_fis[1]) { | |
1157 | case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER: | |
1158 | break; | |
1159 | case 0: | |
1160 | break; | |
1161 | default: | |
1162 | DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " | |
1163 | "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], | |
1164 | cmd_fis[2]); | |
1165 | goto out; | |
1166 | break; | |
1167 | } | |
1168 | ||
1169 | switch (s->dev[port].port_state) { | |
1170 | case STATE_RUN: | |
1171 | if (cmd_fis[15] & ATA_SRST) { | |
1172 | s->dev[port].port_state = STATE_RESET; | |
1173 | } | |
1174 | break; | |
1175 | case STATE_RESET: | |
1176 | if (!(cmd_fis[15] & ATA_SRST)) { | |
1177 | ahci_reset_port(s, port); | |
1178 | } | |
1179 | break; | |
1180 | } | |
1181 | ||
1182 | if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) { | |
1183 | ||
1184 | /* Check for NCQ command */ | |
1185 | if ((cmd_fis[2] == READ_FPDMA_QUEUED) || | |
1186 | (cmd_fis[2] == WRITE_FPDMA_QUEUED)) { | |
1187 | process_ncq_command(s, port, cmd_fis, slot); | |
1188 | goto out; | |
1189 | } | |
1190 | ||
1191 | /* Decompose the FIS */ | |
1192 | ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); | |
1193 | ide_state->feature = cmd_fis[3]; | |
1194 | if (!ide_state->nsector) { | |
1195 | ide_state->nsector = 256; | |
1196 | } | |
1197 | ||
1198 | if (ide_state->drive_kind != IDE_CD) { | |
1199 | ide_set_sector(ide_state, (cmd_fis[6] << 16) | (cmd_fis[5] << 8) | | |
1200 | cmd_fis[4]); | |
1201 | } | |
1202 | ||
1203 | /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command | |
1204 | * table to ide_state->io_buffer | |
1205 | */ | |
1206 | if (opts & AHCI_CMD_ATAPI) { | |
1207 | memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); | |
1208 | ide_state->lcyl = 0x14; | |
1209 | ide_state->hcyl = 0xeb; | |
1210 | debug_print_fis(ide_state->io_buffer, 0x10); | |
1211 | ide_state->feature = IDE_FEATURE_DMA; | |
1212 | s->dev[port].done_atapi_packet = 0; | |
1213 | /* XXX send PIO setup FIS */ | |
1214 | } | |
1215 | ||
1216 | ide_state->error = 0; | |
1217 | ||
1218 | /* Reset transferred byte counter */ | |
1219 | cmd->status = 0; | |
1220 | ||
1221 | /* We're ready to process the command in FIS byte 2. */ | |
1222 | ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); | |
1223 | ||
1224 | if (s->dev[port].port.ifs[0].status & READY_STAT) { | |
1225 | ahci_write_fis_d2h(&s->dev[port], cmd_fis); | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | out: | |
fe6ceac8 | 1230 | cpu_physical_memory_unmap(cmd_fis, cmd_len, 1, cmd_len); |
f6ad2e32 AG |
1231 | |
1232 | if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { | |
1233 | /* async command, complete later */ | |
1234 | s->dev[port].busy_slot = slot; | |
1235 | return -1; | |
1236 | } | |
1237 | ||
1238 | /* done handling the command */ | |
1239 | return 0; | |
1240 | } | |
1241 | ||
1242 | /* DMA dev <-> ram */ | |
1243 | static int ahci_start_transfer(IDEDMA *dma) | |
1244 | { | |
1245 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1246 | IDEState *s = &ad->port.ifs[0]; | |
1247 | uint32_t size = (uint32_t)(s->data_end - s->data_ptr); | |
1248 | /* write == ram -> device */ | |
1249 | uint32_t opts = le32_to_cpu(ad->cur_cmd->opts); | |
1250 | int is_write = opts & AHCI_CMD_WRITE; | |
1251 | int is_atapi = opts & AHCI_CMD_ATAPI; | |
1252 | int has_sglist = 0; | |
1253 | ||
1254 | if (is_atapi && !ad->done_atapi_packet) { | |
1255 | /* already prepopulated iobuffer */ | |
1256 | ad->done_atapi_packet = 1; | |
1257 | goto out; | |
1258 | } | |
1259 | ||
1260 | if (!ahci_populate_sglist(ad, &s->sg)) { | |
1261 | has_sglist = 1; | |
1262 | } | |
1263 | ||
1264 | DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", | |
1265 | is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", | |
1266 | has_sglist ? "" : "o"); | |
1267 | ||
1268 | if (is_write && has_sglist && (s->data_ptr < s->data_end)) { | |
1269 | read_from_sglist(s->data_ptr, size, &s->sg); | |
1270 | } | |
1271 | ||
1272 | if (!is_write && has_sglist && (s->data_ptr < s->data_end)) { | |
1273 | write_to_sglist(s->data_ptr, size, &s->sg); | |
1274 | } | |
1275 | ||
1276 | /* update number of transferred bytes */ | |
1277 | ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size); | |
1278 | ||
1279 | out: | |
1280 | /* declare that we processed everything */ | |
1281 | s->data_ptr = s->data_end; | |
1282 | ||
1283 | if (has_sglist) { | |
1284 | qemu_sglist_destroy(&s->sg); | |
1285 | } | |
1286 | ||
1287 | s->end_transfer_func(s); | |
1288 | ||
1289 | if (!(s->status & DRQ_STAT)) { | |
1290 | /* done with DMA */ | |
1291 | ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); | |
1292 | } | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static void ahci_start_dma(IDEDMA *dma, IDEState *s, | |
1298 | BlockDriverCompletionFunc *dma_cb) | |
1299 | { | |
1300 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1301 | ||
1302 | DPRINTF(ad->port_no, "\n"); | |
1303 | ad->dma_cb = dma_cb; | |
1304 | ad->dma_status |= BM_STATUS_DMAING; | |
1305 | dma_cb(s, 0); | |
1306 | } | |
1307 | ||
1308 | static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write) | |
1309 | { | |
1310 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1311 | IDEState *s = &ad->port.ifs[0]; | |
1312 | int i; | |
1313 | ||
1314 | ahci_populate_sglist(ad, &s->sg); | |
1315 | ||
1316 | s->io_buffer_size = 0; | |
1317 | for (i = 0; i < s->sg.nsg; i++) { | |
1318 | s->io_buffer_size += s->sg.sg[i].len; | |
1319 | } | |
1320 | ||
1321 | DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); | |
1322 | return s->io_buffer_size != 0; | |
1323 | } | |
1324 | ||
1325 | static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) | |
1326 | { | |
1327 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1328 | IDEState *s = &ad->port.ifs[0]; | |
1329 | uint8_t *p = s->io_buffer + s->io_buffer_index; | |
1330 | int l = s->io_buffer_size - s->io_buffer_index; | |
1331 | ||
1332 | if (ahci_populate_sglist(ad, &s->sg)) { | |
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | if (is_write) { | |
1337 | write_to_sglist(p, l, &s->sg); | |
1338 | } else { | |
1339 | read_from_sglist(p, l, &s->sg); | |
1340 | } | |
1341 | ||
1342 | /* update number of transferred bytes */ | |
1343 | ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l); | |
1344 | s->io_buffer_index += l; | |
1345 | ||
1346 | DPRINTF(ad->port_no, "len=%#x\n", l); | |
1347 | ||
1348 | return 1; | |
1349 | } | |
1350 | ||
1351 | static int ahci_dma_set_unit(IDEDMA *dma, int unit) | |
1352 | { | |
1353 | /* only a single unit per link */ | |
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | static int ahci_dma_add_status(IDEDMA *dma, int status) | |
1358 | { | |
1359 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1360 | ad->dma_status |= status; | |
1361 | DPRINTF(ad->port_no, "set status: %x\n", status); | |
1362 | ||
1363 | if (status & BM_STATUS_INT) { | |
1364 | ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); | |
1365 | } | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | static int ahci_dma_set_inactive(IDEDMA *dma) | |
1371 | { | |
1372 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1373 | ||
1374 | DPRINTF(ad->port_no, "dma done\n"); | |
1375 | ||
1376 | /* update d2h status */ | |
1377 | ahci_write_fis_d2h(ad, NULL); | |
1378 | ||
1379 | ad->dma_cb = NULL; | |
1380 | ||
1381 | /* maybe we still have something to process, check later */ | |
1382 | ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); | |
1383 | qemu_bh_schedule(ad->check_bh); | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
1388 | static void ahci_irq_set(void *opaque, int n, int level) | |
1389 | { | |
1390 | } | |
1391 | ||
1392 | static void ahci_dma_restart_cb(void *opaque, int running, int reason) | |
1393 | { | |
1394 | } | |
1395 | ||
1396 | static int ahci_dma_reset(IDEDMA *dma) | |
1397 | { | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static const IDEDMAOps ahci_dma_ops = { | |
1402 | .start_dma = ahci_start_dma, | |
1403 | .start_transfer = ahci_start_transfer, | |
1404 | .prepare_buf = ahci_dma_prepare_buf, | |
1405 | .rw_buf = ahci_dma_rw_buf, | |
1406 | .set_unit = ahci_dma_set_unit, | |
1407 | .add_status = ahci_dma_add_status, | |
1408 | .set_inactive = ahci_dma_set_inactive, | |
1409 | .restart_cb = ahci_dma_restart_cb, | |
1410 | .reset = ahci_dma_reset, | |
1411 | }; | |
1412 | ||
1413 | static void ahci_init(AHCIState *s, DeviceState *qdev) | |
1414 | { | |
1415 | qemu_irq *irqs; | |
1416 | int i; | |
1417 | ||
1418 | ahci_reg_init(s); | |
1419 | s->mem = cpu_register_io_memory(ahci_readfn, ahci_writefn, s, | |
1420 | DEVICE_LITTLE_ENDIAN); | |
1421 | irqs = qemu_allocate_irqs(ahci_irq_set, s, SATA_PORTS); | |
1422 | ||
1423 | for (i = 0; i < SATA_PORTS; i++) { | |
1424 | AHCIDevice *ad = &s->dev[i]; | |
1425 | ||
1426 | ide_bus_new(&ad->port, qdev, i); | |
1427 | ide_init2(&ad->port, irqs[i]); | |
1428 | ||
1429 | ad->hba = s; | |
1430 | ad->port_no = i; | |
1431 | ad->port.dma = &ad->dma; | |
1432 | ad->port.dma->ops = &ahci_dma_ops; | |
1433 | ad->port_regs.cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; | |
1434 | } | |
1435 | } | |
1436 | ||
1437 | static void ahci_pci_map(PCIDevice *pci_dev, int region_num, | |
1438 | pcibus_t addr, pcibus_t size, int type) | |
1439 | { | |
1440 | struct AHCIPCIState *d = (struct AHCIPCIState *)pci_dev; | |
1441 | AHCIState *s = &d->ahci; | |
1442 | ||
1443 | cpu_register_physical_memory(addr, size, s->mem); | |
1444 | } | |
1445 | ||
1446 | static void ahci_reset(void *opaque) | |
1447 | { | |
1448 | struct AHCIPCIState *d = opaque; | |
1449 | int i; | |
1450 | ||
1451 | for (i = 0; i < SATA_PORTS; i++) { | |
1452 | ahci_reset_port(&d->ahci, i); | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | static int pci_ahci_init(PCIDevice *dev) | |
1457 | { | |
1458 | struct AHCIPCIState *d; | |
1459 | d = DO_UPCAST(struct AHCIPCIState, card, dev); | |
1460 | ||
1461 | pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL); | |
1462 | pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR); | |
1463 | ||
1464 | pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA); | |
1465 | pci_config_set_revision(d->card.config, 0x02); | |
1466 | pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1); | |
1467 | ||
1468 | d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ | |
1469 | d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ | |
1470 | pci_config_set_interrupt_pin(d->card.config, 1); | |
1471 | ||
38a08f05 SH |
1472 | /* XXX Software should program this register */ |
1473 | d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ | |
1474 | ||
f6ad2e32 AG |
1475 | qemu_register_reset(ahci_reset, d); |
1476 | ||
1477 | /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ | |
1478 | pci_register_bar(&d->card, 5, 0x1000, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
1479 | ahci_pci_map); | |
1480 | ||
1481 | msi_init(dev, 0x50, 1, true, false); | |
1482 | ||
1483 | ahci_init(&d->ahci, &dev->qdev); | |
1484 | d->ahci.irq = d->card.irq[0]; | |
1485 | ||
1486 | return 0; | |
1487 | } | |
1488 | ||
1489 | static int pci_ahci_uninit(PCIDevice *dev) | |
1490 | { | |
1491 | struct AHCIPCIState *d; | |
1492 | d = DO_UPCAST(struct AHCIPCIState, card, dev); | |
1493 | ||
1494 | if (msi_enabled(dev)) { | |
1495 | msi_uninit(dev); | |
1496 | } | |
1497 | ||
1498 | qemu_unregister_reset(ahci_reset, d); | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | static void pci_ahci_write_config(PCIDevice *pci, uint32_t addr, | |
1504 | uint32_t val, int len) | |
1505 | { | |
1506 | pci_default_write_config(pci, addr, val, len); | |
1507 | msi_write_config(pci, addr, val, len); | |
1508 | } | |
1509 | ||
1510 | static PCIDeviceInfo ahci_info = { | |
1511 | .qdev.name = "ahci", | |
1512 | .qdev.size = sizeof(AHCIPCIState), | |
1513 | .init = pci_ahci_init, | |
1514 | .exit = pci_ahci_uninit, | |
1515 | .config_write = pci_ahci_write_config, | |
1516 | }; | |
1517 | ||
1518 | static void ahci_pci_register_devices(void) | |
1519 | { | |
1520 | pci_qdev_register(&ahci_info); | |
1521 | } | |
1522 | ||
1523 | device_init(ahci_pci_register_devices) |