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ide: Fix crash with too long PRD
[qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787
GH		 25#include <hw/hw.h>
26#include <hw/pc.h>
27#include <hw/pci.h>
4a91d3b3 28#include <hw/isa.h>
c4d74df7 29#include "qemu-error.h"
87ecb68b
PB		 30#include "qemu-timer.h"
31#include "sysemu.h"
1fb8648d 32#include "dma.h"
9db1c0f7 33#include "hw/block-common.h"
2446333c 34#include "blockdev.h"
59f2a787
GH		 35
36#include <hw/ide/internal.h>
e8b54394 37
b93af93d
BW		 38/* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
5391d806
FB		 78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
d353fb72 82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 83
94458802
FB		 84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
5391d806
FB		 89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
67b915a5 91 put_le16(p + 0, 0x0040);
5fafdf24 92 put_le16(p + 1, s->cylinders);
67b915a5
FB		 93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 96 put_le16(p + 6, s->sectors);
fa879c64 97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
47c06340 101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 102 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 103#if MAX_MULT_SECTORS > 1
67b915a5 104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 105#endif
67b915a5 106 put_le16(p + 48, 1); /* dword I/O */
94458802 107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
5391d806 114 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
5391d806 117 if (s->mult_sectors)
67b915a5
FB		 118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
d1b5c20d 121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 123 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
d353fb72
CH		 128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
ccf0fd8b
RE		 131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
94458802
FB		 138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 144 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
145 if (s->wwn) {
146 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
147 } else {
148 put_le16(p + 84, (1 << 14) | 0);
149 }
e900a7b7
CH		 150 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
151 if (bdrv_enable_write_cache(s->bs))
152 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
153 else
154 put_le16(p + 85, (1 << 14) | 1);
c2ff060f 155 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 156 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 157 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
158 if (s->wwn) {
159 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
160 } else {
161 put_le16(p + 87, (1 << 14) | 0);
162 }
94458802
FB		 163 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
164 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
c2ff060f
FB		 165 put_le16(p + 100, s->nb_sectors);
166 put_le16(p + 101, s->nb_sectors >> 16);
167 put_le16(p + 102, s->nb_sectors >> 32);
168 put_le16(p + 103, s->nb_sectors >> 48);
d353fb72 169
57dac7ef
MA		 170 if (dev && dev->conf.physical_block_size)
171 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 172 if (s->wwn) {
173 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
174 put_le16(p + 108, s->wwn >> 48);
175 put_le16(p + 109, s->wwn >> 32);
176 put_le16(p + 110, s->wwn >> 16);
177 put_le16(p + 111, s->wwn);
178 }
d353fb72
CH		 179 if (dev && dev->conf.discard_granularity) {
180 put_le16(p + 169, 1); /* TRIM support */
181 }
94458802
FB		 182
183 memcpy(s->identify_data, p, sizeof(s->identify_data));
184 s->identify_set = 1;
5391d806
FB		 185}
186
187static void ide_atapi_identify(IDEState *s)
188{
189 uint16_t *p;
190
94458802
FB		 191 if (s->identify_set) {
192 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
193 return;
194 }
195
5391d806
FB		 196 memset(s->io_buffer, 0, 512);
197 p = (uint16_t *)s->io_buffer;
198 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 199 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 200 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 201 put_le16(p + 20, 3); /* buffer type */
202 put_le16(p + 21, 512); /* cache size in sectors */
203 put_le16(p + 22, 4); /* ecc bytes */
47c06340 204 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 205 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 206 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 207#ifdef USE_DMA_CDROM
208 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
209 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 210 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 211 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 212#else
67b915a5
FB		 213 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
214 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
215 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 216#endif
79d1d331 217 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 218 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
219 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
220 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
221 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 222
67b915a5
FB		 223 put_le16(p + 71, 30); /* in ns */
224 put_le16(p + 72, 30); /* in ns */
5391d806 225
1bdaa28d
AG		 226 if (s->ncq_queues) {
227 put_le16(p + 75, s->ncq_queues - 1);
228 /* NCQ supported */
229 put_le16(p + 76, (1 << 8));
230 }
231
67b915a5 232 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
8ccad811
FB		 233#ifdef USE_DMA_CDROM
234 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
235#endif
94458802
FB		 236 memcpy(s->identify_data, p, sizeof(s->identify_data));
237 s->identify_set = 1;
5391d806
FB		 238}
239
201a51fc
AZ		 240static void ide_cfata_identify(IDEState *s)
241{
242 uint16_t *p;
243 uint32_t cur_sec;
201a51fc
AZ		 244
245 p = (uint16_t *) s->identify_data;
246 if (s->identify_set)
247 goto fill_buffer;
248
249 memset(p, 0, sizeof(s->identify_data));
250
251 cur_sec = s->cylinders * s->heads * s->sectors;
252
253 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
254 put_le16(p + 1, s->cylinders); /* Default cylinders */
255 put_le16(p + 3, s->heads); /* Default heads */
256 put_le16(p + 6, s->sectors); /* Default sectors per track */
257 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
258 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
fa879c64 259 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 260 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 261 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 262 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 263#if MAX_MULT_SECTORS > 1
264 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
265#else
266 put_le16(p + 47, 0x0000);
267#endif
268 put_le16(p + 49, 0x0f00); /* Capabilities */
269 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
270 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
271 put_le16(p + 53, 0x0003); /* Translation params valid */
272 put_le16(p + 54, s->cylinders); /* Current cylinders */
273 put_le16(p + 55, s->heads); /* Current heads */
274 put_le16(p + 56, s->sectors); /* Current sectors */
275 put_le16(p + 57, cur_sec); /* Current capacity */
276 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
277 if (s->mult_sectors) /* Multiple sector setting */
278 put_le16(p + 59, 0x100 | s->mult_sectors);
279 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
280 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
281 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
282 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
283 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
284 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
285 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
286 put_le16(p + 82, 0x400c); /* Command Set supported */
287 put_le16(p + 83, 0x7068); /* Command Set supported */
288 put_le16(p + 84, 0x4000); /* Features supported */
289 put_le16(p + 85, 0x000c); /* Command Set enabled */
290 put_le16(p + 86, 0x7044); /* Command Set enabled */
291 put_le16(p + 87, 0x4000); /* Features enabled */
292 put_le16(p + 91, 0x4060); /* Current APM level */
293 put_le16(p + 129, 0x0002); /* Current features option */
294 put_le16(p + 130, 0x0005); /* Reassigned sectors */
295 put_le16(p + 131, 0x0001); /* Initial power mode */
296 put_le16(p + 132, 0x0000); /* User signature */
297 put_le16(p + 160, 0x8100); /* Power requirement */
298 put_le16(p + 161, 0x8001); /* CF command set */
299
300 s->identify_set = 1;
301
302fill_buffer:
303 memcpy(s->io_buffer, p, sizeof(s->identify_data));
304}
305
5391d806
FB		 306static void ide_set_signature(IDEState *s)
307{
308 s->select &= 0xf0; /* clear head */
309 /* put signature */
310 s->nsector = 1;
311 s->sector = 1;
cd8722bb 312 if (s->drive_kind == IDE_CD) {
5391d806
FB		 313 s->lcyl = 0x14;
314 s->hcyl = 0xeb;
315 } else if (s->bs) {
316 s->lcyl = 0;
317 s->hcyl = 0;
318 } else {
319 s->lcyl = 0xff;
320 s->hcyl = 0xff;
321 }
322}
323
d353fb72
CH		 324typedef struct TrimAIOCB {
325 BlockDriverAIOCB common;
326 QEMUBH *bh;
327 int ret;
328} TrimAIOCB;
329
330static void trim_aio_cancel(BlockDriverAIOCB *acb)
331{
332 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
333
334 qemu_bh_delete(iocb->bh);
335 iocb->bh = NULL;
336 qemu_aio_release(iocb);
337}
338
d7331bed 339static const AIOCBInfo trim_aiocb_info = {
d353fb72
CH		 340 .aiocb_size = sizeof(TrimAIOCB),
341 .cancel = trim_aio_cancel,
342};
343
344static void ide_trim_bh_cb(void *opaque)
345{
346 TrimAIOCB *iocb = opaque;
347
348 iocb->common.cb(iocb->common.opaque, iocb->ret);
349
350 qemu_bh_delete(iocb->bh);
351 iocb->bh = NULL;
352
353 qemu_aio_release(iocb);
354}
355
356BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
357 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
358 BlockDriverCompletionFunc *cb, void *opaque)
359{
360 TrimAIOCB *iocb;
361 int i, j, ret;
362
d7331bed 363 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
d353fb72
CH		 364 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
365 iocb->ret = 0;
366
367 for (j = 0; j < qiov->niov; j++) {
368 uint64_t *buffer = qiov->iov[j].iov_base;
369
370 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
371 /* 6-byte LBA + 2-byte range per entry */
372 uint64_t entry = le64_to_cpu(buffer[i]);
373 uint64_t sector = entry & 0x0000ffffffffffffULL;
374 uint16_t count = entry >> 48;
375
376 if (count == 0) {
377 break;
378 }
379
380 ret = bdrv_discard(bs, sector, count);
381 if (!iocb->ret) {
382 iocb->ret = ret;
383 }
384 }
385 }
386
387 qemu_bh_schedule(iocb->bh);
388
389 return &iocb->common;
390}
391
5391d806
FB		 392static inline void ide_abort_command(IDEState *s)
393{
394 s->status = READY_STAT | ERR_STAT;
395 s->error = ABRT_ERR;
396}
397
5391d806 398/* prepare data transfer and tell what to do after */
33231e0e
KW		 399void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
400 EndTransferFunc *end_transfer_func)
5391d806
FB		 401{
402 s->end_transfer_func = end_transfer_func;
403 s->data_ptr = buf;
404 s->data_end = buf + size;
40a6238a 405 if (!(s->status & ERR_STAT)) {
7603d156 406 s->status |= DRQ_STAT;
40a6238a
AG		 407 }
408 s->bus->dma->ops->start_transfer(s->bus->dma);
5391d806
FB		 409}
410
33231e0e 411void ide_transfer_stop(IDEState *s)
5391d806
FB		 412{
413 s->end_transfer_func = ide_transfer_stop;
414 s->data_ptr = s->io_buffer;
415 s->data_end = s->io_buffer;
416 s->status &= ~DRQ_STAT;
417}
418
356721ae 419int64_t ide_get_sector(IDEState *s)
5391d806
FB		 420{
421 int64_t sector_num;
422 if (s->select & 0x40) {
423 /* lba */
c2ff060f
FB		 424 if (!s->lba48) {
425 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
426 (s->lcyl << 8) | s->sector;
427 } else {
428 sector_num = ((int64_t)s->hob_hcyl << 40) |
429 ((int64_t) s->hob_lcyl << 32) |
430 ((int64_t) s->hob_sector << 24) |
431 ((int64_t) s->hcyl << 16) |
432 ((int64_t) s->lcyl << 8) | s->sector;
433 }
5391d806
FB		 434 } else {
435 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 436 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 437 }
438 return sector_num;
439}
440
356721ae 441void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 442{
443 unsigned int cyl, r;
444 if (s->select & 0x40) {
c2ff060f
FB		 445 if (!s->lba48) {
446 s->select = (s->select & 0xf0) | (sector_num >> 24);
447 s->hcyl = (sector_num >> 16);
448 s->lcyl = (sector_num >> 8);
449 s->sector = (sector_num);
450 } else {
451 s->sector = sector_num;
452 s->lcyl = sector_num >> 8;
453 s->hcyl = sector_num >> 16;
454 s->hob_sector = sector_num >> 24;
455 s->hob_lcyl = sector_num >> 32;
456 s->hob_hcyl = sector_num >> 40;
457 }
5391d806
FB		 458 } else {
459 cyl = sector_num / (s->heads * s->sectors);
460 r = sector_num % (s->heads * s->sectors);
461 s->hcyl = cyl >> 8;
462 s->lcyl = cyl;
1b8eb456 463 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 464 s->sector = (r % s->sectors) + 1;
465 }
466}
467
e162cfb0
AZ		 468static void ide_rw_error(IDEState *s) {
469 ide_abort_command(s);
9cdd03a7 470 ide_set_irq(s->bus);
e162cfb0
AZ		 471}
472
bef0fd59
SH		 473static void ide_sector_read_cb(void *opaque, int ret)
474{
475 IDEState *s = opaque;
476 int n;
477
478 s->pio_aiocb = NULL;
479 s->status &= ~BUSY_STAT;
480
481 bdrv_acct_done(s->bs, &s->acct);
482 if (ret != 0) {
483 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
484 BM_STATUS_RETRY_READ)) {
485 return;
486 }
487 }
488
489 n = s->nsector;
490 if (n > s->req_nb_sectors) {
491 n = s->req_nb_sectors;
492 }
493
494 /* Allow the guest to read the io_buffer */
495 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
496
497 ide_set_irq(s->bus);
498
499 ide_set_sector(s, ide_get_sector(s) + n);
500 s->nsector -= n;
501}
502
40a6238a 503void ide_sector_read(IDEState *s)
5391d806
FB		 504{
505 int64_t sector_num;
bef0fd59 506 int n;
5391d806
FB		 507
508 s->status = READY_STAT | SEEK_STAT;
a136e5a8 509 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 510 sector_num = ide_get_sector(s);
511 n = s->nsector;
bef0fd59 512
5391d806 513 if (n == 0) {
5391d806 514 ide_transfer_stop(s);
bef0fd59
SH		 515 return;
516 }
517
518 s->status |= BUSY_STAT;
519
520 if (n > s->req_nb_sectors) {
521 n = s->req_nb_sectors;
522 }
523
5391d806 524#if defined(DEBUG_IDE)
bef0fd59 525 printf("sector=%" PRId64 "\n", sector_num);
5391d806 526#endif
a597e79c 527
bef0fd59
SH		 528 s->iov.iov_base = s->io_buffer;
529 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
530 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
531
532 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
533 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
534 ide_sector_read_cb, s);
5391d806
FB		 535}
536
b61744b3 537static void dma_buf_commit(IDEState *s)
7aea4412 538{
1fb8648d 539 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 540}
541
33231e0e 542void ide_set_inactive(IDEState *s)
8337606d 543{
40a6238a
AG		 544 s->bus->dma->aiocb = NULL;
545 s->bus->dma->ops->set_inactive(s->bus->dma);
8337606d
KW		 546}
547
356721ae 548void ide_dma_error(IDEState *s)
e162cfb0
AZ		 549{
550 ide_transfer_stop(s);
551 s->error = ABRT_ERR;
552 s->status = READY_STAT | ERR_STAT;
40a6238a 553 ide_set_inactive(s);
9cdd03a7 554 ide_set_irq(s->bus);
e162cfb0
AZ		 555}
556
ce4b6522 557static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 558{
1ceee0d5 559 bool is_read = (op & BM_STATUS_RETRY_READ) != 0;
3e1caa5f 560 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
428c5705 561
3e1caa5f 562 if (action == BDRV_ACTION_STOP) {
40a6238a 563 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 564 s->bus->error_status = op;
3e1caa5f 565 } else if (action == BDRV_ACTION_REPORT) {
ce4b6522 566 if (op & BM_STATUS_DMA_RETRY) {
b61744b3 567 dma_buf_commit(s);
428c5705 568 ide_dma_error(s);
7aea4412 569 } else {
428c5705 570 ide_rw_error(s);
7aea4412 571 }
428c5705 572 }
3e1caa5f
PB		 573 bdrv_error_action(s->bs, action, is_read, error);
574 return action != BDRV_ACTION_IGNORE;
428c5705
AL		 575}
576
cd369c46 577void ide_dma_cb(void *opaque, int ret)
98087450 578{
40a6238a 579 IDEState *s = opaque;
8ccad811
FB		 580 int n;
581 int64_t sector_num;
038268e2 582 bool stay_active = false;
8ccad811 583
e162cfb0 584 if (ret < 0) {
cd369c46
CH		 585 int op = BM_STATUS_DMA_RETRY;
586
4e1e0051 587 if (s->dma_cmd == IDE_DMA_READ)
cd369c46 588 op |= BM_STATUS_RETRY_READ;
d353fb72
CH		 589 else if (s->dma_cmd == IDE_DMA_TRIM)
590 op |= BM_STATUS_RETRY_TRIM;
591
cd369c46 592 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 593 return;
594 }
e162cfb0
AZ		 595 }
596
8ccad811 597 n = s->io_buffer_size >> 9;
038268e2
KW		 598 if (n > s->nsector) {
599 /* The PRDs were longer than needed for this request. Shorten them so
600 * we don't get a negative remainder. The Active bit must remain set
601 * after the request completes. */
602 n = s->nsector;
603 stay_active = true;
604 }
605
8ccad811
FB		 606 sector_num = ide_get_sector(s);
607 if (n > 0) {
b61744b3 608 dma_buf_commit(s);
8ccad811
FB		 609 sector_num += n;
610 ide_set_sector(s, sector_num);
611 s->nsector -= n;
8ccad811
FB		 612 }
613
614 /* end of transfer ? */
615 if (s->nsector == 0) {
98087450 616 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 617 ide_set_irq(s->bus);
cd369c46 618 goto eot;
98087450 619 }
8ccad811
FB		 620
621 /* launch next transfer */
622 n = s->nsector;
596bb44d 623 s->io_buffer_index = 0;
8ccad811 624 s->io_buffer_size = n * 512;
4e1e0051 625 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 626 /* The PRDs were too short. Reset the Active bit, but don't raise an
627 * interrupt. */
7aea4412 628 goto eot;
69c38b8f 629 }
cd369c46 630
8ccad811 631#ifdef DEBUG_AIO
4e1e0051
CH		 632 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
633 sector_num, n, s->dma_cmd);
8ccad811 634#endif
cd369c46 635
4e1e0051
CH		 636 switch (s->dma_cmd) {
637 case IDE_DMA_READ:
cd369c46
CH		 638 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
639 ide_dma_cb, s);
4e1e0051
CH		 640 break;
641 case IDE_DMA_WRITE:
cd369c46
CH		 642 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
643 ide_dma_cb, s);
4e1e0051 644 break;
d353fb72
CH		 645 case IDE_DMA_TRIM:
646 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
43cf8ae6
DG		 647 ide_issue_trim, ide_dma_cb, s,
648 DMA_DIRECTION_TO_DEVICE);
d353fb72 649 break;
cd369c46 650 }
cd369c46
CH		 651 return;
652
653eot:
a597e79c
CH		 654 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
655 bdrv_acct_done(s->bs, &s->acct);
656 }
657 ide_set_inactive(s);
038268e2
KW		 658 if (stay_active) {
659 s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING);
660 }
98087450
FB		 661}
662
4e1e0051 663static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 664{
8ccad811 665 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 666 s->io_buffer_index = 0;
667 s->io_buffer_size = 0;
4e1e0051 668 s->dma_cmd = dma_cmd;
a597e79c
CH		 669
670 switch (dma_cmd) {
671 case IDE_DMA_READ:
672 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
673 BDRV_ACCT_READ);
674 break;
675 case IDE_DMA_WRITE:
676 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
677 BDRV_ACCT_WRITE);
678 break;
679 default:
680 break;
681 }
682
cd369c46 683 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
98087450
FB		 684}
685
a09db21f
FB		 686static void ide_sector_write_timer_cb(void *opaque)
687{
688 IDEState *s = opaque;
9cdd03a7 689 ide_set_irq(s->bus);
a09db21f
FB		 690}
691
e82dabd8 692static void ide_sector_write_cb(void *opaque, int ret)
5391d806 693{
e82dabd8
SH		 694 IDEState *s = opaque;
695 int n;
a597e79c 696
a597e79c 697 bdrv_acct_done(s->bs, &s->acct);
428c5705 698
e82dabd8
SH		 699 s->pio_aiocb = NULL;
700 s->status &= ~BUSY_STAT;
701
e162cfb0 702 if (ret != 0) {
e82dabd8 703 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
428c5705 704 return;
e82dabd8 705 }
e162cfb0
AZ		 706 }
707
e82dabd8
SH		 708 n = s->nsector;
709 if (n > s->req_nb_sectors) {
710 n = s->req_nb_sectors;
711 }
5391d806
FB		 712 s->nsector -= n;
713 if (s->nsector == 0) {
292eef5a 714 /* no more sectors to write */
5391d806
FB		 715 ide_transfer_stop(s);
716 } else {
e82dabd8
SH		 717 int n1 = s->nsector;
718 if (n1 > s->req_nb_sectors) {
5391d806 719 n1 = s->req_nb_sectors;
e82dabd8
SH		 720 }
721 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
722 ide_sector_write);
5391d806 723 }
e82dabd8 724 ide_set_sector(s, ide_get_sector(s) + n);
3b46e624 725
31c2a146
TS		 726 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
727 /* It seems there is a bug in the Windows 2000 installer HDD
728 IDE driver which fills the disk with empty logs when the
729 IDE write IRQ comes too early. This hack tries to correct
730 that at the expense of slower write performances. Use this
731 option _only_ to install Windows 2000. You must disable it
732 for normal use. */
f7736b91 733 qemu_mod_timer(s->sector_write_timer,
74475455 734 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
f7736b91 735 } else {
9cdd03a7 736 ide_set_irq(s->bus);
31c2a146 737 }
5391d806
FB		 738}
739
e82dabd8
SH		 740void ide_sector_write(IDEState *s)
741{
742 int64_t sector_num;
743 int n;
744
745 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
746 sector_num = ide_get_sector(s);
747#if defined(DEBUG_IDE)
748 printf("sector=%" PRId64 "\n", sector_num);
749#endif
750 n = s->nsector;
751 if (n > s->req_nb_sectors) {
752 n = s->req_nb_sectors;
753 }
754
755 s->iov.iov_base = s->io_buffer;
756 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
757 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
758
759 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
760 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
761 ide_sector_write_cb, s);
762}
763
b0484ae4
CH		 764static void ide_flush_cb(void *opaque, int ret)
765{
766 IDEState *s = opaque;
767
e2bcadad
KW		 768 if (ret < 0) {
769 /* XXX: What sector number to set here? */
770 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
771 return;
772 }
773 }
b0484ae4 774
a597e79c 775 bdrv_acct_done(s->bs, &s->acct);
b0484ae4
CH		 776 s->status = READY_STAT | SEEK_STAT;
777 ide_set_irq(s->bus);
778}
779
40a6238a 780void ide_flush_cache(IDEState *s)
6bcb1a79 781{
b2df7531 782 if (s->bs == NULL) {
6bcb1a79 783 ide_flush_cb(s, 0);
b2df7531
KW		 784 return;
785 }
786
a597e79c 787 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
ad54ae80 788 bdrv_aio_flush(s->bs, ide_flush_cb, s);
6bcb1a79
KW		 789}
790
201a51fc
AZ		 791static void ide_cfata_metadata_inquiry(IDEState *s)
792{
793 uint16_t *p;
794 uint32_t spd;
795
796 p = (uint16_t *) s->io_buffer;
797 memset(p, 0, 0x200);
798 spd = ((s->mdata_size - 1) >> 9) + 1;
799
800 put_le16(p + 0, 0x0001); /* Data format revision */
801 put_le16(p + 1, 0x0000); /* Media property: silicon */
802 put_le16(p + 2, s->media_changed); /* Media status */
803 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
804 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
805 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
806 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
807}
808
809static void ide_cfata_metadata_read(IDEState *s)
810{
811 uint16_t *p;
812
813 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
814 s->status = ERR_STAT;
815 s->error = ABRT_ERR;
816 return;
817 }
818
819 p = (uint16_t *) s->io_buffer;
820 memset(p, 0, 0x200);
821
822 put_le16(p + 0, s->media_changed); /* Media status */
823 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
824 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
825 s->nsector << 9), 0x200 - 2));
826}
827
828static void ide_cfata_metadata_write(IDEState *s)
829{
830 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
831 s->status = ERR_STAT;
832 s->error = ABRT_ERR;
833 return;
834 }
835
836 s->media_changed = 0;
837
838 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
839 s->io_buffer + 2,
840 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
841 s->nsector << 9), 0x200 - 2));
842}
843
bd491d6a 844/* called when the inserted state of the media has changed */
7d4b4ba5 845static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 846{
847 IDEState *s = opaque;
96b8f136 848 uint64_t nb_sectors;
bd491d6a 849
25ad22bc 850 s->tray_open = !load;
bd491d6a
TS		 851 bdrv_get_geometry(s->bs, &nb_sectors);
852 s->nb_sectors = nb_sectors;
9118e7f0 853
4b9b7092
AS		 854 /*
855 * First indicate to the guest that a CD has been removed. That's
856 * done on the next command the guest sends us.
857 *
67cc61e4 858 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 859 * detect a new CD in the drive. See ide_atapi_cmd() for details.
860 */
93c8cfd9 861 s->cdrom_changed = 1;
996faf1a 862 s->events.new_media = true;
2df0a3a3
PB		 863 s->events.eject_request = false;
864 ide_set_irq(s->bus);
865}
866
867static void ide_cd_eject_request_cb(void *opaque, bool force)
868{
869 IDEState *s = opaque;
870
871 s->events.eject_request = true;
872 if (force) {
873 s->tray_locked = false;
874 }
9cdd03a7 875 ide_set_irq(s->bus);
bd491d6a
TS		 876}
877
c2ff060f
FB		 878static void ide_cmd_lba48_transform(IDEState *s, int lba48)
879{
880 s->lba48 = lba48;
881
882 /* handle the 'magic' 0 nsector count conversion here. to avoid
883 * fiddling with the rest of the read logic, we just store the
884 * full sector count in ->nsector and ignore ->hob_nsector from now
885 */
886 if (!s->lba48) {
887 if (!s->nsector)
888 s->nsector = 256;
889 } else {
890 if (!s->nsector && !s->hob_nsector)
891 s->nsector = 65536;
892 else {
893 int lo = s->nsector;
894 int hi = s->hob_nsector;
895
896 s->nsector = (hi << 8) | lo;
897 }
898 }
899}
900
bcbdc4d3 901static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 902{
903 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 904 bus->ifs[0].select &= ~(1 << 7);
905 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 906}
907
356721ae 908void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 909{
bcbdc4d3 910 IDEBus *bus = opaque;
5391d806
FB		 911
912#ifdef DEBUG_IDE
913 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
914#endif
c2ff060f 915
5391d806 916 addr &= 7;
fcdd25ab
AL		 917
918 /* ignore writes to command block while busy with previous command */
bcbdc4d3 919 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 920 return;
921
5391d806
FB		 922 switch(addr) {
923 case 0:
924 break;
925 case 1:
bcbdc4d3 926 ide_clear_hob(bus);
c45c3d00 927 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 928 bus->ifs[0].hob_feature = bus->ifs[0].feature;
929 bus->ifs[1].hob_feature = bus->ifs[1].feature;
930 bus->ifs[0].feature = val;
931 bus->ifs[1].feature = val;
5391d806
FB		 932 break;
933 case 2:
bcbdc4d3
GH		 934 ide_clear_hob(bus);
935 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
936 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
937 bus->ifs[0].nsector = val;
938 bus->ifs[1].nsector = val;
5391d806
FB		 939 break;
940 case 3:
bcbdc4d3
GH		 941 ide_clear_hob(bus);
942 bus->ifs[0].hob_sector = bus->ifs[0].sector;
943 bus->ifs[1].hob_sector = bus->ifs[1].sector;
944 bus->ifs[0].sector = val;
945 bus->ifs[1].sector = val;
5391d806
FB		 946 break;
947 case 4:
bcbdc4d3
GH		 948 ide_clear_hob(bus);
949 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
950 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
951 bus->ifs[0].lcyl = val;
952 bus->ifs[1].lcyl = val;
5391d806
FB		 953 break;
954 case 5:
bcbdc4d3
GH		 955 ide_clear_hob(bus);
956 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
957 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
958 bus->ifs[0].hcyl = val;
959 bus->ifs[1].hcyl = val;
5391d806
FB		 960 break;
961 case 6:
c2ff060f 962 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 963 bus->ifs[0].select = (val & ~0x10) | 0xa0;
964 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 965 /* select drive */
bcbdc4d3 966 bus->unit = (val >> 4) & 1;
5391d806
FB		 967 break;
968 default:
969 case 7:
970 /* command */
7cff87ff
AG		 971 ide_exec_cmd(bus, val);
972 break;
973 }
974}
975
844505b1
MA		 976#define HD_OK (1u << IDE_HD)
977#define CD_OK (1u << IDE_CD)
978#define CFA_OK (1u << IDE_CFATA)
979#define HD_CFA_OK (HD_OK | CFA_OK)
980#define ALL_OK (HD_OK | CD_OK | CFA_OK)
981
982/* See ACS-2 T13/2015-D Table B.2 Command codes */
983static const uint8_t ide_cmd_table[0x100] = {
984 /* NOP not implemented, mandatory for CD */
985 [CFA_REQ_EXT_ERROR_CODE] = CFA_OK,
986 [WIN_DSM] = ALL_OK,
987 [WIN_DEVICE_RESET] = CD_OK,
3cfc2269 988 [WIN_RECAL] = HD_CFA_OK,
844505b1
MA		 989 [WIN_READ] = ALL_OK,
990 [WIN_READ_ONCE] = ALL_OK,
3cfc2269
MA		 991 [WIN_READ_EXT] = HD_CFA_OK,
992 [WIN_READDMA_EXT] = HD_CFA_OK,
993 [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK,
994 [WIN_MULTREAD_EXT] = HD_CFA_OK,
995 [WIN_WRITE] = HD_CFA_OK,
996 [WIN_WRITE_ONCE] = HD_CFA_OK,
997 [WIN_WRITE_EXT] = HD_CFA_OK,
998 [WIN_WRITEDMA_EXT] = HD_CFA_OK,
999 [CFA_WRITE_SECT_WO_ERASE] = CFA_OK,
1000 [WIN_MULTWRITE_EXT] = HD_CFA_OK,
1001 [WIN_WRITE_VERIFY] = HD_CFA_OK,
1002 [WIN_VERIFY] = HD_CFA_OK,
1003 [WIN_VERIFY_ONCE] = HD_CFA_OK,
1004 [WIN_VERIFY_EXT] = HD_CFA_OK,
844505b1
MA		 1005 [WIN_SEEK] = HD_CFA_OK,
1006 [CFA_TRANSLATE_SECTOR] = CFA_OK,
1007 [WIN_DIAGNOSE] = ALL_OK,
3cfc2269 1008 [WIN_SPECIFY] = HD_CFA_OK,
844505b1
MA		 1009 [WIN_STANDBYNOW2] = ALL_OK,
1010 [WIN_IDLEIMMEDIATE2] = ALL_OK,
1011 [WIN_STANDBY2] = ALL_OK,
1012 [WIN_SETIDLE2] = ALL_OK,
1013 [WIN_CHECKPOWERMODE2] = ALL_OK,
1014 [WIN_SLEEPNOW2] = ALL_OK,
1015 [WIN_PACKETCMD] = CD_OK,
1016 [WIN_PIDENTIFY] = CD_OK,
1017 [WIN_SMART] = HD_CFA_OK,
1018 [CFA_ACCESS_METADATA_STORAGE] = CFA_OK,
1019 [CFA_ERASE_SECTORS] = CFA_OK,
3cfc2269
MA		 1020 [WIN_MULTREAD] = HD_CFA_OK,
1021 [WIN_MULTWRITE] = HD_CFA_OK,
1022 [WIN_SETMULT] = HD_CFA_OK,
1023 [WIN_READDMA] = HD_CFA_OK,
1024 [WIN_READDMA_ONCE] = HD_CFA_OK,
1025 [WIN_WRITEDMA] = HD_CFA_OK,
1026 [WIN_WRITEDMA_ONCE] = HD_CFA_OK,
1027 [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK,
844505b1
MA		 1028 [WIN_STANDBYNOW1] = ALL_OK,
1029 [WIN_IDLEIMMEDIATE] = ALL_OK,
1030 [WIN_STANDBY] = ALL_OK,
1031 [WIN_SETIDLE1] = ALL_OK,
1032 [WIN_CHECKPOWERMODE1] = ALL_OK,
1033 [WIN_SLEEPNOW1] = ALL_OK,
1034 [WIN_FLUSH_CACHE] = ALL_OK,
3cfc2269 1035 [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK,
844505b1
MA		 1036 [WIN_IDENTIFY] = ALL_OK,
1037 [WIN_SETFEATURES] = ALL_OK,
1038 [IBM_SENSE_CONDITION] = CFA_OK,
d5b406d9 1039 [CFA_WEAR_LEVEL] = HD_CFA_OK,
844505b1
MA		 1040 [WIN_READ_NATIVE_MAX] = ALL_OK,
1041};
1042
1043static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1044{
1045 return cmd < ARRAY_SIZE(ide_cmd_table)
1046 && (ide_cmd_table[cmd] & (1u << s->drive_kind));
1047}
7cff87ff
AG		 1048
1049void ide_exec_cmd(IDEBus *bus, uint32_t val)
1050{
7cdd481c 1051 uint16_t *identify_data;
7cff87ff
AG		 1052 IDEState *s;
1053 int n;
1054 int lba48 = 0;
1055
5391d806 1056#if defined(DEBUG_IDE)
6ef2ba5e 1057 printf("ide: CMD=%02x\n", val);
5391d806 1058#endif
6ef2ba5e 1059 s = idebus_active_if(bus);
66a0a2cb 1060 /* ignore commands to non existent slave */
6ef2ba5e
AG		 1061 if (s != bus->ifs && !s->bs)
1062 return;
c2ff060f 1063
6ef2ba5e
AG		 1064 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1065 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1066 return;
fcdd25ab 1067
844505b1
MA		 1068 if (!ide_cmd_permitted(s, val)) {
1069 goto abort_cmd;
1070 }
1071
6ef2ba5e 1072 switch(val) {
d353fb72
CH		 1073 case WIN_DSM:
1074 switch (s->feature) {
1075 case DSM_TRIM:
1076 if (!s->bs) {
1077 goto abort_cmd;
1078 }
1079 ide_sector_start_dma(s, IDE_DMA_TRIM);
1080 break;
1081 default:
1082 goto abort_cmd;
1083 }
1084 break;
6ef2ba5e
AG		 1085 case WIN_IDENTIFY:
1086 if (s->bs && s->drive_kind != IDE_CD) {
1087 if (s->drive_kind != IDE_CFATA)
1088 ide_identify(s);
1089 else
1090 ide_cfata_identify(s);
769bec72 1091 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1092 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1093 } else {
1094 if (s->drive_kind == IDE_CD) {
1095 ide_set_signature(s);
5391d806 1096 }
6ef2ba5e
AG		 1097 ide_abort_command(s);
1098 }
1099 ide_set_irq(s->bus);
1100 break;
1101 case WIN_SPECIFY:
1102 case WIN_RECAL:
1103 s->error = 0;
1104 s->status = READY_STAT | SEEK_STAT;
1105 ide_set_irq(s->bus);
1106 break;
1107 case WIN_SETMULT:
1108 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1109 /* Disable Read and Write Multiple */
1110 s->mult_sectors = 0;
41a2b959 1111 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1112 } else if ((s->nsector & 0xff) != 0 &&
1113 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1114 (s->nsector & (s->nsector - 1)) != 0)) {
1115 ide_abort_command(s);
1116 } else {
1117 s->mult_sectors = s->nsector & 0xff;
1118 s->status = READY_STAT | SEEK_STAT;
1119 }
1120 ide_set_irq(s->bus);
1121 break;
1122 case WIN_VERIFY_EXT:
1123 lba48 = 1;
1124 case WIN_VERIFY:
1125 case WIN_VERIFY_ONCE:
1126 /* do sector number check ? */
1127 ide_cmd_lba48_transform(s, lba48);
1128 s->status = READY_STAT | SEEK_STAT;
1129 ide_set_irq(s->bus);
1130 break;
814839c0 1131 case WIN_READ_EXT:
6ef2ba5e
AG		 1132 lba48 = 1;
1133 case WIN_READ:
1134 case WIN_READ_ONCE:
3f76a7c3
MA		 1135 if (s->drive_kind == IDE_CD) {
1136 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
6ef2ba5e 1137 goto abort_cmd;
3f76a7c3 1138 }
d53cdb30
PB		 1139 if (!s->bs) {
1140 goto abort_cmd;
1141 }
6ef2ba5e
AG		 1142 ide_cmd_lba48_transform(s, lba48);
1143 s->req_nb_sectors = 1;
1144 ide_sector_read(s);
1145 break;
814839c0 1146 case WIN_WRITE_EXT:
6ef2ba5e
AG		 1147 lba48 = 1;
1148 case WIN_WRITE:
1149 case WIN_WRITE_ONCE:
1150 case CFA_WRITE_SECT_WO_ERASE:
1151 case WIN_WRITE_VERIFY:
d53cdb30
PB		 1152 if (!s->bs) {
1153 goto abort_cmd;
1154 }
6ef2ba5e
AG		 1155 ide_cmd_lba48_transform(s, lba48);
1156 s->error = 0;
1157 s->status = SEEK_STAT | READY_STAT;
1158 s->req_nb_sectors = 1;
1159 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1160 s->media_changed = 1;
1161 break;
814839c0 1162 case WIN_MULTREAD_EXT:
6ef2ba5e
AG		 1163 lba48 = 1;
1164 case WIN_MULTREAD:
d53cdb30
PB		 1165 if (!s->bs) {
1166 goto abort_cmd;
1167 }
1168 if (!s->mult_sectors) {
6ef2ba5e 1169 goto abort_cmd;
d53cdb30 1170 }
6ef2ba5e
AG		 1171 ide_cmd_lba48_transform(s, lba48);
1172 s->req_nb_sectors = s->mult_sectors;
1173 ide_sector_read(s);
1174 break;
1175 case WIN_MULTWRITE_EXT:
1176 lba48 = 1;
1177 case WIN_MULTWRITE:
1178 case CFA_WRITE_MULTI_WO_ERASE:
d53cdb30
PB		 1179 if (!s->bs) {
1180 goto abort_cmd;
1181 }
1182 if (!s->mult_sectors) {
6ef2ba5e 1183 goto abort_cmd;
d53cdb30 1184 }
6ef2ba5e
AG		 1185 ide_cmd_lba48_transform(s, lba48);
1186 s->error = 0;
1187 s->status = SEEK_STAT | READY_STAT;
1188 s->req_nb_sectors = s->mult_sectors;
1189 n = s->nsector;
1190 if (n > s->req_nb_sectors)
1191 n = s->req_nb_sectors;
1192 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1193 s->media_changed = 1;
1194 break;
814839c0 1195 case WIN_READDMA_EXT:
6ef2ba5e
AG		 1196 lba48 = 1;
1197 case WIN_READDMA:
1198 case WIN_READDMA_ONCE:
d53cdb30 1199 if (!s->bs) {
6ef2ba5e 1200 goto abort_cmd;
d53cdb30 1201 }
6ef2ba5e 1202 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1203 ide_sector_start_dma(s, IDE_DMA_READ);
6ef2ba5e 1204 break;
814839c0 1205 case WIN_WRITEDMA_EXT:
6ef2ba5e
AG		 1206 lba48 = 1;
1207 case WIN_WRITEDMA:
1208 case WIN_WRITEDMA_ONCE:
d53cdb30 1209 if (!s->bs) {
6ef2ba5e 1210 goto abort_cmd;
d53cdb30 1211 }
6ef2ba5e 1212 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1213 ide_sector_start_dma(s, IDE_DMA_WRITE);
6ef2ba5e
AG		 1214 s->media_changed = 1;
1215 break;
1216 case WIN_READ_NATIVE_MAX_EXT:
1217 lba48 = 1;
1218 case WIN_READ_NATIVE_MAX:
1219 ide_cmd_lba48_transform(s, lba48);
1220 ide_set_sector(s, s->nb_sectors - 1);
1221 s->status = READY_STAT | SEEK_STAT;
1222 ide_set_irq(s->bus);
1223 break;
1224 case WIN_CHECKPOWERMODE1:
1225 case WIN_CHECKPOWERMODE2:
b93af93d 1226 s->error = 0;
6ef2ba5e
AG		 1227 s->nsector = 0xff; /* device active or idle */
1228 s->status = READY_STAT | SEEK_STAT;
1229 ide_set_irq(s->bus);
1230 break;
1231 case WIN_SETFEATURES:
1232 if (!s->bs)
1233 goto abort_cmd;
1234 /* XXX: valid for CDROM ? */
1235 switch(s->feature) {
6ef2ba5e 1236 case 0x02: /* write cache enable */
7cdd481c
PB		 1237 bdrv_set_enable_write_cache(s->bs, true);
1238 identify_data = (uint16_t *)s->identify_data;
1239 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1240 s->status = READY_STAT | SEEK_STAT;
1241 ide_set_irq(s->bus);
1242 break;
6ef2ba5e 1243 case 0x82: /* write cache disable */
7cdd481c
PB		 1244 bdrv_set_enable_write_cache(s->bs, false);
1245 identify_data = (uint16_t *)s->identify_data;
1246 put_le16(identify_data + 85, (1 << 14) | 1);
1247 ide_flush_cache(s);
1248 break;
1249 case 0xcc: /* reverting to power-on defaults enable */
1250 case 0x66: /* reverting to power-on defaults disable */
6ef2ba5e
AG		 1251 case 0xaa: /* read look-ahead enable */
1252 case 0x55: /* read look-ahead disable */
1253 case 0x05: /* set advanced power management mode */
1254 case 0x85: /* disable advanced power management mode */
1255 case 0x69: /* NOP */
1256 case 0x67: /* NOP */
1257 case 0x96: /* NOP */
1258 case 0x9a: /* NOP */
1259 case 0x42: /* enable Automatic Acoustic Mode */
1260 case 0xc2: /* disable Automatic Acoustic Mode */
41a2b959 1261 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1262 ide_set_irq(s->bus);
a136e5a8 1263 break;
6ef2ba5e 1264 case 0x03: { /* set transfer mode */
94458802 1265 uint8_t val = s->nsector & 0x07;
7cdd481c 1266 identify_data = (uint16_t *)s->identify_data;
94458802
FB		 1267
1268 switch (s->nsector >> 3) {
6ef2ba5e
AG		 1269 case 0x00: /* pio default */
1270 case 0x01: /* pio mode */
96c35ceb
JQ		 1271 put_le16(identify_data + 62,0x07);
1272 put_le16(identify_data + 63,0x07);
1273 put_le16(identify_data + 88,0x3f);
d1b5c20d 1274 break;
6ef2ba5e 1275 case 0x02: /* sigle word dma mode*/
96c35ceb
JQ		 1276 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1277 put_le16(identify_data + 63,0x07);
1278 put_le16(identify_data + 88,0x3f);
94458802 1279 break;
6ef2ba5e 1280 case 0x04: /* mdma mode */
96c35ceb
JQ		 1281 put_le16(identify_data + 62,0x07);
1282 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1283 put_le16(identify_data + 88,0x3f);
94458802 1284 break;
6ef2ba5e 1285 case 0x08: /* udma mode */
96c35ceb
JQ		 1286 put_le16(identify_data + 62,0x07);
1287 put_le16(identify_data + 63,0x07);
1288 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
94458802 1289 break;
6ef2ba5e 1290 default:
94458802
FB		 1291 goto abort_cmd;
1292 }
4fbfcd6d 1293 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1294 ide_set_irq(s->bus);
4fbfcd6d 1295 break;
6ef2ba5e
AG		 1296 }
1297 default:
1298 goto abort_cmd;
1299 }
1300 break;
1301 case WIN_FLUSH_CACHE:
1302 case WIN_FLUSH_CACHE_EXT:
1303 ide_flush_cache(s);
1304 break;
1305 case WIN_STANDBY:
1306 case WIN_STANDBY2:
1307 case WIN_STANDBYNOW1:
1308 case WIN_STANDBYNOW2:
1309 case WIN_IDLEIMMEDIATE:
1d4316d3 1310 case WIN_IDLEIMMEDIATE2:
6ef2ba5e
AG		 1311 case WIN_SETIDLE1:
1312 case WIN_SETIDLE2:
1313 case WIN_SLEEPNOW1:
1314 case WIN_SLEEPNOW2:
1315 s->status = READY_STAT;
1316 ide_set_irq(s->bus);
1317 break;
1318 case WIN_SEEK:
6ef2ba5e
AG		 1319 /* XXX: Check that seek is within bounds */
1320 s->status = READY_STAT | SEEK_STAT;
1321 ide_set_irq(s->bus);
1322 break;
1323 /* ATAPI commands */
1324 case WIN_PIDENTIFY:
844505b1
MA		 1325 ide_atapi_identify(s);
1326 s->status = READY_STAT | SEEK_STAT;
1327 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
6ef2ba5e
AG		 1328 ide_set_irq(s->bus);
1329 break;
1330 case WIN_DIAGNOSE:
1331 ide_set_signature(s);
1332 if (s->drive_kind == IDE_CD)
1333 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1334 * devices to return a clear status register
1335 * with READY_STAT *not* set. */
1336 else
41a2b959 1337 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1338 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1339 * present.
1340 */
1341 ide_set_irq(s->bus);
1342 break;
1d4316d3 1343 case WIN_DEVICE_RESET:
6ef2ba5e
AG		 1344 ide_set_signature(s);
1345 s->status = 0x00; /* NOTE: READY is _not_ set */
1346 s->error = 0x01;
1347 break;
1348 case WIN_PACKETCMD:
6ef2ba5e
AG		 1349 /* overlapping commands not supported */
1350 if (s->feature & 0x02)
1351 goto abort_cmd;
1352 s->status = READY_STAT | SEEK_STAT;
1353 s->atapi_dma = s->feature & 1;
1354 s->nsector = 1;
1355 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1356 ide_atapi_cmd);
1357 break;
1358 /* CF-ATA commands */
1359 case CFA_REQ_EXT_ERROR_CODE:
6ef2ba5e
AG		 1360 s->error = 0x09; /* miscellaneous error */
1361 s->status = READY_STAT | SEEK_STAT;
1362 ide_set_irq(s->bus);
1363 break;
1364 case CFA_ERASE_SECTORS:
1365 case CFA_WEAR_LEVEL:
d5b406d9
AG		 1366#if 0
1367 /* This one has the same ID as CFA_WEAR_LEVEL and is required for
1368 Windows 8 to work with AHCI */
1369 case WIN_SECURITY_FREEZE_LOCK:
1370#endif
6ef2ba5e
AG		 1371 if (val == CFA_WEAR_LEVEL)
1372 s->nsector = 0;
1373 if (val == CFA_ERASE_SECTORS)
1374 s->media_changed = 1;
1375 s->error = 0x00;
1376 s->status = READY_STAT | SEEK_STAT;
1377 ide_set_irq(s->bus);
1378 break;
1379 case CFA_TRANSLATE_SECTOR:
6ef2ba5e
AG		 1380 s->error = 0x00;
1381 s->status = READY_STAT | SEEK_STAT;
1382 memset(s->io_buffer, 0, 0x200);
1383 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1384 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1385 s->io_buffer[0x02] = s->select; /* Head */
1386 s->io_buffer[0x03] = s->sector; /* Sector */
1387 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1388 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1389 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1390 s->io_buffer[0x13] = 0x00; /* Erase flag */
1391 s->io_buffer[0x18] = 0x00; /* Hot count */
1392 s->io_buffer[0x19] = 0x00; /* Hot count */
1393 s->io_buffer[0x1a] = 0x01; /* Hot count */
1394 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1395 ide_set_irq(s->bus);
1396 break;
1397 case CFA_ACCESS_METADATA_STORAGE:
6ef2ba5e
AG		 1398 switch (s->feature) {
1399 case 0x02: /* Inquiry Metadata Storage */
1400 ide_cfata_metadata_inquiry(s);
201a51fc 1401 break;
6ef2ba5e
AG		 1402 case 0x03: /* Read Metadata Storage */
1403 ide_cfata_metadata_read(s);
201a51fc 1404 break;
6ef2ba5e
AG		 1405 case 0x04: /* Write Metadata Storage */
1406 ide_cfata_metadata_write(s);
201a51fc 1407 break;
6ef2ba5e
AG		 1408 default:
1409 goto abort_cmd;
1410 }
1411 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1412 s->status = 0x00; /* NOTE: READY is _not_ set */
1413 ide_set_irq(s->bus);
1414 break;
1415 case IBM_SENSE_CONDITION:
6ef2ba5e
AG		 1416 switch (s->feature) {
1417 case 0x01: /* sense temperature in device */
1418 s->nsector = 0x50; /* +20 C */
201a51fc 1419 break;
6ef2ba5e
AG		 1420 default:
1421 goto abort_cmd;
1422 }
1423 s->status = READY_STAT | SEEK_STAT;
1424 ide_set_irq(s->bus);
1425 break;
e8b54394 1426
814839c0 1427 case WIN_SMART:
6ef2ba5e 1428 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
e8b54394 1429 goto abort_cmd;
6ef2ba5e 1430 if (!s->smart_enabled && s->feature != SMART_ENABLE)
e8b54394 1431 goto abort_cmd;
6ef2ba5e
AG		 1432 switch (s->feature) {
1433 case SMART_DISABLE:
e8b54394
BW		 1434 s->smart_enabled = 0;
1435 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1436 ide_set_irq(s->bus);
e8b54394 1437 break;
6ef2ba5e 1438 case SMART_ENABLE:
e8b54394
BW		 1439 s->smart_enabled = 1;
1440 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1441 ide_set_irq(s->bus);
e8b54394 1442 break;
6ef2ba5e 1443 case SMART_ATTR_AUTOSAVE:
e8b54394
BW		 1444 switch (s->sector) {
1445 case 0x00:
6ef2ba5e
AG		 1446 s->smart_autosave = 0;
1447 break;
e8b54394 1448 case 0xf1:
6ef2ba5e
AG		 1449 s->smart_autosave = 1;
1450 break;
e8b54394 1451 default:
6ef2ba5e 1452 goto abort_cmd;
e8b54394
BW		 1453 }
1454 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1455 ide_set_irq(s->bus);
e8b54394 1456 break;
6ef2ba5e 1457 case SMART_STATUS:
e8b54394 1458 if (!s->smart_errors) {
6ef2ba5e
AG		 1459 s->hcyl = 0xc2;
1460 s->lcyl = 0x4f;
e8b54394 1461 } else {
6ef2ba5e
AG		 1462 s->hcyl = 0x2c;
1463 s->lcyl = 0xf4;
e8b54394
BW		 1464 }
1465 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1466 ide_set_irq(s->bus);
e8b54394 1467 break;
6ef2ba5e 1468 case SMART_READ_THRESH:
e8b54394
BW		 1469 memset(s->io_buffer, 0, 0x200);
1470 s->io_buffer[0] = 0x01; /* smart struct version */
1e53537f 1471 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
6ef2ba5e 1472 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
b93af93d 1473 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
e8b54394
BW		 1474 }
1475 for (n=0; n<511; n++) /* checksum */
6ef2ba5e 1476 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1477 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1478 s->status = READY_STAT | SEEK_STAT;
1479 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1480 ide_set_irq(s->bus);
e8b54394 1481 break;
6ef2ba5e 1482 case SMART_READ_DATA:
e8b54394
BW		 1483 memset(s->io_buffer, 0, 0x200);
1484 s->io_buffer[0] = 0x01; /* smart struct version */
1e53537f 1485 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
b93af93d
BW		 1486 int i;
1487 for(i = 0; i < 11; i++) {
1488 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1489 }
e8b54394
BW		 1490 }
1491 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1492 if (s->smart_selftest_count == 0) {
6ef2ba5e 1493 s->io_buffer[363] = 0;
e8b54394 1494 } else {
6ef2ba5e 1495 s->io_buffer[363] =
e8b54394 1496 s->smart_selftest_data[3 +
6ef2ba5e
AG		 1497 (s->smart_selftest_count - 1) *
1498 24];
e8b54394
BW		 1499 }
1500 s->io_buffer[364] = 0x20;
1501 s->io_buffer[365] = 0x01;
1502 /* offline data collection capacity: execute + self-test*/
1503 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1504 s->io_buffer[368] = 0x03; /* smart capability (1) */
1505 s->io_buffer[369] = 0x00; /* smart capability (2) */
1506 s->io_buffer[370] = 0x01; /* error logging supported */
1507 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1508 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1509 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1510
1511 for (n=0; n<511; n++)
6ef2ba5e 1512 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1513 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1514 s->status = READY_STAT | SEEK_STAT;
1515 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1516 ide_set_irq(s->bus);
e8b54394 1517 break;
6ef2ba5e 1518 case SMART_READ_LOG:
e8b54394
BW		 1519 switch (s->sector) {
1520 case 0x01: /* summary smart error log */
6ef2ba5e
AG		 1521 memset(s->io_buffer, 0, 0x200);
1522 s->io_buffer[0] = 0x01;
1523 s->io_buffer[1] = 0x00; /* no error entries */
1524 s->io_buffer[452] = s->smart_errors & 0xff;
1525 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
e8b54394 1526
6ef2ba5e 1527 for (n=0; n<511; n++)
e8b54394 1528 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1529 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1530 break;
e8b54394 1531 case 0x06: /* smart self test log */
6ef2ba5e
AG		 1532 memset(s->io_buffer, 0, 0x200);
1533 s->io_buffer[0] = 0x01;
1534 if (s->smart_selftest_count == 0) {
e8b54394 1535 s->io_buffer[508] = 0;
6ef2ba5e 1536 } else {
e8b54394
BW		 1537 s->io_buffer[508] = s->smart_selftest_count;
1538 for (n=2; n<506; n++)
6ef2ba5e
AG		 1539 s->io_buffer[n] = s->smart_selftest_data[n];
1540 }
1541 for (n=0; n<511; n++)
e8b54394 1542 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1543 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1544 break;
e8b54394 1545 default:
6ef2ba5e 1546 goto abort_cmd;
e8b54394
BW		 1547 }
1548 s->status = READY_STAT | SEEK_STAT;
1549 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1550 ide_set_irq(s->bus);
e8b54394 1551 break;
6ef2ba5e 1552 case SMART_EXECUTE_OFFLINE:
e8b54394
BW		 1553 switch (s->sector) {
1554 case 0: /* off-line routine */
1555 case 1: /* short self test */
1556 case 2: /* extended self test */
6ef2ba5e
AG		 1557 s->smart_selftest_count++;
1558 if(s->smart_selftest_count > 21)
e8b54394 1559 s->smart_selftest_count = 0;
6ef2ba5e
AG		 1560 n = 2 + (s->smart_selftest_count - 1) * 24;
1561 s->smart_selftest_data[n] = s->sector;
1562 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1563 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1564 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1565 s->status = READY_STAT | SEEK_STAT;
1566 ide_set_irq(s->bus);
1567 break;
e8b54394 1568 default:
6ef2ba5e 1569 goto abort_cmd;
e8b54394
BW		 1570 }
1571 break;
6ef2ba5e 1572 default:
e8b54394 1573 goto abort_cmd;
6ef2ba5e
AG		 1574 }
1575 break;
1576 default:
844505b1 1577 /* should not be reachable */
6ef2ba5e
AG		 1578 abort_cmd:
1579 ide_abort_command(s);
1580 ide_set_irq(s->bus);
1581 break;
1582 }
5391d806
FB		 1583}
1584
356721ae 1585uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1586{
bcbdc4d3
GH		 1587 IDEBus *bus = opaque;
1588 IDEState *s = idebus_active_if(bus);
5391d806 1589 uint32_t addr;
c2ff060f 1590 int ret, hob;
5391d806
FB		 1591
1592 addr = addr1 & 7;
c2ff060f
FB		 1593 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1594 //hob = s->select & (1 << 7);
1595 hob = 0;
5391d806
FB		 1596 switch(addr) {
1597 case 0:
1598 ret = 0xff;
1599 break;
1600 case 1:
bcbdc4d3
GH		 1601 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1602 (s != bus->ifs && !s->bs))
c45c3d00 1603 ret = 0;
c2ff060f 1604 else if (!hob)
c45c3d00 1605 ret = s->error;
c2ff060f
FB		 1606 else
1607 ret = s->hob_feature;
5391d806
FB		 1608 break;
1609 case 2:
bcbdc4d3 1610 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1611 ret = 0;
c2ff060f 1612 else if (!hob)
c45c3d00 1613 ret = s->nsector & 0xff;
c2ff060f
FB		 1614 else
1615 ret = s->hob_nsector;
5391d806
FB		 1616 break;
1617 case 3:
bcbdc4d3 1618 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1619 ret = 0;
c2ff060f 1620 else if (!hob)
c45c3d00 1621 ret = s->sector;
c2ff060f
FB		 1622 else
1623 ret = s->hob_sector;
5391d806
FB		 1624 break;
1625 case 4:
bcbdc4d3 1626 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1627 ret = 0;
c2ff060f 1628 else if (!hob)
c45c3d00 1629 ret = s->lcyl;
c2ff060f
FB		 1630 else
1631 ret = s->hob_lcyl;
5391d806
FB		 1632 break;
1633 case 5:
bcbdc4d3 1634 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1635 ret = 0;
c2ff060f 1636 else if (!hob)
c45c3d00 1637 ret = s->hcyl;
c2ff060f
FB		 1638 else
1639 ret = s->hob_hcyl;
5391d806
FB		 1640 break;
1641 case 6:
bcbdc4d3 1642 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00
FB		 1643 ret = 0;
1644 else
7ae98627 1645 ret = s->select;
5391d806
FB		 1646 break;
1647 default:
1648 case 7:
bcbdc4d3
GH		 1649 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1650 (s != bus->ifs && !s->bs))
c45c3d00
FB		 1651 ret = 0;
1652 else
1653 ret = s->status;
9cdd03a7 1654 qemu_irq_lower(bus->irq);
5391d806
FB		 1655 break;
1656 }
1657#ifdef DEBUG_IDE
1658 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1659#endif
1660 return ret;
1661}
1662
356721ae 1663uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1664{
bcbdc4d3
GH		 1665 IDEBus *bus = opaque;
1666 IDEState *s = idebus_active_if(bus);
5391d806 1667 int ret;
7ae98627 1668
bcbdc4d3
GH		 1669 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1670 (s != bus->ifs && !s->bs))
7ae98627
FB		 1671 ret = 0;
1672 else
1673 ret = s->status;
5391d806
FB		 1674#ifdef DEBUG_IDE
1675 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1676#endif
1677 return ret;
1678}
1679
356721ae 1680void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1681{
bcbdc4d3 1682 IDEBus *bus = opaque;
5391d806
FB		 1683 IDEState *s;
1684 int i;
1685
1686#ifdef DEBUG_IDE
1687 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1688#endif
1689 /* common for both drives */
9cdd03a7 1690 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1691 (val & IDE_CMD_RESET)) {
1692 /* reset low to high */
1693 for(i = 0;i < 2; i++) {
bcbdc4d3 1694 s = &bus->ifs[i];
5391d806
FB		 1695 s->status = BUSY_STAT | SEEK_STAT;
1696 s->error = 0x01;
1697 }
9cdd03a7 1698 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1699 !(val & IDE_CMD_RESET)) {
1700 /* high to low */
1701 for(i = 0;i < 2; i++) {
bcbdc4d3 1702 s = &bus->ifs[i];
cd8722bb 1703 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1704 s->status = 0x00; /* NOTE: READY is _not_ set */
1705 else
56bf1d37 1706 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1707 ide_set_signature(s);
1708 }
1709 }
1710
9cdd03a7 1711 bus->cmd = val;
5391d806
FB		 1712}
1713
40c4ed3f
KW		 1714/*
1715 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1716 * transferred from the device to the guest), false if it's a PIO in
1717 */
1718static bool ide_is_pio_out(IDEState *s)
1719{
1720 if (s->end_transfer_func == ide_sector_write ||
1721 s->end_transfer_func == ide_atapi_cmd) {
1722 return false;
1723 } else if (s->end_transfer_func == ide_sector_read ||
1724 s->end_transfer_func == ide_transfer_stop ||
1725 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1726 s->end_transfer_func == ide_dummy_transfer_stop) {
1727 return true;
1728 }
1729
1730 abort();
1731}
1732
356721ae 1733void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 1734{
bcbdc4d3
GH		 1735 IDEBus *bus = opaque;
1736 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1737 uint8_t *p;
1738
40c4ed3f
KW		 1739 /* PIO data access allowed only when DRQ bit is set. The result of a write
1740 * during PIO out is indeterminate, just ignore it. */
1741 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1742 return;
40c4ed3f 1743 }
fcdd25ab 1744
5391d806 1745 p = s->data_ptr;
0c4ad8dc 1746 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 1747 p += 2;
1748 s->data_ptr = p;
1749 if (p >= s->data_end)
1750 s->end_transfer_func(s);
1751}
1752
356721ae 1753uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 1754{
bcbdc4d3
GH		 1755 IDEBus *bus = opaque;
1756 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1757 uint8_t *p;
1758 int ret;
fcdd25ab 1759
40c4ed3f
KW		 1760 /* PIO data access allowed only when DRQ bit is set. The result of a read
1761 * during PIO in is indeterminate, return 0 and don't move forward. */
1762 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1763 return 0;
40c4ed3f 1764 }
fcdd25ab 1765
5391d806 1766 p = s->data_ptr;
0c4ad8dc 1767 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 1768 p += 2;
1769 s->data_ptr = p;
1770 if (p >= s->data_end)
1771 s->end_transfer_func(s);
1772 return ret;
1773}
1774
356721ae 1775void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 1776{
bcbdc4d3
GH		 1777 IDEBus *bus = opaque;
1778 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1779 uint8_t *p;
1780
40c4ed3f
KW		 1781 /* PIO data access allowed only when DRQ bit is set. The result of a write
1782 * during PIO out is indeterminate, just ignore it. */
1783 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1784 return;
40c4ed3f 1785 }
fcdd25ab 1786
5391d806 1787 p = s->data_ptr;
0c4ad8dc 1788 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 1789 p += 4;
1790 s->data_ptr = p;
1791 if (p >= s->data_end)
1792 s->end_transfer_func(s);
1793}
1794
356721ae 1795uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 1796{
bcbdc4d3
GH		 1797 IDEBus *bus = opaque;
1798 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1799 uint8_t *p;
1800 int ret;
3b46e624 1801
40c4ed3f
KW		 1802 /* PIO data access allowed only when DRQ bit is set. The result of a read
1803 * during PIO in is indeterminate, return 0 and don't move forward. */
1804 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1805 return 0;
40c4ed3f 1806 }
fcdd25ab 1807
5391d806 1808 p = s->data_ptr;
0c4ad8dc 1809 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 1810 p += 4;
1811 s->data_ptr = p;
1812 if (p >= s->data_end)
1813 s->end_transfer_func(s);
1814 return ret;
1815}
1816
a7dfe172
FB		 1817static void ide_dummy_transfer_stop(IDEState *s)
1818{
1819 s->data_ptr = s->io_buffer;
1820 s->data_end = s->io_buffer;
1821 s->io_buffer[0] = 0xff;
1822 s->io_buffer[1] = 0xff;
1823 s->io_buffer[2] = 0xff;
1824 s->io_buffer[3] = 0xff;
1825}
1826
4a643563 1827static void ide_reset(IDEState *s)
5391d806 1828{
4a643563
BS		 1829#ifdef DEBUG_IDE
1830 printf("ide: reset\n");
1831#endif
bef0fd59
SH		 1832
1833 if (s->pio_aiocb) {
1834 bdrv_aio_cancel(s->pio_aiocb);
1835 s->pio_aiocb = NULL;
1836 }
1837
cd8722bb 1838 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 1839 s->mult_sectors = 0;
1840 else
1841 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 1842 /* ide regs */
1843 s->feature = 0;
1844 s->error = 0;
1845 s->nsector = 0;
1846 s->sector = 0;
1847 s->lcyl = 0;
1848 s->hcyl = 0;
1849
1850 /* lba48 */
1851 s->hob_feature = 0;
1852 s->hob_sector = 0;
1853 s->hob_nsector = 0;
1854 s->hob_lcyl = 0;
1855 s->hob_hcyl = 0;
1856
5391d806 1857 s->select = 0xa0;
41a2b959 1858 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 1859
1860 s->lba48 = 0;
1861
1862 /* ATAPI specific */
1863 s->sense_key = 0;
1864 s->asc = 0;
1865 s->cdrom_changed = 0;
1866 s->packet_transfer_size = 0;
1867 s->elementary_transfer_size = 0;
1868 s->io_buffer_index = 0;
1869 s->cd_sector_size = 0;
1870 s->atapi_dma = 0;
1871 /* ATA DMA state */
1872 s->io_buffer_size = 0;
1873 s->req_nb_sectors = 0;
1874
5391d806 1875 ide_set_signature(s);
a7dfe172
FB		 1876 /* init the transfer handler so that 0xffff is returned on data
1877 accesses */
1878 s->end_transfer_func = ide_dummy_transfer_stop;
1879 ide_dummy_transfer_stop(s);
201a51fc 1880 s->media_changed = 0;
5391d806
FB		 1881}
1882
4a643563
BS		 1883void ide_bus_reset(IDEBus *bus)
1884{
1885 bus->unit = 0;
1886 bus->cmd = 0;
1887 ide_reset(&bus->ifs[0]);
1888 ide_reset(&bus->ifs[1]);
1889 ide_clear_hob(bus);
40a6238a
AG		 1890
1891 /* pending async DMA */
1892 if (bus->dma->aiocb) {
1893#ifdef DEBUG_AIO
1894 printf("aio_cancel\n");
1895#endif
1896 bdrv_aio_cancel(bus->dma->aiocb);
1897 bus->dma->aiocb = NULL;
1898 }
1899
1900 /* reset dma provider too */
1901 bus->dma->ops->reset(bus->dma);
4a643563
BS		 1902}
1903
e4def80b
MA		 1904static bool ide_cd_is_tray_open(void *opaque)
1905{
1906 return ((IDEState *)opaque)->tray_open;
1907}
1908
f107639a
MA		 1909static bool ide_cd_is_medium_locked(void *opaque)
1910{
1911 return ((IDEState *)opaque)->tray_locked;
1912}
1913
0e49de52 1914static const BlockDevOps ide_cd_block_ops = {
145feb17 1915 .change_media_cb = ide_cd_change_cb,
2df0a3a3 1916 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 1917 .is_tray_open = ide_cd_is_tray_open,
f107639a 1918 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 1919};
1920
1f56e32a 1921int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
95ebda85 1922 const char *version, const char *serial, const char *model,
ba801960
MA		 1923 uint64_t wwn,
1924 uint32_t cylinders, uint32_t heads, uint32_t secs,
1925 int chs_trans)
88804180 1926{
88804180
GH		 1927 uint64_t nb_sectors;
1928
f8b6cc00 1929 s->bs = bs;
1f56e32a
MA		 1930 s->drive_kind = kind;
1931
f8b6cc00 1932 bdrv_get_geometry(bs, &nb_sectors);
870111c8
MA		 1933 s->cylinders = cylinders;
1934 s->heads = heads;
1935 s->sectors = secs;
ba801960 1936 s->chs_trans = chs_trans;
870111c8 1937 s->nb_sectors = nb_sectors;
95ebda85 1938 s->wwn = wwn;
870111c8
MA		 1939 /* The SMART values should be preserved across power cycles
1940 but they aren't. */
1941 s->smart_enabled = 1;
1942 s->smart_autosave = 1;
1943 s->smart_errors = 0;
1944 s->smart_selftest_count = 0;
1f56e32a 1945 if (kind == IDE_CD) {
0e49de52 1946 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
7b6f9300 1947 bdrv_set_buffer_alignment(bs, 2048);
7aa9c811 1948 } else {
98f28ad7
MA		 1949 if (!bdrv_is_inserted(s->bs)) {
1950 error_report("Device needs media, but drive is empty");
1951 return -1;
1952 }
7aa9c811
MA		 1953 if (bdrv_is_read_only(bs)) {
1954 error_report("Can't use a read-only drive");
1955 return -1;
1956 }
88804180 1957 }
f8b6cc00 1958 if (serial) {
aa2c91bd 1959 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 1960 } else {
88804180
GH		 1961 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1962 "QM%05d", s->drive_serial);
870111c8 1963 }
27e0c9a1
FB		 1964 if (model) {
1965 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
1966 } else {
1967 switch (kind) {
1968 case IDE_CD:
1969 strcpy(s->drive_model_str, "QEMU DVD-ROM");
1970 break;
1971 case IDE_CFATA:
1972 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
1973 break;
1974 default:
1975 strcpy(s->drive_model_str, "QEMU HARDDISK");
1976 break;
1977 }
1978 }
1979
47c06340
GH		 1980 if (version) {
1981 pstrcpy(s->version, sizeof(s->version), version);
1982 } else {
93bfef4c 1983 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
47c06340 1984 }
40a6238a 1985
88804180 1986 ide_reset(s);
50fb1900 1987 bdrv_iostatus_enable(bs);
c4d74df7 1988 return 0;
88804180
GH		 1989}
1990
57234ee4 1991static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 1992{
1993 static int drive_serial = 1;
1994 IDEState *s = &bus->ifs[unit];
1995
1996 s->bus = bus;
1997 s->unit = unit;
1998 s->drive_serial = drive_serial++;
1b2adf28 1999 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2000 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2001 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2002 memset(s->io_buffer, 0, s->io_buffer_total_len);
2003
d459da0e 2004 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
c925400b
KW		 2005 memset(s->smart_selftest_data, 0, 512);
2006
74475455 2007 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
d459da0e 2008 ide_sector_write_timer_cb, s);
57234ee4
MA		 2009}
2010
40a6238a
AG		 2011static void ide_nop_start(IDEDMA *dma, IDEState *s,
2012 BlockDriverCompletionFunc *cb)
2013{
2014}
2015
2016static int ide_nop(IDEDMA *dma)
2017{
2018 return 0;
2019}
2020
2021static int ide_nop_int(IDEDMA *dma, int x)
2022{
2023 return 0;
2024}
2025
1dfb4dd9 2026static void ide_nop_restart(void *opaque, int x, RunState y)
40a6238a
AG		 2027{
2028}
2029
2030static const IDEDMAOps ide_dma_nop_ops = {
2031 .start_dma = ide_nop_start,
2032 .start_transfer = ide_nop,
2033 .prepare_buf = ide_nop_int,
2034 .rw_buf = ide_nop_int,
2035 .set_unit = ide_nop_int,
2036 .add_status = ide_nop_int,
2037 .set_inactive = ide_nop,
2038 .restart_cb = ide_nop_restart,
2039 .reset = ide_nop,
2040};
2041
2042static IDEDMA ide_dma_nop = {
2043 .ops = &ide_dma_nop_ops,
2044 .aiocb = NULL,
2045};
2046
57234ee4
MA		 2047void ide_init2(IDEBus *bus, qemu_irq irq)
2048{
2049 int i;
2050
2051 for(i = 0; i < 2; i++) {
2052 ide_init1(bus, i);
2053 ide_reset(&bus->ifs[i]);
870111c8 2054 }
57234ee4 2055 bus->irq = irq;
40a6238a 2056 bus->dma = &ide_dma_nop;
d459da0e
MA		 2057}
2058
57234ee4
MA		 2059/* TODO convert users to qdev and remove */
2060void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
2061 DriveInfo *hd1, qemu_irq irq)
5391d806 2062{
ba801960 2063 int i, trans;
57234ee4 2064 DriveInfo *dinfo;
ba801960 2065 uint32_t cyls, heads, secs;
5391d806 2066
caed8802 2067 for(i = 0; i < 2; i++) {
57234ee4
MA		 2068 dinfo = i == 0 ? hd0 : hd1;
2069 ide_init1(bus, i);
2070 if (dinfo) {
ba801960
MA		 2071 cyls = dinfo->cyls;
2072 heads = dinfo->heads;
2073 secs = dinfo->secs;
2074 trans = dinfo->trans;
2075 if (!cyls && !heads && !secs) {
2076 hd_geometry_guess(dinfo->bdrv, &cyls, &heads, &secs, &trans);
2adc99b2
MA		 2077 } else if (trans == BIOS_ATA_TRANSLATION_AUTO) {
2078 trans = hd_bios_chs_auto_trans(cyls, heads, secs);
ba801960 2079 }
b7eb0c9f
MA		 2080 if (cyls < 1 || cyls > 65535) {
2081 error_report("cyls must be between 1 and 65535");
2082 exit(1);
2083 }
2084 if (heads < 1 || heads > 16) {
2085 error_report("heads must be between 1 and 16");
2086 exit(1);
2087 }
2088 if (secs < 1 || secs > 255) {
2089 error_report("secs must be between 1 and 255");
2090 exit(1);
2091 }
1f56e32a 2092 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
577d0a38
MA		 2093 dinfo->media_cd ? IDE_CD : IDE_HD,
2094 NULL, dinfo->serial, NULL, 0,
2095 cyls, heads, secs, trans) < 0) {
c4d74df7
MA		 2096 error_report("Can't set up IDE drive %s", dinfo->id);
2097 exit(1);
2098 }
fa879d62 2099 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
57234ee4
MA		 2100 } else {
2101 ide_reset(&bus->ifs[i]);
2102 }
5391d806 2103 }
9cdd03a7 2104 bus->irq = irq;
40a6238a 2105 bus->dma = &ide_dma_nop;
69b91039
FB		 2106}
2107
4a91d3b3
RH		 2108static const MemoryRegionPortio ide_portio_list[] = {
2109 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2110 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2111 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2112 PORTIO_END_OF_LIST(),
2113};
2114
2115static const MemoryRegionPortio ide_portio2_list[] = {
2116 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2117 PORTIO_END_OF_LIST(),
2118};
2119
2120void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2121{
4a91d3b3
RH		 2122 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2123 bridge has been setup properly to always register with ISA. */
2124 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2125
caed8802 2126 if (iobase2) {
4a91d3b3 2127 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2128 }
5391d806 2129}
69b91039 2130
37159f13 2131static bool is_identify_set(void *opaque, int version_id)
aa941b94 2132{
37159f13
JQ		 2133 IDEState *s = opaque;
2134
2135 return s->identify_set != 0;
2136}
2137
50641c5c
JQ		 2138static EndTransferFunc* transfer_end_table[] = {
2139 ide_sector_read,
2140 ide_sector_write,
2141 ide_transfer_stop,
2142 ide_atapi_cmd_reply_end,
2143 ide_atapi_cmd,
2144 ide_dummy_transfer_stop,
2145};
2146
2147static int transfer_end_table_idx(EndTransferFunc *fn)
2148{
2149 int i;
2150
2151 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2152 if (transfer_end_table[i] == fn)
2153 return i;
2154
2155 return -1;
2156}
2157
37159f13 2158static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2159{
37159f13
JQ		 2160 IDEState *s = opaque;
2161
2162 if (version_id < 3) {
67cc61e4 2163 if (s->sense_key == UNIT_ATTENTION &&
37159f13 2164 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) {
93c8cfd9 2165 s->cdrom_changed = 1;
37159f13 2166 }
93c8cfd9 2167 }
7cdd481c
PB		 2168 if (s->identify_set) {
2169 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2170 }
37159f13 2171 return 0;
aa941b94
AZ		 2172}
2173
50641c5c
JQ		 2174static int ide_drive_pio_post_load(void *opaque, int version_id)
2175{
2176 IDEState *s = opaque;
2177
fb60105d 2178 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2179 return -EINVAL;
2180 }
2181 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2182 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2183 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2184
2185 return 0;
2186}
2187
2188static void ide_drive_pio_pre_save(void *opaque)
2189{
2190 IDEState *s = opaque;
2191 int idx;
2192
2193 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2194 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2195
2196 idx = transfer_end_table_idx(s->end_transfer_func);
2197 if (idx == -1) {
2198 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2199 __func__);
2200 s->end_transfer_fn_idx = 2;
2201 } else {
2202 s->end_transfer_fn_idx = idx;
2203 }
2204}
2205
2206static bool ide_drive_pio_state_needed(void *opaque)
2207{
2208 IDEState *s = opaque;
2209
fdc650d7
KW		 2210 return ((s->status & DRQ_STAT) != 0)
2211 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
50641c5c
JQ		 2212}
2213
db118fe7
MA		 2214static bool ide_tray_state_needed(void *opaque)
2215{
2216 IDEState *s = opaque;
2217
2218 return s->tray_open || s->tray_locked;
2219}
2220
996faf1a
AS		 2221static bool ide_atapi_gesn_needed(void *opaque)
2222{
2223 IDEState *s = opaque;
2224
2225 return s->events.new_media || s->events.eject_request;
2226}
2227
def93791
KW		 2228static bool ide_error_needed(void *opaque)
2229{
2230 IDEBus *bus = opaque;
2231
2232 return (bus->error_status != 0);
2233}
2234
996faf1a 2235/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2236static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2237 .name ="ide_drive/atapi/gesn_state",
2238 .version_id = 1,
2239 .minimum_version_id = 1,
2240 .minimum_version_id_old = 1,
2241 .fields = (VMStateField []) {
2242 VMSTATE_BOOL(events.new_media, IDEState),
2243 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2244 VMSTATE_END_OF_LIST()
996faf1a
AS		 2245 }
2246};
2247
db118fe7
MA		 2248static const VMStateDescription vmstate_ide_tray_state = {
2249 .name = "ide_drive/tray_state",
2250 .version_id = 1,
2251 .minimum_version_id = 1,
2252 .minimum_version_id_old = 1,
db118fe7
MA		 2253 .fields = (VMStateField[]) {
2254 VMSTATE_BOOL(tray_open, IDEState),
2255 VMSTATE_BOOL(tray_locked, IDEState),
2256 VMSTATE_END_OF_LIST()
2257 }
2258};
2259
656fbeff 2260static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2261 .name = "ide_drive/pio_state",
2262 .version_id = 1,
2263 .minimum_version_id = 1,
2264 .minimum_version_id_old = 1,
2265 .pre_save = ide_drive_pio_pre_save,
2266 .post_load = ide_drive_pio_post_load,
2267 .fields = (VMStateField []) {
2268 VMSTATE_INT32(req_nb_sectors, IDEState),
2269 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2270 vmstate_info_uint8, uint8_t),
2271 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2272 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2273 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2274 VMSTATE_INT32(elementary_transfer_size, IDEState),
2275 VMSTATE_INT32(packet_transfer_size, IDEState),
2276 VMSTATE_END_OF_LIST()
2277 }
2278};
2279
37159f13
JQ		 2280const VMStateDescription vmstate_ide_drive = {
2281 .name = "ide_drive",
3abb6260 2282 .version_id = 3,
37159f13
JQ		 2283 .minimum_version_id = 0,
2284 .minimum_version_id_old = 0,
2285 .post_load = ide_drive_post_load,
2286 .fields = (VMStateField []) {
2287 VMSTATE_INT32(mult_sectors, IDEState),
2288 VMSTATE_INT32(identify_set, IDEState),
2289 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2290 VMSTATE_UINT8(feature, IDEState),
2291 VMSTATE_UINT8(error, IDEState),
2292 VMSTATE_UINT32(nsector, IDEState),
2293 VMSTATE_UINT8(sector, IDEState),
2294 VMSTATE_UINT8(lcyl, IDEState),
2295 VMSTATE_UINT8(hcyl, IDEState),
2296 VMSTATE_UINT8(hob_feature, IDEState),
2297 VMSTATE_UINT8(hob_sector, IDEState),
2298 VMSTATE_UINT8(hob_nsector, IDEState),
2299 VMSTATE_UINT8(hob_lcyl, IDEState),
2300 VMSTATE_UINT8(hob_hcyl, IDEState),
2301 VMSTATE_UINT8(select, IDEState),
2302 VMSTATE_UINT8(status, IDEState),
2303 VMSTATE_UINT8(lba48, IDEState),
2304 VMSTATE_UINT8(sense_key, IDEState),
2305 VMSTATE_UINT8(asc, IDEState),
2306 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2307 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2308 },
2309 .subsections = (VMStateSubsection []) {
2310 {
2311 .vmsd = &vmstate_ide_drive_pio_state,
2312 .needed = ide_drive_pio_state_needed,
db118fe7
MA		 2313 }, {
2314 .vmsd = &vmstate_ide_tray_state,
2315 .needed = ide_tray_state_needed,
996faf1a
AS		 2316 }, {
2317 .vmsd = &vmstate_ide_atapi_gesn_state,
2318 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2319 }, {
2320 /* empty */
2321 }
37159f13
JQ		 2322 }
2323};
2324
656fbeff 2325static const VMStateDescription vmstate_ide_error_status = {
def93791
KW		 2326 .name ="ide_bus/error",
2327 .version_id = 1,
2328 .minimum_version_id = 1,
2329 .minimum_version_id_old = 1,
2330 .fields = (VMStateField []) {
2331 VMSTATE_INT32(error_status, IDEBus),
2332 VMSTATE_END_OF_LIST()
2333 }
2334};
2335
6521dc62
JQ		 2336const VMStateDescription vmstate_ide_bus = {
2337 .name = "ide_bus",
2338 .version_id = 1,
2339 .minimum_version_id = 1,
2340 .minimum_version_id_old = 1,
2341 .fields = (VMStateField []) {
2342 VMSTATE_UINT8(cmd, IDEBus),
2343 VMSTATE_UINT8(unit, IDEBus),
2344 VMSTATE_END_OF_LIST()
def93791
KW		 2345 },
2346 .subsections = (VMStateSubsection []) {
2347 {
2348 .vmsd = &vmstate_ide_error_status,
2349 .needed = ide_error_needed,
2350 }, {
2351 /* empty */
2352 }
6521dc62
JQ		 2353 }
2354};
75717903
IY		 2355
2356void ide_drive_get(DriveInfo **hd, int max_bus)
2357{
2358 int i;
2359
2360 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2361 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2362 exit(1);
2363 }
2364
2365 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2366 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2367 }
2368}
Qemu copy for testing