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ide: IDENTIFY word 86 bit 14 is reserved
[qemu.git] / hw / ide / core.c
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5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787
GH		 25#include <hw/hw.h>
26#include <hw/pc.h>
27#include <hw/pci.h>
4a91d3b3 28#include <hw/isa.h>
c4d74df7 29#include "qemu-error.h"
87ecb68b
PB		 30#include "qemu-timer.h"
31#include "sysemu.h"
1fb8648d 32#include "dma.h"
2446333c 33#include "blockdev.h"
59f2a787
GH		 34
35#include <hw/ide/internal.h>
e8b54394 36
b93af93d
BW		 37/* These values were based on a Seagate ST3500418AS but have been modified
38 to make more sense in QEMU */
39static const int smart_attributes[][12] = {
40 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
41 /* raw read error rate*/
42 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
43 /* spin up */
44 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
45 /* start stop count */
46 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
47 /* remapped sectors */
48 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
49 /* power on hours */
50 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
51 /* power cycle count */
52 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
53 /* airflow-temperature-celsius */
54 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
55 /* end of list */
56 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
e8b54394
BW		 57};
58
ce4b6522 59static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 60static void ide_dummy_transfer_stop(IDEState *s);
98087450 61
5391d806
FB		 62static void padstr(char *str, const char *src, int len)
63{
64 int i, v;
65 for(i = 0; i < len; i++) {
66 if (*src)
67 v = *src++;
68 else
69 v = ' ';
69b34976 70 str[i^1] = v;
5391d806
FB		 71 }
72}
73
67b915a5
FB		 74static void put_le16(uint16_t *p, unsigned int v)
75{
0c4ad8dc 76 *p = cpu_to_le16(v);
67b915a5
FB		 77}
78
5391d806
FB		 79static void ide_identify(IDEState *s)
80{
81 uint16_t *p;
82 unsigned int oldsize;
d353fb72 83 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 84
94458802
FB		 85 if (s->identify_set) {
86 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
87 return;
88 }
89
5391d806
FB		 90 memset(s->io_buffer, 0, 512);
91 p = (uint16_t *)s->io_buffer;
67b915a5 92 put_le16(p + 0, 0x0040);
5fafdf24 93 put_le16(p + 1, s->cylinders);
67b915a5
FB		 94 put_le16(p + 3, s->heads);
95 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
96 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 97 put_le16(p + 6, s->sectors);
fa879c64 98 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 99 put_le16(p + 20, 3); /* XXX: retired, remove ? */
100 put_le16(p + 21, 512); /* cache size in sectors */
101 put_le16(p + 22, 4); /* ecc bytes */
47c06340 102 padstr((char *)(p + 23), s->version, 8); /* firmware version */
60fe76f3 103 padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */
3b46e624 104#if MAX_MULT_SECTORS > 1
67b915a5 105 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 106#endif
67b915a5 107 put_le16(p + 48, 1); /* dword I/O */
94458802 108 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 109 put_le16(p + 51, 0x200); /* PIO transfer cycle */
110 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 111 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 112 put_le16(p + 54, s->cylinders);
113 put_le16(p + 55, s->heads);
114 put_le16(p + 56, s->sectors);
5391d806 115 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 116 put_le16(p + 57, oldsize);
117 put_le16(p + 58, oldsize >> 16);
5391d806 118 if (s->mult_sectors)
67b915a5
FB		 119 put_le16(p + 59, 0x100 | s->mult_sectors);
120 put_le16(p + 60, s->nb_sectors);
121 put_le16(p + 61, s->nb_sectors >> 16);
d1b5c20d 122 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 123 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 124 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 125 put_le16(p + 65, 120);
126 put_le16(p + 66, 120);
127 put_le16(p + 67, 120);
128 put_le16(p + 68, 120);
d353fb72
CH		 129 if (dev && dev->conf.discard_granularity) {
130 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
131 }
ccf0fd8b
RE		 132
133 if (s->ncq_queues) {
134 put_le16(p + 75, s->ncq_queues - 1);
135 /* NCQ supported */
136 put_le16(p + 76, (1 << 8));
137 }
138
94458802
FB		 139 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
140 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 141 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
142 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 143 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
144 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
e8b54394
BW		 145 /* 14=set to 1, 1=SMART self test, 0=SMART error logging */
146 put_le16(p + 84, (1 << 14) | 0);
e900a7b7
CH		 147 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
148 if (bdrv_enable_write_cache(s->bs))
149 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
150 else
151 put_le16(p + 85, (1 << 14) | 1);
c2ff060f 152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 153 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
e8b54394
BW		 154 /* 14=set to 1, 1=smart self test, 0=smart error logging */
155 put_le16(p + 87, (1 << 14) | 0);
94458802
FB		 156 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
157 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
c2ff060f
FB		 158 put_le16(p + 100, s->nb_sectors);
159 put_le16(p + 101, s->nb_sectors >> 16);
160 put_le16(p + 102, s->nb_sectors >> 32);
161 put_le16(p + 103, s->nb_sectors >> 48);
d353fb72 162
57dac7ef
MA		 163 if (dev && dev->conf.physical_block_size)
164 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
d353fb72
CH		 165 if (dev && dev->conf.discard_granularity) {
166 put_le16(p + 169, 1); /* TRIM support */
167 }
94458802
FB		 168
169 memcpy(s->identify_data, p, sizeof(s->identify_data));
170 s->identify_set = 1;
5391d806
FB		 171}
172
173static void ide_atapi_identify(IDEState *s)
174{
175 uint16_t *p;
176
94458802
FB		 177 if (s->identify_set) {
178 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
179 return;
180 }
181
5391d806
FB		 182 memset(s->io_buffer, 0, 512);
183 p = (uint16_t *)s->io_buffer;
184 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 185 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 186 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 187 put_le16(p + 20, 3); /* buffer type */
188 put_le16(p + 21, 512); /* cache size in sectors */
189 put_le16(p + 22, 4); /* ecc bytes */
47c06340 190 padstr((char *)(p + 23), s->version, 8); /* firmware version */
38cdea7c 191 padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */
67b915a5 192 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 193#ifdef USE_DMA_CDROM
194 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
195 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 196 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 197 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 198#else
67b915a5
FB		 199 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
200 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
201 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 202#endif
79d1d331 203 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 204 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
205 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
206 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
207 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 208
67b915a5
FB		 209 put_le16(p + 71, 30); /* in ns */
210 put_le16(p + 72, 30); /* in ns */
5391d806 211
1bdaa28d
AG		 212 if (s->ncq_queues) {
213 put_le16(p + 75, s->ncq_queues - 1);
214 /* NCQ supported */
215 put_le16(p + 76, (1 << 8));
216 }
217
67b915a5 218 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
8ccad811
FB		 219#ifdef USE_DMA_CDROM
220 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
221#endif
94458802
FB		 222 memcpy(s->identify_data, p, sizeof(s->identify_data));
223 s->identify_set = 1;
5391d806
FB		 224}
225
201a51fc
AZ		 226static void ide_cfata_identify(IDEState *s)
227{
228 uint16_t *p;
229 uint32_t cur_sec;
201a51fc
AZ		 230
231 p = (uint16_t *) s->identify_data;
232 if (s->identify_set)
233 goto fill_buffer;
234
235 memset(p, 0, sizeof(s->identify_data));
236
237 cur_sec = s->cylinders * s->heads * s->sectors;
238
239 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
240 put_le16(p + 1, s->cylinders); /* Default cylinders */
241 put_le16(p + 3, s->heads); /* Default heads */
242 put_le16(p + 6, s->sectors); /* Default sectors per track */
243 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
244 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
fa879c64 245 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 246 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 247 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
60fe76f3 248 padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
201a51fc
AZ		 249#if MAX_MULT_SECTORS > 1
250 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
251#else
252 put_le16(p + 47, 0x0000);
253#endif
254 put_le16(p + 49, 0x0f00); /* Capabilities */
255 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
256 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
257 put_le16(p + 53, 0x0003); /* Translation params valid */
258 put_le16(p + 54, s->cylinders); /* Current cylinders */
259 put_le16(p + 55, s->heads); /* Current heads */
260 put_le16(p + 56, s->sectors); /* Current sectors */
261 put_le16(p + 57, cur_sec); /* Current capacity */
262 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
263 if (s->mult_sectors) /* Multiple sector setting */
264 put_le16(p + 59, 0x100 | s->mult_sectors);
265 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
266 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
267 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
268 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
269 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
270 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
271 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
272 put_le16(p + 82, 0x400c); /* Command Set supported */
273 put_le16(p + 83, 0x7068); /* Command Set supported */
274 put_le16(p + 84, 0x4000); /* Features supported */
275 put_le16(p + 85, 0x000c); /* Command Set enabled */
276 put_le16(p + 86, 0x7044); /* Command Set enabled */
277 put_le16(p + 87, 0x4000); /* Features enabled */
278 put_le16(p + 91, 0x4060); /* Current APM level */
279 put_le16(p + 129, 0x0002); /* Current features option */
280 put_le16(p + 130, 0x0005); /* Reassigned sectors */
281 put_le16(p + 131, 0x0001); /* Initial power mode */
282 put_le16(p + 132, 0x0000); /* User signature */
283 put_le16(p + 160, 0x8100); /* Power requirement */
284 put_le16(p + 161, 0x8001); /* CF command set */
285
286 s->identify_set = 1;
287
288fill_buffer:
289 memcpy(s->io_buffer, p, sizeof(s->identify_data));
290}
291
5391d806
FB		 292static void ide_set_signature(IDEState *s)
293{
294 s->select &= 0xf0; /* clear head */
295 /* put signature */
296 s->nsector = 1;
297 s->sector = 1;
cd8722bb 298 if (s->drive_kind == IDE_CD) {
5391d806
FB		 299 s->lcyl = 0x14;
300 s->hcyl = 0xeb;
301 } else if (s->bs) {
302 s->lcyl = 0;
303 s->hcyl = 0;
304 } else {
305 s->lcyl = 0xff;
306 s->hcyl = 0xff;
307 }
308}
309
d353fb72
CH		 310typedef struct TrimAIOCB {
311 BlockDriverAIOCB common;
312 QEMUBH *bh;
313 int ret;
314} TrimAIOCB;
315
316static void trim_aio_cancel(BlockDriverAIOCB *acb)
317{
318 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
319
320 qemu_bh_delete(iocb->bh);
321 iocb->bh = NULL;
322 qemu_aio_release(iocb);
323}
324
325static AIOPool trim_aio_pool = {
326 .aiocb_size = sizeof(TrimAIOCB),
327 .cancel = trim_aio_cancel,
328};
329
330static void ide_trim_bh_cb(void *opaque)
331{
332 TrimAIOCB *iocb = opaque;
333
334 iocb->common.cb(iocb->common.opaque, iocb->ret);
335
336 qemu_bh_delete(iocb->bh);
337 iocb->bh = NULL;
338
339 qemu_aio_release(iocb);
340}
341
342BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
343 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
344 BlockDriverCompletionFunc *cb, void *opaque)
345{
346 TrimAIOCB *iocb;
347 int i, j, ret;
348
349 iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque);
350 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
351 iocb->ret = 0;
352
353 for (j = 0; j < qiov->niov; j++) {
354 uint64_t *buffer = qiov->iov[j].iov_base;
355
356 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
357 /* 6-byte LBA + 2-byte range per entry */
358 uint64_t entry = le64_to_cpu(buffer[i]);
359 uint64_t sector = entry & 0x0000ffffffffffffULL;
360 uint16_t count = entry >> 48;
361
362 if (count == 0) {
363 break;
364 }
365
366 ret = bdrv_discard(bs, sector, count);
367 if (!iocb->ret) {
368 iocb->ret = ret;
369 }
370 }
371 }
372
373 qemu_bh_schedule(iocb->bh);
374
375 return &iocb->common;
376}
377
5391d806
FB		 378static inline void ide_abort_command(IDEState *s)
379{
380 s->status = READY_STAT | ERR_STAT;
381 s->error = ABRT_ERR;
382}
383
5391d806 384/* prepare data transfer and tell what to do after */
33231e0e
KW		 385void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
386 EndTransferFunc *end_transfer_func)
5391d806
FB		 387{
388 s->end_transfer_func = end_transfer_func;
389 s->data_ptr = buf;
390 s->data_end = buf + size;
40a6238a 391 if (!(s->status & ERR_STAT)) {
7603d156 392 s->status |= DRQ_STAT;
40a6238a
AG		 393 }
394 s->bus->dma->ops->start_transfer(s->bus->dma);
5391d806
FB		 395}
396
33231e0e 397void ide_transfer_stop(IDEState *s)
5391d806
FB		 398{
399 s->end_transfer_func = ide_transfer_stop;
400 s->data_ptr = s->io_buffer;
401 s->data_end = s->io_buffer;
402 s->status &= ~DRQ_STAT;
403}
404
356721ae 405int64_t ide_get_sector(IDEState *s)
5391d806
FB		 406{
407 int64_t sector_num;
408 if (s->select & 0x40) {
409 /* lba */
c2ff060f
FB		 410 if (!s->lba48) {
411 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
412 (s->lcyl << 8) | s->sector;
413 } else {
414 sector_num = ((int64_t)s->hob_hcyl << 40) |
415 ((int64_t) s->hob_lcyl << 32) |
416 ((int64_t) s->hob_sector << 24) |
417 ((int64_t) s->hcyl << 16) |
418 ((int64_t) s->lcyl << 8) | s->sector;
419 }
5391d806
FB		 420 } else {
421 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 422 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 423 }
424 return sector_num;
425}
426
356721ae 427void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 428{
429 unsigned int cyl, r;
430 if (s->select & 0x40) {
c2ff060f
FB		 431 if (!s->lba48) {
432 s->select = (s->select & 0xf0) | (sector_num >> 24);
433 s->hcyl = (sector_num >> 16);
434 s->lcyl = (sector_num >> 8);
435 s->sector = (sector_num);
436 } else {
437 s->sector = sector_num;
438 s->lcyl = sector_num >> 8;
439 s->hcyl = sector_num >> 16;
440 s->hob_sector = sector_num >> 24;
441 s->hob_lcyl = sector_num >> 32;
442 s->hob_hcyl = sector_num >> 40;
443 }
5391d806
FB		 444 } else {
445 cyl = sector_num / (s->heads * s->sectors);
446 r = sector_num % (s->heads * s->sectors);
447 s->hcyl = cyl >> 8;
448 s->lcyl = cyl;
1b8eb456 449 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 450 s->sector = (r % s->sectors) + 1;
451 }
452}
453
e162cfb0
AZ		 454static void ide_rw_error(IDEState *s) {
455 ide_abort_command(s);
9cdd03a7 456 ide_set_irq(s->bus);
e162cfb0
AZ		 457}
458
40a6238a 459void ide_sector_read(IDEState *s)
5391d806
FB		 460{
461 int64_t sector_num;
462 int ret, n;
463
464 s->status = READY_STAT | SEEK_STAT;
a136e5a8 465 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 466 sector_num = ide_get_sector(s);
467 n = s->nsector;
468 if (n == 0) {
469 /* no more sector to read from disk */
470 ide_transfer_stop(s);
471 } else {
472#if defined(DEBUG_IDE)
18c5f8ea 473 printf("read sector=%" PRId64 "\n", sector_num);
5391d806
FB		 474#endif
475 if (n > s->req_nb_sectors)
476 n = s->req_nb_sectors;
a597e79c
CH		 477
478 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
5391d806 479 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
a597e79c 480 bdrv_acct_done(s->bs, &s->acct);
e162cfb0 481 if (ret != 0) {
ce4b6522
KW		 482 if (ide_handle_rw_error(s, -ret,
483 BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ))
484 {
485 return;
486 }
e162cfb0 487 }
5391d806 488 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
9cdd03a7 489 ide_set_irq(s->bus);
5391d806
FB		 490 ide_set_sector(s, sector_num + n);
491 s->nsector -= n;
492 }
493}
494
b61744b3 495static void dma_buf_commit(IDEState *s)
7aea4412 496{
1fb8648d 497 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 498}
499
33231e0e 500void ide_set_inactive(IDEState *s)
8337606d 501{
40a6238a
AG		 502 s->bus->dma->aiocb = NULL;
503 s->bus->dma->ops->set_inactive(s->bus->dma);
8337606d
KW		 504}
505
356721ae 506void ide_dma_error(IDEState *s)
e162cfb0
AZ		 507{
508 ide_transfer_stop(s);
509 s->error = ABRT_ERR;
510 s->status = READY_STAT | ERR_STAT;
40a6238a 511 ide_set_inactive(s);
9cdd03a7 512 ide_set_irq(s->bus);
e162cfb0
AZ		 513}
514
ce4b6522 515static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 516{
ce4b6522 517 int is_read = (op & BM_STATUS_RETRY_READ);
abd7f68d 518 BlockErrorAction action = bdrv_get_on_error(s->bs, is_read);
428c5705 519
7ad7e3c3 520 if (action == BLOCK_ERR_IGNORE) {
329c0a48 521 bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_IGNORE, is_read);
428c5705 522 return 0;
7ad7e3c3 523 }
428c5705
AL		 524
525 if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)
526 || action == BLOCK_ERR_STOP_ANY) {
40a6238a 527 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 528 s->bus->error_status = op;
329c0a48 529 bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_STOP, is_read);
0461d5a6 530 vm_stop(RUN_STATE_IO_ERROR);
50fb1900 531 bdrv_iostatus_set_err(s->bs, error);
428c5705 532 } else {
ce4b6522 533 if (op & BM_STATUS_DMA_RETRY) {
b61744b3 534 dma_buf_commit(s);
428c5705 535 ide_dma_error(s);
7aea4412 536 } else {
428c5705 537 ide_rw_error(s);
7aea4412 538 }
329c0a48 539 bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_REPORT, is_read);
428c5705
AL		 540 }
541
542 return 1;
543}
544
cd369c46 545void ide_dma_cb(void *opaque, int ret)
98087450 546{
40a6238a 547 IDEState *s = opaque;
8ccad811
FB		 548 int n;
549 int64_t sector_num;
550
e162cfb0 551 if (ret < 0) {
cd369c46
CH		 552 int op = BM_STATUS_DMA_RETRY;
553
4e1e0051 554 if (s->dma_cmd == IDE_DMA_READ)
cd369c46 555 op |= BM_STATUS_RETRY_READ;
d353fb72
CH		 556 else if (s->dma_cmd == IDE_DMA_TRIM)
557 op |= BM_STATUS_RETRY_TRIM;
558
cd369c46 559 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 560 return;
561 }
e162cfb0
AZ		 562 }
563
8ccad811
FB		 564 n = s->io_buffer_size >> 9;
565 sector_num = ide_get_sector(s);
566 if (n > 0) {
b61744b3 567 dma_buf_commit(s);
8ccad811
FB		 568 sector_num += n;
569 ide_set_sector(s, sector_num);
570 s->nsector -= n;
8ccad811
FB		 571 }
572
573 /* end of transfer ? */
574 if (s->nsector == 0) {
98087450 575 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 576 ide_set_irq(s->bus);
cd369c46 577 goto eot;
98087450 578 }
8ccad811
FB		 579
580 /* launch next transfer */
581 n = s->nsector;
596bb44d 582 s->io_buffer_index = 0;
8ccad811 583 s->io_buffer_size = n * 512;
4e1e0051 584 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 585 /* The PRDs were too short. Reset the Active bit, but don't raise an
586 * interrupt. */
7aea4412 587 goto eot;
69c38b8f 588 }
cd369c46 589
8ccad811 590#ifdef DEBUG_AIO
4e1e0051
CH		 591 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
592 sector_num, n, s->dma_cmd);
8ccad811 593#endif
cd369c46 594
4e1e0051
CH		 595 switch (s->dma_cmd) {
596 case IDE_DMA_READ:
cd369c46
CH		 597 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
598 ide_dma_cb, s);
4e1e0051
CH		 599 break;
600 case IDE_DMA_WRITE:
cd369c46
CH		 601 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
602 ide_dma_cb, s);
4e1e0051 603 break;
d353fb72
CH		 604 case IDE_DMA_TRIM:
605 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
bbca72c6 606 ide_issue_trim, ide_dma_cb, s, true);
d353fb72 607 break;
cd369c46 608 }
cd369c46
CH		 609 return;
610
611eot:
a597e79c
CH		 612 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
613 bdrv_acct_done(s->bs, &s->acct);
614 }
615 ide_set_inactive(s);
98087450
FB		 616}
617
4e1e0051 618static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 619{
8ccad811 620 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 621 s->io_buffer_index = 0;
622 s->io_buffer_size = 0;
4e1e0051 623 s->dma_cmd = dma_cmd;
a597e79c
CH		 624
625 switch (dma_cmd) {
626 case IDE_DMA_READ:
627 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
628 BDRV_ACCT_READ);
629 break;
630 case IDE_DMA_WRITE:
631 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
632 BDRV_ACCT_WRITE);
633 break;
634 default:
635 break;
636 }
637
cd369c46 638 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
98087450
FB		 639}
640
a09db21f
FB		 641static void ide_sector_write_timer_cb(void *opaque)
642{
643 IDEState *s = opaque;
9cdd03a7 644 ide_set_irq(s->bus);
a09db21f
FB		 645}
646
40a6238a 647void ide_sector_write(IDEState *s)
5391d806
FB		 648{
649 int64_t sector_num;
31c2a146 650 int ret, n, n1;
5391d806
FB		 651
652 s->status = READY_STAT | SEEK_STAT;
653 sector_num = ide_get_sector(s);
654#if defined(DEBUG_IDE)
18c5f8ea 655 printf("write sector=%" PRId64 "\n", sector_num);
5391d806
FB		 656#endif
657 n = s->nsector;
658 if (n > s->req_nb_sectors)
659 n = s->req_nb_sectors;
a597e79c
CH		 660
661 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
31c2a146 662 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
a597e79c 663 bdrv_acct_done(s->bs, &s->acct);
428c5705 664
e162cfb0 665 if (ret != 0) {
ce4b6522 666 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY))
428c5705 667 return;
e162cfb0
AZ		 668 }
669
5391d806
FB		 670 s->nsector -= n;
671 if (s->nsector == 0) {
292eef5a 672 /* no more sectors to write */
5391d806
FB		 673 ide_transfer_stop(s);
674 } else {
675 n1 = s->nsector;
676 if (n1 > s->req_nb_sectors)
677 n1 = s->req_nb_sectors;
678 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
679 }
680 ide_set_sector(s, sector_num + n);
3b46e624 681
31c2a146
TS		 682 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
683 /* It seems there is a bug in the Windows 2000 installer HDD
684 IDE driver which fills the disk with empty logs when the
685 IDE write IRQ comes too early. This hack tries to correct
686 that at the expense of slower write performances. Use this
687 option _only_ to install Windows 2000. You must disable it
688 for normal use. */
f7736b91 689 qemu_mod_timer(s->sector_write_timer,
74475455 690 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
f7736b91 691 } else {
9cdd03a7 692 ide_set_irq(s->bus);
31c2a146 693 }
5391d806
FB		 694}
695
b0484ae4
CH		 696static void ide_flush_cb(void *opaque, int ret)
697{
698 IDEState *s = opaque;
699
e2bcadad
KW		 700 if (ret < 0) {
701 /* XXX: What sector number to set here? */
702 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
703 return;
704 }
705 }
b0484ae4 706
a597e79c 707 bdrv_acct_done(s->bs, &s->acct);
b0484ae4
CH		 708 s->status = READY_STAT | SEEK_STAT;
709 ide_set_irq(s->bus);
710}
711
40a6238a 712void ide_flush_cache(IDEState *s)
6bcb1a79 713{
b2df7531 714 if (s->bs == NULL) {
6bcb1a79 715 ide_flush_cb(s, 0);
b2df7531
KW		 716 return;
717 }
718
a597e79c 719 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
ad54ae80 720 bdrv_aio_flush(s->bs, ide_flush_cb, s);
6bcb1a79
KW		 721}
722
201a51fc
AZ		 723static void ide_cfata_metadata_inquiry(IDEState *s)
724{
725 uint16_t *p;
726 uint32_t spd;
727
728 p = (uint16_t *) s->io_buffer;
729 memset(p, 0, 0x200);
730 spd = ((s->mdata_size - 1) >> 9) + 1;
731
732 put_le16(p + 0, 0x0001); /* Data format revision */
733 put_le16(p + 1, 0x0000); /* Media property: silicon */
734 put_le16(p + 2, s->media_changed); /* Media status */
735 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
736 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
737 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
738 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
739}
740
741static void ide_cfata_metadata_read(IDEState *s)
742{
743 uint16_t *p;
744
745 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
746 s->status = ERR_STAT;
747 s->error = ABRT_ERR;
748 return;
749 }
750
751 p = (uint16_t *) s->io_buffer;
752 memset(p, 0, 0x200);
753
754 put_le16(p + 0, s->media_changed); /* Media status */
755 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
756 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
757 s->nsector << 9), 0x200 - 2));
758}
759
760static void ide_cfata_metadata_write(IDEState *s)
761{
762 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
763 s->status = ERR_STAT;
764 s->error = ABRT_ERR;
765 return;
766 }
767
768 s->media_changed = 0;
769
770 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
771 s->io_buffer + 2,
772 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
773 s->nsector << 9), 0x200 - 2));
774}
775
bd491d6a 776/* called when the inserted state of the media has changed */
7d4b4ba5 777static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 778{
779 IDEState *s = opaque;
96b8f136 780 uint64_t nb_sectors;
bd491d6a 781
25ad22bc 782 s->tray_open = !load;
bd491d6a
TS		 783 bdrv_get_geometry(s->bs, &nb_sectors);
784 s->nb_sectors = nb_sectors;
9118e7f0 785
4b9b7092
AS		 786 /*
787 * First indicate to the guest that a CD has been removed. That's
788 * done on the next command the guest sends us.
789 *
67cc61e4 790 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 791 * detect a new CD in the drive. See ide_atapi_cmd() for details.
792 */
93c8cfd9 793 s->cdrom_changed = 1;
996faf1a 794 s->events.new_media = true;
2df0a3a3
PB		 795 s->events.eject_request = false;
796 ide_set_irq(s->bus);
797}
798
799static void ide_cd_eject_request_cb(void *opaque, bool force)
800{
801 IDEState *s = opaque;
802
803 s->events.eject_request = true;
804 if (force) {
805 s->tray_locked = false;
806 }
9cdd03a7 807 ide_set_irq(s->bus);
bd491d6a
TS		 808}
809
c2ff060f
FB		 810static void ide_cmd_lba48_transform(IDEState *s, int lba48)
811{
812 s->lba48 = lba48;
813
814 /* handle the 'magic' 0 nsector count conversion here. to avoid
815 * fiddling with the rest of the read logic, we just store the
816 * full sector count in ->nsector and ignore ->hob_nsector from now
817 */
818 if (!s->lba48) {
819 if (!s->nsector)
820 s->nsector = 256;
821 } else {
822 if (!s->nsector && !s->hob_nsector)
823 s->nsector = 65536;
824 else {
825 int lo = s->nsector;
826 int hi = s->hob_nsector;
827
828 s->nsector = (hi << 8) | lo;
829 }
830 }
831}
832
bcbdc4d3 833static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 834{
835 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 836 bus->ifs[0].select &= ~(1 << 7);
837 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 838}
839
356721ae 840void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 841{
bcbdc4d3 842 IDEBus *bus = opaque;
5391d806
FB		 843
844#ifdef DEBUG_IDE
845 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
846#endif
c2ff060f 847
5391d806 848 addr &= 7;
fcdd25ab
AL		 849
850 /* ignore writes to command block while busy with previous command */
bcbdc4d3 851 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 852 return;
853
5391d806
FB		 854 switch(addr) {
855 case 0:
856 break;
857 case 1:
bcbdc4d3 858 ide_clear_hob(bus);
c45c3d00 859 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 860 bus->ifs[0].hob_feature = bus->ifs[0].feature;
861 bus->ifs[1].hob_feature = bus->ifs[1].feature;
862 bus->ifs[0].feature = val;
863 bus->ifs[1].feature = val;
5391d806
FB		 864 break;
865 case 2:
bcbdc4d3
GH		 866 ide_clear_hob(bus);
867 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
868 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
869 bus->ifs[0].nsector = val;
870 bus->ifs[1].nsector = val;
5391d806
FB		 871 break;
872 case 3:
bcbdc4d3
GH		 873 ide_clear_hob(bus);
874 bus->ifs[0].hob_sector = bus->ifs[0].sector;
875 bus->ifs[1].hob_sector = bus->ifs[1].sector;
876 bus->ifs[0].sector = val;
877 bus->ifs[1].sector = val;
5391d806
FB		 878 break;
879 case 4:
bcbdc4d3
GH		 880 ide_clear_hob(bus);
881 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
882 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
883 bus->ifs[0].lcyl = val;
884 bus->ifs[1].lcyl = val;
5391d806
FB		 885 break;
886 case 5:
bcbdc4d3
GH		 887 ide_clear_hob(bus);
888 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
889 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
890 bus->ifs[0].hcyl = val;
891 bus->ifs[1].hcyl = val;
5391d806
FB		 892 break;
893 case 6:
c2ff060f 894 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 895 bus->ifs[0].select = (val & ~0x10) | 0xa0;
896 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 897 /* select drive */
bcbdc4d3 898 bus->unit = (val >> 4) & 1;
5391d806
FB		 899 break;
900 default:
901 case 7:
902 /* command */
7cff87ff
AG		 903 ide_exec_cmd(bus, val);
904 break;
905 }
906}
907
844505b1
MA		 908#define HD_OK (1u << IDE_HD)
909#define CD_OK (1u << IDE_CD)
910#define CFA_OK (1u << IDE_CFATA)
911#define HD_CFA_OK (HD_OK | CFA_OK)
912#define ALL_OK (HD_OK | CD_OK | CFA_OK)
913
914/* See ACS-2 T13/2015-D Table B.2 Command codes */
915static const uint8_t ide_cmd_table[0x100] = {
916 /* NOP not implemented, mandatory for CD */
917 [CFA_REQ_EXT_ERROR_CODE] = CFA_OK,
918 [WIN_DSM] = ALL_OK,
919 [WIN_DEVICE_RESET] = CD_OK,
3cfc2269 920 [WIN_RECAL] = HD_CFA_OK,
844505b1
MA		 921 [WIN_READ] = ALL_OK,
922 [WIN_READ_ONCE] = ALL_OK,
3cfc2269
MA		 923 [WIN_READ_EXT] = HD_CFA_OK,
924 [WIN_READDMA_EXT] = HD_CFA_OK,
925 [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK,
926 [WIN_MULTREAD_EXT] = HD_CFA_OK,
927 [WIN_WRITE] = HD_CFA_OK,
928 [WIN_WRITE_ONCE] = HD_CFA_OK,
929 [WIN_WRITE_EXT] = HD_CFA_OK,
930 [WIN_WRITEDMA_EXT] = HD_CFA_OK,
931 [CFA_WRITE_SECT_WO_ERASE] = CFA_OK,
932 [WIN_MULTWRITE_EXT] = HD_CFA_OK,
933 [WIN_WRITE_VERIFY] = HD_CFA_OK,
934 [WIN_VERIFY] = HD_CFA_OK,
935 [WIN_VERIFY_ONCE] = HD_CFA_OK,
936 [WIN_VERIFY_EXT] = HD_CFA_OK,
844505b1
MA		 937 [WIN_SEEK] = HD_CFA_OK,
938 [CFA_TRANSLATE_SECTOR] = CFA_OK,
939 [WIN_DIAGNOSE] = ALL_OK,
3cfc2269 940 [WIN_SPECIFY] = HD_CFA_OK,
844505b1
MA		 941 [WIN_STANDBYNOW2] = ALL_OK,
942 [WIN_IDLEIMMEDIATE2] = ALL_OK,
943 [WIN_STANDBY2] = ALL_OK,
944 [WIN_SETIDLE2] = ALL_OK,
945 [WIN_CHECKPOWERMODE2] = ALL_OK,
946 [WIN_SLEEPNOW2] = ALL_OK,
947 [WIN_PACKETCMD] = CD_OK,
948 [WIN_PIDENTIFY] = CD_OK,
949 [WIN_SMART] = HD_CFA_OK,
950 [CFA_ACCESS_METADATA_STORAGE] = CFA_OK,
951 [CFA_ERASE_SECTORS] = CFA_OK,
3cfc2269
MA		 952 [WIN_MULTREAD] = HD_CFA_OK,
953 [WIN_MULTWRITE] = HD_CFA_OK,
954 [WIN_SETMULT] = HD_CFA_OK,
955 [WIN_READDMA] = HD_CFA_OK,
956 [WIN_READDMA_ONCE] = HD_CFA_OK,
957 [WIN_WRITEDMA] = HD_CFA_OK,
958 [WIN_WRITEDMA_ONCE] = HD_CFA_OK,
959 [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK,
844505b1
MA		 960 [WIN_STANDBYNOW1] = ALL_OK,
961 [WIN_IDLEIMMEDIATE] = ALL_OK,
962 [WIN_STANDBY] = ALL_OK,
963 [WIN_SETIDLE1] = ALL_OK,
964 [WIN_CHECKPOWERMODE1] = ALL_OK,
965 [WIN_SLEEPNOW1] = ALL_OK,
966 [WIN_FLUSH_CACHE] = ALL_OK,
3cfc2269 967 [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK,
844505b1
MA		 968 [WIN_IDENTIFY] = ALL_OK,
969 [WIN_SETFEATURES] = ALL_OK,
970 [IBM_SENSE_CONDITION] = CFA_OK,
971 [CFA_WEAR_LEVEL] = CFA_OK,
972 [WIN_READ_NATIVE_MAX] = ALL_OK,
973};
974
975static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
976{
977 return cmd < ARRAY_SIZE(ide_cmd_table)
978 && (ide_cmd_table[cmd] & (1u << s->drive_kind));
979}
7cff87ff
AG		 980
981void ide_exec_cmd(IDEBus *bus, uint32_t val)
982{
983 IDEState *s;
984 int n;
985 int lba48 = 0;
986
5391d806 987#if defined(DEBUG_IDE)
6ef2ba5e 988 printf("ide: CMD=%02x\n", val);
5391d806 989#endif
6ef2ba5e 990 s = idebus_active_if(bus);
66a0a2cb 991 /* ignore commands to non existent slave */
6ef2ba5e
AG		 992 if (s != bus->ifs && !s->bs)
993 return;
c2ff060f 994
6ef2ba5e
AG		 995 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
996 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
997 return;
fcdd25ab 998
844505b1
MA		 999 if (!ide_cmd_permitted(s, val)) {
1000 goto abort_cmd;
1001 }
1002
6ef2ba5e 1003 switch(val) {
d353fb72
CH		 1004 case WIN_DSM:
1005 switch (s->feature) {
1006 case DSM_TRIM:
1007 if (!s->bs) {
1008 goto abort_cmd;
1009 }
1010 ide_sector_start_dma(s, IDE_DMA_TRIM);
1011 break;
1012 default:
1013 goto abort_cmd;
1014 }
1015 break;
6ef2ba5e
AG		 1016 case WIN_IDENTIFY:
1017 if (s->bs && s->drive_kind != IDE_CD) {
1018 if (s->drive_kind != IDE_CFATA)
1019 ide_identify(s);
1020 else
1021 ide_cfata_identify(s);
769bec72 1022 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1023 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1024 } else {
1025 if (s->drive_kind == IDE_CD) {
1026 ide_set_signature(s);
5391d806 1027 }
6ef2ba5e
AG		 1028 ide_abort_command(s);
1029 }
1030 ide_set_irq(s->bus);
1031 break;
1032 case WIN_SPECIFY:
1033 case WIN_RECAL:
1034 s->error = 0;
1035 s->status = READY_STAT | SEEK_STAT;
1036 ide_set_irq(s->bus);
1037 break;
1038 case WIN_SETMULT:
1039 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1040 /* Disable Read and Write Multiple */
1041 s->mult_sectors = 0;
41a2b959 1042 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1043 } else if ((s->nsector & 0xff) != 0 &&
1044 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1045 (s->nsector & (s->nsector - 1)) != 0)) {
1046 ide_abort_command(s);
1047 } else {
1048 s->mult_sectors = s->nsector & 0xff;
1049 s->status = READY_STAT | SEEK_STAT;
1050 }
1051 ide_set_irq(s->bus);
1052 break;
1053 case WIN_VERIFY_EXT:
1054 lba48 = 1;
1055 case WIN_VERIFY:
1056 case WIN_VERIFY_ONCE:
1057 /* do sector number check ? */
1058 ide_cmd_lba48_transform(s, lba48);
1059 s->status = READY_STAT | SEEK_STAT;
1060 ide_set_irq(s->bus);
1061 break;
814839c0 1062 case WIN_READ_EXT:
6ef2ba5e
AG		 1063 lba48 = 1;
1064 case WIN_READ:
1065 case WIN_READ_ONCE:
3f76a7c3
MA		 1066 if (s->drive_kind == IDE_CD) {
1067 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
6ef2ba5e 1068 goto abort_cmd;
3f76a7c3 1069 }
d53cdb30
PB		 1070 if (!s->bs) {
1071 goto abort_cmd;
1072 }
6ef2ba5e
AG		 1073 ide_cmd_lba48_transform(s, lba48);
1074 s->req_nb_sectors = 1;
1075 ide_sector_read(s);
1076 break;
814839c0 1077 case WIN_WRITE_EXT:
6ef2ba5e
AG		 1078 lba48 = 1;
1079 case WIN_WRITE:
1080 case WIN_WRITE_ONCE:
1081 case CFA_WRITE_SECT_WO_ERASE:
1082 case WIN_WRITE_VERIFY:
d53cdb30
PB		 1083 if (!s->bs) {
1084 goto abort_cmd;
1085 }
6ef2ba5e
AG		 1086 ide_cmd_lba48_transform(s, lba48);
1087 s->error = 0;
1088 s->status = SEEK_STAT | READY_STAT;
1089 s->req_nb_sectors = 1;
1090 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1091 s->media_changed = 1;
1092 break;
814839c0 1093 case WIN_MULTREAD_EXT:
6ef2ba5e
AG		 1094 lba48 = 1;
1095 case WIN_MULTREAD:
d53cdb30
PB		 1096 if (!s->bs) {
1097 goto abort_cmd;
1098 }
1099 if (!s->mult_sectors) {
6ef2ba5e 1100 goto abort_cmd;
d53cdb30 1101 }
6ef2ba5e
AG		 1102 ide_cmd_lba48_transform(s, lba48);
1103 s->req_nb_sectors = s->mult_sectors;
1104 ide_sector_read(s);
1105 break;
1106 case WIN_MULTWRITE_EXT:
1107 lba48 = 1;
1108 case WIN_MULTWRITE:
1109 case CFA_WRITE_MULTI_WO_ERASE:
d53cdb30
PB		 1110 if (!s->bs) {
1111 goto abort_cmd;
1112 }
1113 if (!s->mult_sectors) {
6ef2ba5e 1114 goto abort_cmd;
d53cdb30 1115 }
6ef2ba5e
AG		 1116 ide_cmd_lba48_transform(s, lba48);
1117 s->error = 0;
1118 s->status = SEEK_STAT | READY_STAT;
1119 s->req_nb_sectors = s->mult_sectors;
1120 n = s->nsector;
1121 if (n > s->req_nb_sectors)
1122 n = s->req_nb_sectors;
1123 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1124 s->media_changed = 1;
1125 break;
814839c0 1126 case WIN_READDMA_EXT:
6ef2ba5e
AG		 1127 lba48 = 1;
1128 case WIN_READDMA:
1129 case WIN_READDMA_ONCE:
d53cdb30 1130 if (!s->bs) {
6ef2ba5e 1131 goto abort_cmd;
d53cdb30 1132 }
6ef2ba5e 1133 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1134 ide_sector_start_dma(s, IDE_DMA_READ);
6ef2ba5e 1135 break;
814839c0 1136 case WIN_WRITEDMA_EXT:
6ef2ba5e
AG		 1137 lba48 = 1;
1138 case WIN_WRITEDMA:
1139 case WIN_WRITEDMA_ONCE:
d53cdb30 1140 if (!s->bs) {
6ef2ba5e 1141 goto abort_cmd;
d53cdb30 1142 }
6ef2ba5e 1143 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1144 ide_sector_start_dma(s, IDE_DMA_WRITE);
6ef2ba5e
AG		 1145 s->media_changed = 1;
1146 break;
1147 case WIN_READ_NATIVE_MAX_EXT:
1148 lba48 = 1;
1149 case WIN_READ_NATIVE_MAX:
1150 ide_cmd_lba48_transform(s, lba48);
1151 ide_set_sector(s, s->nb_sectors - 1);
1152 s->status = READY_STAT | SEEK_STAT;
1153 ide_set_irq(s->bus);
1154 break;
1155 case WIN_CHECKPOWERMODE1:
1156 case WIN_CHECKPOWERMODE2:
b93af93d 1157 s->error = 0;
6ef2ba5e
AG		 1158 s->nsector = 0xff; /* device active or idle */
1159 s->status = READY_STAT | SEEK_STAT;
1160 ide_set_irq(s->bus);
1161 break;
1162 case WIN_SETFEATURES:
1163 if (!s->bs)
1164 goto abort_cmd;
1165 /* XXX: valid for CDROM ? */
1166 switch(s->feature) {
1167 case 0xcc: /* reverting to power-on defaults enable */
1168 case 0x66: /* reverting to power-on defaults disable */
1169 case 0x02: /* write cache enable */
1170 case 0x82: /* write cache disable */
1171 case 0xaa: /* read look-ahead enable */
1172 case 0x55: /* read look-ahead disable */
1173 case 0x05: /* set advanced power management mode */
1174 case 0x85: /* disable advanced power management mode */
1175 case 0x69: /* NOP */
1176 case 0x67: /* NOP */
1177 case 0x96: /* NOP */
1178 case 0x9a: /* NOP */
1179 case 0x42: /* enable Automatic Acoustic Mode */
1180 case 0xc2: /* disable Automatic Acoustic Mode */
41a2b959 1181 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1182 ide_set_irq(s->bus);
a136e5a8 1183 break;
6ef2ba5e 1184 case 0x03: { /* set transfer mode */
94458802 1185 uint8_t val = s->nsector & 0x07;
6ef2ba5e 1186 uint16_t *identify_data = (uint16_t *)s->identify_data;
94458802
FB		 1187
1188 switch (s->nsector >> 3) {
6ef2ba5e
AG		 1189 case 0x00: /* pio default */
1190 case 0x01: /* pio mode */
96c35ceb
JQ		 1191 put_le16(identify_data + 62,0x07);
1192 put_le16(identify_data + 63,0x07);
1193 put_le16(identify_data + 88,0x3f);
d1b5c20d 1194 break;
6ef2ba5e 1195 case 0x02: /* sigle word dma mode*/
96c35ceb
JQ		 1196 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1197 put_le16(identify_data + 63,0x07);
1198 put_le16(identify_data + 88,0x3f);
94458802 1199 break;
6ef2ba5e 1200 case 0x04: /* mdma mode */
96c35ceb
JQ		 1201 put_le16(identify_data + 62,0x07);
1202 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1203 put_le16(identify_data + 88,0x3f);
94458802 1204 break;
6ef2ba5e 1205 case 0x08: /* udma mode */
96c35ceb
JQ		 1206 put_le16(identify_data + 62,0x07);
1207 put_le16(identify_data + 63,0x07);
1208 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
94458802 1209 break;
6ef2ba5e 1210 default:
94458802
FB		 1211 goto abort_cmd;
1212 }
4fbfcd6d 1213 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1214 ide_set_irq(s->bus);
4fbfcd6d 1215 break;
6ef2ba5e
AG		 1216 }
1217 default:
1218 goto abort_cmd;
1219 }
1220 break;
1221 case WIN_FLUSH_CACHE:
1222 case WIN_FLUSH_CACHE_EXT:
1223 ide_flush_cache(s);
1224 break;
1225 case WIN_STANDBY:
1226 case WIN_STANDBY2:
1227 case WIN_STANDBYNOW1:
1228 case WIN_STANDBYNOW2:
1229 case WIN_IDLEIMMEDIATE:
1d4316d3 1230 case WIN_IDLEIMMEDIATE2:
6ef2ba5e
AG		 1231 case WIN_SETIDLE1:
1232 case WIN_SETIDLE2:
1233 case WIN_SLEEPNOW1:
1234 case WIN_SLEEPNOW2:
1235 s->status = READY_STAT;
1236 ide_set_irq(s->bus);
1237 break;
1238 case WIN_SEEK:
6ef2ba5e
AG		 1239 /* XXX: Check that seek is within bounds */
1240 s->status = READY_STAT | SEEK_STAT;
1241 ide_set_irq(s->bus);
1242 break;
1243 /* ATAPI commands */
1244 case WIN_PIDENTIFY:
844505b1
MA		 1245 ide_atapi_identify(s);
1246 s->status = READY_STAT | SEEK_STAT;
1247 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
6ef2ba5e
AG		 1248 ide_set_irq(s->bus);
1249 break;
1250 case WIN_DIAGNOSE:
1251 ide_set_signature(s);
1252 if (s->drive_kind == IDE_CD)
1253 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1254 * devices to return a clear status register
1255 * with READY_STAT *not* set. */
1256 else
41a2b959 1257 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1258 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1259 * present.
1260 */
1261 ide_set_irq(s->bus);
1262 break;
1d4316d3 1263 case WIN_DEVICE_RESET:
6ef2ba5e
AG		 1264 ide_set_signature(s);
1265 s->status = 0x00; /* NOTE: READY is _not_ set */
1266 s->error = 0x01;
1267 break;
1268 case WIN_PACKETCMD:
6ef2ba5e
AG		 1269 /* overlapping commands not supported */
1270 if (s->feature & 0x02)
1271 goto abort_cmd;
1272 s->status = READY_STAT | SEEK_STAT;
1273 s->atapi_dma = s->feature & 1;
1274 s->nsector = 1;
1275 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1276 ide_atapi_cmd);
1277 break;
1278 /* CF-ATA commands */
1279 case CFA_REQ_EXT_ERROR_CODE:
6ef2ba5e
AG		 1280 s->error = 0x09; /* miscellaneous error */
1281 s->status = READY_STAT | SEEK_STAT;
1282 ide_set_irq(s->bus);
1283 break;
1284 case CFA_ERASE_SECTORS:
1285 case CFA_WEAR_LEVEL:
6ef2ba5e
AG		 1286 if (val == CFA_WEAR_LEVEL)
1287 s->nsector = 0;
1288 if (val == CFA_ERASE_SECTORS)
1289 s->media_changed = 1;
1290 s->error = 0x00;
1291 s->status = READY_STAT | SEEK_STAT;
1292 ide_set_irq(s->bus);
1293 break;
1294 case CFA_TRANSLATE_SECTOR:
6ef2ba5e
AG		 1295 s->error = 0x00;
1296 s->status = READY_STAT | SEEK_STAT;
1297 memset(s->io_buffer, 0, 0x200);
1298 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1299 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1300 s->io_buffer[0x02] = s->select; /* Head */
1301 s->io_buffer[0x03] = s->sector; /* Sector */
1302 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1303 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1304 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1305 s->io_buffer[0x13] = 0x00; /* Erase flag */
1306 s->io_buffer[0x18] = 0x00; /* Hot count */
1307 s->io_buffer[0x19] = 0x00; /* Hot count */
1308 s->io_buffer[0x1a] = 0x01; /* Hot count */
1309 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1310 ide_set_irq(s->bus);
1311 break;
1312 case CFA_ACCESS_METADATA_STORAGE:
6ef2ba5e
AG		 1313 switch (s->feature) {
1314 case 0x02: /* Inquiry Metadata Storage */
1315 ide_cfata_metadata_inquiry(s);
201a51fc 1316 break;
6ef2ba5e
AG		 1317 case 0x03: /* Read Metadata Storage */
1318 ide_cfata_metadata_read(s);
201a51fc 1319 break;
6ef2ba5e
AG		 1320 case 0x04: /* Write Metadata Storage */
1321 ide_cfata_metadata_write(s);
201a51fc 1322 break;
6ef2ba5e
AG		 1323 default:
1324 goto abort_cmd;
1325 }
1326 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1327 s->status = 0x00; /* NOTE: READY is _not_ set */
1328 ide_set_irq(s->bus);
1329 break;
1330 case IBM_SENSE_CONDITION:
6ef2ba5e
AG		 1331 switch (s->feature) {
1332 case 0x01: /* sense temperature in device */
1333 s->nsector = 0x50; /* +20 C */
201a51fc 1334 break;
6ef2ba5e
AG		 1335 default:
1336 goto abort_cmd;
1337 }
1338 s->status = READY_STAT | SEEK_STAT;
1339 ide_set_irq(s->bus);
1340 break;
e8b54394 1341
814839c0 1342 case WIN_SMART:
6ef2ba5e 1343 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
e8b54394 1344 goto abort_cmd;
6ef2ba5e 1345 if (!s->smart_enabled && s->feature != SMART_ENABLE)
e8b54394 1346 goto abort_cmd;
6ef2ba5e
AG		 1347 switch (s->feature) {
1348 case SMART_DISABLE:
e8b54394
BW		 1349 s->smart_enabled = 0;
1350 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1351 ide_set_irq(s->bus);
e8b54394 1352 break;
6ef2ba5e 1353 case SMART_ENABLE:
e8b54394
BW		 1354 s->smart_enabled = 1;
1355 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1356 ide_set_irq(s->bus);
e8b54394 1357 break;
6ef2ba5e 1358 case SMART_ATTR_AUTOSAVE:
e8b54394
BW		 1359 switch (s->sector) {
1360 case 0x00:
6ef2ba5e
AG		 1361 s->smart_autosave = 0;
1362 break;
e8b54394 1363 case 0xf1:
6ef2ba5e
AG		 1364 s->smart_autosave = 1;
1365 break;
e8b54394 1366 default:
6ef2ba5e 1367 goto abort_cmd;
e8b54394
BW		 1368 }
1369 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1370 ide_set_irq(s->bus);
e8b54394 1371 break;
6ef2ba5e 1372 case SMART_STATUS:
e8b54394 1373 if (!s->smart_errors) {
6ef2ba5e
AG		 1374 s->hcyl = 0xc2;
1375 s->lcyl = 0x4f;
e8b54394 1376 } else {
6ef2ba5e
AG		 1377 s->hcyl = 0x2c;
1378 s->lcyl = 0xf4;
e8b54394
BW		 1379 }
1380 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1381 ide_set_irq(s->bus);
e8b54394 1382 break;
6ef2ba5e 1383 case SMART_READ_THRESH:
e8b54394
BW		 1384 memset(s->io_buffer, 0, 0x200);
1385 s->io_buffer[0] = 0x01; /* smart struct version */
1386 for (n=0; n<30; n++) {
6ef2ba5e 1387 if (smart_attributes[n][0] == 0)
e8b54394 1388 break;
6ef2ba5e 1389 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
b93af93d 1390 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
e8b54394
BW		 1391 }
1392 for (n=0; n<511; n++) /* checksum */
6ef2ba5e 1393 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1394 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1395 s->status = READY_STAT | SEEK_STAT;
1396 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1397 ide_set_irq(s->bus);
e8b54394 1398 break;
6ef2ba5e 1399 case SMART_READ_DATA:
e8b54394
BW		 1400 memset(s->io_buffer, 0, 0x200);
1401 s->io_buffer[0] = 0x01; /* smart struct version */
1402 for (n=0; n<30; n++) {
b93af93d 1403 if (smart_attributes[n][0] == 0) {
e8b54394 1404 break;
b93af93d
BW		 1405 }
1406 int i;
1407 for(i = 0; i < 11; i++) {
1408 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1409 }
e8b54394
BW		 1410 }
1411 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1412 if (s->smart_selftest_count == 0) {
6ef2ba5e 1413 s->io_buffer[363] = 0;
e8b54394 1414 } else {
6ef2ba5e 1415 s->io_buffer[363] =
e8b54394 1416 s->smart_selftest_data[3 +
6ef2ba5e
AG		 1417 (s->smart_selftest_count - 1) *
1418 24];
e8b54394
BW		 1419 }
1420 s->io_buffer[364] = 0x20;
1421 s->io_buffer[365] = 0x01;
1422 /* offline data collection capacity: execute + self-test*/
1423 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1424 s->io_buffer[368] = 0x03; /* smart capability (1) */
1425 s->io_buffer[369] = 0x00; /* smart capability (2) */
1426 s->io_buffer[370] = 0x01; /* error logging supported */
1427 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1428 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1429 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1430
1431 for (n=0; n<511; n++)
6ef2ba5e 1432 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1433 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1434 s->status = READY_STAT | SEEK_STAT;
1435 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1436 ide_set_irq(s->bus);
e8b54394 1437 break;
6ef2ba5e 1438 case SMART_READ_LOG:
e8b54394
BW		 1439 switch (s->sector) {
1440 case 0x01: /* summary smart error log */
6ef2ba5e
AG		 1441 memset(s->io_buffer, 0, 0x200);
1442 s->io_buffer[0] = 0x01;
1443 s->io_buffer[1] = 0x00; /* no error entries */
1444 s->io_buffer[452] = s->smart_errors & 0xff;
1445 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
e8b54394 1446
6ef2ba5e 1447 for (n=0; n<511; n++)
e8b54394 1448 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1449 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1450 break;
e8b54394 1451 case 0x06: /* smart self test log */
6ef2ba5e
AG		 1452 memset(s->io_buffer, 0, 0x200);
1453 s->io_buffer[0] = 0x01;
1454 if (s->smart_selftest_count == 0) {
e8b54394 1455 s->io_buffer[508] = 0;
6ef2ba5e 1456 } else {
e8b54394
BW		 1457 s->io_buffer[508] = s->smart_selftest_count;
1458 for (n=2; n<506; n++)
6ef2ba5e
AG		 1459 s->io_buffer[n] = s->smart_selftest_data[n];
1460 }
1461 for (n=0; n<511; n++)
e8b54394 1462 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1463 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1464 break;
e8b54394 1465 default:
6ef2ba5e 1466 goto abort_cmd;
e8b54394
BW		 1467 }
1468 s->status = READY_STAT | SEEK_STAT;
1469 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1470 ide_set_irq(s->bus);
e8b54394 1471 break;
6ef2ba5e 1472 case SMART_EXECUTE_OFFLINE:
e8b54394
BW		 1473 switch (s->sector) {
1474 case 0: /* off-line routine */
1475 case 1: /* short self test */
1476 case 2: /* extended self test */
6ef2ba5e
AG		 1477 s->smart_selftest_count++;
1478 if(s->smart_selftest_count > 21)
e8b54394 1479 s->smart_selftest_count = 0;
6ef2ba5e
AG		 1480 n = 2 + (s->smart_selftest_count - 1) * 24;
1481 s->smart_selftest_data[n] = s->sector;
1482 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1483 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1484 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1485 s->status = READY_STAT | SEEK_STAT;
1486 ide_set_irq(s->bus);
1487 break;
e8b54394 1488 default:
6ef2ba5e 1489 goto abort_cmd;
e8b54394
BW		 1490 }
1491 break;
6ef2ba5e 1492 default:
e8b54394 1493 goto abort_cmd;
6ef2ba5e
AG		 1494 }
1495 break;
1496 default:
844505b1 1497 /* should not be reachable */
6ef2ba5e
AG		 1498 abort_cmd:
1499 ide_abort_command(s);
1500 ide_set_irq(s->bus);
1501 break;
1502 }
5391d806
FB		 1503}
1504
356721ae 1505uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1506{
bcbdc4d3
GH		 1507 IDEBus *bus = opaque;
1508 IDEState *s = idebus_active_if(bus);
5391d806 1509 uint32_t addr;
c2ff060f 1510 int ret, hob;
5391d806
FB		 1511
1512 addr = addr1 & 7;
c2ff060f
FB		 1513 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1514 //hob = s->select & (1 << 7);
1515 hob = 0;
5391d806
FB		 1516 switch(addr) {
1517 case 0:
1518 ret = 0xff;
1519 break;
1520 case 1:
bcbdc4d3
GH		 1521 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1522 (s != bus->ifs && !s->bs))
c45c3d00 1523 ret = 0;
c2ff060f 1524 else if (!hob)
c45c3d00 1525 ret = s->error;
c2ff060f
FB		 1526 else
1527 ret = s->hob_feature;
5391d806
FB		 1528 break;
1529 case 2:
bcbdc4d3 1530 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1531 ret = 0;
c2ff060f 1532 else if (!hob)
c45c3d00 1533 ret = s->nsector & 0xff;
c2ff060f
FB		 1534 else
1535 ret = s->hob_nsector;
5391d806
FB		 1536 break;
1537 case 3:
bcbdc4d3 1538 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1539 ret = 0;
c2ff060f 1540 else if (!hob)
c45c3d00 1541 ret = s->sector;
c2ff060f
FB		 1542 else
1543 ret = s->hob_sector;
5391d806
FB		 1544 break;
1545 case 4:
bcbdc4d3 1546 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1547 ret = 0;
c2ff060f 1548 else if (!hob)
c45c3d00 1549 ret = s->lcyl;
c2ff060f
FB		 1550 else
1551 ret = s->hob_lcyl;
5391d806
FB		 1552 break;
1553 case 5:
bcbdc4d3 1554 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1555 ret = 0;
c2ff060f 1556 else if (!hob)
c45c3d00 1557 ret = s->hcyl;
c2ff060f
FB		 1558 else
1559 ret = s->hob_hcyl;
5391d806
FB		 1560 break;
1561 case 6:
bcbdc4d3 1562 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00
FB		 1563 ret = 0;
1564 else
7ae98627 1565 ret = s->select;
5391d806
FB		 1566 break;
1567 default:
1568 case 7:
bcbdc4d3
GH		 1569 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1570 (s != bus->ifs && !s->bs))
c45c3d00
FB		 1571 ret = 0;
1572 else
1573 ret = s->status;
9cdd03a7 1574 qemu_irq_lower(bus->irq);
5391d806
FB		 1575 break;
1576 }
1577#ifdef DEBUG_IDE
1578 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1579#endif
1580 return ret;
1581}
1582
356721ae 1583uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1584{
bcbdc4d3
GH		 1585 IDEBus *bus = opaque;
1586 IDEState *s = idebus_active_if(bus);
5391d806 1587 int ret;
7ae98627 1588
bcbdc4d3
GH		 1589 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1590 (s != bus->ifs && !s->bs))
7ae98627
FB		 1591 ret = 0;
1592 else
1593 ret = s->status;
5391d806
FB		 1594#ifdef DEBUG_IDE
1595 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1596#endif
1597 return ret;
1598}
1599
356721ae 1600void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1601{
bcbdc4d3 1602 IDEBus *bus = opaque;
5391d806
FB		 1603 IDEState *s;
1604 int i;
1605
1606#ifdef DEBUG_IDE
1607 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1608#endif
1609 /* common for both drives */
9cdd03a7 1610 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1611 (val & IDE_CMD_RESET)) {
1612 /* reset low to high */
1613 for(i = 0;i < 2; i++) {
bcbdc4d3 1614 s = &bus->ifs[i];
5391d806
FB		 1615 s->status = BUSY_STAT | SEEK_STAT;
1616 s->error = 0x01;
1617 }
9cdd03a7 1618 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1619 !(val & IDE_CMD_RESET)) {
1620 /* high to low */
1621 for(i = 0;i < 2; i++) {
bcbdc4d3 1622 s = &bus->ifs[i];
cd8722bb 1623 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1624 s->status = 0x00; /* NOTE: READY is _not_ set */
1625 else
56bf1d37 1626 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1627 ide_set_signature(s);
1628 }
1629 }
1630
9cdd03a7 1631 bus->cmd = val;
5391d806
FB		 1632}
1633
40c4ed3f
KW		 1634/*
1635 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1636 * transferred from the device to the guest), false if it's a PIO in
1637 */
1638static bool ide_is_pio_out(IDEState *s)
1639{
1640 if (s->end_transfer_func == ide_sector_write ||
1641 s->end_transfer_func == ide_atapi_cmd) {
1642 return false;
1643 } else if (s->end_transfer_func == ide_sector_read ||
1644 s->end_transfer_func == ide_transfer_stop ||
1645 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1646 s->end_transfer_func == ide_dummy_transfer_stop) {
1647 return true;
1648 }
1649
1650 abort();
1651}
1652
356721ae 1653void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 1654{
bcbdc4d3
GH		 1655 IDEBus *bus = opaque;
1656 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1657 uint8_t *p;
1658
40c4ed3f
KW		 1659 /* PIO data access allowed only when DRQ bit is set. The result of a write
1660 * during PIO out is indeterminate, just ignore it. */
1661 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1662 return;
40c4ed3f 1663 }
fcdd25ab 1664
5391d806 1665 p = s->data_ptr;
0c4ad8dc 1666 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 1667 p += 2;
1668 s->data_ptr = p;
1669 if (p >= s->data_end)
1670 s->end_transfer_func(s);
1671}
1672
356721ae 1673uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 1674{
bcbdc4d3
GH		 1675 IDEBus *bus = opaque;
1676 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1677 uint8_t *p;
1678 int ret;
fcdd25ab 1679
40c4ed3f
KW		 1680 /* PIO data access allowed only when DRQ bit is set. The result of a read
1681 * during PIO in is indeterminate, return 0 and don't move forward. */
1682 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1683 return 0;
40c4ed3f 1684 }
fcdd25ab 1685
5391d806 1686 p = s->data_ptr;
0c4ad8dc 1687 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 1688 p += 2;
1689 s->data_ptr = p;
1690 if (p >= s->data_end)
1691 s->end_transfer_func(s);
1692 return ret;
1693}
1694
356721ae 1695void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 1696{
bcbdc4d3
GH		 1697 IDEBus *bus = opaque;
1698 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1699 uint8_t *p;
1700
40c4ed3f
KW		 1701 /* PIO data access allowed only when DRQ bit is set. The result of a write
1702 * during PIO out is indeterminate, just ignore it. */
1703 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1704 return;
40c4ed3f 1705 }
fcdd25ab 1706
5391d806 1707 p = s->data_ptr;
0c4ad8dc 1708 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 1709 p += 4;
1710 s->data_ptr = p;
1711 if (p >= s->data_end)
1712 s->end_transfer_func(s);
1713}
1714
356721ae 1715uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 1716{
bcbdc4d3
GH		 1717 IDEBus *bus = opaque;
1718 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1719 uint8_t *p;
1720 int ret;
3b46e624 1721
40c4ed3f
KW		 1722 /* PIO data access allowed only when DRQ bit is set. The result of a read
1723 * during PIO in is indeterminate, return 0 and don't move forward. */
1724 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1725 return 0;
40c4ed3f 1726 }
fcdd25ab 1727
5391d806 1728 p = s->data_ptr;
0c4ad8dc 1729 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 1730 p += 4;
1731 s->data_ptr = p;
1732 if (p >= s->data_end)
1733 s->end_transfer_func(s);
1734 return ret;
1735}
1736
a7dfe172
FB		 1737static void ide_dummy_transfer_stop(IDEState *s)
1738{
1739 s->data_ptr = s->io_buffer;
1740 s->data_end = s->io_buffer;
1741 s->io_buffer[0] = 0xff;
1742 s->io_buffer[1] = 0xff;
1743 s->io_buffer[2] = 0xff;
1744 s->io_buffer[3] = 0xff;
1745}
1746
4a643563 1747static void ide_reset(IDEState *s)
5391d806 1748{
4a643563
BS		 1749#ifdef DEBUG_IDE
1750 printf("ide: reset\n");
1751#endif
cd8722bb 1752 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 1753 s->mult_sectors = 0;
1754 else
1755 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 1756 /* ide regs */
1757 s->feature = 0;
1758 s->error = 0;
1759 s->nsector = 0;
1760 s->sector = 0;
1761 s->lcyl = 0;
1762 s->hcyl = 0;
1763
1764 /* lba48 */
1765 s->hob_feature = 0;
1766 s->hob_sector = 0;
1767 s->hob_nsector = 0;
1768 s->hob_lcyl = 0;
1769 s->hob_hcyl = 0;
1770
5391d806 1771 s->select = 0xa0;
41a2b959 1772 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 1773
1774 s->lba48 = 0;
1775
1776 /* ATAPI specific */
1777 s->sense_key = 0;
1778 s->asc = 0;
1779 s->cdrom_changed = 0;
1780 s->packet_transfer_size = 0;
1781 s->elementary_transfer_size = 0;
1782 s->io_buffer_index = 0;
1783 s->cd_sector_size = 0;
1784 s->atapi_dma = 0;
1785 /* ATA DMA state */
1786 s->io_buffer_size = 0;
1787 s->req_nb_sectors = 0;
1788
5391d806 1789 ide_set_signature(s);
a7dfe172
FB		 1790 /* init the transfer handler so that 0xffff is returned on data
1791 accesses */
1792 s->end_transfer_func = ide_dummy_transfer_stop;
1793 ide_dummy_transfer_stop(s);
201a51fc 1794 s->media_changed = 0;
5391d806
FB		 1795}
1796
4a643563
BS		 1797void ide_bus_reset(IDEBus *bus)
1798{
1799 bus->unit = 0;
1800 bus->cmd = 0;
1801 ide_reset(&bus->ifs[0]);
1802 ide_reset(&bus->ifs[1]);
1803 ide_clear_hob(bus);
40a6238a
AG		 1804
1805 /* pending async DMA */
1806 if (bus->dma->aiocb) {
1807#ifdef DEBUG_AIO
1808 printf("aio_cancel\n");
1809#endif
1810 bdrv_aio_cancel(bus->dma->aiocb);
1811 bus->dma->aiocb = NULL;
1812 }
1813
1814 /* reset dma provider too */
1815 bus->dma->ops->reset(bus->dma);
4a643563
BS		 1816}
1817
e4def80b
MA		 1818static bool ide_cd_is_tray_open(void *opaque)
1819{
1820 return ((IDEState *)opaque)->tray_open;
1821}
1822
f107639a
MA		 1823static bool ide_cd_is_medium_locked(void *opaque)
1824{
1825 return ((IDEState *)opaque)->tray_locked;
1826}
1827
0e49de52 1828static const BlockDevOps ide_cd_block_ops = {
145feb17 1829 .change_media_cb = ide_cd_change_cb,
2df0a3a3 1830 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 1831 .is_tray_open = ide_cd_is_tray_open,
f107639a 1832 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 1833};
1834
1f56e32a 1835int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
c4d74df7 1836 const char *version, const char *serial)
88804180
GH		 1837{
1838 int cylinders, heads, secs;
1839 uint64_t nb_sectors;
1840
f8b6cc00 1841 s->bs = bs;
1f56e32a
MA		 1842 s->drive_kind = kind;
1843
f8b6cc00
MA		 1844 bdrv_get_geometry(bs, &nb_sectors);
1845 bdrv_guess_geometry(bs, &cylinders, &heads, &secs);
dce9e928
MA		 1846 if (cylinders < 1 || cylinders > 16383) {
1847 error_report("cyls must be between 1 and 16383");
1848 return -1;
1849 }
1850 if (heads < 1 || heads > 16) {
1851 error_report("heads must be between 1 and 16");
1852 return -1;
1853 }
1854 if (secs < 1 || secs > 63) {
1855 error_report("secs must be between 1 and 63");
1856 return -1;
1857 }
870111c8
MA		 1858 s->cylinders = cylinders;
1859 s->heads = heads;
1860 s->sectors = secs;
1861 s->nb_sectors = nb_sectors;
1862 /* The SMART values should be preserved across power cycles
1863 but they aren't. */
1864 s->smart_enabled = 1;
1865 s->smart_autosave = 1;
1866 s->smart_errors = 0;
1867 s->smart_selftest_count = 0;
1f56e32a 1868 if (kind == IDE_CD) {
0e49de52 1869 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
7b6f9300 1870 bdrv_set_buffer_alignment(bs, 2048);
7aa9c811 1871 } else {
98f28ad7
MA		 1872 if (!bdrv_is_inserted(s->bs)) {
1873 error_report("Device needs media, but drive is empty");
1874 return -1;
1875 }
7aa9c811
MA		 1876 if (bdrv_is_read_only(bs)) {
1877 error_report("Can't use a read-only drive");
1878 return -1;
1879 }
88804180 1880 }
f8b6cc00 1881 if (serial) {
6ced55a5
MA		 1882 strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str));
1883 } else {
88804180
GH		 1884 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1885 "QM%05d", s->drive_serial);
870111c8 1886 }
47c06340
GH		 1887 if (version) {
1888 pstrcpy(s->version, sizeof(s->version), version);
1889 } else {
1890 pstrcpy(s->version, sizeof(s->version), QEMU_VERSION);
1891 }
40a6238a 1892
88804180 1893 ide_reset(s);
50fb1900 1894 bdrv_iostatus_enable(bs);
c4d74df7 1895 return 0;
88804180
GH		 1896}
1897
57234ee4 1898static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 1899{
1900 static int drive_serial = 1;
1901 IDEState *s = &bus->ifs[unit];
1902
1903 s->bus = bus;
1904 s->unit = unit;
1905 s->drive_serial = drive_serial++;
1b2adf28 1906 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 1907 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 1908 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
1909 memset(s->io_buffer, 0, s->io_buffer_total_len);
1910
d459da0e 1911 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
c925400b
KW		 1912 memset(s->smart_selftest_data, 0, 512);
1913
74475455 1914 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
d459da0e 1915 ide_sector_write_timer_cb, s);
57234ee4
MA		 1916}
1917
40a6238a
AG		 1918static void ide_nop_start(IDEDMA *dma, IDEState *s,
1919 BlockDriverCompletionFunc *cb)
1920{
1921}
1922
1923static int ide_nop(IDEDMA *dma)
1924{
1925 return 0;
1926}
1927
1928static int ide_nop_int(IDEDMA *dma, int x)
1929{
1930 return 0;
1931}
1932
1dfb4dd9 1933static void ide_nop_restart(void *opaque, int x, RunState y)
40a6238a
AG		 1934{
1935}
1936
1937static const IDEDMAOps ide_dma_nop_ops = {
1938 .start_dma = ide_nop_start,
1939 .start_transfer = ide_nop,
1940 .prepare_buf = ide_nop_int,
1941 .rw_buf = ide_nop_int,
1942 .set_unit = ide_nop_int,
1943 .add_status = ide_nop_int,
1944 .set_inactive = ide_nop,
1945 .restart_cb = ide_nop_restart,
1946 .reset = ide_nop,
1947};
1948
1949static IDEDMA ide_dma_nop = {
1950 .ops = &ide_dma_nop_ops,
1951 .aiocb = NULL,
1952};
1953
57234ee4
MA		 1954void ide_init2(IDEBus *bus, qemu_irq irq)
1955{
1956 int i;
1957
1958 for(i = 0; i < 2; i++) {
1959 ide_init1(bus, i);
1960 ide_reset(&bus->ifs[i]);
870111c8 1961 }
57234ee4 1962 bus->irq = irq;
40a6238a 1963 bus->dma = &ide_dma_nop;
d459da0e
MA		 1964}
1965
57234ee4
MA		 1966/* TODO convert users to qdev and remove */
1967void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
1968 DriveInfo *hd1, qemu_irq irq)
5391d806 1969{
88804180 1970 int i;
57234ee4 1971 DriveInfo *dinfo;
5391d806 1972
caed8802 1973 for(i = 0; i < 2; i++) {
57234ee4
MA		 1974 dinfo = i == 0 ? hd0 : hd1;
1975 ide_init1(bus, i);
1976 if (dinfo) {
1f56e32a 1977 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
95b5edcd 1978 dinfo->media_cd ? IDE_CD : IDE_HD, NULL,
c4d74df7
MA		 1979 *dinfo->serial ? dinfo->serial : NULL) < 0) {
1980 error_report("Can't set up IDE drive %s", dinfo->id);
1981 exit(1);
1982 }
fa879d62 1983 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
57234ee4
MA		 1984 } else {
1985 ide_reset(&bus->ifs[i]);
1986 }
5391d806 1987 }
9cdd03a7 1988 bus->irq = irq;
40a6238a 1989 bus->dma = &ide_dma_nop;
69b91039
FB		 1990}
1991
4a91d3b3
RH		 1992static const MemoryRegionPortio ide_portio_list[] = {
1993 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
1994 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
1995 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
1996 PORTIO_END_OF_LIST(),
1997};
1998
1999static const MemoryRegionPortio ide_portio2_list[] = {
2000 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2001 PORTIO_END_OF_LIST(),
2002};
2003
2004void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2005{
4a91d3b3
RH		 2006 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2007 bridge has been setup properly to always register with ISA. */
2008 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2009
caed8802 2010 if (iobase2) {
4a91d3b3 2011 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2012 }
5391d806 2013}
69b91039 2014
37159f13 2015static bool is_identify_set(void *opaque, int version_id)
aa941b94 2016{
37159f13
JQ		 2017 IDEState *s = opaque;
2018
2019 return s->identify_set != 0;
2020}
2021
50641c5c
JQ		 2022static EndTransferFunc* transfer_end_table[] = {
2023 ide_sector_read,
2024 ide_sector_write,
2025 ide_transfer_stop,
2026 ide_atapi_cmd_reply_end,
2027 ide_atapi_cmd,
2028 ide_dummy_transfer_stop,
2029};
2030
2031static int transfer_end_table_idx(EndTransferFunc *fn)
2032{
2033 int i;
2034
2035 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2036 if (transfer_end_table[i] == fn)
2037 return i;
2038
2039 return -1;
2040}
2041
37159f13 2042static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2043{
37159f13
JQ		 2044 IDEState *s = opaque;
2045
2046 if (version_id < 3) {
67cc61e4 2047 if (s->sense_key == UNIT_ATTENTION &&
37159f13 2048 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) {
93c8cfd9 2049 s->cdrom_changed = 1;
37159f13 2050 }
93c8cfd9 2051 }
37159f13 2052 return 0;
aa941b94
AZ		 2053}
2054
50641c5c
JQ		 2055static int ide_drive_pio_post_load(void *opaque, int version_id)
2056{
2057 IDEState *s = opaque;
2058
fb60105d 2059 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2060 return -EINVAL;
2061 }
2062 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2063 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2064 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2065
2066 return 0;
2067}
2068
2069static void ide_drive_pio_pre_save(void *opaque)
2070{
2071 IDEState *s = opaque;
2072 int idx;
2073
2074 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2075 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2076
2077 idx = transfer_end_table_idx(s->end_transfer_func);
2078 if (idx == -1) {
2079 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2080 __func__);
2081 s->end_transfer_fn_idx = 2;
2082 } else {
2083 s->end_transfer_fn_idx = idx;
2084 }
2085}
2086
2087static bool ide_drive_pio_state_needed(void *opaque)
2088{
2089 IDEState *s = opaque;
2090
fdc650d7
KW		 2091 return ((s->status & DRQ_STAT) != 0)
2092 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
50641c5c
JQ		 2093}
2094
db118fe7
MA		 2095static bool ide_tray_state_needed(void *opaque)
2096{
2097 IDEState *s = opaque;
2098
2099 return s->tray_open || s->tray_locked;
2100}
2101
996faf1a
AS		 2102static bool ide_atapi_gesn_needed(void *opaque)
2103{
2104 IDEState *s = opaque;
2105
2106 return s->events.new_media || s->events.eject_request;
2107}
2108
def93791
KW		 2109static bool ide_error_needed(void *opaque)
2110{
2111 IDEBus *bus = opaque;
2112
2113 return (bus->error_status != 0);
2114}
2115
996faf1a 2116/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2117static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2118 .name ="ide_drive/atapi/gesn_state",
2119 .version_id = 1,
2120 .minimum_version_id = 1,
2121 .minimum_version_id_old = 1,
2122 .fields = (VMStateField []) {
2123 VMSTATE_BOOL(events.new_media, IDEState),
2124 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2125 VMSTATE_END_OF_LIST()
996faf1a
AS		 2126 }
2127};
2128
db118fe7
MA		 2129static const VMStateDescription vmstate_ide_tray_state = {
2130 .name = "ide_drive/tray_state",
2131 .version_id = 1,
2132 .minimum_version_id = 1,
2133 .minimum_version_id_old = 1,
db118fe7
MA		 2134 .fields = (VMStateField[]) {
2135 VMSTATE_BOOL(tray_open, IDEState),
2136 VMSTATE_BOOL(tray_locked, IDEState),
2137 VMSTATE_END_OF_LIST()
2138 }
2139};
2140
656fbeff 2141static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2142 .name = "ide_drive/pio_state",
2143 .version_id = 1,
2144 .minimum_version_id = 1,
2145 .minimum_version_id_old = 1,
2146 .pre_save = ide_drive_pio_pre_save,
2147 .post_load = ide_drive_pio_post_load,
2148 .fields = (VMStateField []) {
2149 VMSTATE_INT32(req_nb_sectors, IDEState),
2150 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2151 vmstate_info_uint8, uint8_t),
2152 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2153 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2154 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2155 VMSTATE_INT32(elementary_transfer_size, IDEState),
2156 VMSTATE_INT32(packet_transfer_size, IDEState),
2157 VMSTATE_END_OF_LIST()
2158 }
2159};
2160
37159f13
JQ		 2161const VMStateDescription vmstate_ide_drive = {
2162 .name = "ide_drive",
3abb6260 2163 .version_id = 3,
37159f13
JQ		 2164 .minimum_version_id = 0,
2165 .minimum_version_id_old = 0,
2166 .post_load = ide_drive_post_load,
2167 .fields = (VMStateField []) {
2168 VMSTATE_INT32(mult_sectors, IDEState),
2169 VMSTATE_INT32(identify_set, IDEState),
2170 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2171 VMSTATE_UINT8(feature, IDEState),
2172 VMSTATE_UINT8(error, IDEState),
2173 VMSTATE_UINT32(nsector, IDEState),
2174 VMSTATE_UINT8(sector, IDEState),
2175 VMSTATE_UINT8(lcyl, IDEState),
2176 VMSTATE_UINT8(hcyl, IDEState),
2177 VMSTATE_UINT8(hob_feature, IDEState),
2178 VMSTATE_UINT8(hob_sector, IDEState),
2179 VMSTATE_UINT8(hob_nsector, IDEState),
2180 VMSTATE_UINT8(hob_lcyl, IDEState),
2181 VMSTATE_UINT8(hob_hcyl, IDEState),
2182 VMSTATE_UINT8(select, IDEState),
2183 VMSTATE_UINT8(status, IDEState),
2184 VMSTATE_UINT8(lba48, IDEState),
2185 VMSTATE_UINT8(sense_key, IDEState),
2186 VMSTATE_UINT8(asc, IDEState),
2187 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2188 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2189 },
2190 .subsections = (VMStateSubsection []) {
2191 {
2192 .vmsd = &vmstate_ide_drive_pio_state,
2193 .needed = ide_drive_pio_state_needed,
db118fe7
MA		 2194 }, {
2195 .vmsd = &vmstate_ide_tray_state,
2196 .needed = ide_tray_state_needed,
996faf1a
AS		 2197 }, {
2198 .vmsd = &vmstate_ide_atapi_gesn_state,
2199 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2200 }, {
2201 /* empty */
2202 }
37159f13
JQ		 2203 }
2204};
2205
656fbeff 2206static const VMStateDescription vmstate_ide_error_status = {
def93791
KW		 2207 .name ="ide_bus/error",
2208 .version_id = 1,
2209 .minimum_version_id = 1,
2210 .minimum_version_id_old = 1,
2211 .fields = (VMStateField []) {
2212 VMSTATE_INT32(error_status, IDEBus),
2213 VMSTATE_END_OF_LIST()
2214 }
2215};
2216
6521dc62
JQ		 2217const VMStateDescription vmstate_ide_bus = {
2218 .name = "ide_bus",
2219 .version_id = 1,
2220 .minimum_version_id = 1,
2221 .minimum_version_id_old = 1,
2222 .fields = (VMStateField []) {
2223 VMSTATE_UINT8(cmd, IDEBus),
2224 VMSTATE_UINT8(unit, IDEBus),
2225 VMSTATE_END_OF_LIST()
def93791
KW		 2226 },
2227 .subsections = (VMStateSubsection []) {
2228 {
2229 .vmsd = &vmstate_ide_error_status,
2230 .needed = ide_error_needed,
2231 }, {
2232 /* empty */
2233 }
6521dc62
JQ		 2234 }
2235};
75717903
IY		 2236
2237void ide_drive_get(DriveInfo **hd, int max_bus)
2238{
2239 int i;
2240
2241 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2242 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2243 exit(1);
2244 }
2245
2246 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2247 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2248 }
2249}
Qemu copy for testing