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async: Allow nested qemu_bh_poll calls
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5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787
GH		 25#include <hw/hw.h>
26#include <hw/pc.h>
27#include <hw/pci.h>
c4d74df7 28#include "qemu-error.h"
87ecb68b
PB		 29#include "qemu-timer.h"
30#include "sysemu.h"
1fb8648d 31#include "dma.h"
2446333c 32#include "blockdev.h"
59f2a787
GH		 33
34#include <hw/ide/internal.h>
e8b54394 35
b93af93d
BW		 36/* These values were based on a Seagate ST3500418AS but have been modified
37 to make more sense in QEMU */
38static const int smart_attributes[][12] = {
39 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
40 /* raw read error rate*/
41 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
42 /* spin up */
43 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
44 /* start stop count */
45 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
46 /* remapped sectors */
47 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
48 /* power on hours */
49 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
50 /* power cycle count */
51 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* airflow-temperature-celsius */
53 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
54 /* end of list */
55 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
5391d806
FB		 78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
d353fb72 82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 83
94458802
FB		 84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
5391d806
FB		 89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
67b915a5 91 put_le16(p + 0, 0x0040);
5fafdf24 92 put_le16(p + 1, s->cylinders);
67b915a5
FB		 93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 96 put_le16(p + 6, s->sectors);
fa879c64 97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
47c06340 101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
60fe76f3 102 padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */
3b46e624 103#if MAX_MULT_SECTORS > 1
67b915a5 104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 105#endif
67b915a5 106 put_le16(p + 48, 1); /* dword I/O */
94458802 107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
5391d806 114 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
5391d806 117 if (s->mult_sectors)
67b915a5
FB		 118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
d1b5c20d 121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 123 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
d353fb72
CH		 128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
ccf0fd8b
RE		 131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
94458802
FB		 138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
e8b54394
BW		 144 /* 14=set to 1, 1=SMART self test, 0=SMART error logging */
145 put_le16(p + 84, (1 << 14) | 0);
e900a7b7
CH		 146 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
147 if (bdrv_enable_write_cache(s->bs))
148 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
149 else
150 put_le16(p + 85, (1 << 14) | 1);
c2ff060f
FB		 151 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
152 put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
e8b54394
BW		 153 /* 14=set to 1, 1=smart self test, 0=smart error logging */
154 put_le16(p + 87, (1 << 14) | 0);
94458802
FB		 155 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
156 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
c2ff060f
FB		 157 put_le16(p + 100, s->nb_sectors);
158 put_le16(p + 101, s->nb_sectors >> 16);
159 put_le16(p + 102, s->nb_sectors >> 32);
160 put_le16(p + 103, s->nb_sectors >> 48);
d353fb72 161
57dac7ef
MA		 162 if (dev && dev->conf.physical_block_size)
163 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
d353fb72
CH		 164 if (dev && dev->conf.discard_granularity) {
165 put_le16(p + 169, 1); /* TRIM support */
166 }
94458802
FB		 167
168 memcpy(s->identify_data, p, sizeof(s->identify_data));
169 s->identify_set = 1;
5391d806
FB		 170}
171
172static void ide_atapi_identify(IDEState *s)
173{
174 uint16_t *p;
175
94458802
FB		 176 if (s->identify_set) {
177 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
178 return;
179 }
180
5391d806
FB		 181 memset(s->io_buffer, 0, 512);
182 p = (uint16_t *)s->io_buffer;
183 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 184 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 185 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 186 put_le16(p + 20, 3); /* buffer type */
187 put_le16(p + 21, 512); /* cache size in sectors */
188 put_le16(p + 22, 4); /* ecc bytes */
47c06340 189 padstr((char *)(p + 23), s->version, 8); /* firmware version */
38cdea7c 190 padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */
67b915a5 191 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 192#ifdef USE_DMA_CDROM
193 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
194 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 195 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 196 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 197#else
67b915a5
FB		 198 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
199 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
200 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 201#endif
79d1d331 202 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 203 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
204 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
205 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
206 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 207
67b915a5
FB		 208 put_le16(p + 71, 30); /* in ns */
209 put_le16(p + 72, 30); /* in ns */
5391d806 210
1bdaa28d
AG		 211 if (s->ncq_queues) {
212 put_le16(p + 75, s->ncq_queues - 1);
213 /* NCQ supported */
214 put_le16(p + 76, (1 << 8));
215 }
216
67b915a5 217 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
8ccad811
FB		 218#ifdef USE_DMA_CDROM
219 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
220#endif
94458802
FB		 221 memcpy(s->identify_data, p, sizeof(s->identify_data));
222 s->identify_set = 1;
5391d806
FB		 223}
224
201a51fc
AZ		 225static void ide_cfata_identify(IDEState *s)
226{
227 uint16_t *p;
228 uint32_t cur_sec;
201a51fc
AZ		 229
230 p = (uint16_t *) s->identify_data;
231 if (s->identify_set)
232 goto fill_buffer;
233
234 memset(p, 0, sizeof(s->identify_data));
235
236 cur_sec = s->cylinders * s->heads * s->sectors;
237
238 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
239 put_le16(p + 1, s->cylinders); /* Default cylinders */
240 put_le16(p + 3, s->heads); /* Default heads */
241 put_le16(p + 6, s->sectors); /* Default sectors per track */
242 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
243 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
fa879c64 244 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 245 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 246 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
60fe76f3 247 padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
201a51fc
AZ		 248#if MAX_MULT_SECTORS > 1
249 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
250#else
251 put_le16(p + 47, 0x0000);
252#endif
253 put_le16(p + 49, 0x0f00); /* Capabilities */
254 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
255 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
256 put_le16(p + 53, 0x0003); /* Translation params valid */
257 put_le16(p + 54, s->cylinders); /* Current cylinders */
258 put_le16(p + 55, s->heads); /* Current heads */
259 put_le16(p + 56, s->sectors); /* Current sectors */
260 put_le16(p + 57, cur_sec); /* Current capacity */
261 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
262 if (s->mult_sectors) /* Multiple sector setting */
263 put_le16(p + 59, 0x100 | s->mult_sectors);
264 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
265 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
266 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
267 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
268 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
269 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
270 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
271 put_le16(p + 82, 0x400c); /* Command Set supported */
272 put_le16(p + 83, 0x7068); /* Command Set supported */
273 put_le16(p + 84, 0x4000); /* Features supported */
274 put_le16(p + 85, 0x000c); /* Command Set enabled */
275 put_le16(p + 86, 0x7044); /* Command Set enabled */
276 put_le16(p + 87, 0x4000); /* Features enabled */
277 put_le16(p + 91, 0x4060); /* Current APM level */
278 put_le16(p + 129, 0x0002); /* Current features option */
279 put_le16(p + 130, 0x0005); /* Reassigned sectors */
280 put_le16(p + 131, 0x0001); /* Initial power mode */
281 put_le16(p + 132, 0x0000); /* User signature */
282 put_le16(p + 160, 0x8100); /* Power requirement */
283 put_le16(p + 161, 0x8001); /* CF command set */
284
285 s->identify_set = 1;
286
287fill_buffer:
288 memcpy(s->io_buffer, p, sizeof(s->identify_data));
289}
290
5391d806
FB		 291static void ide_set_signature(IDEState *s)
292{
293 s->select &= 0xf0; /* clear head */
294 /* put signature */
295 s->nsector = 1;
296 s->sector = 1;
cd8722bb 297 if (s->drive_kind == IDE_CD) {
5391d806
FB		 298 s->lcyl = 0x14;
299 s->hcyl = 0xeb;
300 } else if (s->bs) {
301 s->lcyl = 0;
302 s->hcyl = 0;
303 } else {
304 s->lcyl = 0xff;
305 s->hcyl = 0xff;
306 }
307}
308
d353fb72
CH		 309typedef struct TrimAIOCB {
310 BlockDriverAIOCB common;
311 QEMUBH *bh;
312 int ret;
313} TrimAIOCB;
314
315static void trim_aio_cancel(BlockDriverAIOCB *acb)
316{
317 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
318
319 qemu_bh_delete(iocb->bh);
320 iocb->bh = NULL;
321 qemu_aio_release(iocb);
322}
323
324static AIOPool trim_aio_pool = {
325 .aiocb_size = sizeof(TrimAIOCB),
326 .cancel = trim_aio_cancel,
327};
328
329static void ide_trim_bh_cb(void *opaque)
330{
331 TrimAIOCB *iocb = opaque;
332
333 iocb->common.cb(iocb->common.opaque, iocb->ret);
334
335 qemu_bh_delete(iocb->bh);
336 iocb->bh = NULL;
337
338 qemu_aio_release(iocb);
339}
340
341BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
342 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
343 BlockDriverCompletionFunc *cb, void *opaque)
344{
345 TrimAIOCB *iocb;
346 int i, j, ret;
347
348 iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque);
349 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
350 iocb->ret = 0;
351
352 for (j = 0; j < qiov->niov; j++) {
353 uint64_t *buffer = qiov->iov[j].iov_base;
354
355 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
356 /* 6-byte LBA + 2-byte range per entry */
357 uint64_t entry = le64_to_cpu(buffer[i]);
358 uint64_t sector = entry & 0x0000ffffffffffffULL;
359 uint16_t count = entry >> 48;
360
361 if (count == 0) {
362 break;
363 }
364
365 ret = bdrv_discard(bs, sector, count);
366 if (!iocb->ret) {
367 iocb->ret = ret;
368 }
369 }
370 }
371
372 qemu_bh_schedule(iocb->bh);
373
374 return &iocb->common;
375}
376
5391d806
FB		 377static inline void ide_abort_command(IDEState *s)
378{
379 s->status = READY_STAT | ERR_STAT;
380 s->error = ABRT_ERR;
381}
382
5391d806 383/* prepare data transfer and tell what to do after */
33231e0e
KW		 384void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
385 EndTransferFunc *end_transfer_func)
5391d806
FB		 386{
387 s->end_transfer_func = end_transfer_func;
388 s->data_ptr = buf;
389 s->data_end = buf + size;
40a6238a 390 if (!(s->status & ERR_STAT)) {
7603d156 391 s->status |= DRQ_STAT;
40a6238a
AG		 392 }
393 s->bus->dma->ops->start_transfer(s->bus->dma);
5391d806
FB		 394}
395
33231e0e 396void ide_transfer_stop(IDEState *s)
5391d806
FB		 397{
398 s->end_transfer_func = ide_transfer_stop;
399 s->data_ptr = s->io_buffer;
400 s->data_end = s->io_buffer;
401 s->status &= ~DRQ_STAT;
402}
403
356721ae 404int64_t ide_get_sector(IDEState *s)
5391d806
FB		 405{
406 int64_t sector_num;
407 if (s->select & 0x40) {
408 /* lba */
c2ff060f
FB		 409 if (!s->lba48) {
410 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
411 (s->lcyl << 8) | s->sector;
412 } else {
413 sector_num = ((int64_t)s->hob_hcyl << 40) |
414 ((int64_t) s->hob_lcyl << 32) |
415 ((int64_t) s->hob_sector << 24) |
416 ((int64_t) s->hcyl << 16) |
417 ((int64_t) s->lcyl << 8) | s->sector;
418 }
5391d806
FB		 419 } else {
420 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 421 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 422 }
423 return sector_num;
424}
425
356721ae 426void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 427{
428 unsigned int cyl, r;
429 if (s->select & 0x40) {
c2ff060f
FB		 430 if (!s->lba48) {
431 s->select = (s->select & 0xf0) | (sector_num >> 24);
432 s->hcyl = (sector_num >> 16);
433 s->lcyl = (sector_num >> 8);
434 s->sector = (sector_num);
435 } else {
436 s->sector = sector_num;
437 s->lcyl = sector_num >> 8;
438 s->hcyl = sector_num >> 16;
439 s->hob_sector = sector_num >> 24;
440 s->hob_lcyl = sector_num >> 32;
441 s->hob_hcyl = sector_num >> 40;
442 }
5391d806
FB		 443 } else {
444 cyl = sector_num / (s->heads * s->sectors);
445 r = sector_num % (s->heads * s->sectors);
446 s->hcyl = cyl >> 8;
447 s->lcyl = cyl;
1b8eb456 448 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 449 s->sector = (r % s->sectors) + 1;
450 }
451}
452
e162cfb0
AZ		 453static void ide_rw_error(IDEState *s) {
454 ide_abort_command(s);
9cdd03a7 455 ide_set_irq(s->bus);
e162cfb0
AZ		 456}
457
40a6238a 458void ide_sector_read(IDEState *s)
5391d806
FB		 459{
460 int64_t sector_num;
461 int ret, n;
462
463 s->status = READY_STAT | SEEK_STAT;
a136e5a8 464 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 465 sector_num = ide_get_sector(s);
466 n = s->nsector;
467 if (n == 0) {
468 /* no more sector to read from disk */
469 ide_transfer_stop(s);
470 } else {
471#if defined(DEBUG_IDE)
18c5f8ea 472 printf("read sector=%" PRId64 "\n", sector_num);
5391d806
FB		 473#endif
474 if (n > s->req_nb_sectors)
475 n = s->req_nb_sectors;
a597e79c
CH		 476
477 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
5391d806 478 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
a597e79c 479 bdrv_acct_done(s->bs, &s->acct);
e162cfb0 480 if (ret != 0) {
ce4b6522
KW		 481 if (ide_handle_rw_error(s, -ret,
482 BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ))
483 {
484 return;
485 }
e162cfb0 486 }
5391d806 487 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
9cdd03a7 488 ide_set_irq(s->bus);
5391d806
FB		 489 ide_set_sector(s, sector_num + n);
490 s->nsector -= n;
491 }
492}
493
7aea4412
AL		 494static void dma_buf_commit(IDEState *s, int is_write)
495{
1fb8648d 496 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 497}
498
33231e0e 499void ide_set_inactive(IDEState *s)
8337606d 500{
40a6238a
AG		 501 s->bus->dma->aiocb = NULL;
502 s->bus->dma->ops->set_inactive(s->bus->dma);
8337606d
KW		 503}
504
356721ae 505void ide_dma_error(IDEState *s)
e162cfb0
AZ		 506{
507 ide_transfer_stop(s);
508 s->error = ABRT_ERR;
509 s->status = READY_STAT | ERR_STAT;
40a6238a 510 ide_set_inactive(s);
9cdd03a7 511 ide_set_irq(s->bus);
e162cfb0
AZ		 512}
513
ce4b6522 514static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 515{
ce4b6522 516 int is_read = (op & BM_STATUS_RETRY_READ);
abd7f68d 517 BlockErrorAction action = bdrv_get_on_error(s->bs, is_read);
428c5705 518
7ad7e3c3
LC		 519 if (action == BLOCK_ERR_IGNORE) {
520 bdrv_mon_event(s->bs, BDRV_ACTION_IGNORE, is_read);
428c5705 521 return 0;
7ad7e3c3 522 }
428c5705
AL		 523
524 if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)
525 || action == BLOCK_ERR_STOP_ANY) {
40a6238a 526 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 527 s->bus->error_status = op;
7ad7e3c3 528 bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read);
e07bbac5 529 vm_stop(VMSTOP_DISKFULL);
428c5705 530 } else {
ce4b6522 531 if (op & BM_STATUS_DMA_RETRY) {
7aea4412 532 dma_buf_commit(s, 0);
428c5705 533 ide_dma_error(s);
7aea4412 534 } else {
428c5705 535 ide_rw_error(s);
7aea4412 536 }
7ad7e3c3 537 bdrv_mon_event(s->bs, BDRV_ACTION_REPORT, is_read);
428c5705
AL		 538 }
539
540 return 1;
541}
542
cd369c46 543void ide_dma_cb(void *opaque, int ret)
98087450 544{
40a6238a 545 IDEState *s = opaque;
8ccad811
FB		 546 int n;
547 int64_t sector_num;
548
c641483f 549handle_rw_error:
e162cfb0 550 if (ret < 0) {
cd369c46
CH		 551 int op = BM_STATUS_DMA_RETRY;
552
4e1e0051 553 if (s->dma_cmd == IDE_DMA_READ)
cd369c46 554 op |= BM_STATUS_RETRY_READ;
d353fb72
CH		 555 else if (s->dma_cmd == IDE_DMA_TRIM)
556 op |= BM_STATUS_RETRY_TRIM;
557
cd369c46 558 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 559 return;
560 }
e162cfb0
AZ		 561 }
562
8ccad811
FB		 563 n = s->io_buffer_size >> 9;
564 sector_num = ide_get_sector(s);
565 if (n > 0) {
4e1e0051 566 dma_buf_commit(s, ide_cmd_is_read(s));
8ccad811
FB		 567 sector_num += n;
568 ide_set_sector(s, sector_num);
569 s->nsector -= n;
8ccad811
FB		 570 }
571
572 /* end of transfer ? */
573 if (s->nsector == 0) {
98087450 574 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 575 ide_set_irq(s->bus);
cd369c46 576 goto eot;
98087450 577 }
8ccad811
FB		 578
579 /* launch next transfer */
580 n = s->nsector;
596bb44d 581 s->io_buffer_index = 0;
8ccad811 582 s->io_buffer_size = n * 512;
4e1e0051 583 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 584 /* The PRDs were too short. Reset the Active bit, but don't raise an
585 * interrupt. */
7aea4412 586 goto eot;
69c38b8f 587 }
cd369c46 588
8ccad811 589#ifdef DEBUG_AIO
4e1e0051
CH		 590 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
591 sector_num, n, s->dma_cmd);
8ccad811 592#endif
cd369c46 593
4e1e0051
CH		 594 switch (s->dma_cmd) {
595 case IDE_DMA_READ:
cd369c46
CH		 596 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
597 ide_dma_cb, s);
4e1e0051
CH		 598 break;
599 case IDE_DMA_WRITE:
cd369c46
CH		 600 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
601 ide_dma_cb, s);
4e1e0051 602 break;
d353fb72
CH		 603 case IDE_DMA_TRIM:
604 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
605 ide_issue_trim, ide_dma_cb, s, 1);
606 break;
cd369c46 607 }
c641483f
CH		 608
609 if (!s->bus->dma->aiocb) {
610 ret = -1;
611 goto handle_rw_error;
612 }
cd369c46
CH		 613 return;
614
615eot:
a597e79c
CH		 616 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
617 bdrv_acct_done(s->bs, &s->acct);
618 }
619 ide_set_inactive(s);
98087450
FB		 620}
621
4e1e0051 622static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 623{
8ccad811 624 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 625 s->io_buffer_index = 0;
626 s->io_buffer_size = 0;
4e1e0051 627 s->dma_cmd = dma_cmd;
a597e79c
CH		 628
629 switch (dma_cmd) {
630 case IDE_DMA_READ:
631 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
632 BDRV_ACCT_READ);
633 break;
634 case IDE_DMA_WRITE:
635 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
636 BDRV_ACCT_WRITE);
637 break;
638 default:
639 break;
640 }
641
cd369c46 642 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
98087450
FB		 643}
644
a09db21f
FB		 645static void ide_sector_write_timer_cb(void *opaque)
646{
647 IDEState *s = opaque;
9cdd03a7 648 ide_set_irq(s->bus);
a09db21f
FB		 649}
650
40a6238a 651void ide_sector_write(IDEState *s)
5391d806
FB		 652{
653 int64_t sector_num;
31c2a146 654 int ret, n, n1;
5391d806
FB		 655
656 s->status = READY_STAT | SEEK_STAT;
657 sector_num = ide_get_sector(s);
658#if defined(DEBUG_IDE)
18c5f8ea 659 printf("write sector=%" PRId64 "\n", sector_num);
5391d806
FB		 660#endif
661 n = s->nsector;
662 if (n > s->req_nb_sectors)
663 n = s->req_nb_sectors;
a597e79c
CH		 664
665 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
31c2a146 666 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
a597e79c 667 bdrv_acct_done(s->bs, &s->acct);
428c5705 668
e162cfb0 669 if (ret != 0) {
ce4b6522 670 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY))
428c5705 671 return;
e162cfb0
AZ		 672 }
673
5391d806
FB		 674 s->nsector -= n;
675 if (s->nsector == 0) {
292eef5a 676 /* no more sectors to write */
5391d806
FB		 677 ide_transfer_stop(s);
678 } else {
679 n1 = s->nsector;
680 if (n1 > s->req_nb_sectors)
681 n1 = s->req_nb_sectors;
682 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
683 }
684 ide_set_sector(s, sector_num + n);
3b46e624 685
31c2a146
TS		 686 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
687 /* It seems there is a bug in the Windows 2000 installer HDD
688 IDE driver which fills the disk with empty logs when the
689 IDE write IRQ comes too early. This hack tries to correct
690 that at the expense of slower write performances. Use this
691 option _only_ to install Windows 2000. You must disable it
692 for normal use. */
f7736b91 693 qemu_mod_timer(s->sector_write_timer,
74475455 694 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
f7736b91 695 } else {
9cdd03a7 696 ide_set_irq(s->bus);
31c2a146 697 }
5391d806
FB		 698}
699
b0484ae4
CH		 700static void ide_flush_cb(void *opaque, int ret)
701{
702 IDEState *s = opaque;
703
e2bcadad
KW		 704 if (ret < 0) {
705 /* XXX: What sector number to set here? */
706 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
707 return;
708 }
709 }
b0484ae4 710
a597e79c 711 bdrv_acct_done(s->bs, &s->acct);
b0484ae4
CH		 712 s->status = READY_STAT | SEEK_STAT;
713 ide_set_irq(s->bus);
714}
715
40a6238a 716void ide_flush_cache(IDEState *s)
6bcb1a79 717{
b2df7531
KW		 718 BlockDriverAIOCB *acb;
719
720 if (s->bs == NULL) {
6bcb1a79 721 ide_flush_cb(s, 0);
b2df7531
KW		 722 return;
723 }
724
a597e79c 725 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
b2df7531
KW		 726 acb = bdrv_aio_flush(s->bs, ide_flush_cb, s);
727 if (acb == NULL) {
728 ide_flush_cb(s, -EIO);
6bcb1a79
KW		 729 }
730}
731
201a51fc
AZ		 732static void ide_cfata_metadata_inquiry(IDEState *s)
733{
734 uint16_t *p;
735 uint32_t spd;
736
737 p = (uint16_t *) s->io_buffer;
738 memset(p, 0, 0x200);
739 spd = ((s->mdata_size - 1) >> 9) + 1;
740
741 put_le16(p + 0, 0x0001); /* Data format revision */
742 put_le16(p + 1, 0x0000); /* Media property: silicon */
743 put_le16(p + 2, s->media_changed); /* Media status */
744 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
745 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
746 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
747 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
748}
749
750static void ide_cfata_metadata_read(IDEState *s)
751{
752 uint16_t *p;
753
754 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
755 s->status = ERR_STAT;
756 s->error = ABRT_ERR;
757 return;
758 }
759
760 p = (uint16_t *) s->io_buffer;
761 memset(p, 0, 0x200);
762
763 put_le16(p + 0, s->media_changed); /* Media status */
764 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
765 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
766 s->nsector << 9), 0x200 - 2));
767}
768
769static void ide_cfata_metadata_write(IDEState *s)
770{
771 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
772 s->status = ERR_STAT;
773 s->error = ABRT_ERR;
774 return;
775 }
776
777 s->media_changed = 0;
778
779 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
780 s->io_buffer + 2,
781 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
782 s->nsector << 9), 0x200 - 2));
783}
784
bd491d6a 785/* called when the inserted state of the media has changed */
db97ee6a 786static void cdrom_change_cb(void *opaque, int reason)
bd491d6a
TS		 787{
788 IDEState *s = opaque;
96b8f136 789 uint64_t nb_sectors;
bd491d6a 790
db97ee6a
CH		 791 if (!(reason & CHANGE_MEDIA)) {
792 return;
793 }
794
bd491d6a
TS		 795 bdrv_get_geometry(s->bs, &nb_sectors);
796 s->nb_sectors = nb_sectors;
9118e7f0 797
4b9b7092
AS		 798 /*
799 * First indicate to the guest that a CD has been removed. That's
800 * done on the next command the guest sends us.
801 *
802 * Then we set SENSE_UNIT_ATTENTION, by which the guest will
803 * detect a new CD in the drive. See ide_atapi_cmd() for details.
804 */
93c8cfd9 805 s->cdrom_changed = 1;
996faf1a 806 s->events.new_media = true;
9cdd03a7 807 ide_set_irq(s->bus);
bd491d6a
TS		 808}
809
c2ff060f
FB		 810static void ide_cmd_lba48_transform(IDEState *s, int lba48)
811{
812 s->lba48 = lba48;
813
814 /* handle the 'magic' 0 nsector count conversion here. to avoid
815 * fiddling with the rest of the read logic, we just store the
816 * full sector count in ->nsector and ignore ->hob_nsector from now
817 */
818 if (!s->lba48) {
819 if (!s->nsector)
820 s->nsector = 256;
821 } else {
822 if (!s->nsector && !s->hob_nsector)
823 s->nsector = 65536;
824 else {
825 int lo = s->nsector;
826 int hi = s->hob_nsector;
827
828 s->nsector = (hi << 8) | lo;
829 }
830 }
831}
832
bcbdc4d3 833static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 834{
835 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 836 bus->ifs[0].select &= ~(1 << 7);
837 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 838}
839
356721ae 840void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 841{
bcbdc4d3 842 IDEBus *bus = opaque;
5391d806
FB		 843
844#ifdef DEBUG_IDE
845 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
846#endif
c2ff060f 847
5391d806 848 addr &= 7;
fcdd25ab
AL		 849
850 /* ignore writes to command block while busy with previous command */
bcbdc4d3 851 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 852 return;
853
5391d806
FB		 854 switch(addr) {
855 case 0:
856 break;
857 case 1:
bcbdc4d3 858 ide_clear_hob(bus);
c45c3d00 859 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 860 bus->ifs[0].hob_feature = bus->ifs[0].feature;
861 bus->ifs[1].hob_feature = bus->ifs[1].feature;
862 bus->ifs[0].feature = val;
863 bus->ifs[1].feature = val;
5391d806
FB		 864 break;
865 case 2:
bcbdc4d3
GH		 866 ide_clear_hob(bus);
867 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
868 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
869 bus->ifs[0].nsector = val;
870 bus->ifs[1].nsector = val;
5391d806
FB		 871 break;
872 case 3:
bcbdc4d3
GH		 873 ide_clear_hob(bus);
874 bus->ifs[0].hob_sector = bus->ifs[0].sector;
875 bus->ifs[1].hob_sector = bus->ifs[1].sector;
876 bus->ifs[0].sector = val;
877 bus->ifs[1].sector = val;
5391d806
FB		 878 break;
879 case 4:
bcbdc4d3
GH		 880 ide_clear_hob(bus);
881 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
882 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
883 bus->ifs[0].lcyl = val;
884 bus->ifs[1].lcyl = val;
5391d806
FB		 885 break;
886 case 5:
bcbdc4d3
GH		 887 ide_clear_hob(bus);
888 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
889 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
890 bus->ifs[0].hcyl = val;
891 bus->ifs[1].hcyl = val;
5391d806
FB		 892 break;
893 case 6:
c2ff060f 894 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 895 bus->ifs[0].select = (val & ~0x10) | 0xa0;
896 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 897 /* select drive */
bcbdc4d3 898 bus->unit = (val >> 4) & 1;
5391d806
FB		 899 break;
900 default:
901 case 7:
902 /* command */
7cff87ff
AG		 903 ide_exec_cmd(bus, val);
904 break;
905 }
906}
907
908
909void ide_exec_cmd(IDEBus *bus, uint32_t val)
910{
911 IDEState *s;
912 int n;
913 int lba48 = 0;
914
5391d806 915#if defined(DEBUG_IDE)
6ef2ba5e 916 printf("ide: CMD=%02x\n", val);
5391d806 917#endif
6ef2ba5e
AG		 918 s = idebus_active_if(bus);
919 /* ignore commands to non existant slave */
920 if (s != bus->ifs && !s->bs)
921 return;
c2ff060f 922
6ef2ba5e
AG		 923 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
924 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
925 return;
fcdd25ab 926
6ef2ba5e 927 switch(val) {
d353fb72
CH		 928 case WIN_DSM:
929 switch (s->feature) {
930 case DSM_TRIM:
931 if (!s->bs) {
932 goto abort_cmd;
933 }
934 ide_sector_start_dma(s, IDE_DMA_TRIM);
935 break;
936 default:
937 goto abort_cmd;
938 }
939 break;
6ef2ba5e
AG		 940 case WIN_IDENTIFY:
941 if (s->bs && s->drive_kind != IDE_CD) {
942 if (s->drive_kind != IDE_CFATA)
943 ide_identify(s);
944 else
945 ide_cfata_identify(s);
769bec72 946 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 947 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
948 } else {
949 if (s->drive_kind == IDE_CD) {
950 ide_set_signature(s);
5391d806 951 }
6ef2ba5e
AG		 952 ide_abort_command(s);
953 }
954 ide_set_irq(s->bus);
955 break;
956 case WIN_SPECIFY:
957 case WIN_RECAL:
958 s->error = 0;
959 s->status = READY_STAT | SEEK_STAT;
960 ide_set_irq(s->bus);
961 break;
962 case WIN_SETMULT:
963 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
964 /* Disable Read and Write Multiple */
965 s->mult_sectors = 0;
41a2b959 966 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 967 } else if ((s->nsector & 0xff) != 0 &&
968 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
969 (s->nsector & (s->nsector - 1)) != 0)) {
970 ide_abort_command(s);
971 } else {
972 s->mult_sectors = s->nsector & 0xff;
973 s->status = READY_STAT | SEEK_STAT;
974 }
975 ide_set_irq(s->bus);
976 break;
977 case WIN_VERIFY_EXT:
978 lba48 = 1;
979 case WIN_VERIFY:
980 case WIN_VERIFY_ONCE:
981 /* do sector number check ? */
982 ide_cmd_lba48_transform(s, lba48);
983 s->status = READY_STAT | SEEK_STAT;
984 ide_set_irq(s->bus);
985 break;
c2ff060f 986 case WIN_READ_EXT:
6ef2ba5e
AG		 987 lba48 = 1;
988 case WIN_READ:
989 case WIN_READ_ONCE:
990 if (!s->bs)
991 goto abort_cmd;
992 ide_cmd_lba48_transform(s, lba48);
993 s->req_nb_sectors = 1;
994 ide_sector_read(s);
995 break;
c2ff060f 996 case WIN_WRITE_EXT:
6ef2ba5e
AG		 997 lba48 = 1;
998 case WIN_WRITE:
999 case WIN_WRITE_ONCE:
1000 case CFA_WRITE_SECT_WO_ERASE:
1001 case WIN_WRITE_VERIFY:
1002 ide_cmd_lba48_transform(s, lba48);
1003 s->error = 0;
1004 s->status = SEEK_STAT | READY_STAT;
1005 s->req_nb_sectors = 1;
1006 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1007 s->media_changed = 1;
1008 break;
c2ff060f 1009 case WIN_MULTREAD_EXT:
6ef2ba5e
AG		 1010 lba48 = 1;
1011 case WIN_MULTREAD:
1012 if (!s->mult_sectors)
1013 goto abort_cmd;
1014 ide_cmd_lba48_transform(s, lba48);
1015 s->req_nb_sectors = s->mult_sectors;
1016 ide_sector_read(s);
1017 break;
1018 case WIN_MULTWRITE_EXT:
1019 lba48 = 1;
1020 case WIN_MULTWRITE:
1021 case CFA_WRITE_MULTI_WO_ERASE:
1022 if (!s->mult_sectors)
1023 goto abort_cmd;
1024 ide_cmd_lba48_transform(s, lba48);
1025 s->error = 0;
1026 s->status = SEEK_STAT | READY_STAT;
1027 s->req_nb_sectors = s->mult_sectors;
1028 n = s->nsector;
1029 if (n > s->req_nb_sectors)
1030 n = s->req_nb_sectors;
1031 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1032 s->media_changed = 1;
1033 break;
c2ff060f 1034 case WIN_READDMA_EXT:
6ef2ba5e
AG		 1035 lba48 = 1;
1036 case WIN_READDMA:
1037 case WIN_READDMA_ONCE:
1038 if (!s->bs)
1039 goto abort_cmd;
1040 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1041 ide_sector_start_dma(s, IDE_DMA_READ);
6ef2ba5e 1042 break;
c2ff060f 1043 case WIN_WRITEDMA_EXT:
6ef2ba5e
AG		 1044 lba48 = 1;
1045 case WIN_WRITEDMA:
1046 case WIN_WRITEDMA_ONCE:
1047 if (!s->bs)
1048 goto abort_cmd;
1049 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1050 ide_sector_start_dma(s, IDE_DMA_WRITE);
6ef2ba5e
AG		 1051 s->media_changed = 1;
1052 break;
1053 case WIN_READ_NATIVE_MAX_EXT:
1054 lba48 = 1;
1055 case WIN_READ_NATIVE_MAX:
1056 ide_cmd_lba48_transform(s, lba48);
1057 ide_set_sector(s, s->nb_sectors - 1);
1058 s->status = READY_STAT | SEEK_STAT;
1059 ide_set_irq(s->bus);
1060 break;
1061 case WIN_CHECKPOWERMODE1:
1062 case WIN_CHECKPOWERMODE2:
b93af93d 1063 s->error = 0;
6ef2ba5e
AG		 1064 s->nsector = 0xff; /* device active or idle */
1065 s->status = READY_STAT | SEEK_STAT;
1066 ide_set_irq(s->bus);
1067 break;
1068 case WIN_SETFEATURES:
1069 if (!s->bs)
1070 goto abort_cmd;
1071 /* XXX: valid for CDROM ? */
1072 switch(s->feature) {
1073 case 0xcc: /* reverting to power-on defaults enable */
1074 case 0x66: /* reverting to power-on defaults disable */
1075 case 0x02: /* write cache enable */
1076 case 0x82: /* write cache disable */
1077 case 0xaa: /* read look-ahead enable */
1078 case 0x55: /* read look-ahead disable */
1079 case 0x05: /* set advanced power management mode */
1080 case 0x85: /* disable advanced power management mode */
1081 case 0x69: /* NOP */
1082 case 0x67: /* NOP */
1083 case 0x96: /* NOP */
1084 case 0x9a: /* NOP */
1085 case 0x42: /* enable Automatic Acoustic Mode */
1086 case 0xc2: /* disable Automatic Acoustic Mode */
41a2b959 1087 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1088 ide_set_irq(s->bus);
a136e5a8 1089 break;
6ef2ba5e 1090 case 0x03: { /* set transfer mode */
94458802 1091 uint8_t val = s->nsector & 0x07;
6ef2ba5e 1092 uint16_t *identify_data = (uint16_t *)s->identify_data;
94458802
FB		 1093
1094 switch (s->nsector >> 3) {
6ef2ba5e
AG		 1095 case 0x00: /* pio default */
1096 case 0x01: /* pio mode */
96c35ceb
JQ		 1097 put_le16(identify_data + 62,0x07);
1098 put_le16(identify_data + 63,0x07);
1099 put_le16(identify_data + 88,0x3f);
d1b5c20d 1100 break;
6ef2ba5e 1101 case 0x02: /* sigle word dma mode*/
96c35ceb
JQ		 1102 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1103 put_le16(identify_data + 63,0x07);
1104 put_le16(identify_data + 88,0x3f);
94458802 1105 break;
6ef2ba5e 1106 case 0x04: /* mdma mode */
96c35ceb
JQ		 1107 put_le16(identify_data + 62,0x07);
1108 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1109 put_le16(identify_data + 88,0x3f);
94458802 1110 break;
6ef2ba5e 1111 case 0x08: /* udma mode */
96c35ceb
JQ		 1112 put_le16(identify_data + 62,0x07);
1113 put_le16(identify_data + 63,0x07);
1114 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
94458802 1115 break;
6ef2ba5e 1116 default:
94458802
FB		 1117 goto abort_cmd;
1118 }
4fbfcd6d 1119 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1120 ide_set_irq(s->bus);
4fbfcd6d 1121 break;
6ef2ba5e
AG		 1122 }
1123 default:
1124 goto abort_cmd;
1125 }
1126 break;
1127 case WIN_FLUSH_CACHE:
1128 case WIN_FLUSH_CACHE_EXT:
1129 ide_flush_cache(s);
1130 break;
1131 case WIN_STANDBY:
1132 case WIN_STANDBY2:
1133 case WIN_STANDBYNOW1:
1134 case WIN_STANDBYNOW2:
1135 case WIN_IDLEIMMEDIATE:
1136 case CFA_IDLEIMMEDIATE:
1137 case WIN_SETIDLE1:
1138 case WIN_SETIDLE2:
1139 case WIN_SLEEPNOW1:
1140 case WIN_SLEEPNOW2:
1141 s->status = READY_STAT;
1142 ide_set_irq(s->bus);
1143 break;
1144 case WIN_SEEK:
1145 if(s->drive_kind == IDE_CD)
1146 goto abort_cmd;
1147 /* XXX: Check that seek is within bounds */
1148 s->status = READY_STAT | SEEK_STAT;
1149 ide_set_irq(s->bus);
1150 break;
1151 /* ATAPI commands */
1152 case WIN_PIDENTIFY:
1153 if (s->drive_kind == IDE_CD) {
1154 ide_atapi_identify(s);
41a2b959 1155 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1156 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1157 } else {
1158 ide_abort_command(s);
1159 }
1160 ide_set_irq(s->bus);
1161 break;
1162 case WIN_DIAGNOSE:
1163 ide_set_signature(s);
1164 if (s->drive_kind == IDE_CD)
1165 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1166 * devices to return a clear status register
1167 * with READY_STAT *not* set. */
1168 else
41a2b959 1169 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1170 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1171 * present.
1172 */
1173 ide_set_irq(s->bus);
1174 break;
1175 case WIN_SRST:
1176 if (s->drive_kind != IDE_CD)
1177 goto abort_cmd;
1178 ide_set_signature(s);
1179 s->status = 0x00; /* NOTE: READY is _not_ set */
1180 s->error = 0x01;
1181 break;
1182 case WIN_PACKETCMD:
1183 if (s->drive_kind != IDE_CD)
1184 goto abort_cmd;
1185 /* overlapping commands not supported */
1186 if (s->feature & 0x02)
1187 goto abort_cmd;
1188 s->status = READY_STAT | SEEK_STAT;
1189 s->atapi_dma = s->feature & 1;
1190 s->nsector = 1;
1191 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1192 ide_atapi_cmd);
1193 break;
1194 /* CF-ATA commands */
1195 case CFA_REQ_EXT_ERROR_CODE:
1196 if (s->drive_kind != IDE_CFATA)
1197 goto abort_cmd;
1198 s->error = 0x09; /* miscellaneous error */
1199 s->status = READY_STAT | SEEK_STAT;
1200 ide_set_irq(s->bus);
1201 break;
1202 case CFA_ERASE_SECTORS:
1203 case CFA_WEAR_LEVEL:
1204 if (s->drive_kind != IDE_CFATA)
1205 goto abort_cmd;
1206 if (val == CFA_WEAR_LEVEL)
1207 s->nsector = 0;
1208 if (val == CFA_ERASE_SECTORS)
1209 s->media_changed = 1;
1210 s->error = 0x00;
1211 s->status = READY_STAT | SEEK_STAT;
1212 ide_set_irq(s->bus);
1213 break;
1214 case CFA_TRANSLATE_SECTOR:
1215 if (s->drive_kind != IDE_CFATA)
1216 goto abort_cmd;
1217 s->error = 0x00;
1218 s->status = READY_STAT | SEEK_STAT;
1219 memset(s->io_buffer, 0, 0x200);
1220 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1221 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1222 s->io_buffer[0x02] = s->select; /* Head */
1223 s->io_buffer[0x03] = s->sector; /* Sector */
1224 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1225 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1226 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1227 s->io_buffer[0x13] = 0x00; /* Erase flag */
1228 s->io_buffer[0x18] = 0x00; /* Hot count */
1229 s->io_buffer[0x19] = 0x00; /* Hot count */
1230 s->io_buffer[0x1a] = 0x01; /* Hot count */
1231 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1232 ide_set_irq(s->bus);
1233 break;
1234 case CFA_ACCESS_METADATA_STORAGE:
1235 if (s->drive_kind != IDE_CFATA)
1236 goto abort_cmd;
1237 switch (s->feature) {
1238 case 0x02: /* Inquiry Metadata Storage */
1239 ide_cfata_metadata_inquiry(s);
201a51fc 1240 break;
6ef2ba5e
AG		 1241 case 0x03: /* Read Metadata Storage */
1242 ide_cfata_metadata_read(s);
201a51fc 1243 break;
6ef2ba5e
AG		 1244 case 0x04: /* Write Metadata Storage */
1245 ide_cfata_metadata_write(s);
201a51fc 1246 break;
6ef2ba5e
AG		 1247 default:
1248 goto abort_cmd;
1249 }
1250 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1251 s->status = 0x00; /* NOTE: READY is _not_ set */
1252 ide_set_irq(s->bus);
1253 break;
1254 case IBM_SENSE_CONDITION:
1255 if (s->drive_kind != IDE_CFATA)
1256 goto abort_cmd;
1257 switch (s->feature) {
1258 case 0x01: /* sense temperature in device */
1259 s->nsector = 0x50; /* +20 C */
201a51fc 1260 break;
6ef2ba5e
AG		 1261 default:
1262 goto abort_cmd;
1263 }
1264 s->status = READY_STAT | SEEK_STAT;
1265 ide_set_irq(s->bus);
1266 break;
e8b54394
BW		 1267
1268 case WIN_SMART:
6ef2ba5e 1269 if (s->drive_kind == IDE_CD)
e8b54394 1270 goto abort_cmd;
6ef2ba5e 1271 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
e8b54394 1272 goto abort_cmd;
6ef2ba5e 1273 if (!s->smart_enabled && s->feature != SMART_ENABLE)
e8b54394 1274 goto abort_cmd;
6ef2ba5e
AG		 1275 switch (s->feature) {
1276 case SMART_DISABLE:
e8b54394
BW		 1277 s->smart_enabled = 0;
1278 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1279 ide_set_irq(s->bus);
e8b54394 1280 break;
6ef2ba5e 1281 case SMART_ENABLE:
e8b54394
BW		 1282 s->smart_enabled = 1;
1283 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1284 ide_set_irq(s->bus);
e8b54394 1285 break;
6ef2ba5e 1286 case SMART_ATTR_AUTOSAVE:
e8b54394
BW		 1287 switch (s->sector) {
1288 case 0x00:
6ef2ba5e
AG		 1289 s->smart_autosave = 0;
1290 break;
e8b54394 1291 case 0xf1:
6ef2ba5e
AG		 1292 s->smart_autosave = 1;
1293 break;
e8b54394 1294 default:
6ef2ba5e 1295 goto abort_cmd;
e8b54394
BW		 1296 }
1297 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1298 ide_set_irq(s->bus);
e8b54394 1299 break;
6ef2ba5e 1300 case SMART_STATUS:
e8b54394 1301 if (!s->smart_errors) {
6ef2ba5e
AG		 1302 s->hcyl = 0xc2;
1303 s->lcyl = 0x4f;
e8b54394 1304 } else {
6ef2ba5e
AG		 1305 s->hcyl = 0x2c;
1306 s->lcyl = 0xf4;
e8b54394
BW		 1307 }
1308 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1309 ide_set_irq(s->bus);
e8b54394 1310 break;
6ef2ba5e 1311 case SMART_READ_THRESH:
e8b54394
BW		 1312 memset(s->io_buffer, 0, 0x200);
1313 s->io_buffer[0] = 0x01; /* smart struct version */
1314 for (n=0; n<30; n++) {
6ef2ba5e 1315 if (smart_attributes[n][0] == 0)
e8b54394 1316 break;
6ef2ba5e 1317 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
b93af93d 1318 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
e8b54394
BW		 1319 }
1320 for (n=0; n<511; n++) /* checksum */
6ef2ba5e 1321 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1322 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1323 s->status = READY_STAT | SEEK_STAT;
1324 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1325 ide_set_irq(s->bus);
e8b54394 1326 break;
6ef2ba5e 1327 case SMART_READ_DATA:
e8b54394
BW		 1328 memset(s->io_buffer, 0, 0x200);
1329 s->io_buffer[0] = 0x01; /* smart struct version */
1330 for (n=0; n<30; n++) {
b93af93d 1331 if (smart_attributes[n][0] == 0) {
e8b54394 1332 break;
b93af93d
BW		 1333 }
1334 int i;
1335 for(i = 0; i < 11; i++) {
1336 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1337 }
e8b54394
BW		 1338 }
1339 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1340 if (s->smart_selftest_count == 0) {
6ef2ba5e 1341 s->io_buffer[363] = 0;
e8b54394 1342 } else {
6ef2ba5e 1343 s->io_buffer[363] =
e8b54394 1344 s->smart_selftest_data[3 +
6ef2ba5e
AG		 1345 (s->smart_selftest_count - 1) *
1346 24];
e8b54394
BW		 1347 }
1348 s->io_buffer[364] = 0x20;
1349 s->io_buffer[365] = 0x01;
1350 /* offline data collection capacity: execute + self-test*/
1351 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1352 s->io_buffer[368] = 0x03; /* smart capability (1) */
1353 s->io_buffer[369] = 0x00; /* smart capability (2) */
1354 s->io_buffer[370] = 0x01; /* error logging supported */
1355 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1356 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1357 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1358
1359 for (n=0; n<511; n++)
6ef2ba5e 1360 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1361 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1362 s->status = READY_STAT | SEEK_STAT;
1363 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1364 ide_set_irq(s->bus);
e8b54394 1365 break;
6ef2ba5e 1366 case SMART_READ_LOG:
e8b54394
BW		 1367 switch (s->sector) {
1368 case 0x01: /* summary smart error log */
6ef2ba5e
AG		 1369 memset(s->io_buffer, 0, 0x200);
1370 s->io_buffer[0] = 0x01;
1371 s->io_buffer[1] = 0x00; /* no error entries */
1372 s->io_buffer[452] = s->smart_errors & 0xff;
1373 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
e8b54394 1374
6ef2ba5e 1375 for (n=0; n<511; n++)
e8b54394 1376 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1377 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1378 break;
e8b54394 1379 case 0x06: /* smart self test log */
6ef2ba5e
AG		 1380 memset(s->io_buffer, 0, 0x200);
1381 s->io_buffer[0] = 0x01;
1382 if (s->smart_selftest_count == 0) {
e8b54394 1383 s->io_buffer[508] = 0;
6ef2ba5e 1384 } else {
e8b54394
BW		 1385 s->io_buffer[508] = s->smart_selftest_count;
1386 for (n=2; n<506; n++)
6ef2ba5e
AG		 1387 s->io_buffer[n] = s->smart_selftest_data[n];
1388 }
1389 for (n=0; n<511; n++)
e8b54394 1390 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1391 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1392 break;
e8b54394 1393 default:
6ef2ba5e 1394 goto abort_cmd;
e8b54394
BW		 1395 }
1396 s->status = READY_STAT | SEEK_STAT;
1397 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1398 ide_set_irq(s->bus);
e8b54394 1399 break;
6ef2ba5e 1400 case SMART_EXECUTE_OFFLINE:
e8b54394
BW		 1401 switch (s->sector) {
1402 case 0: /* off-line routine */
1403 case 1: /* short self test */
1404 case 2: /* extended self test */
6ef2ba5e
AG		 1405 s->smart_selftest_count++;
1406 if(s->smart_selftest_count > 21)
e8b54394 1407 s->smart_selftest_count = 0;
6ef2ba5e
AG		 1408 n = 2 + (s->smart_selftest_count - 1) * 24;
1409 s->smart_selftest_data[n] = s->sector;
1410 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1411 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1412 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1413 s->status = READY_STAT | SEEK_STAT;
1414 ide_set_irq(s->bus);
1415 break;
e8b54394 1416 default:
6ef2ba5e 1417 goto abort_cmd;
e8b54394
BW		 1418 }
1419 break;
6ef2ba5e 1420 default:
e8b54394 1421 goto abort_cmd;
6ef2ba5e
AG		 1422 }
1423 break;
1424 default:
1425 abort_cmd:
1426 ide_abort_command(s);
1427 ide_set_irq(s->bus);
1428 break;
1429 }
5391d806
FB		 1430}
1431
356721ae 1432uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1433{
bcbdc4d3
GH		 1434 IDEBus *bus = opaque;
1435 IDEState *s = idebus_active_if(bus);
5391d806 1436 uint32_t addr;
c2ff060f 1437 int ret, hob;
5391d806
FB		 1438
1439 addr = addr1 & 7;
c2ff060f
FB		 1440 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1441 //hob = s->select & (1 << 7);
1442 hob = 0;
5391d806
FB		 1443 switch(addr) {
1444 case 0:
1445 ret = 0xff;
1446 break;
1447 case 1:
bcbdc4d3
GH		 1448 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1449 (s != bus->ifs && !s->bs))
c45c3d00 1450 ret = 0;
c2ff060f 1451 else if (!hob)
c45c3d00 1452 ret = s->error;
c2ff060f
FB		 1453 else
1454 ret = s->hob_feature;
5391d806
FB		 1455 break;
1456 case 2:
bcbdc4d3 1457 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1458 ret = 0;
c2ff060f 1459 else if (!hob)
c45c3d00 1460 ret = s->nsector & 0xff;
c2ff060f
FB		 1461 else
1462 ret = s->hob_nsector;
5391d806
FB		 1463 break;
1464 case 3:
bcbdc4d3 1465 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1466 ret = 0;
c2ff060f 1467 else if (!hob)
c45c3d00 1468 ret = s->sector;
c2ff060f
FB		 1469 else
1470 ret = s->hob_sector;
5391d806
FB		 1471 break;
1472 case 4:
bcbdc4d3 1473 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1474 ret = 0;
c2ff060f 1475 else if (!hob)
c45c3d00 1476 ret = s->lcyl;
c2ff060f
FB		 1477 else
1478 ret = s->hob_lcyl;
5391d806
FB		 1479 break;
1480 case 5:
bcbdc4d3 1481 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1482 ret = 0;
c2ff060f 1483 else if (!hob)
c45c3d00 1484 ret = s->hcyl;
c2ff060f
FB		 1485 else
1486 ret = s->hob_hcyl;
5391d806
FB		 1487 break;
1488 case 6:
bcbdc4d3 1489 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00
FB		 1490 ret = 0;
1491 else
7ae98627 1492 ret = s->select;
5391d806
FB		 1493 break;
1494 default:
1495 case 7:
bcbdc4d3
GH		 1496 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1497 (s != bus->ifs && !s->bs))
c45c3d00
FB		 1498 ret = 0;
1499 else
1500 ret = s->status;
9cdd03a7 1501 qemu_irq_lower(bus->irq);
5391d806
FB		 1502 break;
1503 }
1504#ifdef DEBUG_IDE
1505 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1506#endif
1507 return ret;
1508}
1509
356721ae 1510uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1511{
bcbdc4d3
GH		 1512 IDEBus *bus = opaque;
1513 IDEState *s = idebus_active_if(bus);
5391d806 1514 int ret;
7ae98627 1515
bcbdc4d3
GH		 1516 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1517 (s != bus->ifs && !s->bs))
7ae98627
FB		 1518 ret = 0;
1519 else
1520 ret = s->status;
5391d806
FB		 1521#ifdef DEBUG_IDE
1522 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1523#endif
1524 return ret;
1525}
1526
356721ae 1527void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1528{
bcbdc4d3 1529 IDEBus *bus = opaque;
5391d806
FB		 1530 IDEState *s;
1531 int i;
1532
1533#ifdef DEBUG_IDE
1534 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1535#endif
1536 /* common for both drives */
9cdd03a7 1537 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1538 (val & IDE_CMD_RESET)) {
1539 /* reset low to high */
1540 for(i = 0;i < 2; i++) {
bcbdc4d3 1541 s = &bus->ifs[i];
5391d806
FB		 1542 s->status = BUSY_STAT | SEEK_STAT;
1543 s->error = 0x01;
1544 }
9cdd03a7 1545 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1546 !(val & IDE_CMD_RESET)) {
1547 /* high to low */
1548 for(i = 0;i < 2; i++) {
bcbdc4d3 1549 s = &bus->ifs[i];
cd8722bb 1550 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1551 s->status = 0x00; /* NOTE: READY is _not_ set */
1552 else
56bf1d37 1553 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1554 ide_set_signature(s);
1555 }
1556 }
1557
9cdd03a7 1558 bus->cmd = val;
5391d806
FB		 1559}
1560
40c4ed3f
KW		 1561/*
1562 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1563 * transferred from the device to the guest), false if it's a PIO in
1564 */
1565static bool ide_is_pio_out(IDEState *s)
1566{
1567 if (s->end_transfer_func == ide_sector_write ||
1568 s->end_transfer_func == ide_atapi_cmd) {
1569 return false;
1570 } else if (s->end_transfer_func == ide_sector_read ||
1571 s->end_transfer_func == ide_transfer_stop ||
1572 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1573 s->end_transfer_func == ide_dummy_transfer_stop) {
1574 return true;
1575 }
1576
1577 abort();
1578}
1579
356721ae 1580void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 1581{
bcbdc4d3
GH		 1582 IDEBus *bus = opaque;
1583 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1584 uint8_t *p;
1585
40c4ed3f
KW		 1586 /* PIO data access allowed only when DRQ bit is set. The result of a write
1587 * during PIO out is indeterminate, just ignore it. */
1588 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1589 return;
40c4ed3f 1590 }
fcdd25ab 1591
5391d806 1592 p = s->data_ptr;
0c4ad8dc 1593 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 1594 p += 2;
1595 s->data_ptr = p;
1596 if (p >= s->data_end)
1597 s->end_transfer_func(s);
1598}
1599
356721ae 1600uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 1601{
bcbdc4d3
GH		 1602 IDEBus *bus = opaque;
1603 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1604 uint8_t *p;
1605 int ret;
fcdd25ab 1606
40c4ed3f
KW		 1607 /* PIO data access allowed only when DRQ bit is set. The result of a read
1608 * during PIO in is indeterminate, return 0 and don't move forward. */
1609 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1610 return 0;
40c4ed3f 1611 }
fcdd25ab 1612
5391d806 1613 p = s->data_ptr;
0c4ad8dc 1614 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 1615 p += 2;
1616 s->data_ptr = p;
1617 if (p >= s->data_end)
1618 s->end_transfer_func(s);
1619 return ret;
1620}
1621
356721ae 1622void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 1623{
bcbdc4d3
GH		 1624 IDEBus *bus = opaque;
1625 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1626 uint8_t *p;
1627
40c4ed3f
KW		 1628 /* PIO data access allowed only when DRQ bit is set. The result of a write
1629 * during PIO out is indeterminate, just ignore it. */
1630 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1631 return;
40c4ed3f 1632 }
fcdd25ab 1633
5391d806 1634 p = s->data_ptr;
0c4ad8dc 1635 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 1636 p += 4;
1637 s->data_ptr = p;
1638 if (p >= s->data_end)
1639 s->end_transfer_func(s);
1640}
1641
356721ae 1642uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 1643{
bcbdc4d3
GH		 1644 IDEBus *bus = opaque;
1645 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1646 uint8_t *p;
1647 int ret;
3b46e624 1648
40c4ed3f
KW		 1649 /* PIO data access allowed only when DRQ bit is set. The result of a read
1650 * during PIO in is indeterminate, return 0 and don't move forward. */
1651 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1652 return 0;
40c4ed3f 1653 }
fcdd25ab 1654
5391d806 1655 p = s->data_ptr;
0c4ad8dc 1656 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 1657 p += 4;
1658 s->data_ptr = p;
1659 if (p >= s->data_end)
1660 s->end_transfer_func(s);
1661 return ret;
1662}
1663
a7dfe172
FB		 1664static void ide_dummy_transfer_stop(IDEState *s)
1665{
1666 s->data_ptr = s->io_buffer;
1667 s->data_end = s->io_buffer;
1668 s->io_buffer[0] = 0xff;
1669 s->io_buffer[1] = 0xff;
1670 s->io_buffer[2] = 0xff;
1671 s->io_buffer[3] = 0xff;
1672}
1673
4a643563 1674static void ide_reset(IDEState *s)
5391d806 1675{
4a643563
BS		 1676#ifdef DEBUG_IDE
1677 printf("ide: reset\n");
1678#endif
cd8722bb 1679 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 1680 s->mult_sectors = 0;
1681 else
1682 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 1683 /* ide regs */
1684 s->feature = 0;
1685 s->error = 0;
1686 s->nsector = 0;
1687 s->sector = 0;
1688 s->lcyl = 0;
1689 s->hcyl = 0;
1690
1691 /* lba48 */
1692 s->hob_feature = 0;
1693 s->hob_sector = 0;
1694 s->hob_nsector = 0;
1695 s->hob_lcyl = 0;
1696 s->hob_hcyl = 0;
1697
5391d806 1698 s->select = 0xa0;
41a2b959 1699 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 1700
1701 s->lba48 = 0;
1702
1703 /* ATAPI specific */
1704 s->sense_key = 0;
1705 s->asc = 0;
1706 s->cdrom_changed = 0;
1707 s->packet_transfer_size = 0;
1708 s->elementary_transfer_size = 0;
1709 s->io_buffer_index = 0;
1710 s->cd_sector_size = 0;
1711 s->atapi_dma = 0;
1712 /* ATA DMA state */
1713 s->io_buffer_size = 0;
1714 s->req_nb_sectors = 0;
1715
5391d806 1716 ide_set_signature(s);
a7dfe172
FB		 1717 /* init the transfer handler so that 0xffff is returned on data
1718 accesses */
1719 s->end_transfer_func = ide_dummy_transfer_stop;
1720 ide_dummy_transfer_stop(s);
201a51fc 1721 s->media_changed = 0;
5391d806
FB		 1722}
1723
4a643563
BS		 1724void ide_bus_reset(IDEBus *bus)
1725{
1726 bus->unit = 0;
1727 bus->cmd = 0;
1728 ide_reset(&bus->ifs[0]);
1729 ide_reset(&bus->ifs[1]);
1730 ide_clear_hob(bus);
40a6238a
AG		 1731
1732 /* pending async DMA */
1733 if (bus->dma->aiocb) {
1734#ifdef DEBUG_AIO
1735 printf("aio_cancel\n");
1736#endif
1737 bdrv_aio_cancel(bus->dma->aiocb);
1738 bus->dma->aiocb = NULL;
1739 }
1740
1741 /* reset dma provider too */
1742 bus->dma->ops->reset(bus->dma);
4a643563
BS		 1743}
1744
1f56e32a 1745int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
c4d74df7 1746 const char *version, const char *serial)
88804180
GH		 1747{
1748 int cylinders, heads, secs;
1749 uint64_t nb_sectors;
1750
f8b6cc00 1751 s->bs = bs;
1f56e32a
MA		 1752 s->drive_kind = kind;
1753
f8b6cc00
MA		 1754 bdrv_get_geometry(bs, &nb_sectors);
1755 bdrv_guess_geometry(bs, &cylinders, &heads, &secs);
dce9e928
MA		 1756 if (cylinders < 1 || cylinders > 16383) {
1757 error_report("cyls must be between 1 and 16383");
1758 return -1;
1759 }
1760 if (heads < 1 || heads > 16) {
1761 error_report("heads must be between 1 and 16");
1762 return -1;
1763 }
1764 if (secs < 1 || secs > 63) {
1765 error_report("secs must be between 1 and 63");
1766 return -1;
1767 }
870111c8
MA		 1768 s->cylinders = cylinders;
1769 s->heads = heads;
1770 s->sectors = secs;
1771 s->nb_sectors = nb_sectors;
1772 /* The SMART values should be preserved across power cycles
1773 but they aren't. */
1774 s->smart_enabled = 1;
1775 s->smart_autosave = 1;
1776 s->smart_errors = 0;
1777 s->smart_selftest_count = 0;
1f56e32a 1778 if (kind == IDE_CD) {
f8b6cc00 1779 bdrv_set_change_cb(bs, cdrom_change_cb, s);
1b2adf28 1780 bs->buffer_alignment = 2048;
7aa9c811 1781 } else {
98f28ad7
MA		 1782 if (!bdrv_is_inserted(s->bs)) {
1783 error_report("Device needs media, but drive is empty");
1784 return -1;
1785 }
7aa9c811
MA		 1786 if (bdrv_is_read_only(bs)) {
1787 error_report("Can't use a read-only drive");
1788 return -1;
1789 }
88804180 1790 }
f8b6cc00 1791 if (serial) {
6ced55a5
MA		 1792 strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str));
1793 } else {
88804180
GH		 1794 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1795 "QM%05d", s->drive_serial);
870111c8 1796 }
47c06340
GH		 1797 if (version) {
1798 pstrcpy(s->version, sizeof(s->version), version);
1799 } else {
1800 pstrcpy(s->version, sizeof(s->version), QEMU_VERSION);
1801 }
40a6238a 1802
88804180 1803 ide_reset(s);
cd8722bb 1804 bdrv_set_removable(bs, s->drive_kind == IDE_CD);
c4d74df7 1805 return 0;
88804180
GH		 1806}
1807
57234ee4 1808static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 1809{
1810 static int drive_serial = 1;
1811 IDEState *s = &bus->ifs[unit];
1812
1813 s->bus = bus;
1814 s->unit = unit;
1815 s->drive_serial = drive_serial++;
1b2adf28 1816 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 1817 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 1818 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
1819 memset(s->io_buffer, 0, s->io_buffer_total_len);
1820
d459da0e 1821 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
c925400b
KW		 1822 memset(s->smart_selftest_data, 0, 512);
1823
74475455 1824 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
d459da0e 1825 ide_sector_write_timer_cb, s);
57234ee4
MA		 1826}
1827
40a6238a
AG		 1828static void ide_nop_start(IDEDMA *dma, IDEState *s,
1829 BlockDriverCompletionFunc *cb)
1830{
1831}
1832
1833static int ide_nop(IDEDMA *dma)
1834{
1835 return 0;
1836}
1837
1838static int ide_nop_int(IDEDMA *dma, int x)
1839{
1840 return 0;
1841}
1842
1843static void ide_nop_restart(void *opaque, int x, int y)
1844{
1845}
1846
1847static const IDEDMAOps ide_dma_nop_ops = {
1848 .start_dma = ide_nop_start,
1849 .start_transfer = ide_nop,
1850 .prepare_buf = ide_nop_int,
1851 .rw_buf = ide_nop_int,
1852 .set_unit = ide_nop_int,
1853 .add_status = ide_nop_int,
1854 .set_inactive = ide_nop,
1855 .restart_cb = ide_nop_restart,
1856 .reset = ide_nop,
1857};
1858
1859static IDEDMA ide_dma_nop = {
1860 .ops = &ide_dma_nop_ops,
1861 .aiocb = NULL,
1862};
1863
57234ee4
MA		 1864void ide_init2(IDEBus *bus, qemu_irq irq)
1865{
1866 int i;
1867
1868 for(i = 0; i < 2; i++) {
1869 ide_init1(bus, i);
1870 ide_reset(&bus->ifs[i]);
870111c8 1871 }
57234ee4 1872 bus->irq = irq;
40a6238a 1873 bus->dma = &ide_dma_nop;
d459da0e
MA		 1874}
1875
57234ee4
MA		 1876/* TODO convert users to qdev and remove */
1877void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
1878 DriveInfo *hd1, qemu_irq irq)
5391d806 1879{
88804180 1880 int i;
57234ee4 1881 DriveInfo *dinfo;
5391d806 1882
caed8802 1883 for(i = 0; i < 2; i++) {
57234ee4
MA		 1884 dinfo = i == 0 ? hd0 : hd1;
1885 ide_init1(bus, i);
1886 if (dinfo) {
1f56e32a 1887 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
95b5edcd 1888 dinfo->media_cd ? IDE_CD : IDE_HD, NULL,
c4d74df7
MA		 1889 *dinfo->serial ? dinfo->serial : NULL) < 0) {
1890 error_report("Can't set up IDE drive %s", dinfo->id);
1891 exit(1);
1892 }
57234ee4
MA		 1893 } else {
1894 ide_reset(&bus->ifs[i]);
1895 }
5391d806 1896 }
9cdd03a7 1897 bus->irq = irq;
40a6238a 1898 bus->dma = &ide_dma_nop;
69b91039
FB		 1899}
1900
356721ae 1901void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
69b91039 1902{
bcbdc4d3
GH		 1903 register_ioport_write(iobase, 8, 1, ide_ioport_write, bus);
1904 register_ioport_read(iobase, 8, 1, ide_ioport_read, bus);
caed8802 1905 if (iobase2) {
bcbdc4d3
GH		 1906 register_ioport_read(iobase2, 1, 1, ide_status_read, bus);
1907 register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus);
5391d806 1908 }
3b46e624 1909
caed8802 1910 /* data ports */
bcbdc4d3
GH		 1911 register_ioport_write(iobase, 2, 2, ide_data_writew, bus);
1912 register_ioport_read(iobase, 2, 2, ide_data_readw, bus);
1913 register_ioport_write(iobase, 4, 4, ide_data_writel, bus);
1914 register_ioport_read(iobase, 4, 4, ide_data_readl, bus);
5391d806 1915}
69b91039 1916
37159f13 1917static bool is_identify_set(void *opaque, int version_id)
aa941b94 1918{
37159f13
JQ		 1919 IDEState *s = opaque;
1920
1921 return s->identify_set != 0;
1922}
1923
50641c5c
JQ		 1924static EndTransferFunc* transfer_end_table[] = {
1925 ide_sector_read,
1926 ide_sector_write,
1927 ide_transfer_stop,
1928 ide_atapi_cmd_reply_end,
1929 ide_atapi_cmd,
1930 ide_dummy_transfer_stop,
1931};
1932
1933static int transfer_end_table_idx(EndTransferFunc *fn)
1934{
1935 int i;
1936
1937 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
1938 if (transfer_end_table[i] == fn)
1939 return i;
1940
1941 return -1;
1942}
1943
37159f13 1944static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 1945{
37159f13
JQ		 1946 IDEState *s = opaque;
1947
1948 if (version_id < 3) {
93c8cfd9 1949 if (s->sense_key == SENSE_UNIT_ATTENTION &&
37159f13 1950 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) {
93c8cfd9 1951 s->cdrom_changed = 1;
37159f13 1952 }
93c8cfd9 1953 }
37159f13 1954 return 0;
aa941b94
AZ		 1955}
1956
50641c5c
JQ		 1957static int ide_drive_pio_post_load(void *opaque, int version_id)
1958{
1959 IDEState *s = opaque;
1960
7bccf573 1961 if (s->end_transfer_fn_idx > ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 1962 return -EINVAL;
1963 }
1964 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
1965 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
1966 s->data_end = s->data_ptr + s->cur_io_buffer_len;
1967
1968 return 0;
1969}
1970
1971static void ide_drive_pio_pre_save(void *opaque)
1972{
1973 IDEState *s = opaque;
1974 int idx;
1975
1976 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
1977 s->cur_io_buffer_len = s->data_end - s->data_ptr;
1978
1979 idx = transfer_end_table_idx(s->end_transfer_func);
1980 if (idx == -1) {
1981 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
1982 __func__);
1983 s->end_transfer_fn_idx = 2;
1984 } else {
1985 s->end_transfer_fn_idx = idx;
1986 }
1987}
1988
1989static bool ide_drive_pio_state_needed(void *opaque)
1990{
1991 IDEState *s = opaque;
1992
fdc650d7
KW		 1993 return ((s->status & DRQ_STAT) != 0)
1994 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
50641c5c
JQ		 1995}
1996
996faf1a
AS		 1997static bool ide_atapi_gesn_needed(void *opaque)
1998{
1999 IDEState *s = opaque;
2000
2001 return s->events.new_media || s->events.eject_request;
2002}
2003
def93791
KW		 2004static bool ide_error_needed(void *opaque)
2005{
2006 IDEBus *bus = opaque;
2007
2008 return (bus->error_status != 0);
2009}
2010
996faf1a
AS		 2011/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2012const VMStateDescription vmstate_ide_atapi_gesn_state = {
2013 .name ="ide_drive/atapi/gesn_state",
2014 .version_id = 1,
2015 .minimum_version_id = 1,
2016 .minimum_version_id_old = 1,
2017 .fields = (VMStateField []) {
2018 VMSTATE_BOOL(events.new_media, IDEState),
2019 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2020 VMSTATE_END_OF_LIST()
996faf1a
AS		 2021 }
2022};
2023
50641c5c
JQ		 2024const VMStateDescription vmstate_ide_drive_pio_state = {
2025 .name = "ide_drive/pio_state",
2026 .version_id = 1,
2027 .minimum_version_id = 1,
2028 .minimum_version_id_old = 1,
2029 .pre_save = ide_drive_pio_pre_save,
2030 .post_load = ide_drive_pio_post_load,
2031 .fields = (VMStateField []) {
2032 VMSTATE_INT32(req_nb_sectors, IDEState),
2033 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2034 vmstate_info_uint8, uint8_t),
2035 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2036 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2037 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2038 VMSTATE_INT32(elementary_transfer_size, IDEState),
2039 VMSTATE_INT32(packet_transfer_size, IDEState),
2040 VMSTATE_END_OF_LIST()
2041 }
2042};
2043
37159f13
JQ		 2044const VMStateDescription vmstate_ide_drive = {
2045 .name = "ide_drive",
3abb6260 2046 .version_id = 3,
37159f13
JQ		 2047 .minimum_version_id = 0,
2048 .minimum_version_id_old = 0,
2049 .post_load = ide_drive_post_load,
2050 .fields = (VMStateField []) {
2051 VMSTATE_INT32(mult_sectors, IDEState),
2052 VMSTATE_INT32(identify_set, IDEState),
2053 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2054 VMSTATE_UINT8(feature, IDEState),
2055 VMSTATE_UINT8(error, IDEState),
2056 VMSTATE_UINT32(nsector, IDEState),
2057 VMSTATE_UINT8(sector, IDEState),
2058 VMSTATE_UINT8(lcyl, IDEState),
2059 VMSTATE_UINT8(hcyl, IDEState),
2060 VMSTATE_UINT8(hob_feature, IDEState),
2061 VMSTATE_UINT8(hob_sector, IDEState),
2062 VMSTATE_UINT8(hob_nsector, IDEState),
2063 VMSTATE_UINT8(hob_lcyl, IDEState),
2064 VMSTATE_UINT8(hob_hcyl, IDEState),
2065 VMSTATE_UINT8(select, IDEState),
2066 VMSTATE_UINT8(status, IDEState),
2067 VMSTATE_UINT8(lba48, IDEState),
2068 VMSTATE_UINT8(sense_key, IDEState),
2069 VMSTATE_UINT8(asc, IDEState),
2070 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2071 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2072 },
2073 .subsections = (VMStateSubsection []) {
2074 {
2075 .vmsd = &vmstate_ide_drive_pio_state,
2076 .needed = ide_drive_pio_state_needed,
996faf1a
AS		 2077 }, {
2078 .vmsd = &vmstate_ide_atapi_gesn_state,
2079 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2080 }, {
2081 /* empty */
2082 }
37159f13
JQ		 2083 }
2084};
2085
def93791
KW		 2086const VMStateDescription vmstate_ide_error_status = {
2087 .name ="ide_bus/error",
2088 .version_id = 1,
2089 .minimum_version_id = 1,
2090 .minimum_version_id_old = 1,
2091 .fields = (VMStateField []) {
2092 VMSTATE_INT32(error_status, IDEBus),
2093 VMSTATE_END_OF_LIST()
2094 }
2095};
2096
6521dc62
JQ		 2097const VMStateDescription vmstate_ide_bus = {
2098 .name = "ide_bus",
2099 .version_id = 1,
2100 .minimum_version_id = 1,
2101 .minimum_version_id_old = 1,
2102 .fields = (VMStateField []) {
2103 VMSTATE_UINT8(cmd, IDEBus),
2104 VMSTATE_UINT8(unit, IDEBus),
2105 VMSTATE_END_OF_LIST()
def93791
KW		 2106 },
2107 .subsections = (VMStateSubsection []) {
2108 {
2109 .vmsd = &vmstate_ide_error_status,
2110 .needed = ide_error_needed,
2111 }, {
2112 /* empty */
2113 }
6521dc62
JQ		 2114 }
2115};
75717903
IY		 2116
2117void ide_drive_get(DriveInfo **hd, int max_bus)
2118{
2119 int i;
2120
2121 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2122 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2123 exit(1);
2124 }
2125
2126 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2127 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2128 }
2129}
Qemu copy for testing