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scsi-disk: Fix START_STOP to fail when it can't eject
[qemu.git] / hw / ide / core.c
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5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787
GH		 25#include <hw/hw.h>
26#include <hw/pc.h>
27#include <hw/pci.h>
c4d74df7 28#include "qemu-error.h"
87ecb68b
PB		 29#include "qemu-timer.h"
30#include "sysemu.h"
1fb8648d 31#include "dma.h"
2446333c 32#include "blockdev.h"
59f2a787
GH		 33
34#include <hw/ide/internal.h>
e8b54394 35
b93af93d
BW		 36/* These values were based on a Seagate ST3500418AS but have been modified
37 to make more sense in QEMU */
38static const int smart_attributes[][12] = {
39 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
40 /* raw read error rate*/
41 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
42 /* spin up */
43 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
44 /* start stop count */
45 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
46 /* remapped sectors */
47 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
48 /* power on hours */
49 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
50 /* power cycle count */
51 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* airflow-temperature-celsius */
53 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
54 /* end of list */
55 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
5391d806
FB		 78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
d353fb72 82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 83
94458802
FB		 84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
5391d806
FB		 89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
67b915a5 91 put_le16(p + 0, 0x0040);
5fafdf24 92 put_le16(p + 1, s->cylinders);
67b915a5
FB		 93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 96 put_le16(p + 6, s->sectors);
fa879c64 97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
47c06340 101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
60fe76f3 102 padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */
3b46e624 103#if MAX_MULT_SECTORS > 1
67b915a5 104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 105#endif
67b915a5 106 put_le16(p + 48, 1); /* dword I/O */
94458802 107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
5391d806 114 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
5391d806 117 if (s->mult_sectors)
67b915a5
FB		 118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
d1b5c20d 121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 123 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
d353fb72
CH		 128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
ccf0fd8b
RE		 131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
94458802
FB		 138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
e8b54394
BW		 144 /* 14=set to 1, 1=SMART self test, 0=SMART error logging */
145 put_le16(p + 84, (1 << 14) | 0);
e900a7b7
CH		 146 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
147 if (bdrv_enable_write_cache(s->bs))
148 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
149 else
150 put_le16(p + 85, (1 << 14) | 1);
c2ff060f
FB		 151 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
152 put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
e8b54394
BW		 153 /* 14=set to 1, 1=smart self test, 0=smart error logging */
154 put_le16(p + 87, (1 << 14) | 0);
94458802
FB		 155 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
156 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
c2ff060f
FB		 157 put_le16(p + 100, s->nb_sectors);
158 put_le16(p + 101, s->nb_sectors >> 16);
159 put_le16(p + 102, s->nb_sectors >> 32);
160 put_le16(p + 103, s->nb_sectors >> 48);
d353fb72 161
57dac7ef
MA		 162 if (dev && dev->conf.physical_block_size)
163 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
d353fb72
CH		 164 if (dev && dev->conf.discard_granularity) {
165 put_le16(p + 169, 1); /* TRIM support */
166 }
94458802
FB		 167
168 memcpy(s->identify_data, p, sizeof(s->identify_data));
169 s->identify_set = 1;
5391d806
FB		 170}
171
172static void ide_atapi_identify(IDEState *s)
173{
174 uint16_t *p;
175
94458802
FB		 176 if (s->identify_set) {
177 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
178 return;
179 }
180
5391d806
FB		 181 memset(s->io_buffer, 0, 512);
182 p = (uint16_t *)s->io_buffer;
183 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 184 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 185 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 186 put_le16(p + 20, 3); /* buffer type */
187 put_le16(p + 21, 512); /* cache size in sectors */
188 put_le16(p + 22, 4); /* ecc bytes */
47c06340 189 padstr((char *)(p + 23), s->version, 8); /* firmware version */
38cdea7c 190 padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */
67b915a5 191 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 192#ifdef USE_DMA_CDROM
193 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
194 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 195 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 196 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 197#else
67b915a5
FB		 198 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
199 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
200 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 201#endif
79d1d331 202 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 203 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
204 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
205 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
206 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 207
67b915a5
FB		 208 put_le16(p + 71, 30); /* in ns */
209 put_le16(p + 72, 30); /* in ns */
5391d806 210
1bdaa28d
AG		 211 if (s->ncq_queues) {
212 put_le16(p + 75, s->ncq_queues - 1);
213 /* NCQ supported */
214 put_le16(p + 76, (1 << 8));
215 }
216
67b915a5 217 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
8ccad811
FB		 218#ifdef USE_DMA_CDROM
219 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
220#endif
94458802
FB		 221 memcpy(s->identify_data, p, sizeof(s->identify_data));
222 s->identify_set = 1;
5391d806
FB		 223}
224
201a51fc
AZ		 225static void ide_cfata_identify(IDEState *s)
226{
227 uint16_t *p;
228 uint32_t cur_sec;
201a51fc
AZ		 229
230 p = (uint16_t *) s->identify_data;
231 if (s->identify_set)
232 goto fill_buffer;
233
234 memset(p, 0, sizeof(s->identify_data));
235
236 cur_sec = s->cylinders * s->heads * s->sectors;
237
238 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
239 put_le16(p + 1, s->cylinders); /* Default cylinders */
240 put_le16(p + 3, s->heads); /* Default heads */
241 put_le16(p + 6, s->sectors); /* Default sectors per track */
242 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
243 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
fa879c64 244 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 245 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 246 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
60fe76f3 247 padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
201a51fc
AZ		 248#if MAX_MULT_SECTORS > 1
249 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
250#else
251 put_le16(p + 47, 0x0000);
252#endif
253 put_le16(p + 49, 0x0f00); /* Capabilities */
254 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
255 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
256 put_le16(p + 53, 0x0003); /* Translation params valid */
257 put_le16(p + 54, s->cylinders); /* Current cylinders */
258 put_le16(p + 55, s->heads); /* Current heads */
259 put_le16(p + 56, s->sectors); /* Current sectors */
260 put_le16(p + 57, cur_sec); /* Current capacity */
261 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
262 if (s->mult_sectors) /* Multiple sector setting */
263 put_le16(p + 59, 0x100 | s->mult_sectors);
264 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
265 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
266 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
267 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
268 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
269 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
270 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
271 put_le16(p + 82, 0x400c); /* Command Set supported */
272 put_le16(p + 83, 0x7068); /* Command Set supported */
273 put_le16(p + 84, 0x4000); /* Features supported */
274 put_le16(p + 85, 0x000c); /* Command Set enabled */
275 put_le16(p + 86, 0x7044); /* Command Set enabled */
276 put_le16(p + 87, 0x4000); /* Features enabled */
277 put_le16(p + 91, 0x4060); /* Current APM level */
278 put_le16(p + 129, 0x0002); /* Current features option */
279 put_le16(p + 130, 0x0005); /* Reassigned sectors */
280 put_le16(p + 131, 0x0001); /* Initial power mode */
281 put_le16(p + 132, 0x0000); /* User signature */
282 put_le16(p + 160, 0x8100); /* Power requirement */
283 put_le16(p + 161, 0x8001); /* CF command set */
284
285 s->identify_set = 1;
286
287fill_buffer:
288 memcpy(s->io_buffer, p, sizeof(s->identify_data));
289}
290
5391d806
FB		 291static void ide_set_signature(IDEState *s)
292{
293 s->select &= 0xf0; /* clear head */
294 /* put signature */
295 s->nsector = 1;
296 s->sector = 1;
cd8722bb 297 if (s->drive_kind == IDE_CD) {
5391d806
FB		 298 s->lcyl = 0x14;
299 s->hcyl = 0xeb;
300 } else if (s->bs) {
301 s->lcyl = 0;
302 s->hcyl = 0;
303 } else {
304 s->lcyl = 0xff;
305 s->hcyl = 0xff;
306 }
307}
308
d353fb72
CH		 309typedef struct TrimAIOCB {
310 BlockDriverAIOCB common;
311 QEMUBH *bh;
312 int ret;
313} TrimAIOCB;
314
315static void trim_aio_cancel(BlockDriverAIOCB *acb)
316{
317 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
318
319 qemu_bh_delete(iocb->bh);
320 iocb->bh = NULL;
321 qemu_aio_release(iocb);
322}
323
324static AIOPool trim_aio_pool = {
325 .aiocb_size = sizeof(TrimAIOCB),
326 .cancel = trim_aio_cancel,
327};
328
329static void ide_trim_bh_cb(void *opaque)
330{
331 TrimAIOCB *iocb = opaque;
332
333 iocb->common.cb(iocb->common.opaque, iocb->ret);
334
335 qemu_bh_delete(iocb->bh);
336 iocb->bh = NULL;
337
338 qemu_aio_release(iocb);
339}
340
341BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
342 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
343 BlockDriverCompletionFunc *cb, void *opaque)
344{
345 TrimAIOCB *iocb;
346 int i, j, ret;
347
348 iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque);
349 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
350 iocb->ret = 0;
351
352 for (j = 0; j < qiov->niov; j++) {
353 uint64_t *buffer = qiov->iov[j].iov_base;
354
355 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
356 /* 6-byte LBA + 2-byte range per entry */
357 uint64_t entry = le64_to_cpu(buffer[i]);
358 uint64_t sector = entry & 0x0000ffffffffffffULL;
359 uint16_t count = entry >> 48;
360
361 if (count == 0) {
362 break;
363 }
364
365 ret = bdrv_discard(bs, sector, count);
366 if (!iocb->ret) {
367 iocb->ret = ret;
368 }
369 }
370 }
371
372 qemu_bh_schedule(iocb->bh);
373
374 return &iocb->common;
375}
376
5391d806
FB		 377static inline void ide_abort_command(IDEState *s)
378{
379 s->status = READY_STAT | ERR_STAT;
380 s->error = ABRT_ERR;
381}
382
5391d806 383/* prepare data transfer and tell what to do after */
33231e0e
KW		 384void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
385 EndTransferFunc *end_transfer_func)
5391d806
FB		 386{
387 s->end_transfer_func = end_transfer_func;
388 s->data_ptr = buf;
389 s->data_end = buf + size;
40a6238a 390 if (!(s->status & ERR_STAT)) {
7603d156 391 s->status |= DRQ_STAT;
40a6238a
AG		 392 }
393 s->bus->dma->ops->start_transfer(s->bus->dma);
5391d806
FB		 394}
395
33231e0e 396void ide_transfer_stop(IDEState *s)
5391d806
FB		 397{
398 s->end_transfer_func = ide_transfer_stop;
399 s->data_ptr = s->io_buffer;
400 s->data_end = s->io_buffer;
401 s->status &= ~DRQ_STAT;
402}
403
356721ae 404int64_t ide_get_sector(IDEState *s)
5391d806
FB		 405{
406 int64_t sector_num;
407 if (s->select & 0x40) {
408 /* lba */
c2ff060f
FB		 409 if (!s->lba48) {
410 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
411 (s->lcyl << 8) | s->sector;
412 } else {
413 sector_num = ((int64_t)s->hob_hcyl << 40) |
414 ((int64_t) s->hob_lcyl << 32) |
415 ((int64_t) s->hob_sector << 24) |
416 ((int64_t) s->hcyl << 16) |
417 ((int64_t) s->lcyl << 8) | s->sector;
418 }
5391d806
FB		 419 } else {
420 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 421 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 422 }
423 return sector_num;
424}
425
356721ae 426void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 427{
428 unsigned int cyl, r;
429 if (s->select & 0x40) {
c2ff060f
FB		 430 if (!s->lba48) {
431 s->select = (s->select & 0xf0) | (sector_num >> 24);
432 s->hcyl = (sector_num >> 16);
433 s->lcyl = (sector_num >> 8);
434 s->sector = (sector_num);
435 } else {
436 s->sector = sector_num;
437 s->lcyl = sector_num >> 8;
438 s->hcyl = sector_num >> 16;
439 s->hob_sector = sector_num >> 24;
440 s->hob_lcyl = sector_num >> 32;
441 s->hob_hcyl = sector_num >> 40;
442 }
5391d806
FB		 443 } else {
444 cyl = sector_num / (s->heads * s->sectors);
445 r = sector_num % (s->heads * s->sectors);
446 s->hcyl = cyl >> 8;
447 s->lcyl = cyl;
1b8eb456 448 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 449 s->sector = (r % s->sectors) + 1;
450 }
451}
452
e162cfb0
AZ		 453static void ide_rw_error(IDEState *s) {
454 ide_abort_command(s);
9cdd03a7 455 ide_set_irq(s->bus);
e162cfb0
AZ		 456}
457
40a6238a 458void ide_sector_read(IDEState *s)
5391d806
FB		 459{
460 int64_t sector_num;
461 int ret, n;
462
463 s->status = READY_STAT | SEEK_STAT;
a136e5a8 464 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 465 sector_num = ide_get_sector(s);
466 n = s->nsector;
467 if (n == 0) {
468 /* no more sector to read from disk */
469 ide_transfer_stop(s);
470 } else {
471#if defined(DEBUG_IDE)
18c5f8ea 472 printf("read sector=%" PRId64 "\n", sector_num);
5391d806
FB		 473#endif
474 if (n > s->req_nb_sectors)
475 n = s->req_nb_sectors;
a597e79c
CH		 476
477 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
5391d806 478 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
a597e79c 479 bdrv_acct_done(s->bs, &s->acct);
e162cfb0 480 if (ret != 0) {
ce4b6522
KW		 481 if (ide_handle_rw_error(s, -ret,
482 BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ))
483 {
484 return;
485 }
e162cfb0 486 }
5391d806 487 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
9cdd03a7 488 ide_set_irq(s->bus);
5391d806
FB		 489 ide_set_sector(s, sector_num + n);
490 s->nsector -= n;
491 }
492}
493
7aea4412
AL		 494static void dma_buf_commit(IDEState *s, int is_write)
495{
1fb8648d 496 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 497}
498
33231e0e 499void ide_set_inactive(IDEState *s)
8337606d 500{
40a6238a
AG		 501 s->bus->dma->aiocb = NULL;
502 s->bus->dma->ops->set_inactive(s->bus->dma);
8337606d
KW		 503}
504
356721ae 505void ide_dma_error(IDEState *s)
e162cfb0
AZ		 506{
507 ide_transfer_stop(s);
508 s->error = ABRT_ERR;
509 s->status = READY_STAT | ERR_STAT;
40a6238a 510 ide_set_inactive(s);
9cdd03a7 511 ide_set_irq(s->bus);
e162cfb0
AZ		 512}
513
ce4b6522 514static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 515{
ce4b6522 516 int is_read = (op & BM_STATUS_RETRY_READ);
abd7f68d 517 BlockErrorAction action = bdrv_get_on_error(s->bs, is_read);
428c5705 518
7ad7e3c3
LC		 519 if (action == BLOCK_ERR_IGNORE) {
520 bdrv_mon_event(s->bs, BDRV_ACTION_IGNORE, is_read);
428c5705 521 return 0;
7ad7e3c3 522 }
428c5705
AL		 523
524 if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)
525 || action == BLOCK_ERR_STOP_ANY) {
40a6238a 526 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 527 s->bus->error_status = op;
7ad7e3c3 528 bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read);
e07bbac5 529 vm_stop(VMSTOP_DISKFULL);
428c5705 530 } else {
ce4b6522 531 if (op & BM_STATUS_DMA_RETRY) {
7aea4412 532 dma_buf_commit(s, 0);
428c5705 533 ide_dma_error(s);
7aea4412 534 } else {
428c5705 535 ide_rw_error(s);
7aea4412 536 }
7ad7e3c3 537 bdrv_mon_event(s->bs, BDRV_ACTION_REPORT, is_read);
428c5705
AL		 538 }
539
540 return 1;
541}
542
cd369c46 543void ide_dma_cb(void *opaque, int ret)
98087450 544{
40a6238a 545 IDEState *s = opaque;
8ccad811
FB		 546 int n;
547 int64_t sector_num;
548
c641483f 549handle_rw_error:
e162cfb0 550 if (ret < 0) {
cd369c46
CH		 551 int op = BM_STATUS_DMA_RETRY;
552
4e1e0051 553 if (s->dma_cmd == IDE_DMA_READ)
cd369c46 554 op |= BM_STATUS_RETRY_READ;
d353fb72
CH		 555 else if (s->dma_cmd == IDE_DMA_TRIM)
556 op |= BM_STATUS_RETRY_TRIM;
557
cd369c46 558 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 559 return;
560 }
e162cfb0
AZ		 561 }
562
8ccad811
FB		 563 n = s->io_buffer_size >> 9;
564 sector_num = ide_get_sector(s);
565 if (n > 0) {
4e1e0051 566 dma_buf_commit(s, ide_cmd_is_read(s));
8ccad811
FB		 567 sector_num += n;
568 ide_set_sector(s, sector_num);
569 s->nsector -= n;
8ccad811
FB		 570 }
571
572 /* end of transfer ? */
573 if (s->nsector == 0) {
98087450 574 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 575 ide_set_irq(s->bus);
cd369c46 576 goto eot;
98087450 577 }
8ccad811
FB		 578
579 /* launch next transfer */
580 n = s->nsector;
596bb44d 581 s->io_buffer_index = 0;
8ccad811 582 s->io_buffer_size = n * 512;
4e1e0051 583 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 584 /* The PRDs were too short. Reset the Active bit, but don't raise an
585 * interrupt. */
7aea4412 586 goto eot;
69c38b8f 587 }
cd369c46 588
8ccad811 589#ifdef DEBUG_AIO
4e1e0051
CH		 590 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
591 sector_num, n, s->dma_cmd);
8ccad811 592#endif
cd369c46 593
4e1e0051
CH		 594 switch (s->dma_cmd) {
595 case IDE_DMA_READ:
cd369c46
CH		 596 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
597 ide_dma_cb, s);
4e1e0051
CH		 598 break;
599 case IDE_DMA_WRITE:
cd369c46
CH		 600 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
601 ide_dma_cb, s);
4e1e0051 602 break;
d353fb72
CH		 603 case IDE_DMA_TRIM:
604 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
605 ide_issue_trim, ide_dma_cb, s, 1);
606 break;
cd369c46 607 }
c641483f
CH		 608
609 if (!s->bus->dma->aiocb) {
610 ret = -1;
611 goto handle_rw_error;
612 }
cd369c46
CH		 613 return;
614
615eot:
a597e79c
CH		 616 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
617 bdrv_acct_done(s->bs, &s->acct);
618 }
619 ide_set_inactive(s);
98087450
FB		 620}
621
4e1e0051 622static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 623{
8ccad811 624 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 625 s->io_buffer_index = 0;
626 s->io_buffer_size = 0;
4e1e0051 627 s->dma_cmd = dma_cmd;
a597e79c
CH		 628
629 switch (dma_cmd) {
630 case IDE_DMA_READ:
631 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
632 BDRV_ACCT_READ);
633 break;
634 case IDE_DMA_WRITE:
635 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
636 BDRV_ACCT_WRITE);
637 break;
638 default:
639 break;
640 }
641
cd369c46 642 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
98087450
FB		 643}
644
a09db21f
FB		 645static void ide_sector_write_timer_cb(void *opaque)
646{
647 IDEState *s = opaque;
9cdd03a7 648 ide_set_irq(s->bus);
a09db21f
FB		 649}
650
40a6238a 651void ide_sector_write(IDEState *s)
5391d806
FB		 652{
653 int64_t sector_num;
31c2a146 654 int ret, n, n1;
5391d806
FB		 655
656 s->status = READY_STAT | SEEK_STAT;
657 sector_num = ide_get_sector(s);
658#if defined(DEBUG_IDE)
18c5f8ea 659 printf("write sector=%" PRId64 "\n", sector_num);
5391d806
FB		 660#endif
661 n = s->nsector;
662 if (n > s->req_nb_sectors)
663 n = s->req_nb_sectors;
a597e79c
CH		 664
665 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
31c2a146 666 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
a597e79c 667 bdrv_acct_done(s->bs, &s->acct);
428c5705 668
e162cfb0 669 if (ret != 0) {
ce4b6522 670 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY))
428c5705 671 return;
e162cfb0
AZ		 672 }
673
5391d806
FB		 674 s->nsector -= n;
675 if (s->nsector == 0) {
292eef5a 676 /* no more sectors to write */
5391d806
FB		 677 ide_transfer_stop(s);
678 } else {
679 n1 = s->nsector;
680 if (n1 > s->req_nb_sectors)
681 n1 = s->req_nb_sectors;
682 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
683 }
684 ide_set_sector(s, sector_num + n);
3b46e624 685
31c2a146
TS		 686 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
687 /* It seems there is a bug in the Windows 2000 installer HDD
688 IDE driver which fills the disk with empty logs when the
689 IDE write IRQ comes too early. This hack tries to correct
690 that at the expense of slower write performances. Use this
691 option _only_ to install Windows 2000. You must disable it
692 for normal use. */
f7736b91 693 qemu_mod_timer(s->sector_write_timer,
74475455 694 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
f7736b91 695 } else {
9cdd03a7 696 ide_set_irq(s->bus);
31c2a146 697 }
5391d806
FB		 698}
699
b0484ae4
CH		 700static void ide_flush_cb(void *opaque, int ret)
701{
702 IDEState *s = opaque;
703
e2bcadad
KW		 704 if (ret < 0) {
705 /* XXX: What sector number to set here? */
706 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
707 return;
708 }
709 }
b0484ae4 710
a597e79c 711 bdrv_acct_done(s->bs, &s->acct);
b0484ae4
CH		 712 s->status = READY_STAT | SEEK_STAT;
713 ide_set_irq(s->bus);
714}
715
40a6238a 716void ide_flush_cache(IDEState *s)
6bcb1a79 717{
b2df7531
KW		 718 BlockDriverAIOCB *acb;
719
720 if (s->bs == NULL) {
6bcb1a79 721 ide_flush_cb(s, 0);
b2df7531
KW		 722 return;
723 }
724
a597e79c 725 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
b2df7531
KW		 726 acb = bdrv_aio_flush(s->bs, ide_flush_cb, s);
727 if (acb == NULL) {
728 ide_flush_cb(s, -EIO);
6bcb1a79
KW		 729 }
730}
731
201a51fc
AZ		 732static void ide_cfata_metadata_inquiry(IDEState *s)
733{
734 uint16_t *p;
735 uint32_t spd;
736
737 p = (uint16_t *) s->io_buffer;
738 memset(p, 0, 0x200);
739 spd = ((s->mdata_size - 1) >> 9) + 1;
740
741 put_le16(p + 0, 0x0001); /* Data format revision */
742 put_le16(p + 1, 0x0000); /* Media property: silicon */
743 put_le16(p + 2, s->media_changed); /* Media status */
744 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
745 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
746 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
747 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
748}
749
750static void ide_cfata_metadata_read(IDEState *s)
751{
752 uint16_t *p;
753
754 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
755 s->status = ERR_STAT;
756 s->error = ABRT_ERR;
757 return;
758 }
759
760 p = (uint16_t *) s->io_buffer;
761 memset(p, 0, 0x200);
762
763 put_le16(p + 0, s->media_changed); /* Media status */
764 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
765 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
766 s->nsector << 9), 0x200 - 2));
767}
768
769static void ide_cfata_metadata_write(IDEState *s)
770{
771 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
772 s->status = ERR_STAT;
773 s->error = ABRT_ERR;
774 return;
775 }
776
777 s->media_changed = 0;
778
779 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
780 s->io_buffer + 2,
781 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
782 s->nsector << 9), 0x200 - 2));
783}
784
bd491d6a 785/* called when the inserted state of the media has changed */
145feb17 786static void ide_cd_change_cb(void *opaque)
bd491d6a
TS		 787{
788 IDEState *s = opaque;
96b8f136 789 uint64_t nb_sectors;
bd491d6a 790
bd491d6a
TS		 791 bdrv_get_geometry(s->bs, &nb_sectors);
792 s->nb_sectors = nb_sectors;
9118e7f0 793
4b9b7092
AS		 794 /*
795 * First indicate to the guest that a CD has been removed. That's
796 * done on the next command the guest sends us.
797 *
798 * Then we set SENSE_UNIT_ATTENTION, by which the guest will
799 * detect a new CD in the drive. See ide_atapi_cmd() for details.
800 */
93c8cfd9 801 s->cdrom_changed = 1;
996faf1a 802 s->events.new_media = true;
9cdd03a7 803 ide_set_irq(s->bus);
bd491d6a
TS		 804}
805
c2ff060f
FB		 806static void ide_cmd_lba48_transform(IDEState *s, int lba48)
807{
808 s->lba48 = lba48;
809
810 /* handle the 'magic' 0 nsector count conversion here. to avoid
811 * fiddling with the rest of the read logic, we just store the
812 * full sector count in ->nsector and ignore ->hob_nsector from now
813 */
814 if (!s->lba48) {
815 if (!s->nsector)
816 s->nsector = 256;
817 } else {
818 if (!s->nsector && !s->hob_nsector)
819 s->nsector = 65536;
820 else {
821 int lo = s->nsector;
822 int hi = s->hob_nsector;
823
824 s->nsector = (hi << 8) | lo;
825 }
826 }
827}
828
bcbdc4d3 829static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 830{
831 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 832 bus->ifs[0].select &= ~(1 << 7);
833 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 834}
835
356721ae 836void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 837{
bcbdc4d3 838 IDEBus *bus = opaque;
5391d806
FB		 839
840#ifdef DEBUG_IDE
841 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
842#endif
c2ff060f 843
5391d806 844 addr &= 7;
fcdd25ab
AL		 845
846 /* ignore writes to command block while busy with previous command */
bcbdc4d3 847 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 848 return;
849
5391d806
FB		 850 switch(addr) {
851 case 0:
852 break;
853 case 1:
bcbdc4d3 854 ide_clear_hob(bus);
c45c3d00 855 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 856 bus->ifs[0].hob_feature = bus->ifs[0].feature;
857 bus->ifs[1].hob_feature = bus->ifs[1].feature;
858 bus->ifs[0].feature = val;
859 bus->ifs[1].feature = val;
5391d806
FB		 860 break;
861 case 2:
bcbdc4d3
GH		 862 ide_clear_hob(bus);
863 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
864 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
865 bus->ifs[0].nsector = val;
866 bus->ifs[1].nsector = val;
5391d806
FB		 867 break;
868 case 3:
bcbdc4d3
GH		 869 ide_clear_hob(bus);
870 bus->ifs[0].hob_sector = bus->ifs[0].sector;
871 bus->ifs[1].hob_sector = bus->ifs[1].sector;
872 bus->ifs[0].sector = val;
873 bus->ifs[1].sector = val;
5391d806
FB		 874 break;
875 case 4:
bcbdc4d3
GH		 876 ide_clear_hob(bus);
877 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
878 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
879 bus->ifs[0].lcyl = val;
880 bus->ifs[1].lcyl = val;
5391d806
FB		 881 break;
882 case 5:
bcbdc4d3
GH		 883 ide_clear_hob(bus);
884 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
885 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
886 bus->ifs[0].hcyl = val;
887 bus->ifs[1].hcyl = val;
5391d806
FB		 888 break;
889 case 6:
c2ff060f 890 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 891 bus->ifs[0].select = (val & ~0x10) | 0xa0;
892 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 893 /* select drive */
bcbdc4d3 894 bus->unit = (val >> 4) & 1;
5391d806
FB		 895 break;
896 default:
897 case 7:
898 /* command */
7cff87ff
AG		 899 ide_exec_cmd(bus, val);
900 break;
901 }
902}
903
844505b1
MA		 904#define HD_OK (1u << IDE_HD)
905#define CD_OK (1u << IDE_CD)
906#define CFA_OK (1u << IDE_CFATA)
907#define HD_CFA_OK (HD_OK | CFA_OK)
908#define ALL_OK (HD_OK | CD_OK | CFA_OK)
909
910/* See ACS-2 T13/2015-D Table B.2 Command codes */
911static const uint8_t ide_cmd_table[0x100] = {
912 /* NOP not implemented, mandatory for CD */
913 [CFA_REQ_EXT_ERROR_CODE] = CFA_OK,
914 [WIN_DSM] = ALL_OK,
915 [WIN_DEVICE_RESET] = CD_OK,
3cfc2269 916 [WIN_RECAL] = HD_CFA_OK,
844505b1
MA		 917 [WIN_READ] = ALL_OK,
918 [WIN_READ_ONCE] = ALL_OK,
3cfc2269
MA		 919 [WIN_READ_EXT] = HD_CFA_OK,
920 [WIN_READDMA_EXT] = HD_CFA_OK,
921 [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK,
922 [WIN_MULTREAD_EXT] = HD_CFA_OK,
923 [WIN_WRITE] = HD_CFA_OK,
924 [WIN_WRITE_ONCE] = HD_CFA_OK,
925 [WIN_WRITE_EXT] = HD_CFA_OK,
926 [WIN_WRITEDMA_EXT] = HD_CFA_OK,
927 [CFA_WRITE_SECT_WO_ERASE] = CFA_OK,
928 [WIN_MULTWRITE_EXT] = HD_CFA_OK,
929 [WIN_WRITE_VERIFY] = HD_CFA_OK,
930 [WIN_VERIFY] = HD_CFA_OK,
931 [WIN_VERIFY_ONCE] = HD_CFA_OK,
932 [WIN_VERIFY_EXT] = HD_CFA_OK,
844505b1
MA		 933 [WIN_SEEK] = HD_CFA_OK,
934 [CFA_TRANSLATE_SECTOR] = CFA_OK,
935 [WIN_DIAGNOSE] = ALL_OK,
3cfc2269 936 [WIN_SPECIFY] = HD_CFA_OK,
844505b1
MA		 937 [WIN_STANDBYNOW2] = ALL_OK,
938 [WIN_IDLEIMMEDIATE2] = ALL_OK,
939 [WIN_STANDBY2] = ALL_OK,
940 [WIN_SETIDLE2] = ALL_OK,
941 [WIN_CHECKPOWERMODE2] = ALL_OK,
942 [WIN_SLEEPNOW2] = ALL_OK,
943 [WIN_PACKETCMD] = CD_OK,
944 [WIN_PIDENTIFY] = CD_OK,
945 [WIN_SMART] = HD_CFA_OK,
946 [CFA_ACCESS_METADATA_STORAGE] = CFA_OK,
947 [CFA_ERASE_SECTORS] = CFA_OK,
3cfc2269
MA		 948 [WIN_MULTREAD] = HD_CFA_OK,
949 [WIN_MULTWRITE] = HD_CFA_OK,
950 [WIN_SETMULT] = HD_CFA_OK,
951 [WIN_READDMA] = HD_CFA_OK,
952 [WIN_READDMA_ONCE] = HD_CFA_OK,
953 [WIN_WRITEDMA] = HD_CFA_OK,
954 [WIN_WRITEDMA_ONCE] = HD_CFA_OK,
955 [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK,
844505b1
MA		 956 [WIN_STANDBYNOW1] = ALL_OK,
957 [WIN_IDLEIMMEDIATE] = ALL_OK,
958 [WIN_STANDBY] = ALL_OK,
959 [WIN_SETIDLE1] = ALL_OK,
960 [WIN_CHECKPOWERMODE1] = ALL_OK,
961 [WIN_SLEEPNOW1] = ALL_OK,
962 [WIN_FLUSH_CACHE] = ALL_OK,
3cfc2269 963 [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK,
844505b1
MA		 964 [WIN_IDENTIFY] = ALL_OK,
965 [WIN_SETFEATURES] = ALL_OK,
966 [IBM_SENSE_CONDITION] = CFA_OK,
967 [CFA_WEAR_LEVEL] = CFA_OK,
968 [WIN_READ_NATIVE_MAX] = ALL_OK,
969};
970
971static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
972{
973 return cmd < ARRAY_SIZE(ide_cmd_table)
974 && (ide_cmd_table[cmd] & (1u << s->drive_kind));
975}
7cff87ff
AG		 976
977void ide_exec_cmd(IDEBus *bus, uint32_t val)
978{
979 IDEState *s;
980 int n;
981 int lba48 = 0;
982
5391d806 983#if defined(DEBUG_IDE)
6ef2ba5e 984 printf("ide: CMD=%02x\n", val);
5391d806 985#endif
6ef2ba5e
AG		 986 s = idebus_active_if(bus);
987 /* ignore commands to non existant slave */
988 if (s != bus->ifs && !s->bs)
989 return;
c2ff060f 990
6ef2ba5e
AG		 991 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
992 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
993 return;
fcdd25ab 994
844505b1
MA		 995 if (!ide_cmd_permitted(s, val)) {
996 goto abort_cmd;
997 }
998
6ef2ba5e 999 switch(val) {
d353fb72
CH		 1000 case WIN_DSM:
1001 switch (s->feature) {
1002 case DSM_TRIM:
1003 if (!s->bs) {
1004 goto abort_cmd;
1005 }
1006 ide_sector_start_dma(s, IDE_DMA_TRIM);
1007 break;
1008 default:
1009 goto abort_cmd;
1010 }
1011 break;
6ef2ba5e
AG		 1012 case WIN_IDENTIFY:
1013 if (s->bs && s->drive_kind != IDE_CD) {
1014 if (s->drive_kind != IDE_CFATA)
1015 ide_identify(s);
1016 else
1017 ide_cfata_identify(s);
769bec72 1018 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1019 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1020 } else {
1021 if (s->drive_kind == IDE_CD) {
1022 ide_set_signature(s);
5391d806 1023 }
6ef2ba5e
AG		 1024 ide_abort_command(s);
1025 }
1026 ide_set_irq(s->bus);
1027 break;
1028 case WIN_SPECIFY:
1029 case WIN_RECAL:
1030 s->error = 0;
1031 s->status = READY_STAT | SEEK_STAT;
1032 ide_set_irq(s->bus);
1033 break;
1034 case WIN_SETMULT:
1035 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1036 /* Disable Read and Write Multiple */
1037 s->mult_sectors = 0;
41a2b959 1038 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1039 } else if ((s->nsector & 0xff) != 0 &&
1040 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1041 (s->nsector & (s->nsector - 1)) != 0)) {
1042 ide_abort_command(s);
1043 } else {
1044 s->mult_sectors = s->nsector & 0xff;
1045 s->status = READY_STAT | SEEK_STAT;
1046 }
1047 ide_set_irq(s->bus);
1048 break;
1049 case WIN_VERIFY_EXT:
1050 lba48 = 1;
1051 case WIN_VERIFY:
1052 case WIN_VERIFY_ONCE:
1053 /* do sector number check ? */
1054 ide_cmd_lba48_transform(s, lba48);
1055 s->status = READY_STAT | SEEK_STAT;
1056 ide_set_irq(s->bus);
1057 break;
814839c0 1058 case WIN_READ_EXT:
6ef2ba5e
AG		 1059 lba48 = 1;
1060 case WIN_READ:
1061 case WIN_READ_ONCE:
3f76a7c3
MA		 1062 if (s->drive_kind == IDE_CD) {
1063 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
6ef2ba5e 1064 goto abort_cmd;
3f76a7c3 1065 }
6ef2ba5e
AG		 1066 ide_cmd_lba48_transform(s, lba48);
1067 s->req_nb_sectors = 1;
1068 ide_sector_read(s);
1069 break;
814839c0 1070 case WIN_WRITE_EXT:
6ef2ba5e
AG		 1071 lba48 = 1;
1072 case WIN_WRITE:
1073 case WIN_WRITE_ONCE:
1074 case CFA_WRITE_SECT_WO_ERASE:
1075 case WIN_WRITE_VERIFY:
1076 ide_cmd_lba48_transform(s, lba48);
1077 s->error = 0;
1078 s->status = SEEK_STAT | READY_STAT;
1079 s->req_nb_sectors = 1;
1080 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1081 s->media_changed = 1;
1082 break;
814839c0 1083 case WIN_MULTREAD_EXT:
6ef2ba5e
AG		 1084 lba48 = 1;
1085 case WIN_MULTREAD:
1086 if (!s->mult_sectors)
1087 goto abort_cmd;
1088 ide_cmd_lba48_transform(s, lba48);
1089 s->req_nb_sectors = s->mult_sectors;
1090 ide_sector_read(s);
1091 break;
1092 case WIN_MULTWRITE_EXT:
1093 lba48 = 1;
1094 case WIN_MULTWRITE:
1095 case CFA_WRITE_MULTI_WO_ERASE:
1096 if (!s->mult_sectors)
1097 goto abort_cmd;
1098 ide_cmd_lba48_transform(s, lba48);
1099 s->error = 0;
1100 s->status = SEEK_STAT | READY_STAT;
1101 s->req_nb_sectors = s->mult_sectors;
1102 n = s->nsector;
1103 if (n > s->req_nb_sectors)
1104 n = s->req_nb_sectors;
1105 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1106 s->media_changed = 1;
1107 break;
814839c0 1108 case WIN_READDMA_EXT:
6ef2ba5e
AG		 1109 lba48 = 1;
1110 case WIN_READDMA:
1111 case WIN_READDMA_ONCE:
1112 if (!s->bs)
1113 goto abort_cmd;
1114 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1115 ide_sector_start_dma(s, IDE_DMA_READ);
6ef2ba5e 1116 break;
814839c0 1117 case WIN_WRITEDMA_EXT:
6ef2ba5e
AG		 1118 lba48 = 1;
1119 case WIN_WRITEDMA:
1120 case WIN_WRITEDMA_ONCE:
1121 if (!s->bs)
1122 goto abort_cmd;
1123 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1124 ide_sector_start_dma(s, IDE_DMA_WRITE);
6ef2ba5e
AG		 1125 s->media_changed = 1;
1126 break;
1127 case WIN_READ_NATIVE_MAX_EXT:
1128 lba48 = 1;
1129 case WIN_READ_NATIVE_MAX:
1130 ide_cmd_lba48_transform(s, lba48);
1131 ide_set_sector(s, s->nb_sectors - 1);
1132 s->status = READY_STAT | SEEK_STAT;
1133 ide_set_irq(s->bus);
1134 break;
1135 case WIN_CHECKPOWERMODE1:
1136 case WIN_CHECKPOWERMODE2:
b93af93d 1137 s->error = 0;
6ef2ba5e
AG		 1138 s->nsector = 0xff; /* device active or idle */
1139 s->status = READY_STAT | SEEK_STAT;
1140 ide_set_irq(s->bus);
1141 break;
1142 case WIN_SETFEATURES:
1143 if (!s->bs)
1144 goto abort_cmd;
1145 /* XXX: valid for CDROM ? */
1146 switch(s->feature) {
1147 case 0xcc: /* reverting to power-on defaults enable */
1148 case 0x66: /* reverting to power-on defaults disable */
1149 case 0x02: /* write cache enable */
1150 case 0x82: /* write cache disable */
1151 case 0xaa: /* read look-ahead enable */
1152 case 0x55: /* read look-ahead disable */
1153 case 0x05: /* set advanced power management mode */
1154 case 0x85: /* disable advanced power management mode */
1155 case 0x69: /* NOP */
1156 case 0x67: /* NOP */
1157 case 0x96: /* NOP */
1158 case 0x9a: /* NOP */
1159 case 0x42: /* enable Automatic Acoustic Mode */
1160 case 0xc2: /* disable Automatic Acoustic Mode */
41a2b959 1161 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1162 ide_set_irq(s->bus);
a136e5a8 1163 break;
6ef2ba5e 1164 case 0x03: { /* set transfer mode */
94458802 1165 uint8_t val = s->nsector & 0x07;
6ef2ba5e 1166 uint16_t *identify_data = (uint16_t *)s->identify_data;
94458802
FB		 1167
1168 switch (s->nsector >> 3) {
6ef2ba5e
AG		 1169 case 0x00: /* pio default */
1170 case 0x01: /* pio mode */
96c35ceb
JQ		 1171 put_le16(identify_data + 62,0x07);
1172 put_le16(identify_data + 63,0x07);
1173 put_le16(identify_data + 88,0x3f);
d1b5c20d 1174 break;
6ef2ba5e 1175 case 0x02: /* sigle word dma mode*/
96c35ceb
JQ		 1176 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1177 put_le16(identify_data + 63,0x07);
1178 put_le16(identify_data + 88,0x3f);
94458802 1179 break;
6ef2ba5e 1180 case 0x04: /* mdma mode */
96c35ceb
JQ		 1181 put_le16(identify_data + 62,0x07);
1182 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1183 put_le16(identify_data + 88,0x3f);
94458802 1184 break;
6ef2ba5e 1185 case 0x08: /* udma mode */
96c35ceb
JQ		 1186 put_le16(identify_data + 62,0x07);
1187 put_le16(identify_data + 63,0x07);
1188 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
94458802 1189 break;
6ef2ba5e 1190 default:
94458802
FB		 1191 goto abort_cmd;
1192 }
4fbfcd6d 1193 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1194 ide_set_irq(s->bus);
4fbfcd6d 1195 break;
6ef2ba5e
AG		 1196 }
1197 default:
1198 goto abort_cmd;
1199 }
1200 break;
1201 case WIN_FLUSH_CACHE:
1202 case WIN_FLUSH_CACHE_EXT:
1203 ide_flush_cache(s);
1204 break;
1205 case WIN_STANDBY:
1206 case WIN_STANDBY2:
1207 case WIN_STANDBYNOW1:
1208 case WIN_STANDBYNOW2:
1209 case WIN_IDLEIMMEDIATE:
1d4316d3 1210 case WIN_IDLEIMMEDIATE2:
6ef2ba5e
AG		 1211 case WIN_SETIDLE1:
1212 case WIN_SETIDLE2:
1213 case WIN_SLEEPNOW1:
1214 case WIN_SLEEPNOW2:
1215 s->status = READY_STAT;
1216 ide_set_irq(s->bus);
1217 break;
1218 case WIN_SEEK:
6ef2ba5e
AG		 1219 /* XXX: Check that seek is within bounds */
1220 s->status = READY_STAT | SEEK_STAT;
1221 ide_set_irq(s->bus);
1222 break;
1223 /* ATAPI commands */
1224 case WIN_PIDENTIFY:
844505b1
MA		 1225 ide_atapi_identify(s);
1226 s->status = READY_STAT | SEEK_STAT;
1227 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
6ef2ba5e
AG		 1228 ide_set_irq(s->bus);
1229 break;
1230 case WIN_DIAGNOSE:
1231 ide_set_signature(s);
1232 if (s->drive_kind == IDE_CD)
1233 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1234 * devices to return a clear status register
1235 * with READY_STAT *not* set. */
1236 else
41a2b959 1237 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1238 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1239 * present.
1240 */
1241 ide_set_irq(s->bus);
1242 break;
1d4316d3 1243 case WIN_DEVICE_RESET:
6ef2ba5e
AG		 1244 ide_set_signature(s);
1245 s->status = 0x00; /* NOTE: READY is _not_ set */
1246 s->error = 0x01;
1247 break;
1248 case WIN_PACKETCMD:
6ef2ba5e
AG		 1249 /* overlapping commands not supported */
1250 if (s->feature & 0x02)
1251 goto abort_cmd;
1252 s->status = READY_STAT | SEEK_STAT;
1253 s->atapi_dma = s->feature & 1;
1254 s->nsector = 1;
1255 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1256 ide_atapi_cmd);
1257 break;
1258 /* CF-ATA commands */
1259 case CFA_REQ_EXT_ERROR_CODE:
6ef2ba5e
AG		 1260 s->error = 0x09; /* miscellaneous error */
1261 s->status = READY_STAT | SEEK_STAT;
1262 ide_set_irq(s->bus);
1263 break;
1264 case CFA_ERASE_SECTORS:
1265 case CFA_WEAR_LEVEL:
6ef2ba5e
AG		 1266 if (val == CFA_WEAR_LEVEL)
1267 s->nsector = 0;
1268 if (val == CFA_ERASE_SECTORS)
1269 s->media_changed = 1;
1270 s->error = 0x00;
1271 s->status = READY_STAT | SEEK_STAT;
1272 ide_set_irq(s->bus);
1273 break;
1274 case CFA_TRANSLATE_SECTOR:
6ef2ba5e
AG		 1275 s->error = 0x00;
1276 s->status = READY_STAT | SEEK_STAT;
1277 memset(s->io_buffer, 0, 0x200);
1278 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1279 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1280 s->io_buffer[0x02] = s->select; /* Head */
1281 s->io_buffer[0x03] = s->sector; /* Sector */
1282 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1283 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1284 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1285 s->io_buffer[0x13] = 0x00; /* Erase flag */
1286 s->io_buffer[0x18] = 0x00; /* Hot count */
1287 s->io_buffer[0x19] = 0x00; /* Hot count */
1288 s->io_buffer[0x1a] = 0x01; /* Hot count */
1289 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1290 ide_set_irq(s->bus);
1291 break;
1292 case CFA_ACCESS_METADATA_STORAGE:
6ef2ba5e
AG		 1293 switch (s->feature) {
1294 case 0x02: /* Inquiry Metadata Storage */
1295 ide_cfata_metadata_inquiry(s);
201a51fc 1296 break;
6ef2ba5e
AG		 1297 case 0x03: /* Read Metadata Storage */
1298 ide_cfata_metadata_read(s);
201a51fc 1299 break;
6ef2ba5e
AG		 1300 case 0x04: /* Write Metadata Storage */
1301 ide_cfata_metadata_write(s);
201a51fc 1302 break;
6ef2ba5e
AG		 1303 default:
1304 goto abort_cmd;
1305 }
1306 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1307 s->status = 0x00; /* NOTE: READY is _not_ set */
1308 ide_set_irq(s->bus);
1309 break;
1310 case IBM_SENSE_CONDITION:
6ef2ba5e
AG		 1311 switch (s->feature) {
1312 case 0x01: /* sense temperature in device */
1313 s->nsector = 0x50; /* +20 C */
201a51fc 1314 break;
6ef2ba5e
AG		 1315 default:
1316 goto abort_cmd;
1317 }
1318 s->status = READY_STAT | SEEK_STAT;
1319 ide_set_irq(s->bus);
1320 break;
e8b54394 1321
814839c0 1322 case WIN_SMART:
6ef2ba5e 1323 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
e8b54394 1324 goto abort_cmd;
6ef2ba5e 1325 if (!s->smart_enabled && s->feature != SMART_ENABLE)
e8b54394 1326 goto abort_cmd;
6ef2ba5e
AG		 1327 switch (s->feature) {
1328 case SMART_DISABLE:
e8b54394
BW		 1329 s->smart_enabled = 0;
1330 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1331 ide_set_irq(s->bus);
e8b54394 1332 break;
6ef2ba5e 1333 case SMART_ENABLE:
e8b54394
BW		 1334 s->smart_enabled = 1;
1335 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1336 ide_set_irq(s->bus);
e8b54394 1337 break;
6ef2ba5e 1338 case SMART_ATTR_AUTOSAVE:
e8b54394
BW		 1339 switch (s->sector) {
1340 case 0x00:
6ef2ba5e
AG		 1341 s->smart_autosave = 0;
1342 break;
e8b54394 1343 case 0xf1:
6ef2ba5e
AG		 1344 s->smart_autosave = 1;
1345 break;
e8b54394 1346 default:
6ef2ba5e 1347 goto abort_cmd;
e8b54394
BW		 1348 }
1349 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1350 ide_set_irq(s->bus);
e8b54394 1351 break;
6ef2ba5e 1352 case SMART_STATUS:
e8b54394 1353 if (!s->smart_errors) {
6ef2ba5e
AG		 1354 s->hcyl = 0xc2;
1355 s->lcyl = 0x4f;
e8b54394 1356 } else {
6ef2ba5e
AG		 1357 s->hcyl = 0x2c;
1358 s->lcyl = 0xf4;
e8b54394
BW		 1359 }
1360 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1361 ide_set_irq(s->bus);
e8b54394 1362 break;
6ef2ba5e 1363 case SMART_READ_THRESH:
e8b54394
BW		 1364 memset(s->io_buffer, 0, 0x200);
1365 s->io_buffer[0] = 0x01; /* smart struct version */
1366 for (n=0; n<30; n++) {
6ef2ba5e 1367 if (smart_attributes[n][0] == 0)
e8b54394 1368 break;
6ef2ba5e 1369 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
b93af93d 1370 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
e8b54394
BW		 1371 }
1372 for (n=0; n<511; n++) /* checksum */
6ef2ba5e 1373 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1374 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1375 s->status = READY_STAT | SEEK_STAT;
1376 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1377 ide_set_irq(s->bus);
e8b54394 1378 break;
6ef2ba5e 1379 case SMART_READ_DATA:
e8b54394
BW		 1380 memset(s->io_buffer, 0, 0x200);
1381 s->io_buffer[0] = 0x01; /* smart struct version */
1382 for (n=0; n<30; n++) {
b93af93d 1383 if (smart_attributes[n][0] == 0) {
e8b54394 1384 break;
b93af93d
BW		 1385 }
1386 int i;
1387 for(i = 0; i < 11; i++) {
1388 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1389 }
e8b54394
BW		 1390 }
1391 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1392 if (s->smart_selftest_count == 0) {
6ef2ba5e 1393 s->io_buffer[363] = 0;
e8b54394 1394 } else {
6ef2ba5e 1395 s->io_buffer[363] =
e8b54394 1396 s->smart_selftest_data[3 +
6ef2ba5e
AG		 1397 (s->smart_selftest_count - 1) *
1398 24];
e8b54394
BW		 1399 }
1400 s->io_buffer[364] = 0x20;
1401 s->io_buffer[365] = 0x01;
1402 /* offline data collection capacity: execute + self-test*/
1403 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1404 s->io_buffer[368] = 0x03; /* smart capability (1) */
1405 s->io_buffer[369] = 0x00; /* smart capability (2) */
1406 s->io_buffer[370] = 0x01; /* error logging supported */
1407 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1408 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1409 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1410
1411 for (n=0; n<511; n++)
6ef2ba5e 1412 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1413 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1414 s->status = READY_STAT | SEEK_STAT;
1415 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1416 ide_set_irq(s->bus);
e8b54394 1417 break;
6ef2ba5e 1418 case SMART_READ_LOG:
e8b54394
BW		 1419 switch (s->sector) {
1420 case 0x01: /* summary smart error log */
6ef2ba5e
AG		 1421 memset(s->io_buffer, 0, 0x200);
1422 s->io_buffer[0] = 0x01;
1423 s->io_buffer[1] = 0x00; /* no error entries */
1424 s->io_buffer[452] = s->smart_errors & 0xff;
1425 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
e8b54394 1426
6ef2ba5e 1427 for (n=0; n<511; n++)
e8b54394 1428 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1429 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1430 break;
e8b54394 1431 case 0x06: /* smart self test log */
6ef2ba5e
AG		 1432 memset(s->io_buffer, 0, 0x200);
1433 s->io_buffer[0] = 0x01;
1434 if (s->smart_selftest_count == 0) {
e8b54394 1435 s->io_buffer[508] = 0;
6ef2ba5e 1436 } else {
e8b54394
BW		 1437 s->io_buffer[508] = s->smart_selftest_count;
1438 for (n=2; n<506; n++)
6ef2ba5e
AG		 1439 s->io_buffer[n] = s->smart_selftest_data[n];
1440 }
1441 for (n=0; n<511; n++)
e8b54394 1442 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1443 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1444 break;
e8b54394 1445 default:
6ef2ba5e 1446 goto abort_cmd;
e8b54394
BW		 1447 }
1448 s->status = READY_STAT | SEEK_STAT;
1449 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1450 ide_set_irq(s->bus);
e8b54394 1451 break;
6ef2ba5e 1452 case SMART_EXECUTE_OFFLINE:
e8b54394
BW		 1453 switch (s->sector) {
1454 case 0: /* off-line routine */
1455 case 1: /* short self test */
1456 case 2: /* extended self test */
6ef2ba5e
AG		 1457 s->smart_selftest_count++;
1458 if(s->smart_selftest_count > 21)
e8b54394 1459 s->smart_selftest_count = 0;
6ef2ba5e
AG		 1460 n = 2 + (s->smart_selftest_count - 1) * 24;
1461 s->smart_selftest_data[n] = s->sector;
1462 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1463 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1464 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1465 s->status = READY_STAT | SEEK_STAT;
1466 ide_set_irq(s->bus);
1467 break;
e8b54394 1468 default:
6ef2ba5e 1469 goto abort_cmd;
e8b54394
BW		 1470 }
1471 break;
6ef2ba5e 1472 default:
e8b54394 1473 goto abort_cmd;
6ef2ba5e
AG		 1474 }
1475 break;
1476 default:
844505b1 1477 /* should not be reachable */
6ef2ba5e
AG		 1478 abort_cmd:
1479 ide_abort_command(s);
1480 ide_set_irq(s->bus);
1481 break;
1482 }
5391d806
FB		 1483}
1484
356721ae 1485uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1486{
bcbdc4d3
GH		 1487 IDEBus *bus = opaque;
1488 IDEState *s = idebus_active_if(bus);
5391d806 1489 uint32_t addr;
c2ff060f 1490 int ret, hob;
5391d806
FB		 1491
1492 addr = addr1 & 7;
c2ff060f
FB		 1493 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1494 //hob = s->select & (1 << 7);
1495 hob = 0;
5391d806
FB		 1496 switch(addr) {
1497 case 0:
1498 ret = 0xff;
1499 break;
1500 case 1:
bcbdc4d3
GH		 1501 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1502 (s != bus->ifs && !s->bs))
c45c3d00 1503 ret = 0;
c2ff060f 1504 else if (!hob)
c45c3d00 1505 ret = s->error;
c2ff060f
FB		 1506 else
1507 ret = s->hob_feature;
5391d806
FB		 1508 break;
1509 case 2:
bcbdc4d3 1510 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1511 ret = 0;
c2ff060f 1512 else if (!hob)
c45c3d00 1513 ret = s->nsector & 0xff;
c2ff060f
FB		 1514 else
1515 ret = s->hob_nsector;
5391d806
FB		 1516 break;
1517 case 3:
bcbdc4d3 1518 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1519 ret = 0;
c2ff060f 1520 else if (!hob)
c45c3d00 1521 ret = s->sector;
c2ff060f
FB		 1522 else
1523 ret = s->hob_sector;
5391d806
FB		 1524 break;
1525 case 4:
bcbdc4d3 1526 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1527 ret = 0;
c2ff060f 1528 else if (!hob)
c45c3d00 1529 ret = s->lcyl;
c2ff060f
FB		 1530 else
1531 ret = s->hob_lcyl;
5391d806
FB		 1532 break;
1533 case 5:
bcbdc4d3 1534 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1535 ret = 0;
c2ff060f 1536 else if (!hob)
c45c3d00 1537 ret = s->hcyl;
c2ff060f
FB		 1538 else
1539 ret = s->hob_hcyl;
5391d806
FB		 1540 break;
1541 case 6:
bcbdc4d3 1542 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00
FB		 1543 ret = 0;
1544 else
7ae98627 1545 ret = s->select;
5391d806
FB		 1546 break;
1547 default:
1548 case 7:
bcbdc4d3
GH		 1549 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1550 (s != bus->ifs && !s->bs))
c45c3d00
FB		 1551 ret = 0;
1552 else
1553 ret = s->status;
9cdd03a7 1554 qemu_irq_lower(bus->irq);
5391d806
FB		 1555 break;
1556 }
1557#ifdef DEBUG_IDE
1558 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1559#endif
1560 return ret;
1561}
1562
356721ae 1563uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1564{
bcbdc4d3
GH		 1565 IDEBus *bus = opaque;
1566 IDEState *s = idebus_active_if(bus);
5391d806 1567 int ret;
7ae98627 1568
bcbdc4d3
GH		 1569 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1570 (s != bus->ifs && !s->bs))
7ae98627
FB		 1571 ret = 0;
1572 else
1573 ret = s->status;
5391d806
FB		 1574#ifdef DEBUG_IDE
1575 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1576#endif
1577 return ret;
1578}
1579
356721ae 1580void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1581{
bcbdc4d3 1582 IDEBus *bus = opaque;
5391d806
FB		 1583 IDEState *s;
1584 int i;
1585
1586#ifdef DEBUG_IDE
1587 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1588#endif
1589 /* common for both drives */
9cdd03a7 1590 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1591 (val & IDE_CMD_RESET)) {
1592 /* reset low to high */
1593 for(i = 0;i < 2; i++) {
bcbdc4d3 1594 s = &bus->ifs[i];
5391d806
FB		 1595 s->status = BUSY_STAT | SEEK_STAT;
1596 s->error = 0x01;
1597 }
9cdd03a7 1598 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1599 !(val & IDE_CMD_RESET)) {
1600 /* high to low */
1601 for(i = 0;i < 2; i++) {
bcbdc4d3 1602 s = &bus->ifs[i];
cd8722bb 1603 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1604 s->status = 0x00; /* NOTE: READY is _not_ set */
1605 else
56bf1d37 1606 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1607 ide_set_signature(s);
1608 }
1609 }
1610
9cdd03a7 1611 bus->cmd = val;
5391d806
FB		 1612}
1613
40c4ed3f
KW		 1614/*
1615 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1616 * transferred from the device to the guest), false if it's a PIO in
1617 */
1618static bool ide_is_pio_out(IDEState *s)
1619{
1620 if (s->end_transfer_func == ide_sector_write ||
1621 s->end_transfer_func == ide_atapi_cmd) {
1622 return false;
1623 } else if (s->end_transfer_func == ide_sector_read ||
1624 s->end_transfer_func == ide_transfer_stop ||
1625 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1626 s->end_transfer_func == ide_dummy_transfer_stop) {
1627 return true;
1628 }
1629
1630 abort();
1631}
1632
356721ae 1633void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 1634{
bcbdc4d3
GH		 1635 IDEBus *bus = opaque;
1636 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1637 uint8_t *p;
1638
40c4ed3f
KW		 1639 /* PIO data access allowed only when DRQ bit is set. The result of a write
1640 * during PIO out is indeterminate, just ignore it. */
1641 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1642 return;
40c4ed3f 1643 }
fcdd25ab 1644
5391d806 1645 p = s->data_ptr;
0c4ad8dc 1646 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 1647 p += 2;
1648 s->data_ptr = p;
1649 if (p >= s->data_end)
1650 s->end_transfer_func(s);
1651}
1652
356721ae 1653uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 1654{
bcbdc4d3
GH		 1655 IDEBus *bus = opaque;
1656 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1657 uint8_t *p;
1658 int ret;
fcdd25ab 1659
40c4ed3f
KW		 1660 /* PIO data access allowed only when DRQ bit is set. The result of a read
1661 * during PIO in is indeterminate, return 0 and don't move forward. */
1662 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1663 return 0;
40c4ed3f 1664 }
fcdd25ab 1665
5391d806 1666 p = s->data_ptr;
0c4ad8dc 1667 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 1668 p += 2;
1669 s->data_ptr = p;
1670 if (p >= s->data_end)
1671 s->end_transfer_func(s);
1672 return ret;
1673}
1674
356721ae 1675void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 1676{
bcbdc4d3
GH		 1677 IDEBus *bus = opaque;
1678 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1679 uint8_t *p;
1680
40c4ed3f
KW		 1681 /* PIO data access allowed only when DRQ bit is set. The result of a write
1682 * during PIO out is indeterminate, just ignore it. */
1683 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1684 return;
40c4ed3f 1685 }
fcdd25ab 1686
5391d806 1687 p = s->data_ptr;
0c4ad8dc 1688 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 1689 p += 4;
1690 s->data_ptr = p;
1691 if (p >= s->data_end)
1692 s->end_transfer_func(s);
1693}
1694
356721ae 1695uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 1696{
bcbdc4d3
GH		 1697 IDEBus *bus = opaque;
1698 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1699 uint8_t *p;
1700 int ret;
3b46e624 1701
40c4ed3f
KW		 1702 /* PIO data access allowed only when DRQ bit is set. The result of a read
1703 * during PIO in is indeterminate, return 0 and don't move forward. */
1704 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1705 return 0;
40c4ed3f 1706 }
fcdd25ab 1707
5391d806 1708 p = s->data_ptr;
0c4ad8dc 1709 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 1710 p += 4;
1711 s->data_ptr = p;
1712 if (p >= s->data_end)
1713 s->end_transfer_func(s);
1714 return ret;
1715}
1716
a7dfe172
FB		 1717static void ide_dummy_transfer_stop(IDEState *s)
1718{
1719 s->data_ptr = s->io_buffer;
1720 s->data_end = s->io_buffer;
1721 s->io_buffer[0] = 0xff;
1722 s->io_buffer[1] = 0xff;
1723 s->io_buffer[2] = 0xff;
1724 s->io_buffer[3] = 0xff;
1725}
1726
4a643563 1727static void ide_reset(IDEState *s)
5391d806 1728{
4a643563
BS		 1729#ifdef DEBUG_IDE
1730 printf("ide: reset\n");
1731#endif
cd8722bb 1732 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 1733 s->mult_sectors = 0;
1734 else
1735 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 1736 /* ide regs */
1737 s->feature = 0;
1738 s->error = 0;
1739 s->nsector = 0;
1740 s->sector = 0;
1741 s->lcyl = 0;
1742 s->hcyl = 0;
1743
1744 /* lba48 */
1745 s->hob_feature = 0;
1746 s->hob_sector = 0;
1747 s->hob_nsector = 0;
1748 s->hob_lcyl = 0;
1749 s->hob_hcyl = 0;
1750
5391d806 1751 s->select = 0xa0;
41a2b959 1752 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 1753
1754 s->lba48 = 0;
1755
1756 /* ATAPI specific */
1757 s->sense_key = 0;
1758 s->asc = 0;
1759 s->cdrom_changed = 0;
1760 s->packet_transfer_size = 0;
1761 s->elementary_transfer_size = 0;
1762 s->io_buffer_index = 0;
1763 s->cd_sector_size = 0;
1764 s->atapi_dma = 0;
1765 /* ATA DMA state */
1766 s->io_buffer_size = 0;
1767 s->req_nb_sectors = 0;
1768
5391d806 1769 ide_set_signature(s);
a7dfe172
FB		 1770 /* init the transfer handler so that 0xffff is returned on data
1771 accesses */
1772 s->end_transfer_func = ide_dummy_transfer_stop;
1773 ide_dummy_transfer_stop(s);
201a51fc 1774 s->media_changed = 0;
5391d806
FB		 1775}
1776
4a643563
BS		 1777void ide_bus_reset(IDEBus *bus)
1778{
1779 bus->unit = 0;
1780 bus->cmd = 0;
1781 ide_reset(&bus->ifs[0]);
1782 ide_reset(&bus->ifs[1]);
1783 ide_clear_hob(bus);
40a6238a
AG		 1784
1785 /* pending async DMA */
1786 if (bus->dma->aiocb) {
1787#ifdef DEBUG_AIO
1788 printf("aio_cancel\n");
1789#endif
1790 bdrv_aio_cancel(bus->dma->aiocb);
1791 bus->dma->aiocb = NULL;
1792 }
1793
1794 /* reset dma provider too */
1795 bus->dma->ops->reset(bus->dma);
4a643563
BS		 1796}
1797
f107639a
MA		 1798static bool ide_cd_is_medium_locked(void *opaque)
1799{
1800 return ((IDEState *)opaque)->tray_locked;
1801}
1802
0e49de52 1803static const BlockDevOps ide_cd_block_ops = {
145feb17 1804 .change_media_cb = ide_cd_change_cb,
f107639a 1805 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 1806};
1807
1f56e32a 1808int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
c4d74df7 1809 const char *version, const char *serial)
88804180
GH		 1810{
1811 int cylinders, heads, secs;
1812 uint64_t nb_sectors;
1813
f8b6cc00 1814 s->bs = bs;
1f56e32a
MA		 1815 s->drive_kind = kind;
1816
f8b6cc00
MA		 1817 bdrv_get_geometry(bs, &nb_sectors);
1818 bdrv_guess_geometry(bs, &cylinders, &heads, &secs);
dce9e928
MA		 1819 if (cylinders < 1 || cylinders > 16383) {
1820 error_report("cyls must be between 1 and 16383");
1821 return -1;
1822 }
1823 if (heads < 1 || heads > 16) {
1824 error_report("heads must be between 1 and 16");
1825 return -1;
1826 }
1827 if (secs < 1 || secs > 63) {
1828 error_report("secs must be between 1 and 63");
1829 return -1;
1830 }
870111c8
MA		 1831 s->cylinders = cylinders;
1832 s->heads = heads;
1833 s->sectors = secs;
1834 s->nb_sectors = nb_sectors;
1835 /* The SMART values should be preserved across power cycles
1836 but they aren't. */
1837 s->smart_enabled = 1;
1838 s->smart_autosave = 1;
1839 s->smart_errors = 0;
1840 s->smart_selftest_count = 0;
1f56e32a 1841 if (kind == IDE_CD) {
0e49de52 1842 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
1b2adf28 1843 bs->buffer_alignment = 2048;
7aa9c811 1844 } else {
98f28ad7
MA		 1845 if (!bdrv_is_inserted(s->bs)) {
1846 error_report("Device needs media, but drive is empty");
1847 return -1;
1848 }
7aa9c811
MA		 1849 if (bdrv_is_read_only(bs)) {
1850 error_report("Can't use a read-only drive");
1851 return -1;
1852 }
88804180 1853 }
f8b6cc00 1854 if (serial) {
6ced55a5
MA		 1855 strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str));
1856 } else {
88804180
GH		 1857 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1858 "QM%05d", s->drive_serial);
870111c8 1859 }
47c06340
GH		 1860 if (version) {
1861 pstrcpy(s->version, sizeof(s->version), version);
1862 } else {
1863 pstrcpy(s->version, sizeof(s->version), QEMU_VERSION);
1864 }
40a6238a 1865
88804180 1866 ide_reset(s);
cd8722bb 1867 bdrv_set_removable(bs, s->drive_kind == IDE_CD);
c4d74df7 1868 return 0;
88804180
GH		 1869}
1870
57234ee4 1871static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 1872{
1873 static int drive_serial = 1;
1874 IDEState *s = &bus->ifs[unit];
1875
1876 s->bus = bus;
1877 s->unit = unit;
1878 s->drive_serial = drive_serial++;
1b2adf28 1879 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 1880 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 1881 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
1882 memset(s->io_buffer, 0, s->io_buffer_total_len);
1883
d459da0e 1884 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
c925400b
KW		 1885 memset(s->smart_selftest_data, 0, 512);
1886
74475455 1887 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
d459da0e 1888 ide_sector_write_timer_cb, s);
57234ee4
MA		 1889}
1890
40a6238a
AG		 1891static void ide_nop_start(IDEDMA *dma, IDEState *s,
1892 BlockDriverCompletionFunc *cb)
1893{
1894}
1895
1896static int ide_nop(IDEDMA *dma)
1897{
1898 return 0;
1899}
1900
1901static int ide_nop_int(IDEDMA *dma, int x)
1902{
1903 return 0;
1904}
1905
1906static void ide_nop_restart(void *opaque, int x, int y)
1907{
1908}
1909
1910static const IDEDMAOps ide_dma_nop_ops = {
1911 .start_dma = ide_nop_start,
1912 .start_transfer = ide_nop,
1913 .prepare_buf = ide_nop_int,
1914 .rw_buf = ide_nop_int,
1915 .set_unit = ide_nop_int,
1916 .add_status = ide_nop_int,
1917 .set_inactive = ide_nop,
1918 .restart_cb = ide_nop_restart,
1919 .reset = ide_nop,
1920};
1921
1922static IDEDMA ide_dma_nop = {
1923 .ops = &ide_dma_nop_ops,
1924 .aiocb = NULL,
1925};
1926
57234ee4
MA		 1927void ide_init2(IDEBus *bus, qemu_irq irq)
1928{
1929 int i;
1930
1931 for(i = 0; i < 2; i++) {
1932 ide_init1(bus, i);
1933 ide_reset(&bus->ifs[i]);
870111c8 1934 }
57234ee4 1935 bus->irq = irq;
40a6238a 1936 bus->dma = &ide_dma_nop;
d459da0e
MA		 1937}
1938
57234ee4
MA		 1939/* TODO convert users to qdev and remove */
1940void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
1941 DriveInfo *hd1, qemu_irq irq)
5391d806 1942{
88804180 1943 int i;
57234ee4 1944 DriveInfo *dinfo;
5391d806 1945
caed8802 1946 for(i = 0; i < 2; i++) {
57234ee4
MA		 1947 dinfo = i == 0 ? hd0 : hd1;
1948 ide_init1(bus, i);
1949 if (dinfo) {
1f56e32a 1950 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
95b5edcd 1951 dinfo->media_cd ? IDE_CD : IDE_HD, NULL,
c4d74df7
MA		 1952 *dinfo->serial ? dinfo->serial : NULL) < 0) {
1953 error_report("Can't set up IDE drive %s", dinfo->id);
1954 exit(1);
1955 }
fa879d62 1956 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
57234ee4
MA		 1957 } else {
1958 ide_reset(&bus->ifs[i]);
1959 }
5391d806 1960 }
9cdd03a7 1961 bus->irq = irq;
40a6238a 1962 bus->dma = &ide_dma_nop;
69b91039
FB		 1963}
1964
356721ae 1965void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
69b91039 1966{
bcbdc4d3
GH		 1967 register_ioport_write(iobase, 8, 1, ide_ioport_write, bus);
1968 register_ioport_read(iobase, 8, 1, ide_ioport_read, bus);
caed8802 1969 if (iobase2) {
bcbdc4d3
GH		 1970 register_ioport_read(iobase2, 1, 1, ide_status_read, bus);
1971 register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus);
5391d806 1972 }
3b46e624 1973
caed8802 1974 /* data ports */
bcbdc4d3
GH		 1975 register_ioport_write(iobase, 2, 2, ide_data_writew, bus);
1976 register_ioport_read(iobase, 2, 2, ide_data_readw, bus);
1977 register_ioport_write(iobase, 4, 4, ide_data_writel, bus);
1978 register_ioport_read(iobase, 4, 4, ide_data_readl, bus);
5391d806 1979}
69b91039 1980
37159f13 1981static bool is_identify_set(void *opaque, int version_id)
aa941b94 1982{
37159f13
JQ		 1983 IDEState *s = opaque;
1984
1985 return s->identify_set != 0;
1986}
1987
50641c5c
JQ		 1988static EndTransferFunc* transfer_end_table[] = {
1989 ide_sector_read,
1990 ide_sector_write,
1991 ide_transfer_stop,
1992 ide_atapi_cmd_reply_end,
1993 ide_atapi_cmd,
1994 ide_dummy_transfer_stop,
1995};
1996
1997static int transfer_end_table_idx(EndTransferFunc *fn)
1998{
1999 int i;
2000
2001 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2002 if (transfer_end_table[i] == fn)
2003 return i;
2004
2005 return -1;
2006}
2007
37159f13 2008static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2009{
37159f13
JQ		 2010 IDEState *s = opaque;
2011
2012 if (version_id < 3) {
93c8cfd9 2013 if (s->sense_key == SENSE_UNIT_ATTENTION &&
37159f13 2014 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) {
93c8cfd9 2015 s->cdrom_changed = 1;
37159f13 2016 }
93c8cfd9 2017 }
37159f13 2018 return 0;
aa941b94
AZ		 2019}
2020
50641c5c
JQ		 2021static int ide_drive_pio_post_load(void *opaque, int version_id)
2022{
2023 IDEState *s = opaque;
2024
7bccf573 2025 if (s->end_transfer_fn_idx > ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2026 return -EINVAL;
2027 }
2028 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2029 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2030 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2031
2032 return 0;
2033}
2034
2035static void ide_drive_pio_pre_save(void *opaque)
2036{
2037 IDEState *s = opaque;
2038 int idx;
2039
2040 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2041 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2042
2043 idx = transfer_end_table_idx(s->end_transfer_func);
2044 if (idx == -1) {
2045 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2046 __func__);
2047 s->end_transfer_fn_idx = 2;
2048 } else {
2049 s->end_transfer_fn_idx = idx;
2050 }
2051}
2052
2053static bool ide_drive_pio_state_needed(void *opaque)
2054{
2055 IDEState *s = opaque;
2056
fdc650d7
KW		 2057 return ((s->status & DRQ_STAT) != 0)
2058 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
50641c5c
JQ		 2059}
2060
996faf1a
AS		 2061static bool ide_atapi_gesn_needed(void *opaque)
2062{
2063 IDEState *s = opaque;
2064
2065 return s->events.new_media || s->events.eject_request;
2066}
2067
def93791
KW		 2068static bool ide_error_needed(void *opaque)
2069{
2070 IDEBus *bus = opaque;
2071
2072 return (bus->error_status != 0);
2073}
2074
996faf1a 2075/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2076static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2077 .name ="ide_drive/atapi/gesn_state",
2078 .version_id = 1,
2079 .minimum_version_id = 1,
2080 .minimum_version_id_old = 1,
2081 .fields = (VMStateField []) {
2082 VMSTATE_BOOL(events.new_media, IDEState),
2083 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2084 VMSTATE_END_OF_LIST()
996faf1a
AS		 2085 }
2086};
2087
656fbeff 2088static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2089 .name = "ide_drive/pio_state",
2090 .version_id = 1,
2091 .minimum_version_id = 1,
2092 .minimum_version_id_old = 1,
2093 .pre_save = ide_drive_pio_pre_save,
2094 .post_load = ide_drive_pio_post_load,
2095 .fields = (VMStateField []) {
2096 VMSTATE_INT32(req_nb_sectors, IDEState),
2097 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2098 vmstate_info_uint8, uint8_t),
2099 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2100 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2101 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2102 VMSTATE_INT32(elementary_transfer_size, IDEState),
2103 VMSTATE_INT32(packet_transfer_size, IDEState),
2104 VMSTATE_END_OF_LIST()
2105 }
2106};
2107
37159f13
JQ		 2108const VMStateDescription vmstate_ide_drive = {
2109 .name = "ide_drive",
3abb6260 2110 .version_id = 3,
37159f13
JQ		 2111 .minimum_version_id = 0,
2112 .minimum_version_id_old = 0,
2113 .post_load = ide_drive_post_load,
2114 .fields = (VMStateField []) {
2115 VMSTATE_INT32(mult_sectors, IDEState),
2116 VMSTATE_INT32(identify_set, IDEState),
2117 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2118 VMSTATE_UINT8(feature, IDEState),
2119 VMSTATE_UINT8(error, IDEState),
2120 VMSTATE_UINT32(nsector, IDEState),
2121 VMSTATE_UINT8(sector, IDEState),
2122 VMSTATE_UINT8(lcyl, IDEState),
2123 VMSTATE_UINT8(hcyl, IDEState),
2124 VMSTATE_UINT8(hob_feature, IDEState),
2125 VMSTATE_UINT8(hob_sector, IDEState),
2126 VMSTATE_UINT8(hob_nsector, IDEState),
2127 VMSTATE_UINT8(hob_lcyl, IDEState),
2128 VMSTATE_UINT8(hob_hcyl, IDEState),
2129 VMSTATE_UINT8(select, IDEState),
2130 VMSTATE_UINT8(status, IDEState),
2131 VMSTATE_UINT8(lba48, IDEState),
2132 VMSTATE_UINT8(sense_key, IDEState),
2133 VMSTATE_UINT8(asc, IDEState),
2134 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2135 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2136 },
2137 .subsections = (VMStateSubsection []) {
2138 {
2139 .vmsd = &vmstate_ide_drive_pio_state,
2140 .needed = ide_drive_pio_state_needed,
996faf1a
AS		 2141 }, {
2142 .vmsd = &vmstate_ide_atapi_gesn_state,
2143 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2144 }, {
2145 /* empty */
2146 }
37159f13
JQ		 2147 }
2148};
2149
656fbeff 2150static const VMStateDescription vmstate_ide_error_status = {
def93791
KW		 2151 .name ="ide_bus/error",
2152 .version_id = 1,
2153 .minimum_version_id = 1,
2154 .minimum_version_id_old = 1,
2155 .fields = (VMStateField []) {
2156 VMSTATE_INT32(error_status, IDEBus),
2157 VMSTATE_END_OF_LIST()
2158 }
2159};
2160
6521dc62
JQ		 2161const VMStateDescription vmstate_ide_bus = {
2162 .name = "ide_bus",
2163 .version_id = 1,
2164 .minimum_version_id = 1,
2165 .minimum_version_id_old = 1,
2166 .fields = (VMStateField []) {
2167 VMSTATE_UINT8(cmd, IDEBus),
2168 VMSTATE_UINT8(unit, IDEBus),
2169 VMSTATE_END_OF_LIST()
def93791
KW		 2170 },
2171 .subsections = (VMStateSubsection []) {
2172 {
2173 .vmsd = &vmstate_ide_error_status,
2174 .needed = ide_error_needed,
2175 }, {
2176 /* empty */
2177 }
6521dc62
JQ		 2178 }
2179};
75717903
IY		 2180
2181void ide_drive_get(DriveInfo **hd, int max_bus)
2182{
2183 int i;
2184
2185 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2186 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2187 exit(1);
2188 }
2189
2190 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2191 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2192 }
2193}
Qemu copy for testing