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Commit | Line | Data |
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5391d806 | 1 | /* |
38cdea7c | 2 | * QEMU IDE disk and CD/DVD-ROM Emulator |
5fafdf24 | 3 | * |
5391d806 | 4 | * Copyright (c) 2003 Fabrice Bellard |
201a51fc | 5 | * Copyright (c) 2006 Openedhand Ltd. |
5fafdf24 | 6 | * |
5391d806 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
59f2a787 GH |
25 | #include <hw/hw.h> |
26 | #include <hw/pc.h> | |
27 | #include <hw/pci.h> | |
c4d74df7 | 28 | #include "qemu-error.h" |
87ecb68b PB |
29 | #include "qemu-timer.h" |
30 | #include "sysemu.h" | |
1fb8648d | 31 | #include "dma.h" |
2446333c | 32 | #include "blockdev.h" |
d1a0739d | 33 | #include "block_int.h" |
59f2a787 GH |
34 | |
35 | #include <hw/ide/internal.h> | |
e8b54394 | 36 | |
b93af93d BW |
37 | /* These values were based on a Seagate ST3500418AS but have been modified |
38 | to make more sense in QEMU */ | |
39 | static const int smart_attributes[][12] = { | |
40 | /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */ | |
41 | /* raw read error rate*/ | |
42 | { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06}, | |
43 | /* spin up */ | |
44 | { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
45 | /* start stop count */ | |
46 | { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14}, | |
47 | /* remapped sectors */ | |
48 | { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24}, | |
49 | /* power on hours */ | |
50 | { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
51 | /* power cycle count */ | |
52 | { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
53 | /* airflow-temperature-celsius */ | |
54 | { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32}, | |
55 | /* end of list */ | |
56 | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} | |
e8b54394 BW |
57 | }; |
58 | ||
ce4b6522 | 59 | static int ide_handle_rw_error(IDEState *s, int error, int op); |
40c4ed3f | 60 | static void ide_dummy_transfer_stop(IDEState *s); |
98087450 | 61 | |
5391d806 FB |
62 | static void padstr(char *str, const char *src, int len) |
63 | { | |
64 | int i, v; | |
65 | for(i = 0; i < len; i++) { | |
66 | if (*src) | |
67 | v = *src++; | |
68 | else | |
69 | v = ' '; | |
69b34976 | 70 | str[i^1] = v; |
5391d806 FB |
71 | } |
72 | } | |
73 | ||
67b915a5 FB |
74 | static void put_le16(uint16_t *p, unsigned int v) |
75 | { | |
0c4ad8dc | 76 | *p = cpu_to_le16(v); |
67b915a5 FB |
77 | } |
78 | ||
5391d806 FB |
79 | static void ide_identify(IDEState *s) |
80 | { | |
81 | uint16_t *p; | |
82 | unsigned int oldsize; | |
d353fb72 | 83 | IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; |
5391d806 | 84 | |
94458802 FB |
85 | if (s->identify_set) { |
86 | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); | |
87 | return; | |
88 | } | |
89 | ||
5391d806 FB |
90 | memset(s->io_buffer, 0, 512); |
91 | p = (uint16_t *)s->io_buffer; | |
67b915a5 | 92 | put_le16(p + 0, 0x0040); |
5fafdf24 | 93 | put_le16(p + 1, s->cylinders); |
67b915a5 FB |
94 | put_le16(p + 3, s->heads); |
95 | put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ | |
96 | put_le16(p + 5, 512); /* XXX: retired, remove ? */ | |
5fafdf24 | 97 | put_le16(p + 6, s->sectors); |
fa879c64 | 98 | padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
67b915a5 FB |
99 | put_le16(p + 20, 3); /* XXX: retired, remove ? */ |
100 | put_le16(p + 21, 512); /* cache size in sectors */ | |
101 | put_le16(p + 22, 4); /* ecc bytes */ | |
47c06340 | 102 | padstr((char *)(p + 23), s->version, 8); /* firmware version */ |
60fe76f3 | 103 | padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */ |
3b46e624 | 104 | #if MAX_MULT_SECTORS > 1 |
67b915a5 | 105 | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
5391d806 | 106 | #endif |
67b915a5 | 107 | put_le16(p + 48, 1); /* dword I/O */ |
94458802 | 108 | put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ |
67b915a5 FB |
109 | put_le16(p + 51, 0x200); /* PIO transfer cycle */ |
110 | put_le16(p + 52, 0x200); /* DMA transfer cycle */ | |
94458802 | 111 | put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ |
67b915a5 FB |
112 | put_le16(p + 54, s->cylinders); |
113 | put_le16(p + 55, s->heads); | |
114 | put_le16(p + 56, s->sectors); | |
5391d806 | 115 | oldsize = s->cylinders * s->heads * s->sectors; |
67b915a5 FB |
116 | put_le16(p + 57, oldsize); |
117 | put_le16(p + 58, oldsize >> 16); | |
5391d806 | 118 | if (s->mult_sectors) |
67b915a5 FB |
119 | put_le16(p + 59, 0x100 | s->mult_sectors); |
120 | put_le16(p + 60, s->nb_sectors); | |
121 | put_le16(p + 61, s->nb_sectors >> 16); | |
d1b5c20d | 122 | put_le16(p + 62, 0x07); /* single word dma0-2 supported */ |
94458802 | 123 | put_le16(p + 63, 0x07); /* mdma0-2 supported */ |
79d1d331 | 124 | put_le16(p + 64, 0x03); /* pio3-4 supported */ |
94458802 FB |
125 | put_le16(p + 65, 120); |
126 | put_le16(p + 66, 120); | |
127 | put_le16(p + 67, 120); | |
128 | put_le16(p + 68, 120); | |
d353fb72 CH |
129 | if (dev && dev->conf.discard_granularity) { |
130 | put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ | |
131 | } | |
ccf0fd8b RE |
132 | |
133 | if (s->ncq_queues) { | |
134 | put_le16(p + 75, s->ncq_queues - 1); | |
135 | /* NCQ supported */ | |
136 | put_le16(p + 76, (1 << 8)); | |
137 | } | |
138 | ||
94458802 FB |
139 | put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ |
140 | put_le16(p + 81, 0x16); /* conforms to ata5 */ | |
a58b8d54 CH |
141 | /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ |
142 | put_le16(p + 82, (1 << 14) | (1 << 5) | 1); | |
c2ff060f FB |
143 | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ |
144 | put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); | |
e8b54394 BW |
145 | /* 14=set to 1, 1=SMART self test, 0=SMART error logging */ |
146 | put_le16(p + 84, (1 << 14) | 0); | |
e900a7b7 CH |
147 | /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */ |
148 | if (bdrv_enable_write_cache(s->bs)) | |
149 | put_le16(p + 85, (1 << 14) | (1 << 5) | 1); | |
150 | else | |
151 | put_le16(p + 85, (1 << 14) | 1); | |
c2ff060f FB |
152 | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ |
153 | put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); | |
e8b54394 BW |
154 | /* 14=set to 1, 1=smart self test, 0=smart error logging */ |
155 | put_le16(p + 87, (1 << 14) | 0); | |
94458802 FB |
156 | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
157 | put_le16(p + 93, 1 | (1 << 14) | 0x2000); | |
c2ff060f FB |
158 | put_le16(p + 100, s->nb_sectors); |
159 | put_le16(p + 101, s->nb_sectors >> 16); | |
160 | put_le16(p + 102, s->nb_sectors >> 32); | |
161 | put_le16(p + 103, s->nb_sectors >> 48); | |
d353fb72 | 162 | |
57dac7ef MA |
163 | if (dev && dev->conf.physical_block_size) |
164 | put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); | |
d353fb72 CH |
165 | if (dev && dev->conf.discard_granularity) { |
166 | put_le16(p + 169, 1); /* TRIM support */ | |
167 | } | |
94458802 FB |
168 | |
169 | memcpy(s->identify_data, p, sizeof(s->identify_data)); | |
170 | s->identify_set = 1; | |
5391d806 FB |
171 | } |
172 | ||
173 | static void ide_atapi_identify(IDEState *s) | |
174 | { | |
175 | uint16_t *p; | |
176 | ||
94458802 FB |
177 | if (s->identify_set) { |
178 | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); | |
179 | return; | |
180 | } | |
181 | ||
5391d806 FB |
182 | memset(s->io_buffer, 0, 512); |
183 | p = (uint16_t *)s->io_buffer; | |
184 | /* Removable CDROM, 50us response, 12 byte packets */ | |
67b915a5 | 185 | put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); |
fa879c64 | 186 | padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
67b915a5 FB |
187 | put_le16(p + 20, 3); /* buffer type */ |
188 | put_le16(p + 21, 512); /* cache size in sectors */ | |
189 | put_le16(p + 22, 4); /* ecc bytes */ | |
47c06340 | 190 | padstr((char *)(p + 23), s->version, 8); /* firmware version */ |
38cdea7c | 191 | padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */ |
67b915a5 | 192 | put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ |
8ccad811 FB |
193 | #ifdef USE_DMA_CDROM |
194 | put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ | |
195 | put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ | |
d1b5c20d | 196 | put_le16(p + 62, 7); /* single word dma0-2 supported */ |
8ccad811 | 197 | put_le16(p + 63, 7); /* mdma0-2 supported */ |
8ccad811 | 198 | #else |
67b915a5 FB |
199 | put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ |
200 | put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ | |
201 | put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ | |
8ccad811 | 202 | #endif |
79d1d331 | 203 | put_le16(p + 64, 3); /* pio3-4 supported */ |
67b915a5 FB |
204 | put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ |
205 | put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ | |
206 | put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ | |
207 | put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ | |
94458802 | 208 | |
67b915a5 FB |
209 | put_le16(p + 71, 30); /* in ns */ |
210 | put_le16(p + 72, 30); /* in ns */ | |
5391d806 | 211 | |
1bdaa28d AG |
212 | if (s->ncq_queues) { |
213 | put_le16(p + 75, s->ncq_queues - 1); | |
214 | /* NCQ supported */ | |
215 | put_le16(p + 76, (1 << 8)); | |
216 | } | |
217 | ||
67b915a5 | 218 | put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ |
8ccad811 FB |
219 | #ifdef USE_DMA_CDROM |
220 | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ | |
221 | #endif | |
94458802 FB |
222 | memcpy(s->identify_data, p, sizeof(s->identify_data)); |
223 | s->identify_set = 1; | |
5391d806 FB |
224 | } |
225 | ||
201a51fc AZ |
226 | static void ide_cfata_identify(IDEState *s) |
227 | { | |
228 | uint16_t *p; | |
229 | uint32_t cur_sec; | |
201a51fc AZ |
230 | |
231 | p = (uint16_t *) s->identify_data; | |
232 | if (s->identify_set) | |
233 | goto fill_buffer; | |
234 | ||
235 | memset(p, 0, sizeof(s->identify_data)); | |
236 | ||
237 | cur_sec = s->cylinders * s->heads * s->sectors; | |
238 | ||
239 | put_le16(p + 0, 0x848a); /* CF Storage Card signature */ | |
240 | put_le16(p + 1, s->cylinders); /* Default cylinders */ | |
241 | put_le16(p + 3, s->heads); /* Default heads */ | |
242 | put_le16(p + 6, s->sectors); /* Default sectors per track */ | |
243 | put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ | |
244 | put_le16(p + 8, s->nb_sectors); /* Sectors per card */ | |
fa879c64 | 245 | padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
201a51fc | 246 | put_le16(p + 22, 0x0004); /* ECC bytes */ |
47c06340 | 247 | padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ |
60fe76f3 | 248 | padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */ |
201a51fc AZ |
249 | #if MAX_MULT_SECTORS > 1 |
250 | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); | |
251 | #else | |
252 | put_le16(p + 47, 0x0000); | |
253 | #endif | |
254 | put_le16(p + 49, 0x0f00); /* Capabilities */ | |
255 | put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ | |
256 | put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ | |
257 | put_le16(p + 53, 0x0003); /* Translation params valid */ | |
258 | put_le16(p + 54, s->cylinders); /* Current cylinders */ | |
259 | put_le16(p + 55, s->heads); /* Current heads */ | |
260 | put_le16(p + 56, s->sectors); /* Current sectors */ | |
261 | put_le16(p + 57, cur_sec); /* Current capacity */ | |
262 | put_le16(p + 58, cur_sec >> 16); /* Current capacity */ | |
263 | if (s->mult_sectors) /* Multiple sector setting */ | |
264 | put_le16(p + 59, 0x100 | s->mult_sectors); | |
265 | put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ | |
266 | put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ | |
267 | put_le16(p + 63, 0x0203); /* Multiword DMA capability */ | |
268 | put_le16(p + 64, 0x0001); /* Flow Control PIO support */ | |
269 | put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ | |
270 | put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ | |
271 | put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ | |
272 | put_le16(p + 82, 0x400c); /* Command Set supported */ | |
273 | put_le16(p + 83, 0x7068); /* Command Set supported */ | |
274 | put_le16(p + 84, 0x4000); /* Features supported */ | |
275 | put_le16(p + 85, 0x000c); /* Command Set enabled */ | |
276 | put_le16(p + 86, 0x7044); /* Command Set enabled */ | |
277 | put_le16(p + 87, 0x4000); /* Features enabled */ | |
278 | put_le16(p + 91, 0x4060); /* Current APM level */ | |
279 | put_le16(p + 129, 0x0002); /* Current features option */ | |
280 | put_le16(p + 130, 0x0005); /* Reassigned sectors */ | |
281 | put_le16(p + 131, 0x0001); /* Initial power mode */ | |
282 | put_le16(p + 132, 0x0000); /* User signature */ | |
283 | put_le16(p + 160, 0x8100); /* Power requirement */ | |
284 | put_le16(p + 161, 0x8001); /* CF command set */ | |
285 | ||
286 | s->identify_set = 1; | |
287 | ||
288 | fill_buffer: | |
289 | memcpy(s->io_buffer, p, sizeof(s->identify_data)); | |
290 | } | |
291 | ||
5391d806 FB |
292 | static void ide_set_signature(IDEState *s) |
293 | { | |
294 | s->select &= 0xf0; /* clear head */ | |
295 | /* put signature */ | |
296 | s->nsector = 1; | |
297 | s->sector = 1; | |
cd8722bb | 298 | if (s->drive_kind == IDE_CD) { |
5391d806 FB |
299 | s->lcyl = 0x14; |
300 | s->hcyl = 0xeb; | |
301 | } else if (s->bs) { | |
302 | s->lcyl = 0; | |
303 | s->hcyl = 0; | |
304 | } else { | |
305 | s->lcyl = 0xff; | |
306 | s->hcyl = 0xff; | |
307 | } | |
308 | } | |
309 | ||
d353fb72 CH |
310 | typedef struct TrimAIOCB { |
311 | BlockDriverAIOCB common; | |
312 | QEMUBH *bh; | |
313 | int ret; | |
314 | } TrimAIOCB; | |
315 | ||
316 | static void trim_aio_cancel(BlockDriverAIOCB *acb) | |
317 | { | |
318 | TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); | |
319 | ||
320 | qemu_bh_delete(iocb->bh); | |
321 | iocb->bh = NULL; | |
322 | qemu_aio_release(iocb); | |
323 | } | |
324 | ||
325 | static AIOPool trim_aio_pool = { | |
326 | .aiocb_size = sizeof(TrimAIOCB), | |
327 | .cancel = trim_aio_cancel, | |
328 | }; | |
329 | ||
330 | static void ide_trim_bh_cb(void *opaque) | |
331 | { | |
332 | TrimAIOCB *iocb = opaque; | |
333 | ||
334 | iocb->common.cb(iocb->common.opaque, iocb->ret); | |
335 | ||
336 | qemu_bh_delete(iocb->bh); | |
337 | iocb->bh = NULL; | |
338 | ||
339 | qemu_aio_release(iocb); | |
340 | } | |
341 | ||
342 | BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs, | |
343 | int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, | |
344 | BlockDriverCompletionFunc *cb, void *opaque) | |
345 | { | |
346 | TrimAIOCB *iocb; | |
347 | int i, j, ret; | |
348 | ||
349 | iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque); | |
350 | iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); | |
351 | iocb->ret = 0; | |
352 | ||
353 | for (j = 0; j < qiov->niov; j++) { | |
354 | uint64_t *buffer = qiov->iov[j].iov_base; | |
355 | ||
356 | for (i = 0; i < qiov->iov[j].iov_len / 8; i++) { | |
357 | /* 6-byte LBA + 2-byte range per entry */ | |
358 | uint64_t entry = le64_to_cpu(buffer[i]); | |
359 | uint64_t sector = entry & 0x0000ffffffffffffULL; | |
360 | uint16_t count = entry >> 48; | |
361 | ||
362 | if (count == 0) { | |
363 | break; | |
364 | } | |
365 | ||
366 | ret = bdrv_discard(bs, sector, count); | |
367 | if (!iocb->ret) { | |
368 | iocb->ret = ret; | |
369 | } | |
370 | } | |
371 | } | |
372 | ||
373 | qemu_bh_schedule(iocb->bh); | |
374 | ||
375 | return &iocb->common; | |
376 | } | |
377 | ||
5391d806 FB |
378 | static inline void ide_abort_command(IDEState *s) |
379 | { | |
380 | s->status = READY_STAT | ERR_STAT; | |
381 | s->error = ABRT_ERR; | |
382 | } | |
383 | ||
5391d806 | 384 | /* prepare data transfer and tell what to do after */ |
33231e0e KW |
385 | void ide_transfer_start(IDEState *s, uint8_t *buf, int size, |
386 | EndTransferFunc *end_transfer_func) | |
5391d806 FB |
387 | { |
388 | s->end_transfer_func = end_transfer_func; | |
389 | s->data_ptr = buf; | |
390 | s->data_end = buf + size; | |
40a6238a | 391 | if (!(s->status & ERR_STAT)) { |
7603d156 | 392 | s->status |= DRQ_STAT; |
40a6238a AG |
393 | } |
394 | s->bus->dma->ops->start_transfer(s->bus->dma); | |
5391d806 FB |
395 | } |
396 | ||
33231e0e | 397 | void ide_transfer_stop(IDEState *s) |
5391d806 FB |
398 | { |
399 | s->end_transfer_func = ide_transfer_stop; | |
400 | s->data_ptr = s->io_buffer; | |
401 | s->data_end = s->io_buffer; | |
402 | s->status &= ~DRQ_STAT; | |
403 | } | |
404 | ||
356721ae | 405 | int64_t ide_get_sector(IDEState *s) |
5391d806 FB |
406 | { |
407 | int64_t sector_num; | |
408 | if (s->select & 0x40) { | |
409 | /* lba */ | |
c2ff060f FB |
410 | if (!s->lba48) { |
411 | sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | | |
412 | (s->lcyl << 8) | s->sector; | |
413 | } else { | |
414 | sector_num = ((int64_t)s->hob_hcyl << 40) | | |
415 | ((int64_t) s->hob_lcyl << 32) | | |
416 | ((int64_t) s->hob_sector << 24) | | |
417 | ((int64_t) s->hcyl << 16) | | |
418 | ((int64_t) s->lcyl << 8) | s->sector; | |
419 | } | |
5391d806 FB |
420 | } else { |
421 | sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors + | |
c2ff060f | 422 | (s->select & 0x0f) * s->sectors + (s->sector - 1); |
5391d806 FB |
423 | } |
424 | return sector_num; | |
425 | } | |
426 | ||
356721ae | 427 | void ide_set_sector(IDEState *s, int64_t sector_num) |
5391d806 FB |
428 | { |
429 | unsigned int cyl, r; | |
430 | if (s->select & 0x40) { | |
c2ff060f FB |
431 | if (!s->lba48) { |
432 | s->select = (s->select & 0xf0) | (sector_num >> 24); | |
433 | s->hcyl = (sector_num >> 16); | |
434 | s->lcyl = (sector_num >> 8); | |
435 | s->sector = (sector_num); | |
436 | } else { | |
437 | s->sector = sector_num; | |
438 | s->lcyl = sector_num >> 8; | |
439 | s->hcyl = sector_num >> 16; | |
440 | s->hob_sector = sector_num >> 24; | |
441 | s->hob_lcyl = sector_num >> 32; | |
442 | s->hob_hcyl = sector_num >> 40; | |
443 | } | |
5391d806 FB |
444 | } else { |
445 | cyl = sector_num / (s->heads * s->sectors); | |
446 | r = sector_num % (s->heads * s->sectors); | |
447 | s->hcyl = cyl >> 8; | |
448 | s->lcyl = cyl; | |
1b8eb456 | 449 | s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); |
5391d806 FB |
450 | s->sector = (r % s->sectors) + 1; |
451 | } | |
452 | } | |
453 | ||
e162cfb0 AZ |
454 | static void ide_rw_error(IDEState *s) { |
455 | ide_abort_command(s); | |
9cdd03a7 | 456 | ide_set_irq(s->bus); |
e162cfb0 AZ |
457 | } |
458 | ||
40a6238a | 459 | void ide_sector_read(IDEState *s) |
5391d806 FB |
460 | { |
461 | int64_t sector_num; | |
462 | int ret, n; | |
463 | ||
464 | s->status = READY_STAT | SEEK_STAT; | |
a136e5a8 | 465 | s->error = 0; /* not needed by IDE spec, but needed by Windows */ |
5391d806 FB |
466 | sector_num = ide_get_sector(s); |
467 | n = s->nsector; | |
468 | if (n == 0) { | |
469 | /* no more sector to read from disk */ | |
470 | ide_transfer_stop(s); | |
471 | } else { | |
472 | #if defined(DEBUG_IDE) | |
18c5f8ea | 473 | printf("read sector=%" PRId64 "\n", sector_num); |
5391d806 FB |
474 | #endif |
475 | if (n > s->req_nb_sectors) | |
476 | n = s->req_nb_sectors; | |
a597e79c CH |
477 | |
478 | bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); | |
5391d806 | 479 | ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); |
a597e79c | 480 | bdrv_acct_done(s->bs, &s->acct); |
e162cfb0 | 481 | if (ret != 0) { |
ce4b6522 KW |
482 | if (ide_handle_rw_error(s, -ret, |
483 | BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ)) | |
484 | { | |
485 | return; | |
486 | } | |
e162cfb0 | 487 | } |
5391d806 | 488 | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read); |
9cdd03a7 | 489 | ide_set_irq(s->bus); |
5391d806 FB |
490 | ide_set_sector(s, sector_num + n); |
491 | s->nsector -= n; | |
492 | } | |
493 | } | |
494 | ||
7aea4412 AL |
495 | static void dma_buf_commit(IDEState *s, int is_write) |
496 | { | |
1fb8648d | 497 | qemu_sglist_destroy(&s->sg); |
7aea4412 AL |
498 | } |
499 | ||
33231e0e | 500 | void ide_set_inactive(IDEState *s) |
8337606d | 501 | { |
40a6238a AG |
502 | s->bus->dma->aiocb = NULL; |
503 | s->bus->dma->ops->set_inactive(s->bus->dma); | |
8337606d KW |
504 | } |
505 | ||
356721ae | 506 | void ide_dma_error(IDEState *s) |
e162cfb0 AZ |
507 | { |
508 | ide_transfer_stop(s); | |
509 | s->error = ABRT_ERR; | |
510 | s->status = READY_STAT | ERR_STAT; | |
40a6238a | 511 | ide_set_inactive(s); |
9cdd03a7 | 512 | ide_set_irq(s->bus); |
e162cfb0 AZ |
513 | } |
514 | ||
ce4b6522 | 515 | static int ide_handle_rw_error(IDEState *s, int error, int op) |
428c5705 | 516 | { |
ce4b6522 | 517 | int is_read = (op & BM_STATUS_RETRY_READ); |
abd7f68d | 518 | BlockErrorAction action = bdrv_get_on_error(s->bs, is_read); |
428c5705 | 519 | |
7ad7e3c3 LC |
520 | if (action == BLOCK_ERR_IGNORE) { |
521 | bdrv_mon_event(s->bs, BDRV_ACTION_IGNORE, is_read); | |
428c5705 | 522 | return 0; |
7ad7e3c3 | 523 | } |
428c5705 AL |
524 | |
525 | if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC) | |
526 | || action == BLOCK_ERR_STOP_ANY) { | |
40a6238a | 527 | s->bus->dma->ops->set_unit(s->bus->dma, s->unit); |
def93791 | 528 | s->bus->error_status = op; |
7ad7e3c3 | 529 | bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read); |
e07bbac5 | 530 | vm_stop(VMSTOP_DISKFULL); |
428c5705 | 531 | } else { |
ce4b6522 | 532 | if (op & BM_STATUS_DMA_RETRY) { |
7aea4412 | 533 | dma_buf_commit(s, 0); |
428c5705 | 534 | ide_dma_error(s); |
7aea4412 | 535 | } else { |
428c5705 | 536 | ide_rw_error(s); |
7aea4412 | 537 | } |
7ad7e3c3 | 538 | bdrv_mon_event(s->bs, BDRV_ACTION_REPORT, is_read); |
428c5705 AL |
539 | } |
540 | ||
541 | return 1; | |
542 | } | |
543 | ||
cd369c46 | 544 | void ide_dma_cb(void *opaque, int ret) |
98087450 | 545 | { |
40a6238a | 546 | IDEState *s = opaque; |
8ccad811 FB |
547 | int n; |
548 | int64_t sector_num; | |
549 | ||
c641483f | 550 | handle_rw_error: |
e162cfb0 | 551 | if (ret < 0) { |
cd369c46 CH |
552 | int op = BM_STATUS_DMA_RETRY; |
553 | ||
4e1e0051 | 554 | if (s->dma_cmd == IDE_DMA_READ) |
cd369c46 | 555 | op |= BM_STATUS_RETRY_READ; |
d353fb72 CH |
556 | else if (s->dma_cmd == IDE_DMA_TRIM) |
557 | op |= BM_STATUS_RETRY_TRIM; | |
558 | ||
cd369c46 | 559 | if (ide_handle_rw_error(s, -ret, op)) { |
ce4b6522 KW |
560 | return; |
561 | } | |
e162cfb0 AZ |
562 | } |
563 | ||
8ccad811 FB |
564 | n = s->io_buffer_size >> 9; |
565 | sector_num = ide_get_sector(s); | |
566 | if (n > 0) { | |
4e1e0051 | 567 | dma_buf_commit(s, ide_cmd_is_read(s)); |
8ccad811 FB |
568 | sector_num += n; |
569 | ide_set_sector(s, sector_num); | |
570 | s->nsector -= n; | |
8ccad811 FB |
571 | } |
572 | ||
573 | /* end of transfer ? */ | |
574 | if (s->nsector == 0) { | |
98087450 | 575 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 576 | ide_set_irq(s->bus); |
cd369c46 | 577 | goto eot; |
98087450 | 578 | } |
8ccad811 FB |
579 | |
580 | /* launch next transfer */ | |
581 | n = s->nsector; | |
596bb44d | 582 | s->io_buffer_index = 0; |
8ccad811 | 583 | s->io_buffer_size = n * 512; |
4e1e0051 | 584 | if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) { |
69c38b8f KW |
585 | /* The PRDs were too short. Reset the Active bit, but don't raise an |
586 | * interrupt. */ | |
7aea4412 | 587 | goto eot; |
69c38b8f | 588 | } |
cd369c46 | 589 | |
8ccad811 | 590 | #ifdef DEBUG_AIO |
4e1e0051 CH |
591 | printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", |
592 | sector_num, n, s->dma_cmd); | |
8ccad811 | 593 | #endif |
cd369c46 | 594 | |
4e1e0051 CH |
595 | switch (s->dma_cmd) { |
596 | case IDE_DMA_READ: | |
cd369c46 CH |
597 | s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, |
598 | ide_dma_cb, s); | |
4e1e0051 CH |
599 | break; |
600 | case IDE_DMA_WRITE: | |
cd369c46 CH |
601 | s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, |
602 | ide_dma_cb, s); | |
4e1e0051 | 603 | break; |
d353fb72 CH |
604 | case IDE_DMA_TRIM: |
605 | s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num, | |
606 | ide_issue_trim, ide_dma_cb, s, 1); | |
607 | break; | |
cd369c46 | 608 | } |
c641483f CH |
609 | |
610 | if (!s->bus->dma->aiocb) { | |
611 | ret = -1; | |
612 | goto handle_rw_error; | |
613 | } | |
cd369c46 CH |
614 | return; |
615 | ||
616 | eot: | |
a597e79c CH |
617 | if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { |
618 | bdrv_acct_done(s->bs, &s->acct); | |
619 | } | |
620 | ide_set_inactive(s); | |
98087450 FB |
621 | } |
622 | ||
4e1e0051 | 623 | static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) |
98087450 | 624 | { |
8ccad811 | 625 | s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
98087450 FB |
626 | s->io_buffer_index = 0; |
627 | s->io_buffer_size = 0; | |
4e1e0051 | 628 | s->dma_cmd = dma_cmd; |
a597e79c CH |
629 | |
630 | switch (dma_cmd) { | |
631 | case IDE_DMA_READ: | |
632 | bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, | |
633 | BDRV_ACCT_READ); | |
634 | break; | |
635 | case IDE_DMA_WRITE: | |
636 | bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, | |
637 | BDRV_ACCT_WRITE); | |
638 | break; | |
639 | default: | |
640 | break; | |
641 | } | |
642 | ||
cd369c46 | 643 | s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb); |
98087450 FB |
644 | } |
645 | ||
a09db21f FB |
646 | static void ide_sector_write_timer_cb(void *opaque) |
647 | { | |
648 | IDEState *s = opaque; | |
9cdd03a7 | 649 | ide_set_irq(s->bus); |
a09db21f FB |
650 | } |
651 | ||
40a6238a | 652 | void ide_sector_write(IDEState *s) |
5391d806 FB |
653 | { |
654 | int64_t sector_num; | |
31c2a146 | 655 | int ret, n, n1; |
5391d806 FB |
656 | |
657 | s->status = READY_STAT | SEEK_STAT; | |
658 | sector_num = ide_get_sector(s); | |
659 | #if defined(DEBUG_IDE) | |
18c5f8ea | 660 | printf("write sector=%" PRId64 "\n", sector_num); |
5391d806 FB |
661 | #endif |
662 | n = s->nsector; | |
663 | if (n > s->req_nb_sectors) | |
664 | n = s->req_nb_sectors; | |
a597e79c CH |
665 | |
666 | bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); | |
31c2a146 | 667 | ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); |
a597e79c | 668 | bdrv_acct_done(s->bs, &s->acct); |
428c5705 | 669 | |
e162cfb0 | 670 | if (ret != 0) { |
ce4b6522 | 671 | if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) |
428c5705 | 672 | return; |
e162cfb0 AZ |
673 | } |
674 | ||
5391d806 FB |
675 | s->nsector -= n; |
676 | if (s->nsector == 0) { | |
292eef5a | 677 | /* no more sectors to write */ |
5391d806 FB |
678 | ide_transfer_stop(s); |
679 | } else { | |
680 | n1 = s->nsector; | |
681 | if (n1 > s->req_nb_sectors) | |
682 | n1 = s->req_nb_sectors; | |
683 | ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write); | |
684 | } | |
685 | ide_set_sector(s, sector_num + n); | |
3b46e624 | 686 | |
31c2a146 TS |
687 | if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { |
688 | /* It seems there is a bug in the Windows 2000 installer HDD | |
689 | IDE driver which fills the disk with empty logs when the | |
690 | IDE write IRQ comes too early. This hack tries to correct | |
691 | that at the expense of slower write performances. Use this | |
692 | option _only_ to install Windows 2000. You must disable it | |
693 | for normal use. */ | |
f7736b91 | 694 | qemu_mod_timer(s->sector_write_timer, |
74475455 | 695 | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000)); |
f7736b91 | 696 | } else { |
9cdd03a7 | 697 | ide_set_irq(s->bus); |
31c2a146 | 698 | } |
5391d806 FB |
699 | } |
700 | ||
b0484ae4 CH |
701 | static void ide_flush_cb(void *opaque, int ret) |
702 | { | |
703 | IDEState *s = opaque; | |
704 | ||
e2bcadad KW |
705 | if (ret < 0) { |
706 | /* XXX: What sector number to set here? */ | |
707 | if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) { | |
708 | return; | |
709 | } | |
710 | } | |
b0484ae4 | 711 | |
a597e79c | 712 | bdrv_acct_done(s->bs, &s->acct); |
b0484ae4 CH |
713 | s->status = READY_STAT | SEEK_STAT; |
714 | ide_set_irq(s->bus); | |
715 | } | |
716 | ||
40a6238a | 717 | void ide_flush_cache(IDEState *s) |
6bcb1a79 | 718 | { |
b2df7531 KW |
719 | BlockDriverAIOCB *acb; |
720 | ||
721 | if (s->bs == NULL) { | |
6bcb1a79 | 722 | ide_flush_cb(s, 0); |
b2df7531 KW |
723 | return; |
724 | } | |
725 | ||
a597e79c | 726 | bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH); |
b2df7531 KW |
727 | acb = bdrv_aio_flush(s->bs, ide_flush_cb, s); |
728 | if (acb == NULL) { | |
729 | ide_flush_cb(s, -EIO); | |
6bcb1a79 KW |
730 | } |
731 | } | |
732 | ||
201a51fc AZ |
733 | static void ide_cfata_metadata_inquiry(IDEState *s) |
734 | { | |
735 | uint16_t *p; | |
736 | uint32_t spd; | |
737 | ||
738 | p = (uint16_t *) s->io_buffer; | |
739 | memset(p, 0, 0x200); | |
740 | spd = ((s->mdata_size - 1) >> 9) + 1; | |
741 | ||
742 | put_le16(p + 0, 0x0001); /* Data format revision */ | |
743 | put_le16(p + 1, 0x0000); /* Media property: silicon */ | |
744 | put_le16(p + 2, s->media_changed); /* Media status */ | |
745 | put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ | |
746 | put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ | |
747 | put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ | |
748 | put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ | |
749 | } | |
750 | ||
751 | static void ide_cfata_metadata_read(IDEState *s) | |
752 | { | |
753 | uint16_t *p; | |
754 | ||
755 | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { | |
756 | s->status = ERR_STAT; | |
757 | s->error = ABRT_ERR; | |
758 | return; | |
759 | } | |
760 | ||
761 | p = (uint16_t *) s->io_buffer; | |
762 | memset(p, 0, 0x200); | |
763 | ||
764 | put_le16(p + 0, s->media_changed); /* Media status */ | |
765 | memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), | |
766 | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), | |
767 | s->nsector << 9), 0x200 - 2)); | |
768 | } | |
769 | ||
770 | static void ide_cfata_metadata_write(IDEState *s) | |
771 | { | |
772 | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { | |
773 | s->status = ERR_STAT; | |
774 | s->error = ABRT_ERR; | |
775 | return; | |
776 | } | |
777 | ||
778 | s->media_changed = 0; | |
779 | ||
780 | memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), | |
781 | s->io_buffer + 2, | |
782 | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), | |
783 | s->nsector << 9), 0x200 - 2)); | |
784 | } | |
785 | ||
bd491d6a | 786 | /* called when the inserted state of the media has changed */ |
7d4b4ba5 | 787 | static void ide_cd_change_cb(void *opaque, bool load) |
bd491d6a TS |
788 | { |
789 | IDEState *s = opaque; | |
96b8f136 | 790 | uint64_t nb_sectors; |
bd491d6a | 791 | |
bd491d6a TS |
792 | bdrv_get_geometry(s->bs, &nb_sectors); |
793 | s->nb_sectors = nb_sectors; | |
9118e7f0 | 794 | |
4b9b7092 AS |
795 | /* |
796 | * First indicate to the guest that a CD has been removed. That's | |
797 | * done on the next command the guest sends us. | |
798 | * | |
799 | * Then we set SENSE_UNIT_ATTENTION, by which the guest will | |
800 | * detect a new CD in the drive. See ide_atapi_cmd() for details. | |
801 | */ | |
93c8cfd9 | 802 | s->cdrom_changed = 1; |
996faf1a | 803 | s->events.new_media = true; |
9cdd03a7 | 804 | ide_set_irq(s->bus); |
bd491d6a TS |
805 | } |
806 | ||
c2ff060f FB |
807 | static void ide_cmd_lba48_transform(IDEState *s, int lba48) |
808 | { | |
809 | s->lba48 = lba48; | |
810 | ||
811 | /* handle the 'magic' 0 nsector count conversion here. to avoid | |
812 | * fiddling with the rest of the read logic, we just store the | |
813 | * full sector count in ->nsector and ignore ->hob_nsector from now | |
814 | */ | |
815 | if (!s->lba48) { | |
816 | if (!s->nsector) | |
817 | s->nsector = 256; | |
818 | } else { | |
819 | if (!s->nsector && !s->hob_nsector) | |
820 | s->nsector = 65536; | |
821 | else { | |
822 | int lo = s->nsector; | |
823 | int hi = s->hob_nsector; | |
824 | ||
825 | s->nsector = (hi << 8) | lo; | |
826 | } | |
827 | } | |
828 | } | |
829 | ||
bcbdc4d3 | 830 | static void ide_clear_hob(IDEBus *bus) |
c2ff060f FB |
831 | { |
832 | /* any write clears HOB high bit of device control register */ | |
bcbdc4d3 GH |
833 | bus->ifs[0].select &= ~(1 << 7); |
834 | bus->ifs[1].select &= ~(1 << 7); | |
c2ff060f FB |
835 | } |
836 | ||
356721ae | 837 | void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
caed8802 | 838 | { |
bcbdc4d3 | 839 | IDEBus *bus = opaque; |
5391d806 FB |
840 | |
841 | #ifdef DEBUG_IDE | |
842 | printf("IDE: write addr=0x%x val=0x%02x\n", addr, val); | |
843 | #endif | |
c2ff060f | 844 | |
5391d806 | 845 | addr &= 7; |
fcdd25ab AL |
846 | |
847 | /* ignore writes to command block while busy with previous command */ | |
bcbdc4d3 | 848 | if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) |
fcdd25ab AL |
849 | return; |
850 | ||
5391d806 FB |
851 | switch(addr) { |
852 | case 0: | |
853 | break; | |
854 | case 1: | |
bcbdc4d3 | 855 | ide_clear_hob(bus); |
c45c3d00 | 856 | /* NOTE: data is written to the two drives */ |
bcbdc4d3 GH |
857 | bus->ifs[0].hob_feature = bus->ifs[0].feature; |
858 | bus->ifs[1].hob_feature = bus->ifs[1].feature; | |
859 | bus->ifs[0].feature = val; | |
860 | bus->ifs[1].feature = val; | |
5391d806 FB |
861 | break; |
862 | case 2: | |
bcbdc4d3 GH |
863 | ide_clear_hob(bus); |
864 | bus->ifs[0].hob_nsector = bus->ifs[0].nsector; | |
865 | bus->ifs[1].hob_nsector = bus->ifs[1].nsector; | |
866 | bus->ifs[0].nsector = val; | |
867 | bus->ifs[1].nsector = val; | |
5391d806 FB |
868 | break; |
869 | case 3: | |
bcbdc4d3 GH |
870 | ide_clear_hob(bus); |
871 | bus->ifs[0].hob_sector = bus->ifs[0].sector; | |
872 | bus->ifs[1].hob_sector = bus->ifs[1].sector; | |
873 | bus->ifs[0].sector = val; | |
874 | bus->ifs[1].sector = val; | |
5391d806 FB |
875 | break; |
876 | case 4: | |
bcbdc4d3 GH |
877 | ide_clear_hob(bus); |
878 | bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; | |
879 | bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; | |
880 | bus->ifs[0].lcyl = val; | |
881 | bus->ifs[1].lcyl = val; | |
5391d806 FB |
882 | break; |
883 | case 5: | |
bcbdc4d3 GH |
884 | ide_clear_hob(bus); |
885 | bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; | |
886 | bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; | |
887 | bus->ifs[0].hcyl = val; | |
888 | bus->ifs[1].hcyl = val; | |
5391d806 FB |
889 | break; |
890 | case 6: | |
c2ff060f | 891 | /* FIXME: HOB readback uses bit 7 */ |
bcbdc4d3 GH |
892 | bus->ifs[0].select = (val & ~0x10) | 0xa0; |
893 | bus->ifs[1].select = (val | 0x10) | 0xa0; | |
5391d806 | 894 | /* select drive */ |
bcbdc4d3 | 895 | bus->unit = (val >> 4) & 1; |
5391d806 FB |
896 | break; |
897 | default: | |
898 | case 7: | |
899 | /* command */ | |
7cff87ff AG |
900 | ide_exec_cmd(bus, val); |
901 | break; | |
902 | } | |
903 | } | |
904 | ||
844505b1 MA |
905 | #define HD_OK (1u << IDE_HD) |
906 | #define CD_OK (1u << IDE_CD) | |
907 | #define CFA_OK (1u << IDE_CFATA) | |
908 | #define HD_CFA_OK (HD_OK | CFA_OK) | |
909 | #define ALL_OK (HD_OK | CD_OK | CFA_OK) | |
910 | ||
911 | /* See ACS-2 T13/2015-D Table B.2 Command codes */ | |
912 | static const uint8_t ide_cmd_table[0x100] = { | |
913 | /* NOP not implemented, mandatory for CD */ | |
914 | [CFA_REQ_EXT_ERROR_CODE] = CFA_OK, | |
915 | [WIN_DSM] = ALL_OK, | |
916 | [WIN_DEVICE_RESET] = CD_OK, | |
3cfc2269 | 917 | [WIN_RECAL] = HD_CFA_OK, |
844505b1 MA |
918 | [WIN_READ] = ALL_OK, |
919 | [WIN_READ_ONCE] = ALL_OK, | |
3cfc2269 MA |
920 | [WIN_READ_EXT] = HD_CFA_OK, |
921 | [WIN_READDMA_EXT] = HD_CFA_OK, | |
922 | [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK, | |
923 | [WIN_MULTREAD_EXT] = HD_CFA_OK, | |
924 | [WIN_WRITE] = HD_CFA_OK, | |
925 | [WIN_WRITE_ONCE] = HD_CFA_OK, | |
926 | [WIN_WRITE_EXT] = HD_CFA_OK, | |
927 | [WIN_WRITEDMA_EXT] = HD_CFA_OK, | |
928 | [CFA_WRITE_SECT_WO_ERASE] = CFA_OK, | |
929 | [WIN_MULTWRITE_EXT] = HD_CFA_OK, | |
930 | [WIN_WRITE_VERIFY] = HD_CFA_OK, | |
931 | [WIN_VERIFY] = HD_CFA_OK, | |
932 | [WIN_VERIFY_ONCE] = HD_CFA_OK, | |
933 | [WIN_VERIFY_EXT] = HD_CFA_OK, | |
844505b1 MA |
934 | [WIN_SEEK] = HD_CFA_OK, |
935 | [CFA_TRANSLATE_SECTOR] = CFA_OK, | |
936 | [WIN_DIAGNOSE] = ALL_OK, | |
3cfc2269 | 937 | [WIN_SPECIFY] = HD_CFA_OK, |
844505b1 MA |
938 | [WIN_STANDBYNOW2] = ALL_OK, |
939 | [WIN_IDLEIMMEDIATE2] = ALL_OK, | |
940 | [WIN_STANDBY2] = ALL_OK, | |
941 | [WIN_SETIDLE2] = ALL_OK, | |
942 | [WIN_CHECKPOWERMODE2] = ALL_OK, | |
943 | [WIN_SLEEPNOW2] = ALL_OK, | |
944 | [WIN_PACKETCMD] = CD_OK, | |
945 | [WIN_PIDENTIFY] = CD_OK, | |
946 | [WIN_SMART] = HD_CFA_OK, | |
947 | [CFA_ACCESS_METADATA_STORAGE] = CFA_OK, | |
948 | [CFA_ERASE_SECTORS] = CFA_OK, | |
3cfc2269 MA |
949 | [WIN_MULTREAD] = HD_CFA_OK, |
950 | [WIN_MULTWRITE] = HD_CFA_OK, | |
951 | [WIN_SETMULT] = HD_CFA_OK, | |
952 | [WIN_READDMA] = HD_CFA_OK, | |
953 | [WIN_READDMA_ONCE] = HD_CFA_OK, | |
954 | [WIN_WRITEDMA] = HD_CFA_OK, | |
955 | [WIN_WRITEDMA_ONCE] = HD_CFA_OK, | |
956 | [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK, | |
844505b1 MA |
957 | [WIN_STANDBYNOW1] = ALL_OK, |
958 | [WIN_IDLEIMMEDIATE] = ALL_OK, | |
959 | [WIN_STANDBY] = ALL_OK, | |
960 | [WIN_SETIDLE1] = ALL_OK, | |
961 | [WIN_CHECKPOWERMODE1] = ALL_OK, | |
962 | [WIN_SLEEPNOW1] = ALL_OK, | |
963 | [WIN_FLUSH_CACHE] = ALL_OK, | |
3cfc2269 | 964 | [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK, |
844505b1 MA |
965 | [WIN_IDENTIFY] = ALL_OK, |
966 | [WIN_SETFEATURES] = ALL_OK, | |
967 | [IBM_SENSE_CONDITION] = CFA_OK, | |
968 | [CFA_WEAR_LEVEL] = CFA_OK, | |
969 | [WIN_READ_NATIVE_MAX] = ALL_OK, | |
970 | }; | |
971 | ||
972 | static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) | |
973 | { | |
974 | return cmd < ARRAY_SIZE(ide_cmd_table) | |
975 | && (ide_cmd_table[cmd] & (1u << s->drive_kind)); | |
976 | } | |
7cff87ff AG |
977 | |
978 | void ide_exec_cmd(IDEBus *bus, uint32_t val) | |
979 | { | |
980 | IDEState *s; | |
981 | int n; | |
982 | int lba48 = 0; | |
983 | ||
5391d806 | 984 | #if defined(DEBUG_IDE) |
6ef2ba5e | 985 | printf("ide: CMD=%02x\n", val); |
5391d806 | 986 | #endif |
6ef2ba5e AG |
987 | s = idebus_active_if(bus); |
988 | /* ignore commands to non existant slave */ | |
989 | if (s != bus->ifs && !s->bs) | |
990 | return; | |
c2ff060f | 991 | |
6ef2ba5e AG |
992 | /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ |
993 | if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) | |
994 | return; | |
fcdd25ab | 995 | |
844505b1 MA |
996 | if (!ide_cmd_permitted(s, val)) { |
997 | goto abort_cmd; | |
998 | } | |
999 | ||
6ef2ba5e | 1000 | switch(val) { |
d353fb72 CH |
1001 | case WIN_DSM: |
1002 | switch (s->feature) { | |
1003 | case DSM_TRIM: | |
1004 | if (!s->bs) { | |
1005 | goto abort_cmd; | |
1006 | } | |
1007 | ide_sector_start_dma(s, IDE_DMA_TRIM); | |
1008 | break; | |
1009 | default: | |
1010 | goto abort_cmd; | |
1011 | } | |
1012 | break; | |
6ef2ba5e AG |
1013 | case WIN_IDENTIFY: |
1014 | if (s->bs && s->drive_kind != IDE_CD) { | |
1015 | if (s->drive_kind != IDE_CFATA) | |
1016 | ide_identify(s); | |
1017 | else | |
1018 | ide_cfata_identify(s); | |
769bec72 | 1019 | s->status = READY_STAT | SEEK_STAT; |
6ef2ba5e AG |
1020 | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); |
1021 | } else { | |
1022 | if (s->drive_kind == IDE_CD) { | |
1023 | ide_set_signature(s); | |
5391d806 | 1024 | } |
6ef2ba5e AG |
1025 | ide_abort_command(s); |
1026 | } | |
1027 | ide_set_irq(s->bus); | |
1028 | break; | |
1029 | case WIN_SPECIFY: | |
1030 | case WIN_RECAL: | |
1031 | s->error = 0; | |
1032 | s->status = READY_STAT | SEEK_STAT; | |
1033 | ide_set_irq(s->bus); | |
1034 | break; | |
1035 | case WIN_SETMULT: | |
1036 | if (s->drive_kind == IDE_CFATA && s->nsector == 0) { | |
1037 | /* Disable Read and Write Multiple */ | |
1038 | s->mult_sectors = 0; | |
41a2b959 | 1039 | s->status = READY_STAT | SEEK_STAT; |
6ef2ba5e AG |
1040 | } else if ((s->nsector & 0xff) != 0 && |
1041 | ((s->nsector & 0xff) > MAX_MULT_SECTORS || | |
1042 | (s->nsector & (s->nsector - 1)) != 0)) { | |
1043 | ide_abort_command(s); | |
1044 | } else { | |
1045 | s->mult_sectors = s->nsector & 0xff; | |
1046 | s->status = READY_STAT | SEEK_STAT; | |
1047 | } | |
1048 | ide_set_irq(s->bus); | |
1049 | break; | |
1050 | case WIN_VERIFY_EXT: | |
1051 | lba48 = 1; | |
1052 | case WIN_VERIFY: | |
1053 | case WIN_VERIFY_ONCE: | |
1054 | /* do sector number check ? */ | |
1055 | ide_cmd_lba48_transform(s, lba48); | |
1056 | s->status = READY_STAT | SEEK_STAT; | |
1057 | ide_set_irq(s->bus); | |
1058 | break; | |
814839c0 | 1059 | case WIN_READ_EXT: |
6ef2ba5e AG |
1060 | lba48 = 1; |
1061 | case WIN_READ: | |
1062 | case WIN_READ_ONCE: | |
3f76a7c3 MA |
1063 | if (s->drive_kind == IDE_CD) { |
1064 | ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */ | |
6ef2ba5e | 1065 | goto abort_cmd; |
3f76a7c3 | 1066 | } |
6ef2ba5e AG |
1067 | ide_cmd_lba48_transform(s, lba48); |
1068 | s->req_nb_sectors = 1; | |
1069 | ide_sector_read(s); | |
1070 | break; | |
814839c0 | 1071 | case WIN_WRITE_EXT: |
6ef2ba5e AG |
1072 | lba48 = 1; |
1073 | case WIN_WRITE: | |
1074 | case WIN_WRITE_ONCE: | |
1075 | case CFA_WRITE_SECT_WO_ERASE: | |
1076 | case WIN_WRITE_VERIFY: | |
1077 | ide_cmd_lba48_transform(s, lba48); | |
1078 | s->error = 0; | |
1079 | s->status = SEEK_STAT | READY_STAT; | |
1080 | s->req_nb_sectors = 1; | |
1081 | ide_transfer_start(s, s->io_buffer, 512, ide_sector_write); | |
1082 | s->media_changed = 1; | |
1083 | break; | |
814839c0 | 1084 | case WIN_MULTREAD_EXT: |
6ef2ba5e AG |
1085 | lba48 = 1; |
1086 | case WIN_MULTREAD: | |
1087 | if (!s->mult_sectors) | |
1088 | goto abort_cmd; | |
1089 | ide_cmd_lba48_transform(s, lba48); | |
1090 | s->req_nb_sectors = s->mult_sectors; | |
1091 | ide_sector_read(s); | |
1092 | break; | |
1093 | case WIN_MULTWRITE_EXT: | |
1094 | lba48 = 1; | |
1095 | case WIN_MULTWRITE: | |
1096 | case CFA_WRITE_MULTI_WO_ERASE: | |
1097 | if (!s->mult_sectors) | |
1098 | goto abort_cmd; | |
1099 | ide_cmd_lba48_transform(s, lba48); | |
1100 | s->error = 0; | |
1101 | s->status = SEEK_STAT | READY_STAT; | |
1102 | s->req_nb_sectors = s->mult_sectors; | |
1103 | n = s->nsector; | |
1104 | if (n > s->req_nb_sectors) | |
1105 | n = s->req_nb_sectors; | |
1106 | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write); | |
1107 | s->media_changed = 1; | |
1108 | break; | |
814839c0 | 1109 | case WIN_READDMA_EXT: |
6ef2ba5e AG |
1110 | lba48 = 1; |
1111 | case WIN_READDMA: | |
1112 | case WIN_READDMA_ONCE: | |
1113 | if (!s->bs) | |
1114 | goto abort_cmd; | |
1115 | ide_cmd_lba48_transform(s, lba48); | |
4e1e0051 | 1116 | ide_sector_start_dma(s, IDE_DMA_READ); |
6ef2ba5e | 1117 | break; |
814839c0 | 1118 | case WIN_WRITEDMA_EXT: |
6ef2ba5e AG |
1119 | lba48 = 1; |
1120 | case WIN_WRITEDMA: | |
1121 | case WIN_WRITEDMA_ONCE: | |
1122 | if (!s->bs) | |
1123 | goto abort_cmd; | |
1124 | ide_cmd_lba48_transform(s, lba48); | |
4e1e0051 | 1125 | ide_sector_start_dma(s, IDE_DMA_WRITE); |
6ef2ba5e AG |
1126 | s->media_changed = 1; |
1127 | break; | |
1128 | case WIN_READ_NATIVE_MAX_EXT: | |
1129 | lba48 = 1; | |
1130 | case WIN_READ_NATIVE_MAX: | |
1131 | ide_cmd_lba48_transform(s, lba48); | |
1132 | ide_set_sector(s, s->nb_sectors - 1); | |
1133 | s->status = READY_STAT | SEEK_STAT; | |
1134 | ide_set_irq(s->bus); | |
1135 | break; | |
1136 | case WIN_CHECKPOWERMODE1: | |
1137 | case WIN_CHECKPOWERMODE2: | |
b93af93d | 1138 | s->error = 0; |
6ef2ba5e AG |
1139 | s->nsector = 0xff; /* device active or idle */ |
1140 | s->status = READY_STAT | SEEK_STAT; | |
1141 | ide_set_irq(s->bus); | |
1142 | break; | |
1143 | case WIN_SETFEATURES: | |
1144 | if (!s->bs) | |
1145 | goto abort_cmd; | |
1146 | /* XXX: valid for CDROM ? */ | |
1147 | switch(s->feature) { | |
1148 | case 0xcc: /* reverting to power-on defaults enable */ | |
1149 | case 0x66: /* reverting to power-on defaults disable */ | |
1150 | case 0x02: /* write cache enable */ | |
1151 | case 0x82: /* write cache disable */ | |
1152 | case 0xaa: /* read look-ahead enable */ | |
1153 | case 0x55: /* read look-ahead disable */ | |
1154 | case 0x05: /* set advanced power management mode */ | |
1155 | case 0x85: /* disable advanced power management mode */ | |
1156 | case 0x69: /* NOP */ | |
1157 | case 0x67: /* NOP */ | |
1158 | case 0x96: /* NOP */ | |
1159 | case 0x9a: /* NOP */ | |
1160 | case 0x42: /* enable Automatic Acoustic Mode */ | |
1161 | case 0xc2: /* disable Automatic Acoustic Mode */ | |
41a2b959 | 1162 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 1163 | ide_set_irq(s->bus); |
a136e5a8 | 1164 | break; |
6ef2ba5e | 1165 | case 0x03: { /* set transfer mode */ |
94458802 | 1166 | uint8_t val = s->nsector & 0x07; |
6ef2ba5e | 1167 | uint16_t *identify_data = (uint16_t *)s->identify_data; |
94458802 FB |
1168 | |
1169 | switch (s->nsector >> 3) { | |
6ef2ba5e AG |
1170 | case 0x00: /* pio default */ |
1171 | case 0x01: /* pio mode */ | |
96c35ceb JQ |
1172 | put_le16(identify_data + 62,0x07); |
1173 | put_le16(identify_data + 63,0x07); | |
1174 | put_le16(identify_data + 88,0x3f); | |
d1b5c20d | 1175 | break; |
6ef2ba5e | 1176 | case 0x02: /* sigle word dma mode*/ |
96c35ceb JQ |
1177 | put_le16(identify_data + 62,0x07 | (1 << (val + 8))); |
1178 | put_le16(identify_data + 63,0x07); | |
1179 | put_le16(identify_data + 88,0x3f); | |
94458802 | 1180 | break; |
6ef2ba5e | 1181 | case 0x04: /* mdma mode */ |
96c35ceb JQ |
1182 | put_le16(identify_data + 62,0x07); |
1183 | put_le16(identify_data + 63,0x07 | (1 << (val + 8))); | |
1184 | put_le16(identify_data + 88,0x3f); | |
94458802 | 1185 | break; |
6ef2ba5e | 1186 | case 0x08: /* udma mode */ |
96c35ceb JQ |
1187 | put_le16(identify_data + 62,0x07); |
1188 | put_le16(identify_data + 63,0x07); | |
1189 | put_le16(identify_data + 88,0x3f | (1 << (val + 8))); | |
94458802 | 1190 | break; |
6ef2ba5e | 1191 | default: |
94458802 FB |
1192 | goto abort_cmd; |
1193 | } | |
4fbfcd6d | 1194 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 1195 | ide_set_irq(s->bus); |
4fbfcd6d | 1196 | break; |
6ef2ba5e AG |
1197 | } |
1198 | default: | |
1199 | goto abort_cmd; | |
1200 | } | |
1201 | break; | |
1202 | case WIN_FLUSH_CACHE: | |
1203 | case WIN_FLUSH_CACHE_EXT: | |
1204 | ide_flush_cache(s); | |
1205 | break; | |
1206 | case WIN_STANDBY: | |
1207 | case WIN_STANDBY2: | |
1208 | case WIN_STANDBYNOW1: | |
1209 | case WIN_STANDBYNOW2: | |
1210 | case WIN_IDLEIMMEDIATE: | |
1d4316d3 | 1211 | case WIN_IDLEIMMEDIATE2: |
6ef2ba5e AG |
1212 | case WIN_SETIDLE1: |
1213 | case WIN_SETIDLE2: | |
1214 | case WIN_SLEEPNOW1: | |
1215 | case WIN_SLEEPNOW2: | |
1216 | s->status = READY_STAT; | |
1217 | ide_set_irq(s->bus); | |
1218 | break; | |
1219 | case WIN_SEEK: | |
6ef2ba5e AG |
1220 | /* XXX: Check that seek is within bounds */ |
1221 | s->status = READY_STAT | SEEK_STAT; | |
1222 | ide_set_irq(s->bus); | |
1223 | break; | |
1224 | /* ATAPI commands */ | |
1225 | case WIN_PIDENTIFY: | |
844505b1 MA |
1226 | ide_atapi_identify(s); |
1227 | s->status = READY_STAT | SEEK_STAT; | |
1228 | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); | |
6ef2ba5e AG |
1229 | ide_set_irq(s->bus); |
1230 | break; | |
1231 | case WIN_DIAGNOSE: | |
1232 | ide_set_signature(s); | |
1233 | if (s->drive_kind == IDE_CD) | |
1234 | s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet | |
1235 | * devices to return a clear status register | |
1236 | * with READY_STAT *not* set. */ | |
1237 | else | |
41a2b959 | 1238 | s->status = READY_STAT | SEEK_STAT; |
6ef2ba5e AG |
1239 | s->error = 0x01; /* Device 0 passed, Device 1 passed or not |
1240 | * present. | |
1241 | */ | |
1242 | ide_set_irq(s->bus); | |
1243 | break; | |
1d4316d3 | 1244 | case WIN_DEVICE_RESET: |
6ef2ba5e AG |
1245 | ide_set_signature(s); |
1246 | s->status = 0x00; /* NOTE: READY is _not_ set */ | |
1247 | s->error = 0x01; | |
1248 | break; | |
1249 | case WIN_PACKETCMD: | |
6ef2ba5e AG |
1250 | /* overlapping commands not supported */ |
1251 | if (s->feature & 0x02) | |
1252 | goto abort_cmd; | |
1253 | s->status = READY_STAT | SEEK_STAT; | |
1254 | s->atapi_dma = s->feature & 1; | |
1255 | s->nsector = 1; | |
1256 | ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, | |
1257 | ide_atapi_cmd); | |
1258 | break; | |
1259 | /* CF-ATA commands */ | |
1260 | case CFA_REQ_EXT_ERROR_CODE: | |
6ef2ba5e AG |
1261 | s->error = 0x09; /* miscellaneous error */ |
1262 | s->status = READY_STAT | SEEK_STAT; | |
1263 | ide_set_irq(s->bus); | |
1264 | break; | |
1265 | case CFA_ERASE_SECTORS: | |
1266 | case CFA_WEAR_LEVEL: | |
6ef2ba5e AG |
1267 | if (val == CFA_WEAR_LEVEL) |
1268 | s->nsector = 0; | |
1269 | if (val == CFA_ERASE_SECTORS) | |
1270 | s->media_changed = 1; | |
1271 | s->error = 0x00; | |
1272 | s->status = READY_STAT | SEEK_STAT; | |
1273 | ide_set_irq(s->bus); | |
1274 | break; | |
1275 | case CFA_TRANSLATE_SECTOR: | |
6ef2ba5e AG |
1276 | s->error = 0x00; |
1277 | s->status = READY_STAT | SEEK_STAT; | |
1278 | memset(s->io_buffer, 0, 0x200); | |
1279 | s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ | |
1280 | s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ | |
1281 | s->io_buffer[0x02] = s->select; /* Head */ | |
1282 | s->io_buffer[0x03] = s->sector; /* Sector */ | |
1283 | s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ | |
1284 | s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ | |
1285 | s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ | |
1286 | s->io_buffer[0x13] = 0x00; /* Erase flag */ | |
1287 | s->io_buffer[0x18] = 0x00; /* Hot count */ | |
1288 | s->io_buffer[0x19] = 0x00; /* Hot count */ | |
1289 | s->io_buffer[0x1a] = 0x01; /* Hot count */ | |
1290 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
1291 | ide_set_irq(s->bus); | |
1292 | break; | |
1293 | case CFA_ACCESS_METADATA_STORAGE: | |
6ef2ba5e AG |
1294 | switch (s->feature) { |
1295 | case 0x02: /* Inquiry Metadata Storage */ | |
1296 | ide_cfata_metadata_inquiry(s); | |
201a51fc | 1297 | break; |
6ef2ba5e AG |
1298 | case 0x03: /* Read Metadata Storage */ |
1299 | ide_cfata_metadata_read(s); | |
201a51fc | 1300 | break; |
6ef2ba5e AG |
1301 | case 0x04: /* Write Metadata Storage */ |
1302 | ide_cfata_metadata_write(s); | |
201a51fc | 1303 | break; |
6ef2ba5e AG |
1304 | default: |
1305 | goto abort_cmd; | |
1306 | } | |
1307 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
1308 | s->status = 0x00; /* NOTE: READY is _not_ set */ | |
1309 | ide_set_irq(s->bus); | |
1310 | break; | |
1311 | case IBM_SENSE_CONDITION: | |
6ef2ba5e AG |
1312 | switch (s->feature) { |
1313 | case 0x01: /* sense temperature in device */ | |
1314 | s->nsector = 0x50; /* +20 C */ | |
201a51fc | 1315 | break; |
6ef2ba5e AG |
1316 | default: |
1317 | goto abort_cmd; | |
1318 | } | |
1319 | s->status = READY_STAT | SEEK_STAT; | |
1320 | ide_set_irq(s->bus); | |
1321 | break; | |
e8b54394 | 1322 | |
814839c0 | 1323 | case WIN_SMART: |
6ef2ba5e | 1324 | if (s->hcyl != 0xc2 || s->lcyl != 0x4f) |
e8b54394 | 1325 | goto abort_cmd; |
6ef2ba5e | 1326 | if (!s->smart_enabled && s->feature != SMART_ENABLE) |
e8b54394 | 1327 | goto abort_cmd; |
6ef2ba5e AG |
1328 | switch (s->feature) { |
1329 | case SMART_DISABLE: | |
e8b54394 BW |
1330 | s->smart_enabled = 0; |
1331 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1332 | ide_set_irq(s->bus); |
e8b54394 | 1333 | break; |
6ef2ba5e | 1334 | case SMART_ENABLE: |
e8b54394 BW |
1335 | s->smart_enabled = 1; |
1336 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1337 | ide_set_irq(s->bus); |
e8b54394 | 1338 | break; |
6ef2ba5e | 1339 | case SMART_ATTR_AUTOSAVE: |
e8b54394 BW |
1340 | switch (s->sector) { |
1341 | case 0x00: | |
6ef2ba5e AG |
1342 | s->smart_autosave = 0; |
1343 | break; | |
e8b54394 | 1344 | case 0xf1: |
6ef2ba5e AG |
1345 | s->smart_autosave = 1; |
1346 | break; | |
e8b54394 | 1347 | default: |
6ef2ba5e | 1348 | goto abort_cmd; |
e8b54394 BW |
1349 | } |
1350 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1351 | ide_set_irq(s->bus); |
e8b54394 | 1352 | break; |
6ef2ba5e | 1353 | case SMART_STATUS: |
e8b54394 | 1354 | if (!s->smart_errors) { |
6ef2ba5e AG |
1355 | s->hcyl = 0xc2; |
1356 | s->lcyl = 0x4f; | |
e8b54394 | 1357 | } else { |
6ef2ba5e AG |
1358 | s->hcyl = 0x2c; |
1359 | s->lcyl = 0xf4; | |
e8b54394 BW |
1360 | } |
1361 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1362 | ide_set_irq(s->bus); |
e8b54394 | 1363 | break; |
6ef2ba5e | 1364 | case SMART_READ_THRESH: |
e8b54394 BW |
1365 | memset(s->io_buffer, 0, 0x200); |
1366 | s->io_buffer[0] = 0x01; /* smart struct version */ | |
1367 | for (n=0; n<30; n++) { | |
6ef2ba5e | 1368 | if (smart_attributes[n][0] == 0) |
e8b54394 | 1369 | break; |
6ef2ba5e | 1370 | s->io_buffer[2+0+(n*12)] = smart_attributes[n][0]; |
b93af93d | 1371 | s->io_buffer[2+1+(n*12)] = smart_attributes[n][11]; |
e8b54394 BW |
1372 | } |
1373 | for (n=0; n<511; n++) /* checksum */ | |
6ef2ba5e | 1374 | s->io_buffer[511] += s->io_buffer[n]; |
e8b54394 BW |
1375 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1376 | s->status = READY_STAT | SEEK_STAT; | |
1377 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
9cdd03a7 | 1378 | ide_set_irq(s->bus); |
e8b54394 | 1379 | break; |
6ef2ba5e | 1380 | case SMART_READ_DATA: |
e8b54394 BW |
1381 | memset(s->io_buffer, 0, 0x200); |
1382 | s->io_buffer[0] = 0x01; /* smart struct version */ | |
1383 | for (n=0; n<30; n++) { | |
b93af93d | 1384 | if (smart_attributes[n][0] == 0) { |
e8b54394 | 1385 | break; |
b93af93d BW |
1386 | } |
1387 | int i; | |
1388 | for(i = 0; i < 11; i++) { | |
1389 | s->io_buffer[2+i+(n*12)] = smart_attributes[n][i]; | |
1390 | } | |
e8b54394 BW |
1391 | } |
1392 | s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00); | |
1393 | if (s->smart_selftest_count == 0) { | |
6ef2ba5e | 1394 | s->io_buffer[363] = 0; |
e8b54394 | 1395 | } else { |
6ef2ba5e | 1396 | s->io_buffer[363] = |
e8b54394 | 1397 | s->smart_selftest_data[3 + |
6ef2ba5e AG |
1398 | (s->smart_selftest_count - 1) * |
1399 | 24]; | |
e8b54394 BW |
1400 | } |
1401 | s->io_buffer[364] = 0x20; | |
1402 | s->io_buffer[365] = 0x01; | |
1403 | /* offline data collection capacity: execute + self-test*/ | |
1404 | s->io_buffer[367] = (1<<4 | 1<<3 | 1); | |
1405 | s->io_buffer[368] = 0x03; /* smart capability (1) */ | |
1406 | s->io_buffer[369] = 0x00; /* smart capability (2) */ | |
1407 | s->io_buffer[370] = 0x01; /* error logging supported */ | |
1408 | s->io_buffer[372] = 0x02; /* minutes for poll short test */ | |
1409 | s->io_buffer[373] = 0x36; /* minutes for poll ext test */ | |
1410 | s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ | |
1411 | ||
1412 | for (n=0; n<511; n++) | |
6ef2ba5e | 1413 | s->io_buffer[511] += s->io_buffer[n]; |
e8b54394 BW |
1414 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1415 | s->status = READY_STAT | SEEK_STAT; | |
1416 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
9cdd03a7 | 1417 | ide_set_irq(s->bus); |
e8b54394 | 1418 | break; |
6ef2ba5e | 1419 | case SMART_READ_LOG: |
e8b54394 BW |
1420 | switch (s->sector) { |
1421 | case 0x01: /* summary smart error log */ | |
6ef2ba5e AG |
1422 | memset(s->io_buffer, 0, 0x200); |
1423 | s->io_buffer[0] = 0x01; | |
1424 | s->io_buffer[1] = 0x00; /* no error entries */ | |
1425 | s->io_buffer[452] = s->smart_errors & 0xff; | |
1426 | s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; | |
e8b54394 | 1427 | |
6ef2ba5e | 1428 | for (n=0; n<511; n++) |
e8b54394 | 1429 | s->io_buffer[511] += s->io_buffer[n]; |
6ef2ba5e AG |
1430 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1431 | break; | |
e8b54394 | 1432 | case 0x06: /* smart self test log */ |
6ef2ba5e AG |
1433 | memset(s->io_buffer, 0, 0x200); |
1434 | s->io_buffer[0] = 0x01; | |
1435 | if (s->smart_selftest_count == 0) { | |
e8b54394 | 1436 | s->io_buffer[508] = 0; |
6ef2ba5e | 1437 | } else { |
e8b54394 BW |
1438 | s->io_buffer[508] = s->smart_selftest_count; |
1439 | for (n=2; n<506; n++) | |
6ef2ba5e AG |
1440 | s->io_buffer[n] = s->smart_selftest_data[n]; |
1441 | } | |
1442 | for (n=0; n<511; n++) | |
e8b54394 | 1443 | s->io_buffer[511] += s->io_buffer[n]; |
6ef2ba5e AG |
1444 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1445 | break; | |
e8b54394 | 1446 | default: |
6ef2ba5e | 1447 | goto abort_cmd; |
e8b54394 BW |
1448 | } |
1449 | s->status = READY_STAT | SEEK_STAT; | |
1450 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
9cdd03a7 | 1451 | ide_set_irq(s->bus); |
e8b54394 | 1452 | break; |
6ef2ba5e | 1453 | case SMART_EXECUTE_OFFLINE: |
e8b54394 BW |
1454 | switch (s->sector) { |
1455 | case 0: /* off-line routine */ | |
1456 | case 1: /* short self test */ | |
1457 | case 2: /* extended self test */ | |
6ef2ba5e AG |
1458 | s->smart_selftest_count++; |
1459 | if(s->smart_selftest_count > 21) | |
e8b54394 | 1460 | s->smart_selftest_count = 0; |
6ef2ba5e AG |
1461 | n = 2 + (s->smart_selftest_count - 1) * 24; |
1462 | s->smart_selftest_data[n] = s->sector; | |
1463 | s->smart_selftest_data[n+1] = 0x00; /* OK and finished */ | |
1464 | s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */ | |
1465 | s->smart_selftest_data[n+3] = 0x12; /* hour count msb */ | |
1466 | s->status = READY_STAT | SEEK_STAT; | |
1467 | ide_set_irq(s->bus); | |
1468 | break; | |
e8b54394 | 1469 | default: |
6ef2ba5e | 1470 | goto abort_cmd; |
e8b54394 BW |
1471 | } |
1472 | break; | |
6ef2ba5e | 1473 | default: |
e8b54394 | 1474 | goto abort_cmd; |
6ef2ba5e AG |
1475 | } |
1476 | break; | |
1477 | default: | |
844505b1 | 1478 | /* should not be reachable */ |
6ef2ba5e AG |
1479 | abort_cmd: |
1480 | ide_abort_command(s); | |
1481 | ide_set_irq(s->bus); | |
1482 | break; | |
1483 | } | |
5391d806 FB |
1484 | } |
1485 | ||
356721ae | 1486 | uint32_t ide_ioport_read(void *opaque, uint32_t addr1) |
5391d806 | 1487 | { |
bcbdc4d3 GH |
1488 | IDEBus *bus = opaque; |
1489 | IDEState *s = idebus_active_if(bus); | |
5391d806 | 1490 | uint32_t addr; |
c2ff060f | 1491 | int ret, hob; |
5391d806 FB |
1492 | |
1493 | addr = addr1 & 7; | |
c2ff060f FB |
1494 | /* FIXME: HOB readback uses bit 7, but it's always set right now */ |
1495 | //hob = s->select & (1 << 7); | |
1496 | hob = 0; | |
5391d806 FB |
1497 | switch(addr) { |
1498 | case 0: | |
1499 | ret = 0xff; | |
1500 | break; | |
1501 | case 1: | |
bcbdc4d3 GH |
1502 | if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
1503 | (s != bus->ifs && !s->bs)) | |
c45c3d00 | 1504 | ret = 0; |
c2ff060f | 1505 | else if (!hob) |
c45c3d00 | 1506 | ret = s->error; |
c2ff060f FB |
1507 | else |
1508 | ret = s->hob_feature; | |
5391d806 FB |
1509 | break; |
1510 | case 2: | |
bcbdc4d3 | 1511 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1512 | ret = 0; |
c2ff060f | 1513 | else if (!hob) |
c45c3d00 | 1514 | ret = s->nsector & 0xff; |
c2ff060f FB |
1515 | else |
1516 | ret = s->hob_nsector; | |
5391d806 FB |
1517 | break; |
1518 | case 3: | |
bcbdc4d3 | 1519 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1520 | ret = 0; |
c2ff060f | 1521 | else if (!hob) |
c45c3d00 | 1522 | ret = s->sector; |
c2ff060f FB |
1523 | else |
1524 | ret = s->hob_sector; | |
5391d806 FB |
1525 | break; |
1526 | case 4: | |
bcbdc4d3 | 1527 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1528 | ret = 0; |
c2ff060f | 1529 | else if (!hob) |
c45c3d00 | 1530 | ret = s->lcyl; |
c2ff060f FB |
1531 | else |
1532 | ret = s->hob_lcyl; | |
5391d806 FB |
1533 | break; |
1534 | case 5: | |
bcbdc4d3 | 1535 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1536 | ret = 0; |
c2ff060f | 1537 | else if (!hob) |
c45c3d00 | 1538 | ret = s->hcyl; |
c2ff060f FB |
1539 | else |
1540 | ret = s->hob_hcyl; | |
5391d806 FB |
1541 | break; |
1542 | case 6: | |
bcbdc4d3 | 1543 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 FB |
1544 | ret = 0; |
1545 | else | |
7ae98627 | 1546 | ret = s->select; |
5391d806 FB |
1547 | break; |
1548 | default: | |
1549 | case 7: | |
bcbdc4d3 GH |
1550 | if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
1551 | (s != bus->ifs && !s->bs)) | |
c45c3d00 FB |
1552 | ret = 0; |
1553 | else | |
1554 | ret = s->status; | |
9cdd03a7 | 1555 | qemu_irq_lower(bus->irq); |
5391d806 FB |
1556 | break; |
1557 | } | |
1558 | #ifdef DEBUG_IDE | |
1559 | printf("ide: read addr=0x%x val=%02x\n", addr1, ret); | |
1560 | #endif | |
1561 | return ret; | |
1562 | } | |
1563 | ||
356721ae | 1564 | uint32_t ide_status_read(void *opaque, uint32_t addr) |
5391d806 | 1565 | { |
bcbdc4d3 GH |
1566 | IDEBus *bus = opaque; |
1567 | IDEState *s = idebus_active_if(bus); | |
5391d806 | 1568 | int ret; |
7ae98627 | 1569 | |
bcbdc4d3 GH |
1570 | if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
1571 | (s != bus->ifs && !s->bs)) | |
7ae98627 FB |
1572 | ret = 0; |
1573 | else | |
1574 | ret = s->status; | |
5391d806 FB |
1575 | #ifdef DEBUG_IDE |
1576 | printf("ide: read status addr=0x%x val=%02x\n", addr, ret); | |
1577 | #endif | |
1578 | return ret; | |
1579 | } | |
1580 | ||
356721ae | 1581 | void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) |
5391d806 | 1582 | { |
bcbdc4d3 | 1583 | IDEBus *bus = opaque; |
5391d806 FB |
1584 | IDEState *s; |
1585 | int i; | |
1586 | ||
1587 | #ifdef DEBUG_IDE | |
1588 | printf("ide: write control addr=0x%x val=%02x\n", addr, val); | |
1589 | #endif | |
1590 | /* common for both drives */ | |
9cdd03a7 | 1591 | if (!(bus->cmd & IDE_CMD_RESET) && |
5391d806 FB |
1592 | (val & IDE_CMD_RESET)) { |
1593 | /* reset low to high */ | |
1594 | for(i = 0;i < 2; i++) { | |
bcbdc4d3 | 1595 | s = &bus->ifs[i]; |
5391d806 FB |
1596 | s->status = BUSY_STAT | SEEK_STAT; |
1597 | s->error = 0x01; | |
1598 | } | |
9cdd03a7 | 1599 | } else if ((bus->cmd & IDE_CMD_RESET) && |
5391d806 FB |
1600 | !(val & IDE_CMD_RESET)) { |
1601 | /* high to low */ | |
1602 | for(i = 0;i < 2; i++) { | |
bcbdc4d3 | 1603 | s = &bus->ifs[i]; |
cd8722bb | 1604 | if (s->drive_kind == IDE_CD) |
6b136f9e FB |
1605 | s->status = 0x00; /* NOTE: READY is _not_ set */ |
1606 | else | |
56bf1d37 | 1607 | s->status = READY_STAT | SEEK_STAT; |
5391d806 FB |
1608 | ide_set_signature(s); |
1609 | } | |
1610 | } | |
1611 | ||
9cdd03a7 | 1612 | bus->cmd = val; |
5391d806 FB |
1613 | } |
1614 | ||
40c4ed3f KW |
1615 | /* |
1616 | * Returns true if the running PIO transfer is a PIO out (i.e. data is | |
1617 | * transferred from the device to the guest), false if it's a PIO in | |
1618 | */ | |
1619 | static bool ide_is_pio_out(IDEState *s) | |
1620 | { | |
1621 | if (s->end_transfer_func == ide_sector_write || | |
1622 | s->end_transfer_func == ide_atapi_cmd) { | |
1623 | return false; | |
1624 | } else if (s->end_transfer_func == ide_sector_read || | |
1625 | s->end_transfer_func == ide_transfer_stop || | |
1626 | s->end_transfer_func == ide_atapi_cmd_reply_end || | |
1627 | s->end_transfer_func == ide_dummy_transfer_stop) { | |
1628 | return true; | |
1629 | } | |
1630 | ||
1631 | abort(); | |
1632 | } | |
1633 | ||
356721ae | 1634 | void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) |
5391d806 | 1635 | { |
bcbdc4d3 GH |
1636 | IDEBus *bus = opaque; |
1637 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1638 | uint8_t *p; |
1639 | ||
40c4ed3f KW |
1640 | /* PIO data access allowed only when DRQ bit is set. The result of a write |
1641 | * during PIO out is indeterminate, just ignore it. */ | |
1642 | if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { | |
fcdd25ab | 1643 | return; |
40c4ed3f | 1644 | } |
fcdd25ab | 1645 | |
5391d806 | 1646 | p = s->data_ptr; |
0c4ad8dc | 1647 | *(uint16_t *)p = le16_to_cpu(val); |
5391d806 FB |
1648 | p += 2; |
1649 | s->data_ptr = p; | |
1650 | if (p >= s->data_end) | |
1651 | s->end_transfer_func(s); | |
1652 | } | |
1653 | ||
356721ae | 1654 | uint32_t ide_data_readw(void *opaque, uint32_t addr) |
5391d806 | 1655 | { |
bcbdc4d3 GH |
1656 | IDEBus *bus = opaque; |
1657 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1658 | uint8_t *p; |
1659 | int ret; | |
fcdd25ab | 1660 | |
40c4ed3f KW |
1661 | /* PIO data access allowed only when DRQ bit is set. The result of a read |
1662 | * during PIO in is indeterminate, return 0 and don't move forward. */ | |
1663 | if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { | |
fcdd25ab | 1664 | return 0; |
40c4ed3f | 1665 | } |
fcdd25ab | 1666 | |
5391d806 | 1667 | p = s->data_ptr; |
0c4ad8dc | 1668 | ret = cpu_to_le16(*(uint16_t *)p); |
5391d806 FB |
1669 | p += 2; |
1670 | s->data_ptr = p; | |
1671 | if (p >= s->data_end) | |
1672 | s->end_transfer_func(s); | |
1673 | return ret; | |
1674 | } | |
1675 | ||
356721ae | 1676 | void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) |
5391d806 | 1677 | { |
bcbdc4d3 GH |
1678 | IDEBus *bus = opaque; |
1679 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1680 | uint8_t *p; |
1681 | ||
40c4ed3f KW |
1682 | /* PIO data access allowed only when DRQ bit is set. The result of a write |
1683 | * during PIO out is indeterminate, just ignore it. */ | |
1684 | if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { | |
fcdd25ab | 1685 | return; |
40c4ed3f | 1686 | } |
fcdd25ab | 1687 | |
5391d806 | 1688 | p = s->data_ptr; |
0c4ad8dc | 1689 | *(uint32_t *)p = le32_to_cpu(val); |
5391d806 FB |
1690 | p += 4; |
1691 | s->data_ptr = p; | |
1692 | if (p >= s->data_end) | |
1693 | s->end_transfer_func(s); | |
1694 | } | |
1695 | ||
356721ae | 1696 | uint32_t ide_data_readl(void *opaque, uint32_t addr) |
5391d806 | 1697 | { |
bcbdc4d3 GH |
1698 | IDEBus *bus = opaque; |
1699 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1700 | uint8_t *p; |
1701 | int ret; | |
3b46e624 | 1702 | |
40c4ed3f KW |
1703 | /* PIO data access allowed only when DRQ bit is set. The result of a read |
1704 | * during PIO in is indeterminate, return 0 and don't move forward. */ | |
1705 | if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { | |
fcdd25ab | 1706 | return 0; |
40c4ed3f | 1707 | } |
fcdd25ab | 1708 | |
5391d806 | 1709 | p = s->data_ptr; |
0c4ad8dc | 1710 | ret = cpu_to_le32(*(uint32_t *)p); |
5391d806 FB |
1711 | p += 4; |
1712 | s->data_ptr = p; | |
1713 | if (p >= s->data_end) | |
1714 | s->end_transfer_func(s); | |
1715 | return ret; | |
1716 | } | |
1717 | ||
a7dfe172 FB |
1718 | static void ide_dummy_transfer_stop(IDEState *s) |
1719 | { | |
1720 | s->data_ptr = s->io_buffer; | |
1721 | s->data_end = s->io_buffer; | |
1722 | s->io_buffer[0] = 0xff; | |
1723 | s->io_buffer[1] = 0xff; | |
1724 | s->io_buffer[2] = 0xff; | |
1725 | s->io_buffer[3] = 0xff; | |
1726 | } | |
1727 | ||
4a643563 | 1728 | static void ide_reset(IDEState *s) |
5391d806 | 1729 | { |
4a643563 BS |
1730 | #ifdef DEBUG_IDE |
1731 | printf("ide: reset\n"); | |
1732 | #endif | |
cd8722bb | 1733 | if (s->drive_kind == IDE_CFATA) |
201a51fc AZ |
1734 | s->mult_sectors = 0; |
1735 | else | |
1736 | s->mult_sectors = MAX_MULT_SECTORS; | |
4a643563 BS |
1737 | /* ide regs */ |
1738 | s->feature = 0; | |
1739 | s->error = 0; | |
1740 | s->nsector = 0; | |
1741 | s->sector = 0; | |
1742 | s->lcyl = 0; | |
1743 | s->hcyl = 0; | |
1744 | ||
1745 | /* lba48 */ | |
1746 | s->hob_feature = 0; | |
1747 | s->hob_sector = 0; | |
1748 | s->hob_nsector = 0; | |
1749 | s->hob_lcyl = 0; | |
1750 | s->hob_hcyl = 0; | |
1751 | ||
5391d806 | 1752 | s->select = 0xa0; |
41a2b959 | 1753 | s->status = READY_STAT | SEEK_STAT; |
4a643563 BS |
1754 | |
1755 | s->lba48 = 0; | |
1756 | ||
1757 | /* ATAPI specific */ | |
1758 | s->sense_key = 0; | |
1759 | s->asc = 0; | |
1760 | s->cdrom_changed = 0; | |
1761 | s->packet_transfer_size = 0; | |
1762 | s->elementary_transfer_size = 0; | |
1763 | s->io_buffer_index = 0; | |
1764 | s->cd_sector_size = 0; | |
1765 | s->atapi_dma = 0; | |
1766 | /* ATA DMA state */ | |
1767 | s->io_buffer_size = 0; | |
1768 | s->req_nb_sectors = 0; | |
1769 | ||
5391d806 | 1770 | ide_set_signature(s); |
a7dfe172 FB |
1771 | /* init the transfer handler so that 0xffff is returned on data |
1772 | accesses */ | |
1773 | s->end_transfer_func = ide_dummy_transfer_stop; | |
1774 | ide_dummy_transfer_stop(s); | |
201a51fc | 1775 | s->media_changed = 0; |
5391d806 FB |
1776 | } |
1777 | ||
4a643563 BS |
1778 | void ide_bus_reset(IDEBus *bus) |
1779 | { | |
1780 | bus->unit = 0; | |
1781 | bus->cmd = 0; | |
1782 | ide_reset(&bus->ifs[0]); | |
1783 | ide_reset(&bus->ifs[1]); | |
1784 | ide_clear_hob(bus); | |
40a6238a AG |
1785 | |
1786 | /* pending async DMA */ | |
1787 | if (bus->dma->aiocb) { | |
1788 | #ifdef DEBUG_AIO | |
1789 | printf("aio_cancel\n"); | |
1790 | #endif | |
1791 | bdrv_aio_cancel(bus->dma->aiocb); | |
1792 | bus->dma->aiocb = NULL; | |
1793 | } | |
1794 | ||
1795 | /* reset dma provider too */ | |
1796 | bus->dma->ops->reset(bus->dma); | |
4a643563 BS |
1797 | } |
1798 | ||
e4def80b MA |
1799 | static bool ide_cd_is_tray_open(void *opaque) |
1800 | { | |
1801 | return ((IDEState *)opaque)->tray_open; | |
1802 | } | |
1803 | ||
f107639a MA |
1804 | static bool ide_cd_is_medium_locked(void *opaque) |
1805 | { | |
1806 | return ((IDEState *)opaque)->tray_locked; | |
1807 | } | |
1808 | ||
0e49de52 | 1809 | static const BlockDevOps ide_cd_block_ops = { |
145feb17 | 1810 | .change_media_cb = ide_cd_change_cb, |
e4def80b | 1811 | .is_tray_open = ide_cd_is_tray_open, |
f107639a | 1812 | .is_medium_locked = ide_cd_is_medium_locked, |
0e49de52 MA |
1813 | }; |
1814 | ||
1f56e32a | 1815 | int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind, |
c4d74df7 | 1816 | const char *version, const char *serial) |
88804180 GH |
1817 | { |
1818 | int cylinders, heads, secs; | |
1819 | uint64_t nb_sectors; | |
1820 | ||
f8b6cc00 | 1821 | s->bs = bs; |
1f56e32a MA |
1822 | s->drive_kind = kind; |
1823 | ||
f8b6cc00 MA |
1824 | bdrv_get_geometry(bs, &nb_sectors); |
1825 | bdrv_guess_geometry(bs, &cylinders, &heads, &secs); | |
dce9e928 MA |
1826 | if (cylinders < 1 || cylinders > 16383) { |
1827 | error_report("cyls must be between 1 and 16383"); | |
1828 | return -1; | |
1829 | } | |
1830 | if (heads < 1 || heads > 16) { | |
1831 | error_report("heads must be between 1 and 16"); | |
1832 | return -1; | |
1833 | } | |
1834 | if (secs < 1 || secs > 63) { | |
1835 | error_report("secs must be between 1 and 63"); | |
1836 | return -1; | |
1837 | } | |
870111c8 MA |
1838 | s->cylinders = cylinders; |
1839 | s->heads = heads; | |
1840 | s->sectors = secs; | |
1841 | s->nb_sectors = nb_sectors; | |
1842 | /* The SMART values should be preserved across power cycles | |
1843 | but they aren't. */ | |
1844 | s->smart_enabled = 1; | |
1845 | s->smart_autosave = 1; | |
1846 | s->smart_errors = 0; | |
1847 | s->smart_selftest_count = 0; | |
1f56e32a | 1848 | if (kind == IDE_CD) { |
0e49de52 | 1849 | bdrv_set_dev_ops(bs, &ide_cd_block_ops, s); |
7b6f9300 | 1850 | bdrv_set_buffer_alignment(bs, 2048); |
7aa9c811 | 1851 | } else { |
98f28ad7 MA |
1852 | if (!bdrv_is_inserted(s->bs)) { |
1853 | error_report("Device needs media, but drive is empty"); | |
1854 | return -1; | |
1855 | } | |
7aa9c811 MA |
1856 | if (bdrv_is_read_only(bs)) { |
1857 | error_report("Can't use a read-only drive"); | |
1858 | return -1; | |
1859 | } | |
88804180 | 1860 | } |
f8b6cc00 | 1861 | if (serial) { |
6ced55a5 MA |
1862 | strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str)); |
1863 | } else { | |
88804180 GH |
1864 | snprintf(s->drive_serial_str, sizeof(s->drive_serial_str), |
1865 | "QM%05d", s->drive_serial); | |
870111c8 | 1866 | } |
47c06340 GH |
1867 | if (version) { |
1868 | pstrcpy(s->version, sizeof(s->version), version); | |
1869 | } else { | |
1870 | pstrcpy(s->version, sizeof(s->version), QEMU_VERSION); | |
1871 | } | |
40a6238a | 1872 | |
88804180 | 1873 | ide_reset(s); |
c4d74df7 | 1874 | return 0; |
88804180 GH |
1875 | } |
1876 | ||
57234ee4 | 1877 | static void ide_init1(IDEBus *bus, int unit) |
d459da0e MA |
1878 | { |
1879 | static int drive_serial = 1; | |
1880 | IDEState *s = &bus->ifs[unit]; | |
1881 | ||
1882 | s->bus = bus; | |
1883 | s->unit = unit; | |
1884 | s->drive_serial = drive_serial++; | |
1b2adf28 | 1885 | /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ |
50641c5c | 1886 | s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; |
c925400b KW |
1887 | s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); |
1888 | memset(s->io_buffer, 0, s->io_buffer_total_len); | |
1889 | ||
d459da0e | 1890 | s->smart_selftest_data = qemu_blockalign(s->bs, 512); |
c925400b KW |
1891 | memset(s->smart_selftest_data, 0, 512); |
1892 | ||
74475455 | 1893 | s->sector_write_timer = qemu_new_timer_ns(vm_clock, |
d459da0e | 1894 | ide_sector_write_timer_cb, s); |
57234ee4 MA |
1895 | } |
1896 | ||
40a6238a AG |
1897 | static void ide_nop_start(IDEDMA *dma, IDEState *s, |
1898 | BlockDriverCompletionFunc *cb) | |
1899 | { | |
1900 | } | |
1901 | ||
1902 | static int ide_nop(IDEDMA *dma) | |
1903 | { | |
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | static int ide_nop_int(IDEDMA *dma, int x) | |
1908 | { | |
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | static void ide_nop_restart(void *opaque, int x, int y) | |
1913 | { | |
1914 | } | |
1915 | ||
1916 | static const IDEDMAOps ide_dma_nop_ops = { | |
1917 | .start_dma = ide_nop_start, | |
1918 | .start_transfer = ide_nop, | |
1919 | .prepare_buf = ide_nop_int, | |
1920 | .rw_buf = ide_nop_int, | |
1921 | .set_unit = ide_nop_int, | |
1922 | .add_status = ide_nop_int, | |
1923 | .set_inactive = ide_nop, | |
1924 | .restart_cb = ide_nop_restart, | |
1925 | .reset = ide_nop, | |
1926 | }; | |
1927 | ||
1928 | static IDEDMA ide_dma_nop = { | |
1929 | .ops = &ide_dma_nop_ops, | |
1930 | .aiocb = NULL, | |
1931 | }; | |
1932 | ||
57234ee4 MA |
1933 | void ide_init2(IDEBus *bus, qemu_irq irq) |
1934 | { | |
1935 | int i; | |
1936 | ||
1937 | for(i = 0; i < 2; i++) { | |
1938 | ide_init1(bus, i); | |
1939 | ide_reset(&bus->ifs[i]); | |
870111c8 | 1940 | } |
57234ee4 | 1941 | bus->irq = irq; |
40a6238a | 1942 | bus->dma = &ide_dma_nop; |
d459da0e MA |
1943 | } |
1944 | ||
57234ee4 MA |
1945 | /* TODO convert users to qdev and remove */ |
1946 | void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0, | |
1947 | DriveInfo *hd1, qemu_irq irq) | |
5391d806 | 1948 | { |
88804180 | 1949 | int i; |
57234ee4 | 1950 | DriveInfo *dinfo; |
5391d806 | 1951 | |
caed8802 | 1952 | for(i = 0; i < 2; i++) { |
57234ee4 MA |
1953 | dinfo = i == 0 ? hd0 : hd1; |
1954 | ide_init1(bus, i); | |
1955 | if (dinfo) { | |
1f56e32a | 1956 | if (ide_init_drive(&bus->ifs[i], dinfo->bdrv, |
95b5edcd | 1957 | dinfo->media_cd ? IDE_CD : IDE_HD, NULL, |
c4d74df7 MA |
1958 | *dinfo->serial ? dinfo->serial : NULL) < 0) { |
1959 | error_report("Can't set up IDE drive %s", dinfo->id); | |
1960 | exit(1); | |
1961 | } | |
fa879d62 | 1962 | bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]); |
57234ee4 MA |
1963 | } else { |
1964 | ide_reset(&bus->ifs[i]); | |
1965 | } | |
5391d806 | 1966 | } |
9cdd03a7 | 1967 | bus->irq = irq; |
40a6238a | 1968 | bus->dma = &ide_dma_nop; |
69b91039 FB |
1969 | } |
1970 | ||
356721ae | 1971 | void ide_init_ioport(IDEBus *bus, int iobase, int iobase2) |
69b91039 | 1972 | { |
bcbdc4d3 GH |
1973 | register_ioport_write(iobase, 8, 1, ide_ioport_write, bus); |
1974 | register_ioport_read(iobase, 8, 1, ide_ioport_read, bus); | |
caed8802 | 1975 | if (iobase2) { |
bcbdc4d3 GH |
1976 | register_ioport_read(iobase2, 1, 1, ide_status_read, bus); |
1977 | register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus); | |
5391d806 | 1978 | } |
3b46e624 | 1979 | |
caed8802 | 1980 | /* data ports */ |
bcbdc4d3 GH |
1981 | register_ioport_write(iobase, 2, 2, ide_data_writew, bus); |
1982 | register_ioport_read(iobase, 2, 2, ide_data_readw, bus); | |
1983 | register_ioport_write(iobase, 4, 4, ide_data_writel, bus); | |
1984 | register_ioport_read(iobase, 4, 4, ide_data_readl, bus); | |
5391d806 | 1985 | } |
69b91039 | 1986 | |
37159f13 | 1987 | static bool is_identify_set(void *opaque, int version_id) |
aa941b94 | 1988 | { |
37159f13 JQ |
1989 | IDEState *s = opaque; |
1990 | ||
1991 | return s->identify_set != 0; | |
1992 | } | |
1993 | ||
50641c5c JQ |
1994 | static EndTransferFunc* transfer_end_table[] = { |
1995 | ide_sector_read, | |
1996 | ide_sector_write, | |
1997 | ide_transfer_stop, | |
1998 | ide_atapi_cmd_reply_end, | |
1999 | ide_atapi_cmd, | |
2000 | ide_dummy_transfer_stop, | |
2001 | }; | |
2002 | ||
2003 | static int transfer_end_table_idx(EndTransferFunc *fn) | |
2004 | { | |
2005 | int i; | |
2006 | ||
2007 | for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) | |
2008 | if (transfer_end_table[i] == fn) | |
2009 | return i; | |
2010 | ||
2011 | return -1; | |
2012 | } | |
2013 | ||
37159f13 | 2014 | static int ide_drive_post_load(void *opaque, int version_id) |
aa941b94 | 2015 | { |
37159f13 JQ |
2016 | IDEState *s = opaque; |
2017 | ||
2018 | if (version_id < 3) { | |
93c8cfd9 | 2019 | if (s->sense_key == SENSE_UNIT_ATTENTION && |
37159f13 | 2020 | s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) { |
93c8cfd9 | 2021 | s->cdrom_changed = 1; |
37159f13 | 2022 | } |
93c8cfd9 | 2023 | } |
37159f13 | 2024 | return 0; |
aa941b94 AZ |
2025 | } |
2026 | ||
50641c5c JQ |
2027 | static int ide_drive_pio_post_load(void *opaque, int version_id) |
2028 | { | |
2029 | IDEState *s = opaque; | |
2030 | ||
7bccf573 | 2031 | if (s->end_transfer_fn_idx > ARRAY_SIZE(transfer_end_table)) { |
50641c5c JQ |
2032 | return -EINVAL; |
2033 | } | |
2034 | s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; | |
2035 | s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; | |
2036 | s->data_end = s->data_ptr + s->cur_io_buffer_len; | |
2037 | ||
2038 | return 0; | |
2039 | } | |
2040 | ||
2041 | static void ide_drive_pio_pre_save(void *opaque) | |
2042 | { | |
2043 | IDEState *s = opaque; | |
2044 | int idx; | |
2045 | ||
2046 | s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; | |
2047 | s->cur_io_buffer_len = s->data_end - s->data_ptr; | |
2048 | ||
2049 | idx = transfer_end_table_idx(s->end_transfer_func); | |
2050 | if (idx == -1) { | |
2051 | fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n", | |
2052 | __func__); | |
2053 | s->end_transfer_fn_idx = 2; | |
2054 | } else { | |
2055 | s->end_transfer_fn_idx = idx; | |
2056 | } | |
2057 | } | |
2058 | ||
2059 | static bool ide_drive_pio_state_needed(void *opaque) | |
2060 | { | |
2061 | IDEState *s = opaque; | |
2062 | ||
fdc650d7 KW |
2063 | return ((s->status & DRQ_STAT) != 0) |
2064 | || (s->bus->error_status & BM_STATUS_PIO_RETRY); | |
50641c5c JQ |
2065 | } |
2066 | ||
db118fe7 MA |
2067 | static int ide_tray_state_post_load(void *opaque, int version_id) |
2068 | { | |
2069 | IDEState *s = opaque; | |
2070 | ||
2071 | bdrv_eject(s->bs, s->tray_open); | |
2072 | bdrv_lock_medium(s->bs, s->tray_locked); | |
2073 | return 0; | |
2074 | } | |
2075 | ||
2076 | static bool ide_tray_state_needed(void *opaque) | |
2077 | { | |
2078 | IDEState *s = opaque; | |
2079 | ||
2080 | return s->tray_open || s->tray_locked; | |
2081 | } | |
2082 | ||
996faf1a AS |
2083 | static bool ide_atapi_gesn_needed(void *opaque) |
2084 | { | |
2085 | IDEState *s = opaque; | |
2086 | ||
2087 | return s->events.new_media || s->events.eject_request; | |
2088 | } | |
2089 | ||
def93791 KW |
2090 | static bool ide_error_needed(void *opaque) |
2091 | { | |
2092 | IDEBus *bus = opaque; | |
2093 | ||
2094 | return (bus->error_status != 0); | |
2095 | } | |
2096 | ||
996faf1a | 2097 | /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */ |
656fbeff | 2098 | static const VMStateDescription vmstate_ide_atapi_gesn_state = { |
996faf1a AS |
2099 | .name ="ide_drive/atapi/gesn_state", |
2100 | .version_id = 1, | |
2101 | .minimum_version_id = 1, | |
2102 | .minimum_version_id_old = 1, | |
2103 | .fields = (VMStateField []) { | |
2104 | VMSTATE_BOOL(events.new_media, IDEState), | |
2105 | VMSTATE_BOOL(events.eject_request, IDEState), | |
0754f9ec | 2106 | VMSTATE_END_OF_LIST() |
996faf1a AS |
2107 | } |
2108 | }; | |
2109 | ||
db118fe7 MA |
2110 | static const VMStateDescription vmstate_ide_tray_state = { |
2111 | .name = "ide_drive/tray_state", | |
2112 | .version_id = 1, | |
2113 | .minimum_version_id = 1, | |
2114 | .minimum_version_id_old = 1, | |
2115 | .post_load = ide_tray_state_post_load, | |
2116 | .fields = (VMStateField[]) { | |
2117 | VMSTATE_BOOL(tray_open, IDEState), | |
2118 | VMSTATE_BOOL(tray_locked, IDEState), | |
2119 | VMSTATE_END_OF_LIST() | |
2120 | } | |
2121 | }; | |
2122 | ||
656fbeff | 2123 | static const VMStateDescription vmstate_ide_drive_pio_state = { |
50641c5c JQ |
2124 | .name = "ide_drive/pio_state", |
2125 | .version_id = 1, | |
2126 | .minimum_version_id = 1, | |
2127 | .minimum_version_id_old = 1, | |
2128 | .pre_save = ide_drive_pio_pre_save, | |
2129 | .post_load = ide_drive_pio_post_load, | |
2130 | .fields = (VMStateField []) { | |
2131 | VMSTATE_INT32(req_nb_sectors, IDEState), | |
2132 | VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1, | |
2133 | vmstate_info_uint8, uint8_t), | |
2134 | VMSTATE_INT32(cur_io_buffer_offset, IDEState), | |
2135 | VMSTATE_INT32(cur_io_buffer_len, IDEState), | |
2136 | VMSTATE_UINT8(end_transfer_fn_idx, IDEState), | |
2137 | VMSTATE_INT32(elementary_transfer_size, IDEState), | |
2138 | VMSTATE_INT32(packet_transfer_size, IDEState), | |
2139 | VMSTATE_END_OF_LIST() | |
2140 | } | |
2141 | }; | |
2142 | ||
37159f13 JQ |
2143 | const VMStateDescription vmstate_ide_drive = { |
2144 | .name = "ide_drive", | |
3abb6260 | 2145 | .version_id = 3, |
37159f13 JQ |
2146 | .minimum_version_id = 0, |
2147 | .minimum_version_id_old = 0, | |
2148 | .post_load = ide_drive_post_load, | |
2149 | .fields = (VMStateField []) { | |
2150 | VMSTATE_INT32(mult_sectors, IDEState), | |
2151 | VMSTATE_INT32(identify_set, IDEState), | |
2152 | VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), | |
2153 | VMSTATE_UINT8(feature, IDEState), | |
2154 | VMSTATE_UINT8(error, IDEState), | |
2155 | VMSTATE_UINT32(nsector, IDEState), | |
2156 | VMSTATE_UINT8(sector, IDEState), | |
2157 | VMSTATE_UINT8(lcyl, IDEState), | |
2158 | VMSTATE_UINT8(hcyl, IDEState), | |
2159 | VMSTATE_UINT8(hob_feature, IDEState), | |
2160 | VMSTATE_UINT8(hob_sector, IDEState), | |
2161 | VMSTATE_UINT8(hob_nsector, IDEState), | |
2162 | VMSTATE_UINT8(hob_lcyl, IDEState), | |
2163 | VMSTATE_UINT8(hob_hcyl, IDEState), | |
2164 | VMSTATE_UINT8(select, IDEState), | |
2165 | VMSTATE_UINT8(status, IDEState), | |
2166 | VMSTATE_UINT8(lba48, IDEState), | |
2167 | VMSTATE_UINT8(sense_key, IDEState), | |
2168 | VMSTATE_UINT8(asc, IDEState), | |
2169 | VMSTATE_UINT8_V(cdrom_changed, IDEState, 3), | |
37159f13 | 2170 | VMSTATE_END_OF_LIST() |
50641c5c JQ |
2171 | }, |
2172 | .subsections = (VMStateSubsection []) { | |
2173 | { | |
2174 | .vmsd = &vmstate_ide_drive_pio_state, | |
2175 | .needed = ide_drive_pio_state_needed, | |
db118fe7 MA |
2176 | }, { |
2177 | .vmsd = &vmstate_ide_tray_state, | |
2178 | .needed = ide_tray_state_needed, | |
996faf1a AS |
2179 | }, { |
2180 | .vmsd = &vmstate_ide_atapi_gesn_state, | |
2181 | .needed = ide_atapi_gesn_needed, | |
50641c5c JQ |
2182 | }, { |
2183 | /* empty */ | |
2184 | } | |
37159f13 JQ |
2185 | } |
2186 | }; | |
2187 | ||
656fbeff | 2188 | static const VMStateDescription vmstate_ide_error_status = { |
def93791 KW |
2189 | .name ="ide_bus/error", |
2190 | .version_id = 1, | |
2191 | .minimum_version_id = 1, | |
2192 | .minimum_version_id_old = 1, | |
2193 | .fields = (VMStateField []) { | |
2194 | VMSTATE_INT32(error_status, IDEBus), | |
2195 | VMSTATE_END_OF_LIST() | |
2196 | } | |
2197 | }; | |
2198 | ||
6521dc62 JQ |
2199 | const VMStateDescription vmstate_ide_bus = { |
2200 | .name = "ide_bus", | |
2201 | .version_id = 1, | |
2202 | .minimum_version_id = 1, | |
2203 | .minimum_version_id_old = 1, | |
2204 | .fields = (VMStateField []) { | |
2205 | VMSTATE_UINT8(cmd, IDEBus), | |
2206 | VMSTATE_UINT8(unit, IDEBus), | |
2207 | VMSTATE_END_OF_LIST() | |
def93791 KW |
2208 | }, |
2209 | .subsections = (VMStateSubsection []) { | |
2210 | { | |
2211 | .vmsd = &vmstate_ide_error_status, | |
2212 | .needed = ide_error_needed, | |
2213 | }, { | |
2214 | /* empty */ | |
2215 | } | |
6521dc62 JQ |
2216 | } |
2217 | }; | |
75717903 IY |
2218 | |
2219 | void ide_drive_get(DriveInfo **hd, int max_bus) | |
2220 | { | |
2221 | int i; | |
2222 | ||
2223 | if (drive_get_max_bus(IF_IDE) >= max_bus) { | |
2224 | fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus); | |
2225 | exit(1); | |
2226 | } | |
2227 | ||
2228 | for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) { | |
2229 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
2230 | } | |
2231 | } |