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Commit | Line | Data |
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5391d806 | 1 | /* |
38cdea7c | 2 | * QEMU IDE disk and CD/DVD-ROM Emulator |
5fafdf24 | 3 | * |
5391d806 | 4 | * Copyright (c) 2003 Fabrice Bellard |
201a51fc | 5 | * Copyright (c) 2006 Openedhand Ltd. |
5fafdf24 | 6 | * |
5391d806 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
59f2a787 GH |
25 | #include <hw/hw.h> |
26 | #include <hw/pc.h> | |
27 | #include <hw/pci.h> | |
4a91d3b3 | 28 | #include <hw/isa.h> |
c4d74df7 | 29 | #include "qemu-error.h" |
87ecb68b PB |
30 | #include "qemu-timer.h" |
31 | #include "sysemu.h" | |
1fb8648d | 32 | #include "dma.h" |
2446333c | 33 | #include "blockdev.h" |
d1a0739d | 34 | #include "block_int.h" |
59f2a787 GH |
35 | |
36 | #include <hw/ide/internal.h> | |
e8b54394 | 37 | |
b93af93d BW |
38 | /* These values were based on a Seagate ST3500418AS but have been modified |
39 | to make more sense in QEMU */ | |
40 | static const int smart_attributes[][12] = { | |
41 | /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */ | |
42 | /* raw read error rate*/ | |
43 | { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06}, | |
44 | /* spin up */ | |
45 | { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
46 | /* start stop count */ | |
47 | { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14}, | |
48 | /* remapped sectors */ | |
49 | { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24}, | |
50 | /* power on hours */ | |
51 | { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
52 | /* power cycle count */ | |
53 | { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
54 | /* airflow-temperature-celsius */ | |
55 | { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32}, | |
56 | /* end of list */ | |
57 | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} | |
e8b54394 BW |
58 | }; |
59 | ||
ce4b6522 | 60 | static int ide_handle_rw_error(IDEState *s, int error, int op); |
40c4ed3f | 61 | static void ide_dummy_transfer_stop(IDEState *s); |
98087450 | 62 | |
5391d806 FB |
63 | static void padstr(char *str, const char *src, int len) |
64 | { | |
65 | int i, v; | |
66 | for(i = 0; i < len; i++) { | |
67 | if (*src) | |
68 | v = *src++; | |
69 | else | |
70 | v = ' '; | |
69b34976 | 71 | str[i^1] = v; |
5391d806 FB |
72 | } |
73 | } | |
74 | ||
67b915a5 FB |
75 | static void put_le16(uint16_t *p, unsigned int v) |
76 | { | |
0c4ad8dc | 77 | *p = cpu_to_le16(v); |
67b915a5 FB |
78 | } |
79 | ||
5391d806 FB |
80 | static void ide_identify(IDEState *s) |
81 | { | |
82 | uint16_t *p; | |
83 | unsigned int oldsize; | |
d353fb72 | 84 | IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; |
5391d806 | 85 | |
94458802 FB |
86 | if (s->identify_set) { |
87 | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); | |
88 | return; | |
89 | } | |
90 | ||
5391d806 FB |
91 | memset(s->io_buffer, 0, 512); |
92 | p = (uint16_t *)s->io_buffer; | |
67b915a5 | 93 | put_le16(p + 0, 0x0040); |
5fafdf24 | 94 | put_le16(p + 1, s->cylinders); |
67b915a5 FB |
95 | put_le16(p + 3, s->heads); |
96 | put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ | |
97 | put_le16(p + 5, 512); /* XXX: retired, remove ? */ | |
5fafdf24 | 98 | put_le16(p + 6, s->sectors); |
fa879c64 | 99 | padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
67b915a5 FB |
100 | put_le16(p + 20, 3); /* XXX: retired, remove ? */ |
101 | put_le16(p + 21, 512); /* cache size in sectors */ | |
102 | put_le16(p + 22, 4); /* ecc bytes */ | |
47c06340 | 103 | padstr((char *)(p + 23), s->version, 8); /* firmware version */ |
60fe76f3 | 104 | padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */ |
3b46e624 | 105 | #if MAX_MULT_SECTORS > 1 |
67b915a5 | 106 | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
5391d806 | 107 | #endif |
67b915a5 | 108 | put_le16(p + 48, 1); /* dword I/O */ |
94458802 | 109 | put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ |
67b915a5 FB |
110 | put_le16(p + 51, 0x200); /* PIO transfer cycle */ |
111 | put_le16(p + 52, 0x200); /* DMA transfer cycle */ | |
94458802 | 112 | put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ |
67b915a5 FB |
113 | put_le16(p + 54, s->cylinders); |
114 | put_le16(p + 55, s->heads); | |
115 | put_le16(p + 56, s->sectors); | |
5391d806 | 116 | oldsize = s->cylinders * s->heads * s->sectors; |
67b915a5 FB |
117 | put_le16(p + 57, oldsize); |
118 | put_le16(p + 58, oldsize >> 16); | |
5391d806 | 119 | if (s->mult_sectors) |
67b915a5 FB |
120 | put_le16(p + 59, 0x100 | s->mult_sectors); |
121 | put_le16(p + 60, s->nb_sectors); | |
122 | put_le16(p + 61, s->nb_sectors >> 16); | |
d1b5c20d | 123 | put_le16(p + 62, 0x07); /* single word dma0-2 supported */ |
94458802 | 124 | put_le16(p + 63, 0x07); /* mdma0-2 supported */ |
79d1d331 | 125 | put_le16(p + 64, 0x03); /* pio3-4 supported */ |
94458802 FB |
126 | put_le16(p + 65, 120); |
127 | put_le16(p + 66, 120); | |
128 | put_le16(p + 67, 120); | |
129 | put_le16(p + 68, 120); | |
d353fb72 CH |
130 | if (dev && dev->conf.discard_granularity) { |
131 | put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ | |
132 | } | |
ccf0fd8b RE |
133 | |
134 | if (s->ncq_queues) { | |
135 | put_le16(p + 75, s->ncq_queues - 1); | |
136 | /* NCQ supported */ | |
137 | put_le16(p + 76, (1 << 8)); | |
138 | } | |
139 | ||
94458802 FB |
140 | put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ |
141 | put_le16(p + 81, 0x16); /* conforms to ata5 */ | |
a58b8d54 CH |
142 | /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ |
143 | put_le16(p + 82, (1 << 14) | (1 << 5) | 1); | |
c2ff060f FB |
144 | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ |
145 | put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); | |
e8b54394 BW |
146 | /* 14=set to 1, 1=SMART self test, 0=SMART error logging */ |
147 | put_le16(p + 84, (1 << 14) | 0); | |
e900a7b7 CH |
148 | /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */ |
149 | if (bdrv_enable_write_cache(s->bs)) | |
150 | put_le16(p + 85, (1 << 14) | (1 << 5) | 1); | |
151 | else | |
152 | put_le16(p + 85, (1 << 14) | 1); | |
c2ff060f FB |
153 | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ |
154 | put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); | |
e8b54394 BW |
155 | /* 14=set to 1, 1=smart self test, 0=smart error logging */ |
156 | put_le16(p + 87, (1 << 14) | 0); | |
94458802 FB |
157 | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
158 | put_le16(p + 93, 1 | (1 << 14) | 0x2000); | |
c2ff060f FB |
159 | put_le16(p + 100, s->nb_sectors); |
160 | put_le16(p + 101, s->nb_sectors >> 16); | |
161 | put_le16(p + 102, s->nb_sectors >> 32); | |
162 | put_le16(p + 103, s->nb_sectors >> 48); | |
d353fb72 | 163 | |
57dac7ef MA |
164 | if (dev && dev->conf.physical_block_size) |
165 | put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); | |
d353fb72 CH |
166 | if (dev && dev->conf.discard_granularity) { |
167 | put_le16(p + 169, 1); /* TRIM support */ | |
168 | } | |
94458802 FB |
169 | |
170 | memcpy(s->identify_data, p, sizeof(s->identify_data)); | |
171 | s->identify_set = 1; | |
5391d806 FB |
172 | } |
173 | ||
174 | static void ide_atapi_identify(IDEState *s) | |
175 | { | |
176 | uint16_t *p; | |
177 | ||
94458802 FB |
178 | if (s->identify_set) { |
179 | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); | |
180 | return; | |
181 | } | |
182 | ||
5391d806 FB |
183 | memset(s->io_buffer, 0, 512); |
184 | p = (uint16_t *)s->io_buffer; | |
185 | /* Removable CDROM, 50us response, 12 byte packets */ | |
67b915a5 | 186 | put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); |
fa879c64 | 187 | padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
67b915a5 FB |
188 | put_le16(p + 20, 3); /* buffer type */ |
189 | put_le16(p + 21, 512); /* cache size in sectors */ | |
190 | put_le16(p + 22, 4); /* ecc bytes */ | |
47c06340 | 191 | padstr((char *)(p + 23), s->version, 8); /* firmware version */ |
38cdea7c | 192 | padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */ |
67b915a5 | 193 | put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ |
8ccad811 FB |
194 | #ifdef USE_DMA_CDROM |
195 | put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ | |
196 | put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ | |
d1b5c20d | 197 | put_le16(p + 62, 7); /* single word dma0-2 supported */ |
8ccad811 | 198 | put_le16(p + 63, 7); /* mdma0-2 supported */ |
8ccad811 | 199 | #else |
67b915a5 FB |
200 | put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ |
201 | put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ | |
202 | put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ | |
8ccad811 | 203 | #endif |
79d1d331 | 204 | put_le16(p + 64, 3); /* pio3-4 supported */ |
67b915a5 FB |
205 | put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ |
206 | put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ | |
207 | put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ | |
208 | put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ | |
94458802 | 209 | |
67b915a5 FB |
210 | put_le16(p + 71, 30); /* in ns */ |
211 | put_le16(p + 72, 30); /* in ns */ | |
5391d806 | 212 | |
1bdaa28d AG |
213 | if (s->ncq_queues) { |
214 | put_le16(p + 75, s->ncq_queues - 1); | |
215 | /* NCQ supported */ | |
216 | put_le16(p + 76, (1 << 8)); | |
217 | } | |
218 | ||
67b915a5 | 219 | put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ |
8ccad811 FB |
220 | #ifdef USE_DMA_CDROM |
221 | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ | |
222 | #endif | |
94458802 FB |
223 | memcpy(s->identify_data, p, sizeof(s->identify_data)); |
224 | s->identify_set = 1; | |
5391d806 FB |
225 | } |
226 | ||
201a51fc AZ |
227 | static void ide_cfata_identify(IDEState *s) |
228 | { | |
229 | uint16_t *p; | |
230 | uint32_t cur_sec; | |
201a51fc AZ |
231 | |
232 | p = (uint16_t *) s->identify_data; | |
233 | if (s->identify_set) | |
234 | goto fill_buffer; | |
235 | ||
236 | memset(p, 0, sizeof(s->identify_data)); | |
237 | ||
238 | cur_sec = s->cylinders * s->heads * s->sectors; | |
239 | ||
240 | put_le16(p + 0, 0x848a); /* CF Storage Card signature */ | |
241 | put_le16(p + 1, s->cylinders); /* Default cylinders */ | |
242 | put_le16(p + 3, s->heads); /* Default heads */ | |
243 | put_le16(p + 6, s->sectors); /* Default sectors per track */ | |
244 | put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ | |
245 | put_le16(p + 8, s->nb_sectors); /* Sectors per card */ | |
fa879c64 | 246 | padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
201a51fc | 247 | put_le16(p + 22, 0x0004); /* ECC bytes */ |
47c06340 | 248 | padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ |
60fe76f3 | 249 | padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */ |
201a51fc AZ |
250 | #if MAX_MULT_SECTORS > 1 |
251 | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); | |
252 | #else | |
253 | put_le16(p + 47, 0x0000); | |
254 | #endif | |
255 | put_le16(p + 49, 0x0f00); /* Capabilities */ | |
256 | put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ | |
257 | put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ | |
258 | put_le16(p + 53, 0x0003); /* Translation params valid */ | |
259 | put_le16(p + 54, s->cylinders); /* Current cylinders */ | |
260 | put_le16(p + 55, s->heads); /* Current heads */ | |
261 | put_le16(p + 56, s->sectors); /* Current sectors */ | |
262 | put_le16(p + 57, cur_sec); /* Current capacity */ | |
263 | put_le16(p + 58, cur_sec >> 16); /* Current capacity */ | |
264 | if (s->mult_sectors) /* Multiple sector setting */ | |
265 | put_le16(p + 59, 0x100 | s->mult_sectors); | |
266 | put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ | |
267 | put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ | |
268 | put_le16(p + 63, 0x0203); /* Multiword DMA capability */ | |
269 | put_le16(p + 64, 0x0001); /* Flow Control PIO support */ | |
270 | put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ | |
271 | put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ | |
272 | put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ | |
273 | put_le16(p + 82, 0x400c); /* Command Set supported */ | |
274 | put_le16(p + 83, 0x7068); /* Command Set supported */ | |
275 | put_le16(p + 84, 0x4000); /* Features supported */ | |
276 | put_le16(p + 85, 0x000c); /* Command Set enabled */ | |
277 | put_le16(p + 86, 0x7044); /* Command Set enabled */ | |
278 | put_le16(p + 87, 0x4000); /* Features enabled */ | |
279 | put_le16(p + 91, 0x4060); /* Current APM level */ | |
280 | put_le16(p + 129, 0x0002); /* Current features option */ | |
281 | put_le16(p + 130, 0x0005); /* Reassigned sectors */ | |
282 | put_le16(p + 131, 0x0001); /* Initial power mode */ | |
283 | put_le16(p + 132, 0x0000); /* User signature */ | |
284 | put_le16(p + 160, 0x8100); /* Power requirement */ | |
285 | put_le16(p + 161, 0x8001); /* CF command set */ | |
286 | ||
287 | s->identify_set = 1; | |
288 | ||
289 | fill_buffer: | |
290 | memcpy(s->io_buffer, p, sizeof(s->identify_data)); | |
291 | } | |
292 | ||
5391d806 FB |
293 | static void ide_set_signature(IDEState *s) |
294 | { | |
295 | s->select &= 0xf0; /* clear head */ | |
296 | /* put signature */ | |
297 | s->nsector = 1; | |
298 | s->sector = 1; | |
cd8722bb | 299 | if (s->drive_kind == IDE_CD) { |
5391d806 FB |
300 | s->lcyl = 0x14; |
301 | s->hcyl = 0xeb; | |
302 | } else if (s->bs) { | |
303 | s->lcyl = 0; | |
304 | s->hcyl = 0; | |
305 | } else { | |
306 | s->lcyl = 0xff; | |
307 | s->hcyl = 0xff; | |
308 | } | |
309 | } | |
310 | ||
d353fb72 CH |
311 | typedef struct TrimAIOCB { |
312 | BlockDriverAIOCB common; | |
313 | QEMUBH *bh; | |
314 | int ret; | |
315 | } TrimAIOCB; | |
316 | ||
317 | static void trim_aio_cancel(BlockDriverAIOCB *acb) | |
318 | { | |
319 | TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); | |
320 | ||
321 | qemu_bh_delete(iocb->bh); | |
322 | iocb->bh = NULL; | |
323 | qemu_aio_release(iocb); | |
324 | } | |
325 | ||
326 | static AIOPool trim_aio_pool = { | |
327 | .aiocb_size = sizeof(TrimAIOCB), | |
328 | .cancel = trim_aio_cancel, | |
329 | }; | |
330 | ||
331 | static void ide_trim_bh_cb(void *opaque) | |
332 | { | |
333 | TrimAIOCB *iocb = opaque; | |
334 | ||
335 | iocb->common.cb(iocb->common.opaque, iocb->ret); | |
336 | ||
337 | qemu_bh_delete(iocb->bh); | |
338 | iocb->bh = NULL; | |
339 | ||
340 | qemu_aio_release(iocb); | |
341 | } | |
342 | ||
343 | BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs, | |
344 | int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, | |
345 | BlockDriverCompletionFunc *cb, void *opaque) | |
346 | { | |
347 | TrimAIOCB *iocb; | |
348 | int i, j, ret; | |
349 | ||
350 | iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque); | |
351 | iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); | |
352 | iocb->ret = 0; | |
353 | ||
354 | for (j = 0; j < qiov->niov; j++) { | |
355 | uint64_t *buffer = qiov->iov[j].iov_base; | |
356 | ||
357 | for (i = 0; i < qiov->iov[j].iov_len / 8; i++) { | |
358 | /* 6-byte LBA + 2-byte range per entry */ | |
359 | uint64_t entry = le64_to_cpu(buffer[i]); | |
360 | uint64_t sector = entry & 0x0000ffffffffffffULL; | |
361 | uint16_t count = entry >> 48; | |
362 | ||
363 | if (count == 0) { | |
364 | break; | |
365 | } | |
366 | ||
367 | ret = bdrv_discard(bs, sector, count); | |
368 | if (!iocb->ret) { | |
369 | iocb->ret = ret; | |
370 | } | |
371 | } | |
372 | } | |
373 | ||
374 | qemu_bh_schedule(iocb->bh); | |
375 | ||
376 | return &iocb->common; | |
377 | } | |
378 | ||
5391d806 FB |
379 | static inline void ide_abort_command(IDEState *s) |
380 | { | |
381 | s->status = READY_STAT | ERR_STAT; | |
382 | s->error = ABRT_ERR; | |
383 | } | |
384 | ||
5391d806 | 385 | /* prepare data transfer and tell what to do after */ |
33231e0e KW |
386 | void ide_transfer_start(IDEState *s, uint8_t *buf, int size, |
387 | EndTransferFunc *end_transfer_func) | |
5391d806 FB |
388 | { |
389 | s->end_transfer_func = end_transfer_func; | |
390 | s->data_ptr = buf; | |
391 | s->data_end = buf + size; | |
40a6238a | 392 | if (!(s->status & ERR_STAT)) { |
7603d156 | 393 | s->status |= DRQ_STAT; |
40a6238a AG |
394 | } |
395 | s->bus->dma->ops->start_transfer(s->bus->dma); | |
5391d806 FB |
396 | } |
397 | ||
33231e0e | 398 | void ide_transfer_stop(IDEState *s) |
5391d806 FB |
399 | { |
400 | s->end_transfer_func = ide_transfer_stop; | |
401 | s->data_ptr = s->io_buffer; | |
402 | s->data_end = s->io_buffer; | |
403 | s->status &= ~DRQ_STAT; | |
404 | } | |
405 | ||
356721ae | 406 | int64_t ide_get_sector(IDEState *s) |
5391d806 FB |
407 | { |
408 | int64_t sector_num; | |
409 | if (s->select & 0x40) { | |
410 | /* lba */ | |
c2ff060f FB |
411 | if (!s->lba48) { |
412 | sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | | |
413 | (s->lcyl << 8) | s->sector; | |
414 | } else { | |
415 | sector_num = ((int64_t)s->hob_hcyl << 40) | | |
416 | ((int64_t) s->hob_lcyl << 32) | | |
417 | ((int64_t) s->hob_sector << 24) | | |
418 | ((int64_t) s->hcyl << 16) | | |
419 | ((int64_t) s->lcyl << 8) | s->sector; | |
420 | } | |
5391d806 FB |
421 | } else { |
422 | sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors + | |
c2ff060f | 423 | (s->select & 0x0f) * s->sectors + (s->sector - 1); |
5391d806 FB |
424 | } |
425 | return sector_num; | |
426 | } | |
427 | ||
356721ae | 428 | void ide_set_sector(IDEState *s, int64_t sector_num) |
5391d806 FB |
429 | { |
430 | unsigned int cyl, r; | |
431 | if (s->select & 0x40) { | |
c2ff060f FB |
432 | if (!s->lba48) { |
433 | s->select = (s->select & 0xf0) | (sector_num >> 24); | |
434 | s->hcyl = (sector_num >> 16); | |
435 | s->lcyl = (sector_num >> 8); | |
436 | s->sector = (sector_num); | |
437 | } else { | |
438 | s->sector = sector_num; | |
439 | s->lcyl = sector_num >> 8; | |
440 | s->hcyl = sector_num >> 16; | |
441 | s->hob_sector = sector_num >> 24; | |
442 | s->hob_lcyl = sector_num >> 32; | |
443 | s->hob_hcyl = sector_num >> 40; | |
444 | } | |
5391d806 FB |
445 | } else { |
446 | cyl = sector_num / (s->heads * s->sectors); | |
447 | r = sector_num % (s->heads * s->sectors); | |
448 | s->hcyl = cyl >> 8; | |
449 | s->lcyl = cyl; | |
1b8eb456 | 450 | s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); |
5391d806 FB |
451 | s->sector = (r % s->sectors) + 1; |
452 | } | |
453 | } | |
454 | ||
e162cfb0 AZ |
455 | static void ide_rw_error(IDEState *s) { |
456 | ide_abort_command(s); | |
9cdd03a7 | 457 | ide_set_irq(s->bus); |
e162cfb0 AZ |
458 | } |
459 | ||
40a6238a | 460 | void ide_sector_read(IDEState *s) |
5391d806 FB |
461 | { |
462 | int64_t sector_num; | |
463 | int ret, n; | |
464 | ||
465 | s->status = READY_STAT | SEEK_STAT; | |
a136e5a8 | 466 | s->error = 0; /* not needed by IDE spec, but needed by Windows */ |
5391d806 FB |
467 | sector_num = ide_get_sector(s); |
468 | n = s->nsector; | |
469 | if (n == 0) { | |
470 | /* no more sector to read from disk */ | |
471 | ide_transfer_stop(s); | |
472 | } else { | |
473 | #if defined(DEBUG_IDE) | |
18c5f8ea | 474 | printf("read sector=%" PRId64 "\n", sector_num); |
5391d806 FB |
475 | #endif |
476 | if (n > s->req_nb_sectors) | |
477 | n = s->req_nb_sectors; | |
a597e79c CH |
478 | |
479 | bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); | |
5391d806 | 480 | ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); |
a597e79c | 481 | bdrv_acct_done(s->bs, &s->acct); |
e162cfb0 | 482 | if (ret != 0) { |
ce4b6522 KW |
483 | if (ide_handle_rw_error(s, -ret, |
484 | BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ)) | |
485 | { | |
486 | return; | |
487 | } | |
e162cfb0 | 488 | } |
5391d806 | 489 | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read); |
9cdd03a7 | 490 | ide_set_irq(s->bus); |
5391d806 FB |
491 | ide_set_sector(s, sector_num + n); |
492 | s->nsector -= n; | |
493 | } | |
494 | } | |
495 | ||
b61744b3 | 496 | static void dma_buf_commit(IDEState *s) |
7aea4412 | 497 | { |
1fb8648d | 498 | qemu_sglist_destroy(&s->sg); |
7aea4412 AL |
499 | } |
500 | ||
33231e0e | 501 | void ide_set_inactive(IDEState *s) |
8337606d | 502 | { |
40a6238a AG |
503 | s->bus->dma->aiocb = NULL; |
504 | s->bus->dma->ops->set_inactive(s->bus->dma); | |
8337606d KW |
505 | } |
506 | ||
356721ae | 507 | void ide_dma_error(IDEState *s) |
e162cfb0 AZ |
508 | { |
509 | ide_transfer_stop(s); | |
510 | s->error = ABRT_ERR; | |
511 | s->status = READY_STAT | ERR_STAT; | |
40a6238a | 512 | ide_set_inactive(s); |
9cdd03a7 | 513 | ide_set_irq(s->bus); |
e162cfb0 AZ |
514 | } |
515 | ||
ce4b6522 | 516 | static int ide_handle_rw_error(IDEState *s, int error, int op) |
428c5705 | 517 | { |
ce4b6522 | 518 | int is_read = (op & BM_STATUS_RETRY_READ); |
abd7f68d | 519 | BlockErrorAction action = bdrv_get_on_error(s->bs, is_read); |
428c5705 | 520 | |
7ad7e3c3 | 521 | if (action == BLOCK_ERR_IGNORE) { |
329c0a48 | 522 | bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_IGNORE, is_read); |
428c5705 | 523 | return 0; |
7ad7e3c3 | 524 | } |
428c5705 AL |
525 | |
526 | if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC) | |
527 | || action == BLOCK_ERR_STOP_ANY) { | |
40a6238a | 528 | s->bus->dma->ops->set_unit(s->bus->dma, s->unit); |
def93791 | 529 | s->bus->error_status = op; |
329c0a48 | 530 | bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_STOP, is_read); |
0461d5a6 | 531 | vm_stop(RUN_STATE_IO_ERROR); |
50fb1900 | 532 | bdrv_iostatus_set_err(s->bs, error); |
428c5705 | 533 | } else { |
ce4b6522 | 534 | if (op & BM_STATUS_DMA_RETRY) { |
b61744b3 | 535 | dma_buf_commit(s); |
428c5705 | 536 | ide_dma_error(s); |
7aea4412 | 537 | } else { |
428c5705 | 538 | ide_rw_error(s); |
7aea4412 | 539 | } |
329c0a48 | 540 | bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_REPORT, is_read); |
428c5705 AL |
541 | } |
542 | ||
543 | return 1; | |
544 | } | |
545 | ||
cd369c46 | 546 | void ide_dma_cb(void *opaque, int ret) |
98087450 | 547 | { |
40a6238a | 548 | IDEState *s = opaque; |
8ccad811 FB |
549 | int n; |
550 | int64_t sector_num; | |
551 | ||
e162cfb0 | 552 | if (ret < 0) { |
cd369c46 CH |
553 | int op = BM_STATUS_DMA_RETRY; |
554 | ||
4e1e0051 | 555 | if (s->dma_cmd == IDE_DMA_READ) |
cd369c46 | 556 | op |= BM_STATUS_RETRY_READ; |
d353fb72 CH |
557 | else if (s->dma_cmd == IDE_DMA_TRIM) |
558 | op |= BM_STATUS_RETRY_TRIM; | |
559 | ||
cd369c46 | 560 | if (ide_handle_rw_error(s, -ret, op)) { |
ce4b6522 KW |
561 | return; |
562 | } | |
e162cfb0 AZ |
563 | } |
564 | ||
8ccad811 FB |
565 | n = s->io_buffer_size >> 9; |
566 | sector_num = ide_get_sector(s); | |
567 | if (n > 0) { | |
b61744b3 | 568 | dma_buf_commit(s); |
8ccad811 FB |
569 | sector_num += n; |
570 | ide_set_sector(s, sector_num); | |
571 | s->nsector -= n; | |
8ccad811 FB |
572 | } |
573 | ||
574 | /* end of transfer ? */ | |
575 | if (s->nsector == 0) { | |
98087450 | 576 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 577 | ide_set_irq(s->bus); |
cd369c46 | 578 | goto eot; |
98087450 | 579 | } |
8ccad811 FB |
580 | |
581 | /* launch next transfer */ | |
582 | n = s->nsector; | |
596bb44d | 583 | s->io_buffer_index = 0; |
8ccad811 | 584 | s->io_buffer_size = n * 512; |
4e1e0051 | 585 | if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) { |
69c38b8f KW |
586 | /* The PRDs were too short. Reset the Active bit, but don't raise an |
587 | * interrupt. */ | |
7aea4412 | 588 | goto eot; |
69c38b8f | 589 | } |
cd369c46 | 590 | |
8ccad811 | 591 | #ifdef DEBUG_AIO |
4e1e0051 CH |
592 | printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", |
593 | sector_num, n, s->dma_cmd); | |
8ccad811 | 594 | #endif |
cd369c46 | 595 | |
4e1e0051 CH |
596 | switch (s->dma_cmd) { |
597 | case IDE_DMA_READ: | |
cd369c46 CH |
598 | s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, |
599 | ide_dma_cb, s); | |
4e1e0051 CH |
600 | break; |
601 | case IDE_DMA_WRITE: | |
cd369c46 CH |
602 | s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, |
603 | ide_dma_cb, s); | |
4e1e0051 | 604 | break; |
d353fb72 CH |
605 | case IDE_DMA_TRIM: |
606 | s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num, | |
bbca72c6 | 607 | ide_issue_trim, ide_dma_cb, s, true); |
d353fb72 | 608 | break; |
cd369c46 | 609 | } |
cd369c46 CH |
610 | return; |
611 | ||
612 | eot: | |
a597e79c CH |
613 | if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { |
614 | bdrv_acct_done(s->bs, &s->acct); | |
615 | } | |
616 | ide_set_inactive(s); | |
98087450 FB |
617 | } |
618 | ||
4e1e0051 | 619 | static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) |
98087450 | 620 | { |
8ccad811 | 621 | s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
98087450 FB |
622 | s->io_buffer_index = 0; |
623 | s->io_buffer_size = 0; | |
4e1e0051 | 624 | s->dma_cmd = dma_cmd; |
a597e79c CH |
625 | |
626 | switch (dma_cmd) { | |
627 | case IDE_DMA_READ: | |
628 | bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, | |
629 | BDRV_ACCT_READ); | |
630 | break; | |
631 | case IDE_DMA_WRITE: | |
632 | bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, | |
633 | BDRV_ACCT_WRITE); | |
634 | break; | |
635 | default: | |
636 | break; | |
637 | } | |
638 | ||
cd369c46 | 639 | s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb); |
98087450 FB |
640 | } |
641 | ||
a09db21f FB |
642 | static void ide_sector_write_timer_cb(void *opaque) |
643 | { | |
644 | IDEState *s = opaque; | |
9cdd03a7 | 645 | ide_set_irq(s->bus); |
a09db21f FB |
646 | } |
647 | ||
40a6238a | 648 | void ide_sector_write(IDEState *s) |
5391d806 FB |
649 | { |
650 | int64_t sector_num; | |
31c2a146 | 651 | int ret, n, n1; |
5391d806 FB |
652 | |
653 | s->status = READY_STAT | SEEK_STAT; | |
654 | sector_num = ide_get_sector(s); | |
655 | #if defined(DEBUG_IDE) | |
18c5f8ea | 656 | printf("write sector=%" PRId64 "\n", sector_num); |
5391d806 FB |
657 | #endif |
658 | n = s->nsector; | |
659 | if (n > s->req_nb_sectors) | |
660 | n = s->req_nb_sectors; | |
a597e79c CH |
661 | |
662 | bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); | |
31c2a146 | 663 | ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); |
a597e79c | 664 | bdrv_acct_done(s->bs, &s->acct); |
428c5705 | 665 | |
e162cfb0 | 666 | if (ret != 0) { |
ce4b6522 | 667 | if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) |
428c5705 | 668 | return; |
e162cfb0 AZ |
669 | } |
670 | ||
5391d806 FB |
671 | s->nsector -= n; |
672 | if (s->nsector == 0) { | |
292eef5a | 673 | /* no more sectors to write */ |
5391d806 FB |
674 | ide_transfer_stop(s); |
675 | } else { | |
676 | n1 = s->nsector; | |
677 | if (n1 > s->req_nb_sectors) | |
678 | n1 = s->req_nb_sectors; | |
679 | ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write); | |
680 | } | |
681 | ide_set_sector(s, sector_num + n); | |
3b46e624 | 682 | |
31c2a146 TS |
683 | if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { |
684 | /* It seems there is a bug in the Windows 2000 installer HDD | |
685 | IDE driver which fills the disk with empty logs when the | |
686 | IDE write IRQ comes too early. This hack tries to correct | |
687 | that at the expense of slower write performances. Use this | |
688 | option _only_ to install Windows 2000. You must disable it | |
689 | for normal use. */ | |
f7736b91 | 690 | qemu_mod_timer(s->sector_write_timer, |
74475455 | 691 | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000)); |
f7736b91 | 692 | } else { |
9cdd03a7 | 693 | ide_set_irq(s->bus); |
31c2a146 | 694 | } |
5391d806 FB |
695 | } |
696 | ||
b0484ae4 CH |
697 | static void ide_flush_cb(void *opaque, int ret) |
698 | { | |
699 | IDEState *s = opaque; | |
700 | ||
e2bcadad KW |
701 | if (ret < 0) { |
702 | /* XXX: What sector number to set here? */ | |
703 | if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) { | |
704 | return; | |
705 | } | |
706 | } | |
b0484ae4 | 707 | |
a597e79c | 708 | bdrv_acct_done(s->bs, &s->acct); |
b0484ae4 CH |
709 | s->status = READY_STAT | SEEK_STAT; |
710 | ide_set_irq(s->bus); | |
711 | } | |
712 | ||
40a6238a | 713 | void ide_flush_cache(IDEState *s) |
6bcb1a79 | 714 | { |
b2df7531 | 715 | if (s->bs == NULL) { |
6bcb1a79 | 716 | ide_flush_cb(s, 0); |
b2df7531 KW |
717 | return; |
718 | } | |
719 | ||
a597e79c | 720 | bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH); |
ad54ae80 | 721 | bdrv_aio_flush(s->bs, ide_flush_cb, s); |
6bcb1a79 KW |
722 | } |
723 | ||
201a51fc AZ |
724 | static void ide_cfata_metadata_inquiry(IDEState *s) |
725 | { | |
726 | uint16_t *p; | |
727 | uint32_t spd; | |
728 | ||
729 | p = (uint16_t *) s->io_buffer; | |
730 | memset(p, 0, 0x200); | |
731 | spd = ((s->mdata_size - 1) >> 9) + 1; | |
732 | ||
733 | put_le16(p + 0, 0x0001); /* Data format revision */ | |
734 | put_le16(p + 1, 0x0000); /* Media property: silicon */ | |
735 | put_le16(p + 2, s->media_changed); /* Media status */ | |
736 | put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ | |
737 | put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ | |
738 | put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ | |
739 | put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ | |
740 | } | |
741 | ||
742 | static void ide_cfata_metadata_read(IDEState *s) | |
743 | { | |
744 | uint16_t *p; | |
745 | ||
746 | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { | |
747 | s->status = ERR_STAT; | |
748 | s->error = ABRT_ERR; | |
749 | return; | |
750 | } | |
751 | ||
752 | p = (uint16_t *) s->io_buffer; | |
753 | memset(p, 0, 0x200); | |
754 | ||
755 | put_le16(p + 0, s->media_changed); /* Media status */ | |
756 | memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), | |
757 | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), | |
758 | s->nsector << 9), 0x200 - 2)); | |
759 | } | |
760 | ||
761 | static void ide_cfata_metadata_write(IDEState *s) | |
762 | { | |
763 | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { | |
764 | s->status = ERR_STAT; | |
765 | s->error = ABRT_ERR; | |
766 | return; | |
767 | } | |
768 | ||
769 | s->media_changed = 0; | |
770 | ||
771 | memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), | |
772 | s->io_buffer + 2, | |
773 | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), | |
774 | s->nsector << 9), 0x200 - 2)); | |
775 | } | |
776 | ||
bd491d6a | 777 | /* called when the inserted state of the media has changed */ |
7d4b4ba5 | 778 | static void ide_cd_change_cb(void *opaque, bool load) |
bd491d6a TS |
779 | { |
780 | IDEState *s = opaque; | |
96b8f136 | 781 | uint64_t nb_sectors; |
bd491d6a | 782 | |
25ad22bc | 783 | s->tray_open = !load; |
bd491d6a TS |
784 | bdrv_get_geometry(s->bs, &nb_sectors); |
785 | s->nb_sectors = nb_sectors; | |
9118e7f0 | 786 | |
4b9b7092 AS |
787 | /* |
788 | * First indicate to the guest that a CD has been removed. That's | |
789 | * done on the next command the guest sends us. | |
790 | * | |
67cc61e4 | 791 | * Then we set UNIT_ATTENTION, by which the guest will |
4b9b7092 AS |
792 | * detect a new CD in the drive. See ide_atapi_cmd() for details. |
793 | */ | |
93c8cfd9 | 794 | s->cdrom_changed = 1; |
996faf1a | 795 | s->events.new_media = true; |
2df0a3a3 PB |
796 | s->events.eject_request = false; |
797 | ide_set_irq(s->bus); | |
798 | } | |
799 | ||
800 | static void ide_cd_eject_request_cb(void *opaque, bool force) | |
801 | { | |
802 | IDEState *s = opaque; | |
803 | ||
804 | s->events.eject_request = true; | |
805 | if (force) { | |
806 | s->tray_locked = false; | |
807 | } | |
9cdd03a7 | 808 | ide_set_irq(s->bus); |
bd491d6a TS |
809 | } |
810 | ||
c2ff060f FB |
811 | static void ide_cmd_lba48_transform(IDEState *s, int lba48) |
812 | { | |
813 | s->lba48 = lba48; | |
814 | ||
815 | /* handle the 'magic' 0 nsector count conversion here. to avoid | |
816 | * fiddling with the rest of the read logic, we just store the | |
817 | * full sector count in ->nsector and ignore ->hob_nsector from now | |
818 | */ | |
819 | if (!s->lba48) { | |
820 | if (!s->nsector) | |
821 | s->nsector = 256; | |
822 | } else { | |
823 | if (!s->nsector && !s->hob_nsector) | |
824 | s->nsector = 65536; | |
825 | else { | |
826 | int lo = s->nsector; | |
827 | int hi = s->hob_nsector; | |
828 | ||
829 | s->nsector = (hi << 8) | lo; | |
830 | } | |
831 | } | |
832 | } | |
833 | ||
bcbdc4d3 | 834 | static void ide_clear_hob(IDEBus *bus) |
c2ff060f FB |
835 | { |
836 | /* any write clears HOB high bit of device control register */ | |
bcbdc4d3 GH |
837 | bus->ifs[0].select &= ~(1 << 7); |
838 | bus->ifs[1].select &= ~(1 << 7); | |
c2ff060f FB |
839 | } |
840 | ||
356721ae | 841 | void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
caed8802 | 842 | { |
bcbdc4d3 | 843 | IDEBus *bus = opaque; |
5391d806 FB |
844 | |
845 | #ifdef DEBUG_IDE | |
846 | printf("IDE: write addr=0x%x val=0x%02x\n", addr, val); | |
847 | #endif | |
c2ff060f | 848 | |
5391d806 | 849 | addr &= 7; |
fcdd25ab AL |
850 | |
851 | /* ignore writes to command block while busy with previous command */ | |
bcbdc4d3 | 852 | if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) |
fcdd25ab AL |
853 | return; |
854 | ||
5391d806 FB |
855 | switch(addr) { |
856 | case 0: | |
857 | break; | |
858 | case 1: | |
bcbdc4d3 | 859 | ide_clear_hob(bus); |
c45c3d00 | 860 | /* NOTE: data is written to the two drives */ |
bcbdc4d3 GH |
861 | bus->ifs[0].hob_feature = bus->ifs[0].feature; |
862 | bus->ifs[1].hob_feature = bus->ifs[1].feature; | |
863 | bus->ifs[0].feature = val; | |
864 | bus->ifs[1].feature = val; | |
5391d806 FB |
865 | break; |
866 | case 2: | |
bcbdc4d3 GH |
867 | ide_clear_hob(bus); |
868 | bus->ifs[0].hob_nsector = bus->ifs[0].nsector; | |
869 | bus->ifs[1].hob_nsector = bus->ifs[1].nsector; | |
870 | bus->ifs[0].nsector = val; | |
871 | bus->ifs[1].nsector = val; | |
5391d806 FB |
872 | break; |
873 | case 3: | |
bcbdc4d3 GH |
874 | ide_clear_hob(bus); |
875 | bus->ifs[0].hob_sector = bus->ifs[0].sector; | |
876 | bus->ifs[1].hob_sector = bus->ifs[1].sector; | |
877 | bus->ifs[0].sector = val; | |
878 | bus->ifs[1].sector = val; | |
5391d806 FB |
879 | break; |
880 | case 4: | |
bcbdc4d3 GH |
881 | ide_clear_hob(bus); |
882 | bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; | |
883 | bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; | |
884 | bus->ifs[0].lcyl = val; | |
885 | bus->ifs[1].lcyl = val; | |
5391d806 FB |
886 | break; |
887 | case 5: | |
bcbdc4d3 GH |
888 | ide_clear_hob(bus); |
889 | bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; | |
890 | bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; | |
891 | bus->ifs[0].hcyl = val; | |
892 | bus->ifs[1].hcyl = val; | |
5391d806 FB |
893 | break; |
894 | case 6: | |
c2ff060f | 895 | /* FIXME: HOB readback uses bit 7 */ |
bcbdc4d3 GH |
896 | bus->ifs[0].select = (val & ~0x10) | 0xa0; |
897 | bus->ifs[1].select = (val | 0x10) | 0xa0; | |
5391d806 | 898 | /* select drive */ |
bcbdc4d3 | 899 | bus->unit = (val >> 4) & 1; |
5391d806 FB |
900 | break; |
901 | default: | |
902 | case 7: | |
903 | /* command */ | |
7cff87ff AG |
904 | ide_exec_cmd(bus, val); |
905 | break; | |
906 | } | |
907 | } | |
908 | ||
844505b1 MA |
909 | #define HD_OK (1u << IDE_HD) |
910 | #define CD_OK (1u << IDE_CD) | |
911 | #define CFA_OK (1u << IDE_CFATA) | |
912 | #define HD_CFA_OK (HD_OK | CFA_OK) | |
913 | #define ALL_OK (HD_OK | CD_OK | CFA_OK) | |
914 | ||
915 | /* See ACS-2 T13/2015-D Table B.2 Command codes */ | |
916 | static const uint8_t ide_cmd_table[0x100] = { | |
917 | /* NOP not implemented, mandatory for CD */ | |
918 | [CFA_REQ_EXT_ERROR_CODE] = CFA_OK, | |
919 | [WIN_DSM] = ALL_OK, | |
920 | [WIN_DEVICE_RESET] = CD_OK, | |
3cfc2269 | 921 | [WIN_RECAL] = HD_CFA_OK, |
844505b1 MA |
922 | [WIN_READ] = ALL_OK, |
923 | [WIN_READ_ONCE] = ALL_OK, | |
3cfc2269 MA |
924 | [WIN_READ_EXT] = HD_CFA_OK, |
925 | [WIN_READDMA_EXT] = HD_CFA_OK, | |
926 | [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK, | |
927 | [WIN_MULTREAD_EXT] = HD_CFA_OK, | |
928 | [WIN_WRITE] = HD_CFA_OK, | |
929 | [WIN_WRITE_ONCE] = HD_CFA_OK, | |
930 | [WIN_WRITE_EXT] = HD_CFA_OK, | |
931 | [WIN_WRITEDMA_EXT] = HD_CFA_OK, | |
932 | [CFA_WRITE_SECT_WO_ERASE] = CFA_OK, | |
933 | [WIN_MULTWRITE_EXT] = HD_CFA_OK, | |
934 | [WIN_WRITE_VERIFY] = HD_CFA_OK, | |
935 | [WIN_VERIFY] = HD_CFA_OK, | |
936 | [WIN_VERIFY_ONCE] = HD_CFA_OK, | |
937 | [WIN_VERIFY_EXT] = HD_CFA_OK, | |
844505b1 MA |
938 | [WIN_SEEK] = HD_CFA_OK, |
939 | [CFA_TRANSLATE_SECTOR] = CFA_OK, | |
940 | [WIN_DIAGNOSE] = ALL_OK, | |
3cfc2269 | 941 | [WIN_SPECIFY] = HD_CFA_OK, |
844505b1 MA |
942 | [WIN_STANDBYNOW2] = ALL_OK, |
943 | [WIN_IDLEIMMEDIATE2] = ALL_OK, | |
944 | [WIN_STANDBY2] = ALL_OK, | |
945 | [WIN_SETIDLE2] = ALL_OK, | |
946 | [WIN_CHECKPOWERMODE2] = ALL_OK, | |
947 | [WIN_SLEEPNOW2] = ALL_OK, | |
948 | [WIN_PACKETCMD] = CD_OK, | |
949 | [WIN_PIDENTIFY] = CD_OK, | |
950 | [WIN_SMART] = HD_CFA_OK, | |
951 | [CFA_ACCESS_METADATA_STORAGE] = CFA_OK, | |
952 | [CFA_ERASE_SECTORS] = CFA_OK, | |
3cfc2269 MA |
953 | [WIN_MULTREAD] = HD_CFA_OK, |
954 | [WIN_MULTWRITE] = HD_CFA_OK, | |
955 | [WIN_SETMULT] = HD_CFA_OK, | |
956 | [WIN_READDMA] = HD_CFA_OK, | |
957 | [WIN_READDMA_ONCE] = HD_CFA_OK, | |
958 | [WIN_WRITEDMA] = HD_CFA_OK, | |
959 | [WIN_WRITEDMA_ONCE] = HD_CFA_OK, | |
960 | [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK, | |
844505b1 MA |
961 | [WIN_STANDBYNOW1] = ALL_OK, |
962 | [WIN_IDLEIMMEDIATE] = ALL_OK, | |
963 | [WIN_STANDBY] = ALL_OK, | |
964 | [WIN_SETIDLE1] = ALL_OK, | |
965 | [WIN_CHECKPOWERMODE1] = ALL_OK, | |
966 | [WIN_SLEEPNOW1] = ALL_OK, | |
967 | [WIN_FLUSH_CACHE] = ALL_OK, | |
3cfc2269 | 968 | [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK, |
844505b1 MA |
969 | [WIN_IDENTIFY] = ALL_OK, |
970 | [WIN_SETFEATURES] = ALL_OK, | |
971 | [IBM_SENSE_CONDITION] = CFA_OK, | |
972 | [CFA_WEAR_LEVEL] = CFA_OK, | |
973 | [WIN_READ_NATIVE_MAX] = ALL_OK, | |
974 | }; | |
975 | ||
976 | static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) | |
977 | { | |
978 | return cmd < ARRAY_SIZE(ide_cmd_table) | |
979 | && (ide_cmd_table[cmd] & (1u << s->drive_kind)); | |
980 | } | |
7cff87ff AG |
981 | |
982 | void ide_exec_cmd(IDEBus *bus, uint32_t val) | |
983 | { | |
984 | IDEState *s; | |
985 | int n; | |
986 | int lba48 = 0; | |
987 | ||
5391d806 | 988 | #if defined(DEBUG_IDE) |
6ef2ba5e | 989 | printf("ide: CMD=%02x\n", val); |
5391d806 | 990 | #endif |
6ef2ba5e | 991 | s = idebus_active_if(bus); |
66a0a2cb | 992 | /* ignore commands to non existent slave */ |
6ef2ba5e AG |
993 | if (s != bus->ifs && !s->bs) |
994 | return; | |
c2ff060f | 995 | |
6ef2ba5e AG |
996 | /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ |
997 | if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) | |
998 | return; | |
fcdd25ab | 999 | |
844505b1 MA |
1000 | if (!ide_cmd_permitted(s, val)) { |
1001 | goto abort_cmd; | |
1002 | } | |
1003 | ||
6ef2ba5e | 1004 | switch(val) { |
d353fb72 CH |
1005 | case WIN_DSM: |
1006 | switch (s->feature) { | |
1007 | case DSM_TRIM: | |
1008 | if (!s->bs) { | |
1009 | goto abort_cmd; | |
1010 | } | |
1011 | ide_sector_start_dma(s, IDE_DMA_TRIM); | |
1012 | break; | |
1013 | default: | |
1014 | goto abort_cmd; | |
1015 | } | |
1016 | break; | |
6ef2ba5e AG |
1017 | case WIN_IDENTIFY: |
1018 | if (s->bs && s->drive_kind != IDE_CD) { | |
1019 | if (s->drive_kind != IDE_CFATA) | |
1020 | ide_identify(s); | |
1021 | else | |
1022 | ide_cfata_identify(s); | |
769bec72 | 1023 | s->status = READY_STAT | SEEK_STAT; |
6ef2ba5e AG |
1024 | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); |
1025 | } else { | |
1026 | if (s->drive_kind == IDE_CD) { | |
1027 | ide_set_signature(s); | |
5391d806 | 1028 | } |
6ef2ba5e AG |
1029 | ide_abort_command(s); |
1030 | } | |
1031 | ide_set_irq(s->bus); | |
1032 | break; | |
1033 | case WIN_SPECIFY: | |
1034 | case WIN_RECAL: | |
1035 | s->error = 0; | |
1036 | s->status = READY_STAT | SEEK_STAT; | |
1037 | ide_set_irq(s->bus); | |
1038 | break; | |
1039 | case WIN_SETMULT: | |
1040 | if (s->drive_kind == IDE_CFATA && s->nsector == 0) { | |
1041 | /* Disable Read and Write Multiple */ | |
1042 | s->mult_sectors = 0; | |
41a2b959 | 1043 | s->status = READY_STAT | SEEK_STAT; |
6ef2ba5e AG |
1044 | } else if ((s->nsector & 0xff) != 0 && |
1045 | ((s->nsector & 0xff) > MAX_MULT_SECTORS || | |
1046 | (s->nsector & (s->nsector - 1)) != 0)) { | |
1047 | ide_abort_command(s); | |
1048 | } else { | |
1049 | s->mult_sectors = s->nsector & 0xff; | |
1050 | s->status = READY_STAT | SEEK_STAT; | |
1051 | } | |
1052 | ide_set_irq(s->bus); | |
1053 | break; | |
1054 | case WIN_VERIFY_EXT: | |
1055 | lba48 = 1; | |
1056 | case WIN_VERIFY: | |
1057 | case WIN_VERIFY_ONCE: | |
1058 | /* do sector number check ? */ | |
1059 | ide_cmd_lba48_transform(s, lba48); | |
1060 | s->status = READY_STAT | SEEK_STAT; | |
1061 | ide_set_irq(s->bus); | |
1062 | break; | |
814839c0 | 1063 | case WIN_READ_EXT: |
6ef2ba5e AG |
1064 | lba48 = 1; |
1065 | case WIN_READ: | |
1066 | case WIN_READ_ONCE: | |
3f76a7c3 MA |
1067 | if (s->drive_kind == IDE_CD) { |
1068 | ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */ | |
6ef2ba5e | 1069 | goto abort_cmd; |
3f76a7c3 | 1070 | } |
6ef2ba5e AG |
1071 | ide_cmd_lba48_transform(s, lba48); |
1072 | s->req_nb_sectors = 1; | |
1073 | ide_sector_read(s); | |
1074 | break; | |
814839c0 | 1075 | case WIN_WRITE_EXT: |
6ef2ba5e AG |
1076 | lba48 = 1; |
1077 | case WIN_WRITE: | |
1078 | case WIN_WRITE_ONCE: | |
1079 | case CFA_WRITE_SECT_WO_ERASE: | |
1080 | case WIN_WRITE_VERIFY: | |
1081 | ide_cmd_lba48_transform(s, lba48); | |
1082 | s->error = 0; | |
1083 | s->status = SEEK_STAT | READY_STAT; | |
1084 | s->req_nb_sectors = 1; | |
1085 | ide_transfer_start(s, s->io_buffer, 512, ide_sector_write); | |
1086 | s->media_changed = 1; | |
1087 | break; | |
814839c0 | 1088 | case WIN_MULTREAD_EXT: |
6ef2ba5e AG |
1089 | lba48 = 1; |
1090 | case WIN_MULTREAD: | |
1091 | if (!s->mult_sectors) | |
1092 | goto abort_cmd; | |
1093 | ide_cmd_lba48_transform(s, lba48); | |
1094 | s->req_nb_sectors = s->mult_sectors; | |
1095 | ide_sector_read(s); | |
1096 | break; | |
1097 | case WIN_MULTWRITE_EXT: | |
1098 | lba48 = 1; | |
1099 | case WIN_MULTWRITE: | |
1100 | case CFA_WRITE_MULTI_WO_ERASE: | |
1101 | if (!s->mult_sectors) | |
1102 | goto abort_cmd; | |
1103 | ide_cmd_lba48_transform(s, lba48); | |
1104 | s->error = 0; | |
1105 | s->status = SEEK_STAT | READY_STAT; | |
1106 | s->req_nb_sectors = s->mult_sectors; | |
1107 | n = s->nsector; | |
1108 | if (n > s->req_nb_sectors) | |
1109 | n = s->req_nb_sectors; | |
1110 | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write); | |
1111 | s->media_changed = 1; | |
1112 | break; | |
814839c0 | 1113 | case WIN_READDMA_EXT: |
6ef2ba5e AG |
1114 | lba48 = 1; |
1115 | case WIN_READDMA: | |
1116 | case WIN_READDMA_ONCE: | |
1117 | if (!s->bs) | |
1118 | goto abort_cmd; | |
1119 | ide_cmd_lba48_transform(s, lba48); | |
4e1e0051 | 1120 | ide_sector_start_dma(s, IDE_DMA_READ); |
6ef2ba5e | 1121 | break; |
814839c0 | 1122 | case WIN_WRITEDMA_EXT: |
6ef2ba5e AG |
1123 | lba48 = 1; |
1124 | case WIN_WRITEDMA: | |
1125 | case WIN_WRITEDMA_ONCE: | |
1126 | if (!s->bs) | |
1127 | goto abort_cmd; | |
1128 | ide_cmd_lba48_transform(s, lba48); | |
4e1e0051 | 1129 | ide_sector_start_dma(s, IDE_DMA_WRITE); |
6ef2ba5e AG |
1130 | s->media_changed = 1; |
1131 | break; | |
1132 | case WIN_READ_NATIVE_MAX_EXT: | |
1133 | lba48 = 1; | |
1134 | case WIN_READ_NATIVE_MAX: | |
1135 | ide_cmd_lba48_transform(s, lba48); | |
1136 | ide_set_sector(s, s->nb_sectors - 1); | |
1137 | s->status = READY_STAT | SEEK_STAT; | |
1138 | ide_set_irq(s->bus); | |
1139 | break; | |
1140 | case WIN_CHECKPOWERMODE1: | |
1141 | case WIN_CHECKPOWERMODE2: | |
b93af93d | 1142 | s->error = 0; |
6ef2ba5e AG |
1143 | s->nsector = 0xff; /* device active or idle */ |
1144 | s->status = READY_STAT | SEEK_STAT; | |
1145 | ide_set_irq(s->bus); | |
1146 | break; | |
1147 | case WIN_SETFEATURES: | |
1148 | if (!s->bs) | |
1149 | goto abort_cmd; | |
1150 | /* XXX: valid for CDROM ? */ | |
1151 | switch(s->feature) { | |
1152 | case 0xcc: /* reverting to power-on defaults enable */ | |
1153 | case 0x66: /* reverting to power-on defaults disable */ | |
1154 | case 0x02: /* write cache enable */ | |
1155 | case 0x82: /* write cache disable */ | |
1156 | case 0xaa: /* read look-ahead enable */ | |
1157 | case 0x55: /* read look-ahead disable */ | |
1158 | case 0x05: /* set advanced power management mode */ | |
1159 | case 0x85: /* disable advanced power management mode */ | |
1160 | case 0x69: /* NOP */ | |
1161 | case 0x67: /* NOP */ | |
1162 | case 0x96: /* NOP */ | |
1163 | case 0x9a: /* NOP */ | |
1164 | case 0x42: /* enable Automatic Acoustic Mode */ | |
1165 | case 0xc2: /* disable Automatic Acoustic Mode */ | |
41a2b959 | 1166 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 1167 | ide_set_irq(s->bus); |
a136e5a8 | 1168 | break; |
6ef2ba5e | 1169 | case 0x03: { /* set transfer mode */ |
94458802 | 1170 | uint8_t val = s->nsector & 0x07; |
6ef2ba5e | 1171 | uint16_t *identify_data = (uint16_t *)s->identify_data; |
94458802 FB |
1172 | |
1173 | switch (s->nsector >> 3) { | |
6ef2ba5e AG |
1174 | case 0x00: /* pio default */ |
1175 | case 0x01: /* pio mode */ | |
96c35ceb JQ |
1176 | put_le16(identify_data + 62,0x07); |
1177 | put_le16(identify_data + 63,0x07); | |
1178 | put_le16(identify_data + 88,0x3f); | |
d1b5c20d | 1179 | break; |
6ef2ba5e | 1180 | case 0x02: /* sigle word dma mode*/ |
96c35ceb JQ |
1181 | put_le16(identify_data + 62,0x07 | (1 << (val + 8))); |
1182 | put_le16(identify_data + 63,0x07); | |
1183 | put_le16(identify_data + 88,0x3f); | |
94458802 | 1184 | break; |
6ef2ba5e | 1185 | case 0x04: /* mdma mode */ |
96c35ceb JQ |
1186 | put_le16(identify_data + 62,0x07); |
1187 | put_le16(identify_data + 63,0x07 | (1 << (val + 8))); | |
1188 | put_le16(identify_data + 88,0x3f); | |
94458802 | 1189 | break; |
6ef2ba5e | 1190 | case 0x08: /* udma mode */ |
96c35ceb JQ |
1191 | put_le16(identify_data + 62,0x07); |
1192 | put_le16(identify_data + 63,0x07); | |
1193 | put_le16(identify_data + 88,0x3f | (1 << (val + 8))); | |
94458802 | 1194 | break; |
6ef2ba5e | 1195 | default: |
94458802 FB |
1196 | goto abort_cmd; |
1197 | } | |
4fbfcd6d | 1198 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 1199 | ide_set_irq(s->bus); |
4fbfcd6d | 1200 | break; |
6ef2ba5e AG |
1201 | } |
1202 | default: | |
1203 | goto abort_cmd; | |
1204 | } | |
1205 | break; | |
1206 | case WIN_FLUSH_CACHE: | |
1207 | case WIN_FLUSH_CACHE_EXT: | |
1208 | ide_flush_cache(s); | |
1209 | break; | |
1210 | case WIN_STANDBY: | |
1211 | case WIN_STANDBY2: | |
1212 | case WIN_STANDBYNOW1: | |
1213 | case WIN_STANDBYNOW2: | |
1214 | case WIN_IDLEIMMEDIATE: | |
1d4316d3 | 1215 | case WIN_IDLEIMMEDIATE2: |
6ef2ba5e AG |
1216 | case WIN_SETIDLE1: |
1217 | case WIN_SETIDLE2: | |
1218 | case WIN_SLEEPNOW1: | |
1219 | case WIN_SLEEPNOW2: | |
1220 | s->status = READY_STAT; | |
1221 | ide_set_irq(s->bus); | |
1222 | break; | |
1223 | case WIN_SEEK: | |
6ef2ba5e AG |
1224 | /* XXX: Check that seek is within bounds */ |
1225 | s->status = READY_STAT | SEEK_STAT; | |
1226 | ide_set_irq(s->bus); | |
1227 | break; | |
1228 | /* ATAPI commands */ | |
1229 | case WIN_PIDENTIFY: | |
844505b1 MA |
1230 | ide_atapi_identify(s); |
1231 | s->status = READY_STAT | SEEK_STAT; | |
1232 | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); | |
6ef2ba5e AG |
1233 | ide_set_irq(s->bus); |
1234 | break; | |
1235 | case WIN_DIAGNOSE: | |
1236 | ide_set_signature(s); | |
1237 | if (s->drive_kind == IDE_CD) | |
1238 | s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet | |
1239 | * devices to return a clear status register | |
1240 | * with READY_STAT *not* set. */ | |
1241 | else | |
41a2b959 | 1242 | s->status = READY_STAT | SEEK_STAT; |
6ef2ba5e AG |
1243 | s->error = 0x01; /* Device 0 passed, Device 1 passed or not |
1244 | * present. | |
1245 | */ | |
1246 | ide_set_irq(s->bus); | |
1247 | break; | |
1d4316d3 | 1248 | case WIN_DEVICE_RESET: |
6ef2ba5e AG |
1249 | ide_set_signature(s); |
1250 | s->status = 0x00; /* NOTE: READY is _not_ set */ | |
1251 | s->error = 0x01; | |
1252 | break; | |
1253 | case WIN_PACKETCMD: | |
6ef2ba5e AG |
1254 | /* overlapping commands not supported */ |
1255 | if (s->feature & 0x02) | |
1256 | goto abort_cmd; | |
1257 | s->status = READY_STAT | SEEK_STAT; | |
1258 | s->atapi_dma = s->feature & 1; | |
1259 | s->nsector = 1; | |
1260 | ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, | |
1261 | ide_atapi_cmd); | |
1262 | break; | |
1263 | /* CF-ATA commands */ | |
1264 | case CFA_REQ_EXT_ERROR_CODE: | |
6ef2ba5e AG |
1265 | s->error = 0x09; /* miscellaneous error */ |
1266 | s->status = READY_STAT | SEEK_STAT; | |
1267 | ide_set_irq(s->bus); | |
1268 | break; | |
1269 | case CFA_ERASE_SECTORS: | |
1270 | case CFA_WEAR_LEVEL: | |
6ef2ba5e AG |
1271 | if (val == CFA_WEAR_LEVEL) |
1272 | s->nsector = 0; | |
1273 | if (val == CFA_ERASE_SECTORS) | |
1274 | s->media_changed = 1; | |
1275 | s->error = 0x00; | |
1276 | s->status = READY_STAT | SEEK_STAT; | |
1277 | ide_set_irq(s->bus); | |
1278 | break; | |
1279 | case CFA_TRANSLATE_SECTOR: | |
6ef2ba5e AG |
1280 | s->error = 0x00; |
1281 | s->status = READY_STAT | SEEK_STAT; | |
1282 | memset(s->io_buffer, 0, 0x200); | |
1283 | s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ | |
1284 | s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ | |
1285 | s->io_buffer[0x02] = s->select; /* Head */ | |
1286 | s->io_buffer[0x03] = s->sector; /* Sector */ | |
1287 | s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ | |
1288 | s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ | |
1289 | s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ | |
1290 | s->io_buffer[0x13] = 0x00; /* Erase flag */ | |
1291 | s->io_buffer[0x18] = 0x00; /* Hot count */ | |
1292 | s->io_buffer[0x19] = 0x00; /* Hot count */ | |
1293 | s->io_buffer[0x1a] = 0x01; /* Hot count */ | |
1294 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
1295 | ide_set_irq(s->bus); | |
1296 | break; | |
1297 | case CFA_ACCESS_METADATA_STORAGE: | |
6ef2ba5e AG |
1298 | switch (s->feature) { |
1299 | case 0x02: /* Inquiry Metadata Storage */ | |
1300 | ide_cfata_metadata_inquiry(s); | |
201a51fc | 1301 | break; |
6ef2ba5e AG |
1302 | case 0x03: /* Read Metadata Storage */ |
1303 | ide_cfata_metadata_read(s); | |
201a51fc | 1304 | break; |
6ef2ba5e AG |
1305 | case 0x04: /* Write Metadata Storage */ |
1306 | ide_cfata_metadata_write(s); | |
201a51fc | 1307 | break; |
6ef2ba5e AG |
1308 | default: |
1309 | goto abort_cmd; | |
1310 | } | |
1311 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
1312 | s->status = 0x00; /* NOTE: READY is _not_ set */ | |
1313 | ide_set_irq(s->bus); | |
1314 | break; | |
1315 | case IBM_SENSE_CONDITION: | |
6ef2ba5e AG |
1316 | switch (s->feature) { |
1317 | case 0x01: /* sense temperature in device */ | |
1318 | s->nsector = 0x50; /* +20 C */ | |
201a51fc | 1319 | break; |
6ef2ba5e AG |
1320 | default: |
1321 | goto abort_cmd; | |
1322 | } | |
1323 | s->status = READY_STAT | SEEK_STAT; | |
1324 | ide_set_irq(s->bus); | |
1325 | break; | |
e8b54394 | 1326 | |
814839c0 | 1327 | case WIN_SMART: |
6ef2ba5e | 1328 | if (s->hcyl != 0xc2 || s->lcyl != 0x4f) |
e8b54394 | 1329 | goto abort_cmd; |
6ef2ba5e | 1330 | if (!s->smart_enabled && s->feature != SMART_ENABLE) |
e8b54394 | 1331 | goto abort_cmd; |
6ef2ba5e AG |
1332 | switch (s->feature) { |
1333 | case SMART_DISABLE: | |
e8b54394 BW |
1334 | s->smart_enabled = 0; |
1335 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1336 | ide_set_irq(s->bus); |
e8b54394 | 1337 | break; |
6ef2ba5e | 1338 | case SMART_ENABLE: |
e8b54394 BW |
1339 | s->smart_enabled = 1; |
1340 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1341 | ide_set_irq(s->bus); |
e8b54394 | 1342 | break; |
6ef2ba5e | 1343 | case SMART_ATTR_AUTOSAVE: |
e8b54394 BW |
1344 | switch (s->sector) { |
1345 | case 0x00: | |
6ef2ba5e AG |
1346 | s->smart_autosave = 0; |
1347 | break; | |
e8b54394 | 1348 | case 0xf1: |
6ef2ba5e AG |
1349 | s->smart_autosave = 1; |
1350 | break; | |
e8b54394 | 1351 | default: |
6ef2ba5e | 1352 | goto abort_cmd; |
e8b54394 BW |
1353 | } |
1354 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1355 | ide_set_irq(s->bus); |
e8b54394 | 1356 | break; |
6ef2ba5e | 1357 | case SMART_STATUS: |
e8b54394 | 1358 | if (!s->smart_errors) { |
6ef2ba5e AG |
1359 | s->hcyl = 0xc2; |
1360 | s->lcyl = 0x4f; | |
e8b54394 | 1361 | } else { |
6ef2ba5e AG |
1362 | s->hcyl = 0x2c; |
1363 | s->lcyl = 0xf4; | |
e8b54394 BW |
1364 | } |
1365 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 1366 | ide_set_irq(s->bus); |
e8b54394 | 1367 | break; |
6ef2ba5e | 1368 | case SMART_READ_THRESH: |
e8b54394 BW |
1369 | memset(s->io_buffer, 0, 0x200); |
1370 | s->io_buffer[0] = 0x01; /* smart struct version */ | |
1371 | for (n=0; n<30; n++) { | |
6ef2ba5e | 1372 | if (smart_attributes[n][0] == 0) |
e8b54394 | 1373 | break; |
6ef2ba5e | 1374 | s->io_buffer[2+0+(n*12)] = smart_attributes[n][0]; |
b93af93d | 1375 | s->io_buffer[2+1+(n*12)] = smart_attributes[n][11]; |
e8b54394 BW |
1376 | } |
1377 | for (n=0; n<511; n++) /* checksum */ | |
6ef2ba5e | 1378 | s->io_buffer[511] += s->io_buffer[n]; |
e8b54394 BW |
1379 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1380 | s->status = READY_STAT | SEEK_STAT; | |
1381 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
9cdd03a7 | 1382 | ide_set_irq(s->bus); |
e8b54394 | 1383 | break; |
6ef2ba5e | 1384 | case SMART_READ_DATA: |
e8b54394 BW |
1385 | memset(s->io_buffer, 0, 0x200); |
1386 | s->io_buffer[0] = 0x01; /* smart struct version */ | |
1387 | for (n=0; n<30; n++) { | |
b93af93d | 1388 | if (smart_attributes[n][0] == 0) { |
e8b54394 | 1389 | break; |
b93af93d BW |
1390 | } |
1391 | int i; | |
1392 | for(i = 0; i < 11; i++) { | |
1393 | s->io_buffer[2+i+(n*12)] = smart_attributes[n][i]; | |
1394 | } | |
e8b54394 BW |
1395 | } |
1396 | s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00); | |
1397 | if (s->smart_selftest_count == 0) { | |
6ef2ba5e | 1398 | s->io_buffer[363] = 0; |
e8b54394 | 1399 | } else { |
6ef2ba5e | 1400 | s->io_buffer[363] = |
e8b54394 | 1401 | s->smart_selftest_data[3 + |
6ef2ba5e AG |
1402 | (s->smart_selftest_count - 1) * |
1403 | 24]; | |
e8b54394 BW |
1404 | } |
1405 | s->io_buffer[364] = 0x20; | |
1406 | s->io_buffer[365] = 0x01; | |
1407 | /* offline data collection capacity: execute + self-test*/ | |
1408 | s->io_buffer[367] = (1<<4 | 1<<3 | 1); | |
1409 | s->io_buffer[368] = 0x03; /* smart capability (1) */ | |
1410 | s->io_buffer[369] = 0x00; /* smart capability (2) */ | |
1411 | s->io_buffer[370] = 0x01; /* error logging supported */ | |
1412 | s->io_buffer[372] = 0x02; /* minutes for poll short test */ | |
1413 | s->io_buffer[373] = 0x36; /* minutes for poll ext test */ | |
1414 | s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ | |
1415 | ||
1416 | for (n=0; n<511; n++) | |
6ef2ba5e | 1417 | s->io_buffer[511] += s->io_buffer[n]; |
e8b54394 BW |
1418 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1419 | s->status = READY_STAT | SEEK_STAT; | |
1420 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
9cdd03a7 | 1421 | ide_set_irq(s->bus); |
e8b54394 | 1422 | break; |
6ef2ba5e | 1423 | case SMART_READ_LOG: |
e8b54394 BW |
1424 | switch (s->sector) { |
1425 | case 0x01: /* summary smart error log */ | |
6ef2ba5e AG |
1426 | memset(s->io_buffer, 0, 0x200); |
1427 | s->io_buffer[0] = 0x01; | |
1428 | s->io_buffer[1] = 0x00; /* no error entries */ | |
1429 | s->io_buffer[452] = s->smart_errors & 0xff; | |
1430 | s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; | |
e8b54394 | 1431 | |
6ef2ba5e | 1432 | for (n=0; n<511; n++) |
e8b54394 | 1433 | s->io_buffer[511] += s->io_buffer[n]; |
6ef2ba5e AG |
1434 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1435 | break; | |
e8b54394 | 1436 | case 0x06: /* smart self test log */ |
6ef2ba5e AG |
1437 | memset(s->io_buffer, 0, 0x200); |
1438 | s->io_buffer[0] = 0x01; | |
1439 | if (s->smart_selftest_count == 0) { | |
e8b54394 | 1440 | s->io_buffer[508] = 0; |
6ef2ba5e | 1441 | } else { |
e8b54394 BW |
1442 | s->io_buffer[508] = s->smart_selftest_count; |
1443 | for (n=2; n<506; n++) | |
6ef2ba5e AG |
1444 | s->io_buffer[n] = s->smart_selftest_data[n]; |
1445 | } | |
1446 | for (n=0; n<511; n++) | |
e8b54394 | 1447 | s->io_buffer[511] += s->io_buffer[n]; |
6ef2ba5e AG |
1448 | s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
1449 | break; | |
e8b54394 | 1450 | default: |
6ef2ba5e | 1451 | goto abort_cmd; |
e8b54394 BW |
1452 | } |
1453 | s->status = READY_STAT | SEEK_STAT; | |
1454 | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); | |
9cdd03a7 | 1455 | ide_set_irq(s->bus); |
e8b54394 | 1456 | break; |
6ef2ba5e | 1457 | case SMART_EXECUTE_OFFLINE: |
e8b54394 BW |
1458 | switch (s->sector) { |
1459 | case 0: /* off-line routine */ | |
1460 | case 1: /* short self test */ | |
1461 | case 2: /* extended self test */ | |
6ef2ba5e AG |
1462 | s->smart_selftest_count++; |
1463 | if(s->smart_selftest_count > 21) | |
e8b54394 | 1464 | s->smart_selftest_count = 0; |
6ef2ba5e AG |
1465 | n = 2 + (s->smart_selftest_count - 1) * 24; |
1466 | s->smart_selftest_data[n] = s->sector; | |
1467 | s->smart_selftest_data[n+1] = 0x00; /* OK and finished */ | |
1468 | s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */ | |
1469 | s->smart_selftest_data[n+3] = 0x12; /* hour count msb */ | |
1470 | s->status = READY_STAT | SEEK_STAT; | |
1471 | ide_set_irq(s->bus); | |
1472 | break; | |
e8b54394 | 1473 | default: |
6ef2ba5e | 1474 | goto abort_cmd; |
e8b54394 BW |
1475 | } |
1476 | break; | |
6ef2ba5e | 1477 | default: |
e8b54394 | 1478 | goto abort_cmd; |
6ef2ba5e AG |
1479 | } |
1480 | break; | |
1481 | default: | |
844505b1 | 1482 | /* should not be reachable */ |
6ef2ba5e AG |
1483 | abort_cmd: |
1484 | ide_abort_command(s); | |
1485 | ide_set_irq(s->bus); | |
1486 | break; | |
1487 | } | |
5391d806 FB |
1488 | } |
1489 | ||
356721ae | 1490 | uint32_t ide_ioport_read(void *opaque, uint32_t addr1) |
5391d806 | 1491 | { |
bcbdc4d3 GH |
1492 | IDEBus *bus = opaque; |
1493 | IDEState *s = idebus_active_if(bus); | |
5391d806 | 1494 | uint32_t addr; |
c2ff060f | 1495 | int ret, hob; |
5391d806 FB |
1496 | |
1497 | addr = addr1 & 7; | |
c2ff060f FB |
1498 | /* FIXME: HOB readback uses bit 7, but it's always set right now */ |
1499 | //hob = s->select & (1 << 7); | |
1500 | hob = 0; | |
5391d806 FB |
1501 | switch(addr) { |
1502 | case 0: | |
1503 | ret = 0xff; | |
1504 | break; | |
1505 | case 1: | |
bcbdc4d3 GH |
1506 | if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
1507 | (s != bus->ifs && !s->bs)) | |
c45c3d00 | 1508 | ret = 0; |
c2ff060f | 1509 | else if (!hob) |
c45c3d00 | 1510 | ret = s->error; |
c2ff060f FB |
1511 | else |
1512 | ret = s->hob_feature; | |
5391d806 FB |
1513 | break; |
1514 | case 2: | |
bcbdc4d3 | 1515 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1516 | ret = 0; |
c2ff060f | 1517 | else if (!hob) |
c45c3d00 | 1518 | ret = s->nsector & 0xff; |
c2ff060f FB |
1519 | else |
1520 | ret = s->hob_nsector; | |
5391d806 FB |
1521 | break; |
1522 | case 3: | |
bcbdc4d3 | 1523 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1524 | ret = 0; |
c2ff060f | 1525 | else if (!hob) |
c45c3d00 | 1526 | ret = s->sector; |
c2ff060f FB |
1527 | else |
1528 | ret = s->hob_sector; | |
5391d806 FB |
1529 | break; |
1530 | case 4: | |
bcbdc4d3 | 1531 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1532 | ret = 0; |
c2ff060f | 1533 | else if (!hob) |
c45c3d00 | 1534 | ret = s->lcyl; |
c2ff060f FB |
1535 | else |
1536 | ret = s->hob_lcyl; | |
5391d806 FB |
1537 | break; |
1538 | case 5: | |
bcbdc4d3 | 1539 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 | 1540 | ret = 0; |
c2ff060f | 1541 | else if (!hob) |
c45c3d00 | 1542 | ret = s->hcyl; |
c2ff060f FB |
1543 | else |
1544 | ret = s->hob_hcyl; | |
5391d806 FB |
1545 | break; |
1546 | case 6: | |
bcbdc4d3 | 1547 | if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
c45c3d00 FB |
1548 | ret = 0; |
1549 | else | |
7ae98627 | 1550 | ret = s->select; |
5391d806 FB |
1551 | break; |
1552 | default: | |
1553 | case 7: | |
bcbdc4d3 GH |
1554 | if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
1555 | (s != bus->ifs && !s->bs)) | |
c45c3d00 FB |
1556 | ret = 0; |
1557 | else | |
1558 | ret = s->status; | |
9cdd03a7 | 1559 | qemu_irq_lower(bus->irq); |
5391d806 FB |
1560 | break; |
1561 | } | |
1562 | #ifdef DEBUG_IDE | |
1563 | printf("ide: read addr=0x%x val=%02x\n", addr1, ret); | |
1564 | #endif | |
1565 | return ret; | |
1566 | } | |
1567 | ||
356721ae | 1568 | uint32_t ide_status_read(void *opaque, uint32_t addr) |
5391d806 | 1569 | { |
bcbdc4d3 GH |
1570 | IDEBus *bus = opaque; |
1571 | IDEState *s = idebus_active_if(bus); | |
5391d806 | 1572 | int ret; |
7ae98627 | 1573 | |
bcbdc4d3 GH |
1574 | if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
1575 | (s != bus->ifs && !s->bs)) | |
7ae98627 FB |
1576 | ret = 0; |
1577 | else | |
1578 | ret = s->status; | |
5391d806 FB |
1579 | #ifdef DEBUG_IDE |
1580 | printf("ide: read status addr=0x%x val=%02x\n", addr, ret); | |
1581 | #endif | |
1582 | return ret; | |
1583 | } | |
1584 | ||
356721ae | 1585 | void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) |
5391d806 | 1586 | { |
bcbdc4d3 | 1587 | IDEBus *bus = opaque; |
5391d806 FB |
1588 | IDEState *s; |
1589 | int i; | |
1590 | ||
1591 | #ifdef DEBUG_IDE | |
1592 | printf("ide: write control addr=0x%x val=%02x\n", addr, val); | |
1593 | #endif | |
1594 | /* common for both drives */ | |
9cdd03a7 | 1595 | if (!(bus->cmd & IDE_CMD_RESET) && |
5391d806 FB |
1596 | (val & IDE_CMD_RESET)) { |
1597 | /* reset low to high */ | |
1598 | for(i = 0;i < 2; i++) { | |
bcbdc4d3 | 1599 | s = &bus->ifs[i]; |
5391d806 FB |
1600 | s->status = BUSY_STAT | SEEK_STAT; |
1601 | s->error = 0x01; | |
1602 | } | |
9cdd03a7 | 1603 | } else if ((bus->cmd & IDE_CMD_RESET) && |
5391d806 FB |
1604 | !(val & IDE_CMD_RESET)) { |
1605 | /* high to low */ | |
1606 | for(i = 0;i < 2; i++) { | |
bcbdc4d3 | 1607 | s = &bus->ifs[i]; |
cd8722bb | 1608 | if (s->drive_kind == IDE_CD) |
6b136f9e FB |
1609 | s->status = 0x00; /* NOTE: READY is _not_ set */ |
1610 | else | |
56bf1d37 | 1611 | s->status = READY_STAT | SEEK_STAT; |
5391d806 FB |
1612 | ide_set_signature(s); |
1613 | } | |
1614 | } | |
1615 | ||
9cdd03a7 | 1616 | bus->cmd = val; |
5391d806 FB |
1617 | } |
1618 | ||
40c4ed3f KW |
1619 | /* |
1620 | * Returns true if the running PIO transfer is a PIO out (i.e. data is | |
1621 | * transferred from the device to the guest), false if it's a PIO in | |
1622 | */ | |
1623 | static bool ide_is_pio_out(IDEState *s) | |
1624 | { | |
1625 | if (s->end_transfer_func == ide_sector_write || | |
1626 | s->end_transfer_func == ide_atapi_cmd) { | |
1627 | return false; | |
1628 | } else if (s->end_transfer_func == ide_sector_read || | |
1629 | s->end_transfer_func == ide_transfer_stop || | |
1630 | s->end_transfer_func == ide_atapi_cmd_reply_end || | |
1631 | s->end_transfer_func == ide_dummy_transfer_stop) { | |
1632 | return true; | |
1633 | } | |
1634 | ||
1635 | abort(); | |
1636 | } | |
1637 | ||
356721ae | 1638 | void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) |
5391d806 | 1639 | { |
bcbdc4d3 GH |
1640 | IDEBus *bus = opaque; |
1641 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1642 | uint8_t *p; |
1643 | ||
40c4ed3f KW |
1644 | /* PIO data access allowed only when DRQ bit is set. The result of a write |
1645 | * during PIO out is indeterminate, just ignore it. */ | |
1646 | if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { | |
fcdd25ab | 1647 | return; |
40c4ed3f | 1648 | } |
fcdd25ab | 1649 | |
5391d806 | 1650 | p = s->data_ptr; |
0c4ad8dc | 1651 | *(uint16_t *)p = le16_to_cpu(val); |
5391d806 FB |
1652 | p += 2; |
1653 | s->data_ptr = p; | |
1654 | if (p >= s->data_end) | |
1655 | s->end_transfer_func(s); | |
1656 | } | |
1657 | ||
356721ae | 1658 | uint32_t ide_data_readw(void *opaque, uint32_t addr) |
5391d806 | 1659 | { |
bcbdc4d3 GH |
1660 | IDEBus *bus = opaque; |
1661 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1662 | uint8_t *p; |
1663 | int ret; | |
fcdd25ab | 1664 | |
40c4ed3f KW |
1665 | /* PIO data access allowed only when DRQ bit is set. The result of a read |
1666 | * during PIO in is indeterminate, return 0 and don't move forward. */ | |
1667 | if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { | |
fcdd25ab | 1668 | return 0; |
40c4ed3f | 1669 | } |
fcdd25ab | 1670 | |
5391d806 | 1671 | p = s->data_ptr; |
0c4ad8dc | 1672 | ret = cpu_to_le16(*(uint16_t *)p); |
5391d806 FB |
1673 | p += 2; |
1674 | s->data_ptr = p; | |
1675 | if (p >= s->data_end) | |
1676 | s->end_transfer_func(s); | |
1677 | return ret; | |
1678 | } | |
1679 | ||
356721ae | 1680 | void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) |
5391d806 | 1681 | { |
bcbdc4d3 GH |
1682 | IDEBus *bus = opaque; |
1683 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1684 | uint8_t *p; |
1685 | ||
40c4ed3f KW |
1686 | /* PIO data access allowed only when DRQ bit is set. The result of a write |
1687 | * during PIO out is indeterminate, just ignore it. */ | |
1688 | if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { | |
fcdd25ab | 1689 | return; |
40c4ed3f | 1690 | } |
fcdd25ab | 1691 | |
5391d806 | 1692 | p = s->data_ptr; |
0c4ad8dc | 1693 | *(uint32_t *)p = le32_to_cpu(val); |
5391d806 FB |
1694 | p += 4; |
1695 | s->data_ptr = p; | |
1696 | if (p >= s->data_end) | |
1697 | s->end_transfer_func(s); | |
1698 | } | |
1699 | ||
356721ae | 1700 | uint32_t ide_data_readl(void *opaque, uint32_t addr) |
5391d806 | 1701 | { |
bcbdc4d3 GH |
1702 | IDEBus *bus = opaque; |
1703 | IDEState *s = idebus_active_if(bus); | |
5391d806 FB |
1704 | uint8_t *p; |
1705 | int ret; | |
3b46e624 | 1706 | |
40c4ed3f KW |
1707 | /* PIO data access allowed only when DRQ bit is set. The result of a read |
1708 | * during PIO in is indeterminate, return 0 and don't move forward. */ | |
1709 | if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { | |
fcdd25ab | 1710 | return 0; |
40c4ed3f | 1711 | } |
fcdd25ab | 1712 | |
5391d806 | 1713 | p = s->data_ptr; |
0c4ad8dc | 1714 | ret = cpu_to_le32(*(uint32_t *)p); |
5391d806 FB |
1715 | p += 4; |
1716 | s->data_ptr = p; | |
1717 | if (p >= s->data_end) | |
1718 | s->end_transfer_func(s); | |
1719 | return ret; | |
1720 | } | |
1721 | ||
a7dfe172 FB |
1722 | static void ide_dummy_transfer_stop(IDEState *s) |
1723 | { | |
1724 | s->data_ptr = s->io_buffer; | |
1725 | s->data_end = s->io_buffer; | |
1726 | s->io_buffer[0] = 0xff; | |
1727 | s->io_buffer[1] = 0xff; | |
1728 | s->io_buffer[2] = 0xff; | |
1729 | s->io_buffer[3] = 0xff; | |
1730 | } | |
1731 | ||
4a643563 | 1732 | static void ide_reset(IDEState *s) |
5391d806 | 1733 | { |
4a643563 BS |
1734 | #ifdef DEBUG_IDE |
1735 | printf("ide: reset\n"); | |
1736 | #endif | |
cd8722bb | 1737 | if (s->drive_kind == IDE_CFATA) |
201a51fc AZ |
1738 | s->mult_sectors = 0; |
1739 | else | |
1740 | s->mult_sectors = MAX_MULT_SECTORS; | |
4a643563 BS |
1741 | /* ide regs */ |
1742 | s->feature = 0; | |
1743 | s->error = 0; | |
1744 | s->nsector = 0; | |
1745 | s->sector = 0; | |
1746 | s->lcyl = 0; | |
1747 | s->hcyl = 0; | |
1748 | ||
1749 | /* lba48 */ | |
1750 | s->hob_feature = 0; | |
1751 | s->hob_sector = 0; | |
1752 | s->hob_nsector = 0; | |
1753 | s->hob_lcyl = 0; | |
1754 | s->hob_hcyl = 0; | |
1755 | ||
5391d806 | 1756 | s->select = 0xa0; |
41a2b959 | 1757 | s->status = READY_STAT | SEEK_STAT; |
4a643563 BS |
1758 | |
1759 | s->lba48 = 0; | |
1760 | ||
1761 | /* ATAPI specific */ | |
1762 | s->sense_key = 0; | |
1763 | s->asc = 0; | |
1764 | s->cdrom_changed = 0; | |
1765 | s->packet_transfer_size = 0; | |
1766 | s->elementary_transfer_size = 0; | |
1767 | s->io_buffer_index = 0; | |
1768 | s->cd_sector_size = 0; | |
1769 | s->atapi_dma = 0; | |
1770 | /* ATA DMA state */ | |
1771 | s->io_buffer_size = 0; | |
1772 | s->req_nb_sectors = 0; | |
1773 | ||
5391d806 | 1774 | ide_set_signature(s); |
a7dfe172 FB |
1775 | /* init the transfer handler so that 0xffff is returned on data |
1776 | accesses */ | |
1777 | s->end_transfer_func = ide_dummy_transfer_stop; | |
1778 | ide_dummy_transfer_stop(s); | |
201a51fc | 1779 | s->media_changed = 0; |
5391d806 FB |
1780 | } |
1781 | ||
4a643563 BS |
1782 | void ide_bus_reset(IDEBus *bus) |
1783 | { | |
1784 | bus->unit = 0; | |
1785 | bus->cmd = 0; | |
1786 | ide_reset(&bus->ifs[0]); | |
1787 | ide_reset(&bus->ifs[1]); | |
1788 | ide_clear_hob(bus); | |
40a6238a AG |
1789 | |
1790 | /* pending async DMA */ | |
1791 | if (bus->dma->aiocb) { | |
1792 | #ifdef DEBUG_AIO | |
1793 | printf("aio_cancel\n"); | |
1794 | #endif | |
1795 | bdrv_aio_cancel(bus->dma->aiocb); | |
1796 | bus->dma->aiocb = NULL; | |
1797 | } | |
1798 | ||
1799 | /* reset dma provider too */ | |
1800 | bus->dma->ops->reset(bus->dma); | |
4a643563 BS |
1801 | } |
1802 | ||
e4def80b MA |
1803 | static bool ide_cd_is_tray_open(void *opaque) |
1804 | { | |
1805 | return ((IDEState *)opaque)->tray_open; | |
1806 | } | |
1807 | ||
f107639a MA |
1808 | static bool ide_cd_is_medium_locked(void *opaque) |
1809 | { | |
1810 | return ((IDEState *)opaque)->tray_locked; | |
1811 | } | |
1812 | ||
0e49de52 | 1813 | static const BlockDevOps ide_cd_block_ops = { |
145feb17 | 1814 | .change_media_cb = ide_cd_change_cb, |
2df0a3a3 | 1815 | .eject_request_cb = ide_cd_eject_request_cb, |
e4def80b | 1816 | .is_tray_open = ide_cd_is_tray_open, |
f107639a | 1817 | .is_medium_locked = ide_cd_is_medium_locked, |
0e49de52 MA |
1818 | }; |
1819 | ||
1f56e32a | 1820 | int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind, |
c4d74df7 | 1821 | const char *version, const char *serial) |
88804180 GH |
1822 | { |
1823 | int cylinders, heads, secs; | |
1824 | uint64_t nb_sectors; | |
1825 | ||
f8b6cc00 | 1826 | s->bs = bs; |
1f56e32a MA |
1827 | s->drive_kind = kind; |
1828 | ||
f8b6cc00 MA |
1829 | bdrv_get_geometry(bs, &nb_sectors); |
1830 | bdrv_guess_geometry(bs, &cylinders, &heads, &secs); | |
dce9e928 MA |
1831 | if (cylinders < 1 || cylinders > 16383) { |
1832 | error_report("cyls must be between 1 and 16383"); | |
1833 | return -1; | |
1834 | } | |
1835 | if (heads < 1 || heads > 16) { | |
1836 | error_report("heads must be between 1 and 16"); | |
1837 | return -1; | |
1838 | } | |
1839 | if (secs < 1 || secs > 63) { | |
1840 | error_report("secs must be between 1 and 63"); | |
1841 | return -1; | |
1842 | } | |
870111c8 MA |
1843 | s->cylinders = cylinders; |
1844 | s->heads = heads; | |
1845 | s->sectors = secs; | |
1846 | s->nb_sectors = nb_sectors; | |
1847 | /* The SMART values should be preserved across power cycles | |
1848 | but they aren't. */ | |
1849 | s->smart_enabled = 1; | |
1850 | s->smart_autosave = 1; | |
1851 | s->smart_errors = 0; | |
1852 | s->smart_selftest_count = 0; | |
1f56e32a | 1853 | if (kind == IDE_CD) { |
0e49de52 | 1854 | bdrv_set_dev_ops(bs, &ide_cd_block_ops, s); |
7b6f9300 | 1855 | bdrv_set_buffer_alignment(bs, 2048); |
7aa9c811 | 1856 | } else { |
98f28ad7 MA |
1857 | if (!bdrv_is_inserted(s->bs)) { |
1858 | error_report("Device needs media, but drive is empty"); | |
1859 | return -1; | |
1860 | } | |
7aa9c811 MA |
1861 | if (bdrv_is_read_only(bs)) { |
1862 | error_report("Can't use a read-only drive"); | |
1863 | return -1; | |
1864 | } | |
88804180 | 1865 | } |
f8b6cc00 | 1866 | if (serial) { |
6ced55a5 MA |
1867 | strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str)); |
1868 | } else { | |
88804180 GH |
1869 | snprintf(s->drive_serial_str, sizeof(s->drive_serial_str), |
1870 | "QM%05d", s->drive_serial); | |
870111c8 | 1871 | } |
47c06340 GH |
1872 | if (version) { |
1873 | pstrcpy(s->version, sizeof(s->version), version); | |
1874 | } else { | |
1875 | pstrcpy(s->version, sizeof(s->version), QEMU_VERSION); | |
1876 | } | |
40a6238a | 1877 | |
88804180 | 1878 | ide_reset(s); |
50fb1900 | 1879 | bdrv_iostatus_enable(bs); |
c4d74df7 | 1880 | return 0; |
88804180 GH |
1881 | } |
1882 | ||
57234ee4 | 1883 | static void ide_init1(IDEBus *bus, int unit) |
d459da0e MA |
1884 | { |
1885 | static int drive_serial = 1; | |
1886 | IDEState *s = &bus->ifs[unit]; | |
1887 | ||
1888 | s->bus = bus; | |
1889 | s->unit = unit; | |
1890 | s->drive_serial = drive_serial++; | |
1b2adf28 | 1891 | /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ |
50641c5c | 1892 | s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; |
c925400b KW |
1893 | s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); |
1894 | memset(s->io_buffer, 0, s->io_buffer_total_len); | |
1895 | ||
d459da0e | 1896 | s->smart_selftest_data = qemu_blockalign(s->bs, 512); |
c925400b KW |
1897 | memset(s->smart_selftest_data, 0, 512); |
1898 | ||
74475455 | 1899 | s->sector_write_timer = qemu_new_timer_ns(vm_clock, |
d459da0e | 1900 | ide_sector_write_timer_cb, s); |
57234ee4 MA |
1901 | } |
1902 | ||
40a6238a AG |
1903 | static void ide_nop_start(IDEDMA *dma, IDEState *s, |
1904 | BlockDriverCompletionFunc *cb) | |
1905 | { | |
1906 | } | |
1907 | ||
1908 | static int ide_nop(IDEDMA *dma) | |
1909 | { | |
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | static int ide_nop_int(IDEDMA *dma, int x) | |
1914 | { | |
1915 | return 0; | |
1916 | } | |
1917 | ||
1dfb4dd9 | 1918 | static void ide_nop_restart(void *opaque, int x, RunState y) |
40a6238a AG |
1919 | { |
1920 | } | |
1921 | ||
1922 | static const IDEDMAOps ide_dma_nop_ops = { | |
1923 | .start_dma = ide_nop_start, | |
1924 | .start_transfer = ide_nop, | |
1925 | .prepare_buf = ide_nop_int, | |
1926 | .rw_buf = ide_nop_int, | |
1927 | .set_unit = ide_nop_int, | |
1928 | .add_status = ide_nop_int, | |
1929 | .set_inactive = ide_nop, | |
1930 | .restart_cb = ide_nop_restart, | |
1931 | .reset = ide_nop, | |
1932 | }; | |
1933 | ||
1934 | static IDEDMA ide_dma_nop = { | |
1935 | .ops = &ide_dma_nop_ops, | |
1936 | .aiocb = NULL, | |
1937 | }; | |
1938 | ||
57234ee4 MA |
1939 | void ide_init2(IDEBus *bus, qemu_irq irq) |
1940 | { | |
1941 | int i; | |
1942 | ||
1943 | for(i = 0; i < 2; i++) { | |
1944 | ide_init1(bus, i); | |
1945 | ide_reset(&bus->ifs[i]); | |
870111c8 | 1946 | } |
57234ee4 | 1947 | bus->irq = irq; |
40a6238a | 1948 | bus->dma = &ide_dma_nop; |
d459da0e MA |
1949 | } |
1950 | ||
57234ee4 MA |
1951 | /* TODO convert users to qdev and remove */ |
1952 | void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0, | |
1953 | DriveInfo *hd1, qemu_irq irq) | |
5391d806 | 1954 | { |
88804180 | 1955 | int i; |
57234ee4 | 1956 | DriveInfo *dinfo; |
5391d806 | 1957 | |
caed8802 | 1958 | for(i = 0; i < 2; i++) { |
57234ee4 MA |
1959 | dinfo = i == 0 ? hd0 : hd1; |
1960 | ide_init1(bus, i); | |
1961 | if (dinfo) { | |
1f56e32a | 1962 | if (ide_init_drive(&bus->ifs[i], dinfo->bdrv, |
95b5edcd | 1963 | dinfo->media_cd ? IDE_CD : IDE_HD, NULL, |
c4d74df7 MA |
1964 | *dinfo->serial ? dinfo->serial : NULL) < 0) { |
1965 | error_report("Can't set up IDE drive %s", dinfo->id); | |
1966 | exit(1); | |
1967 | } | |
fa879d62 | 1968 | bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]); |
57234ee4 MA |
1969 | } else { |
1970 | ide_reset(&bus->ifs[i]); | |
1971 | } | |
5391d806 | 1972 | } |
9cdd03a7 | 1973 | bus->irq = irq; |
40a6238a | 1974 | bus->dma = &ide_dma_nop; |
69b91039 FB |
1975 | } |
1976 | ||
4a91d3b3 RH |
1977 | static const MemoryRegionPortio ide_portio_list[] = { |
1978 | { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write }, | |
1979 | { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew }, | |
1980 | { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel }, | |
1981 | PORTIO_END_OF_LIST(), | |
1982 | }; | |
1983 | ||
1984 | static const MemoryRegionPortio ide_portio2_list[] = { | |
1985 | { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write }, | |
1986 | PORTIO_END_OF_LIST(), | |
1987 | }; | |
1988 | ||
1989 | void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2) | |
69b91039 | 1990 | { |
4a91d3b3 RH |
1991 | /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA |
1992 | bridge has been setup properly to always register with ISA. */ | |
1993 | isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide"); | |
1994 | ||
caed8802 | 1995 | if (iobase2) { |
4a91d3b3 | 1996 | isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide"); |
5391d806 | 1997 | } |
5391d806 | 1998 | } |
69b91039 | 1999 | |
37159f13 | 2000 | static bool is_identify_set(void *opaque, int version_id) |
aa941b94 | 2001 | { |
37159f13 JQ |
2002 | IDEState *s = opaque; |
2003 | ||
2004 | return s->identify_set != 0; | |
2005 | } | |
2006 | ||
50641c5c JQ |
2007 | static EndTransferFunc* transfer_end_table[] = { |
2008 | ide_sector_read, | |
2009 | ide_sector_write, | |
2010 | ide_transfer_stop, | |
2011 | ide_atapi_cmd_reply_end, | |
2012 | ide_atapi_cmd, | |
2013 | ide_dummy_transfer_stop, | |
2014 | }; | |
2015 | ||
2016 | static int transfer_end_table_idx(EndTransferFunc *fn) | |
2017 | { | |
2018 | int i; | |
2019 | ||
2020 | for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) | |
2021 | if (transfer_end_table[i] == fn) | |
2022 | return i; | |
2023 | ||
2024 | return -1; | |
2025 | } | |
2026 | ||
37159f13 | 2027 | static int ide_drive_post_load(void *opaque, int version_id) |
aa941b94 | 2028 | { |
37159f13 JQ |
2029 | IDEState *s = opaque; |
2030 | ||
2031 | if (version_id < 3) { | |
67cc61e4 | 2032 | if (s->sense_key == UNIT_ATTENTION && |
37159f13 | 2033 | s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) { |
93c8cfd9 | 2034 | s->cdrom_changed = 1; |
37159f13 | 2035 | } |
93c8cfd9 | 2036 | } |
37159f13 | 2037 | return 0; |
aa941b94 AZ |
2038 | } |
2039 | ||
50641c5c JQ |
2040 | static int ide_drive_pio_post_load(void *opaque, int version_id) |
2041 | { | |
2042 | IDEState *s = opaque; | |
2043 | ||
fb60105d | 2044 | if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) { |
50641c5c JQ |
2045 | return -EINVAL; |
2046 | } | |
2047 | s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; | |
2048 | s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; | |
2049 | s->data_end = s->data_ptr + s->cur_io_buffer_len; | |
2050 | ||
2051 | return 0; | |
2052 | } | |
2053 | ||
2054 | static void ide_drive_pio_pre_save(void *opaque) | |
2055 | { | |
2056 | IDEState *s = opaque; | |
2057 | int idx; | |
2058 | ||
2059 | s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; | |
2060 | s->cur_io_buffer_len = s->data_end - s->data_ptr; | |
2061 | ||
2062 | idx = transfer_end_table_idx(s->end_transfer_func); | |
2063 | if (idx == -1) { | |
2064 | fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n", | |
2065 | __func__); | |
2066 | s->end_transfer_fn_idx = 2; | |
2067 | } else { | |
2068 | s->end_transfer_fn_idx = idx; | |
2069 | } | |
2070 | } | |
2071 | ||
2072 | static bool ide_drive_pio_state_needed(void *opaque) | |
2073 | { | |
2074 | IDEState *s = opaque; | |
2075 | ||
fdc650d7 KW |
2076 | return ((s->status & DRQ_STAT) != 0) |
2077 | || (s->bus->error_status & BM_STATUS_PIO_RETRY); | |
50641c5c JQ |
2078 | } |
2079 | ||
db118fe7 MA |
2080 | static bool ide_tray_state_needed(void *opaque) |
2081 | { | |
2082 | IDEState *s = opaque; | |
2083 | ||
2084 | return s->tray_open || s->tray_locked; | |
2085 | } | |
2086 | ||
996faf1a AS |
2087 | static bool ide_atapi_gesn_needed(void *opaque) |
2088 | { | |
2089 | IDEState *s = opaque; | |
2090 | ||
2091 | return s->events.new_media || s->events.eject_request; | |
2092 | } | |
2093 | ||
def93791 KW |
2094 | static bool ide_error_needed(void *opaque) |
2095 | { | |
2096 | IDEBus *bus = opaque; | |
2097 | ||
2098 | return (bus->error_status != 0); | |
2099 | } | |
2100 | ||
996faf1a | 2101 | /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */ |
656fbeff | 2102 | static const VMStateDescription vmstate_ide_atapi_gesn_state = { |
996faf1a AS |
2103 | .name ="ide_drive/atapi/gesn_state", |
2104 | .version_id = 1, | |
2105 | .minimum_version_id = 1, | |
2106 | .minimum_version_id_old = 1, | |
2107 | .fields = (VMStateField []) { | |
2108 | VMSTATE_BOOL(events.new_media, IDEState), | |
2109 | VMSTATE_BOOL(events.eject_request, IDEState), | |
0754f9ec | 2110 | VMSTATE_END_OF_LIST() |
996faf1a AS |
2111 | } |
2112 | }; | |
2113 | ||
db118fe7 MA |
2114 | static const VMStateDescription vmstate_ide_tray_state = { |
2115 | .name = "ide_drive/tray_state", | |
2116 | .version_id = 1, | |
2117 | .minimum_version_id = 1, | |
2118 | .minimum_version_id_old = 1, | |
db118fe7 MA |
2119 | .fields = (VMStateField[]) { |
2120 | VMSTATE_BOOL(tray_open, IDEState), | |
2121 | VMSTATE_BOOL(tray_locked, IDEState), | |
2122 | VMSTATE_END_OF_LIST() | |
2123 | } | |
2124 | }; | |
2125 | ||
656fbeff | 2126 | static const VMStateDescription vmstate_ide_drive_pio_state = { |
50641c5c JQ |
2127 | .name = "ide_drive/pio_state", |
2128 | .version_id = 1, | |
2129 | .minimum_version_id = 1, | |
2130 | .minimum_version_id_old = 1, | |
2131 | .pre_save = ide_drive_pio_pre_save, | |
2132 | .post_load = ide_drive_pio_post_load, | |
2133 | .fields = (VMStateField []) { | |
2134 | VMSTATE_INT32(req_nb_sectors, IDEState), | |
2135 | VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1, | |
2136 | vmstate_info_uint8, uint8_t), | |
2137 | VMSTATE_INT32(cur_io_buffer_offset, IDEState), | |
2138 | VMSTATE_INT32(cur_io_buffer_len, IDEState), | |
2139 | VMSTATE_UINT8(end_transfer_fn_idx, IDEState), | |
2140 | VMSTATE_INT32(elementary_transfer_size, IDEState), | |
2141 | VMSTATE_INT32(packet_transfer_size, IDEState), | |
2142 | VMSTATE_END_OF_LIST() | |
2143 | } | |
2144 | }; | |
2145 | ||
37159f13 JQ |
2146 | const VMStateDescription vmstate_ide_drive = { |
2147 | .name = "ide_drive", | |
3abb6260 | 2148 | .version_id = 3, |
37159f13 JQ |
2149 | .minimum_version_id = 0, |
2150 | .minimum_version_id_old = 0, | |
2151 | .post_load = ide_drive_post_load, | |
2152 | .fields = (VMStateField []) { | |
2153 | VMSTATE_INT32(mult_sectors, IDEState), | |
2154 | VMSTATE_INT32(identify_set, IDEState), | |
2155 | VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), | |
2156 | VMSTATE_UINT8(feature, IDEState), | |
2157 | VMSTATE_UINT8(error, IDEState), | |
2158 | VMSTATE_UINT32(nsector, IDEState), | |
2159 | VMSTATE_UINT8(sector, IDEState), | |
2160 | VMSTATE_UINT8(lcyl, IDEState), | |
2161 | VMSTATE_UINT8(hcyl, IDEState), | |
2162 | VMSTATE_UINT8(hob_feature, IDEState), | |
2163 | VMSTATE_UINT8(hob_sector, IDEState), | |
2164 | VMSTATE_UINT8(hob_nsector, IDEState), | |
2165 | VMSTATE_UINT8(hob_lcyl, IDEState), | |
2166 | VMSTATE_UINT8(hob_hcyl, IDEState), | |
2167 | VMSTATE_UINT8(select, IDEState), | |
2168 | VMSTATE_UINT8(status, IDEState), | |
2169 | VMSTATE_UINT8(lba48, IDEState), | |
2170 | VMSTATE_UINT8(sense_key, IDEState), | |
2171 | VMSTATE_UINT8(asc, IDEState), | |
2172 | VMSTATE_UINT8_V(cdrom_changed, IDEState, 3), | |
37159f13 | 2173 | VMSTATE_END_OF_LIST() |
50641c5c JQ |
2174 | }, |
2175 | .subsections = (VMStateSubsection []) { | |
2176 | { | |
2177 | .vmsd = &vmstate_ide_drive_pio_state, | |
2178 | .needed = ide_drive_pio_state_needed, | |
db118fe7 MA |
2179 | }, { |
2180 | .vmsd = &vmstate_ide_tray_state, | |
2181 | .needed = ide_tray_state_needed, | |
996faf1a AS |
2182 | }, { |
2183 | .vmsd = &vmstate_ide_atapi_gesn_state, | |
2184 | .needed = ide_atapi_gesn_needed, | |
50641c5c JQ |
2185 | }, { |
2186 | /* empty */ | |
2187 | } | |
37159f13 JQ |
2188 | } |
2189 | }; | |
2190 | ||
656fbeff | 2191 | static const VMStateDescription vmstate_ide_error_status = { |
def93791 KW |
2192 | .name ="ide_bus/error", |
2193 | .version_id = 1, | |
2194 | .minimum_version_id = 1, | |
2195 | .minimum_version_id_old = 1, | |
2196 | .fields = (VMStateField []) { | |
2197 | VMSTATE_INT32(error_status, IDEBus), | |
2198 | VMSTATE_END_OF_LIST() | |
2199 | } | |
2200 | }; | |
2201 | ||
6521dc62 JQ |
2202 | const VMStateDescription vmstate_ide_bus = { |
2203 | .name = "ide_bus", | |
2204 | .version_id = 1, | |
2205 | .minimum_version_id = 1, | |
2206 | .minimum_version_id_old = 1, | |
2207 | .fields = (VMStateField []) { | |
2208 | VMSTATE_UINT8(cmd, IDEBus), | |
2209 | VMSTATE_UINT8(unit, IDEBus), | |
2210 | VMSTATE_END_OF_LIST() | |
def93791 KW |
2211 | }, |
2212 | .subsections = (VMStateSubsection []) { | |
2213 | { | |
2214 | .vmsd = &vmstate_ide_error_status, | |
2215 | .needed = ide_error_needed, | |
2216 | }, { | |
2217 | /* empty */ | |
2218 | } | |
6521dc62 JQ |
2219 | } |
2220 | }; | |
75717903 IY |
2221 | |
2222 | void ide_drive_get(DriveInfo **hd, int max_bus) | |
2223 | { | |
2224 | int i; | |
2225 | ||
2226 | if (drive_get_max_bus(IF_IDE) >= max_bus) { | |
2227 | fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus); | |
2228 | exit(1); | |
2229 | } | |
2230 | ||
2231 | for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) { | |
2232 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
2233 | } | |
2234 | } |