[qemu.git] / hw / ide / macio.c

/*
 * QEMU IDE Emulation: MacIO support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/ppc_mac.h>
#include <hw/mac_dbdma.h>
#include "block.h"
#include "block_int.h"
#include "dma.h"

#include <hw/ide/internal.h>

/***********************************************************/
/* MacIO based PowerPC IDE */

typedef struct MACIOIDEState {
    IDEBus bus;
    BlockDriverAIOCB *aiocb;
} MACIOIDEState;

#define MACIO_PAGE_SIZE 4096

static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        ide_atapi_io_error(s, ret);
        io->dma_end(opaque);
        return;
    }

    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);

        s->packet_transfer_size -= s->io_buffer_size;

        s->io_buffer_index += s->io_buffer_size;
	s->lba += s->io_buffer_index >> 11;
        s->io_buffer_index &= 0x7ff;
    }

    if (s->packet_transfer_size <= 0)
        ide_atapi_cmd_ok(s);

    if (io->len == 0) {
        io->dma_end(opaque);
        return;
    }

    /* launch next transfer */

    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    m->aiocb = dma_bdrv_read(s->bs, &s->sg,
                             (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
                             pmac_ide_atapi_transfer_cb, io);
    if (!m->aiocb) {
        qemu_sglist_destroy(&s->sg);
        /* Note: media not present is the most likely case */
        ide_atapi_cmd_error(s, SENSE_NOT_READY,
                            ASC_MEDIUM_NOT_PRESENT);
        io->dma_end(opaque);
        return;
    }
}

static void pmac_ide_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);
    int n;
    int64_t sector_num;

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
	ide_dma_error(s);
        io->dma_end(io);
        return;
    }

    sector_num = ide_get_sector(s);
    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        n = (s->io_buffer_size + 0x1ff) >> 9;
        sector_num += n;
        ide_set_sector(s, sector_num);
        s->nsector -= n;
    }

    /* end of transfer ? */
    if (s->nsector == 0) {
        s->status = READY_STAT | SEEK_STAT;
        ide_set_irq(s->bus);
    }

    /* end of DMA ? */

    if (io->len == 0) {
        io->dma_end(io);
	return;
    }

    /* launch next transfer */

    s->io_buffer_index = 0;
    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    if (s->is_read)
        m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
		                 pmac_ide_transfer_cb, io);
    else
        m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
		                  pmac_ide_transfer_cb, io);
    if (!m->aiocb)
        pmac_ide_transfer_cb(io, -1);
}

static void pmac_ide_transfer(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    s->io_buffer_size = 0;
    if (s->drive_kind == IDE_CD) {
        pmac_ide_atapi_transfer_cb(io, 0);
        return;
    }

    pmac_ide_transfer_cb(io, 0);
}

static void pmac_ide_flush(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;

    if (m->aiocb)
        qemu_aio_flush();
}

/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        ide_ioport_write(&d->bus, addr, val);
        break;
    case 8:
    case 22:
        ide_cmd_write(&d->bus, 0, val);
        break;
    default:
        break;
    }
}

static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
{
    uint8_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        retval = ide_ioport_read(&d->bus, addr);
        break;
    case 8:
    case 22:
        retval = ide_status_read(&d->bus, 0);
        break;
    default:
        retval = 0xFF;
        break;
    }
    return retval;
}

static void pmac_ide_writew (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap16(val);
    if (addr == 0) {
        ide_data_writew(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
{
    uint16_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readw(&d->bus, 0);
    } else {
        retval = 0xFFFF;
    }
    retval = bswap16(retval);
    return retval;
}

static void pmac_ide_writel (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap32(val);
    if (addr == 0) {
        ide_data_writel(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
{
    uint32_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readl(&d->bus, 0);
    } else {
        retval = 0xFFFFFFFF;
    }
    retval = bswap32(retval);
    return retval;
}

static CPUWriteMemoryFunc * const pmac_ide_write[] = {
    pmac_ide_writeb,
    pmac_ide_writew,
    pmac_ide_writel,
};

static CPUReadMemoryFunc * const pmac_ide_read[] = {
    pmac_ide_readb,
    pmac_ide_readw,
    pmac_ide_readl,
};

static const VMStateDescription vmstate_pmac = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField []) {
        VMSTATE_IDE_BUS(bus, MACIOIDEState),
        VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
        VMSTATE_END_OF_LIST()
    }
};

static void pmac_ide_reset(void *opaque)
{
    MACIOIDEState *d = opaque;

    ide_bus_reset(&d->bus);
}

/* hd_table must contain 4 block drivers */
/* PowerMac uses memory mapped registers, not I/O. Return the memory
   I/O index to access the ide. */
int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
		   void *dbdma, int channel, qemu_irq dma_irq)
{
    MACIOIDEState *d;
    int pmac_ide_memory;

    d = qemu_mallocz(sizeof(MACIOIDEState));
    ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);

    if (dbdma)
        DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);

    pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
                                             pmac_ide_write, d,
                                             DEVICE_NATIVE_ENDIAN);
    vmstate_register(NULL, 0, &vmstate_pmac, d);
    qemu_register_reset(pmac_ide_reset, d);

    return pmac_ide_memory;
}
Commit	Line	Data
b8842209 GH	1	/*
	2	* QEMU IDE Emulation: MacIO support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787 GH	25	#include <hw/hw.h>
	26	#include <hw/ppc_mac.h>
	27	#include <hw/mac_dbdma.h>
b8842209 GH	28	#include "block.h"
b8842209 GH	29	#include "block_int.h"
b8842209	30	#include "dma.h"
59f2a787 GH	31
59f2a787 GH	32	#include <hw/ide/internal.h>
b8842209 GH	33
	34	/***********************************************************/
	35	/* MacIO based PowerPC IDE */
	36
	37	typedef struct MACIOIDEState {
	38	IDEBus bus;
	39	BlockDriverAIOCB *aiocb;
	40	} MACIOIDEState;
	41
02c7c992 BS	42	#define MACIO_PAGE_SIZE 4096
02c7c992 BS	43
b8842209 GH	44	static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
	45	{
	46	DBDMA_io *io = opaque;
	47	MACIOIDEState *m = io->opaque;
	48	IDEState *s = idebus_active_if(&m->bus);
	49
	50	if (ret < 0) {
	51	m->aiocb = NULL;
	52	qemu_sglist_destroy(&s->sg);
	53	ide_atapi_io_error(s, ret);
	54	io->dma_end(opaque);
	55	return;
	56	}
	57
	58	if (s->io_buffer_size > 0) {
	59	m->aiocb = NULL;
	60	qemu_sglist_destroy(&s->sg);
	61
	62	s->packet_transfer_size -= s->io_buffer_size;
	63
	64	s->io_buffer_index += s->io_buffer_size;
	65	s->lba += s->io_buffer_index >> 11;
	66	s->io_buffer_index &= 0x7ff;
	67	}
	68
	69	if (s->packet_transfer_size <= 0)
	70	ide_atapi_cmd_ok(s);
	71
	72	if (io->len == 0) {
	73	io->dma_end(opaque);
	74	return;
	75	}
	76
	77	/* launch next transfer */
	78
	79	s->io_buffer_size = io->len;
	80
02c7c992	81	qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
b8842209 GH	82	qemu_sglist_add(&s->sg, io->addr, io->len);
	83	io->addr += io->len;
	84	io->len = 0;
	85
	86	m->aiocb = dma_bdrv_read(s->bs, &s->sg,
	87	(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
	88	pmac_ide_atapi_transfer_cb, io);
	89	if (!m->aiocb) {
	90	qemu_sglist_destroy(&s->sg);
	91	/* Note: media not present is the most likely case */
	92	ide_atapi_cmd_error(s, SENSE_NOT_READY,
	93	ASC_MEDIUM_NOT_PRESENT);
	94	io->dma_end(opaque);
	95	return;
	96	}
	97	}
	98
	99	static void pmac_ide_transfer_cb(void *opaque, int ret)
	100	{
	101	DBDMA_io *io = opaque;
	102	MACIOIDEState *m = io->opaque;
	103	IDEState *s = idebus_active_if(&m->bus);
	104	int n;
	105	int64_t sector_num;
	106
	107	if (ret < 0) {
	108	m->aiocb = NULL;
	109	qemu_sglist_destroy(&s->sg);
	110	ide_dma_error(s);
	111	io->dma_end(io);
	112	return;
	113	}
	114
	115	sector_num = ide_get_sector(s);
	116	if (s->io_buffer_size > 0) {
	117	m->aiocb = NULL;
	118	qemu_sglist_destroy(&s->sg);
	119	n = (s->io_buffer_size + 0x1ff) >> 9;
	120	sector_num += n;
	121	ide_set_sector(s, sector_num);
	122	s->nsector -= n;
	123	}
	124
	125	/* end of transfer ? */
	126	if (s->nsector == 0) {
	127	s->status = READY_STAT \| SEEK_STAT;
9cdd03a7	128	ide_set_irq(s->bus);
b8842209 GH	129	}
	130
	131	/* end of DMA ? */
	132
	133	if (io->len == 0) {
	134	io->dma_end(io);
	135	return;
	136	}
	137
	138	/* launch next transfer */
	139
	140	s->io_buffer_index = 0;
	141	s->io_buffer_size = io->len;
	142
02c7c992	143	qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
b8842209 GH	144	qemu_sglist_add(&s->sg, io->addr, io->len);
	145	io->addr += io->len;
	146	io->len = 0;
	147
	148	if (s->is_read)
	149	m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
	150	pmac_ide_transfer_cb, io);
	151	else
	152	m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
	153	pmac_ide_transfer_cb, io);
	154	if (!m->aiocb)
	155	pmac_ide_transfer_cb(io, -1);
	156	}
	157
	158	static void pmac_ide_transfer(DBDMA_io *io)
	159	{
	160	MACIOIDEState *m = io->opaque;
	161	IDEState *s = idebus_active_if(&m->bus);
	162
	163	s->io_buffer_size = 0;
cd8722bb	164	if (s->drive_kind == IDE_CD) {
b8842209 GH	165	pmac_ide_atapi_transfer_cb(io, 0);
	166	return;
	167	}
	168
	169	pmac_ide_transfer_cb(io, 0);
	170	}
	171
	172	static void pmac_ide_flush(DBDMA_io *io)
	173	{
	174	MACIOIDEState *m = io->opaque;
	175
	176	if (m->aiocb)
	177	qemu_aio_flush();
	178	}
	179
	180	/* PowerMac IDE memory IO */
	181	static void pmac_ide_writeb (void *opaque,
c227f099	182	target_phys_addr_t addr, uint32_t val)
b8842209 GH	183	{
	184	MACIOIDEState *d = opaque;
	185
	186	addr = (addr & 0xFFF) >> 4;
	187	switch (addr) {
	188	case 1 ... 7:
	189	ide_ioport_write(&d->bus, addr, val);
	190	break;
	191	case 8:
	192	case 22:
	193	ide_cmd_write(&d->bus, 0, val);
	194	break;
	195	default:
	196	break;
	197	}
	198	}
	199
c227f099	200	static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
b8842209 GH	201	{
	202	uint8_t retval;
	203	MACIOIDEState *d = opaque;
	204
	205	addr = (addr & 0xFFF) >> 4;
	206	switch (addr) {
	207	case 1 ... 7:
	208	retval = ide_ioport_read(&d->bus, addr);
	209	break;
	210	case 8:
	211	case 22:
	212	retval = ide_status_read(&d->bus, 0);
	213	break;
	214	default:
	215	retval = 0xFF;
	216	break;
	217	}
	218	return retval;
	219	}
	220
	221	static void pmac_ide_writew (void *opaque,
c227f099	222	target_phys_addr_t addr, uint32_t val)
b8842209 GH	223	{
	224	MACIOIDEState *d = opaque;
	225
	226	addr = (addr & 0xFFF) >> 4;
b8842209	227	val = bswap16(val);
b8842209 GH	228	if (addr == 0) {
	229	ide_data_writew(&d->bus, 0, val);
	230	}
	231	}
	232
c227f099	233	static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
b8842209 GH	234	{
	235	uint16_t retval;
	236	MACIOIDEState *d = opaque;
	237
	238	addr = (addr & 0xFFF) >> 4;
	239	if (addr == 0) {
	240	retval = ide_data_readw(&d->bus, 0);
	241	} else {
	242	retval = 0xFFFF;
	243	}
b8842209	244	retval = bswap16(retval);
b8842209 GH	245	return retval;
	246	}
	247
	248	static void pmac_ide_writel (void *opaque,
c227f099	249	target_phys_addr_t addr, uint32_t val)
b8842209 GH	250	{
	251	MACIOIDEState *d = opaque;
	252
	253	addr = (addr & 0xFFF) >> 4;
b8842209	254	val = bswap32(val);
b8842209 GH	255	if (addr == 0) {
	256	ide_data_writel(&d->bus, 0, val);
	257	}
	258	}
	259
c227f099	260	static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
b8842209 GH	261	{
	262	uint32_t retval;
	263	MACIOIDEState *d = opaque;
	264
	265	addr = (addr & 0xFFF) >> 4;
	266	if (addr == 0) {
	267	retval = ide_data_readl(&d->bus, 0);
	268	} else {
	269	retval = 0xFFFFFFFF;
	270	}
b8842209	271	retval = bswap32(retval);
b8842209 GH	272	return retval;
	273	}
	274
bdae2298	275	static CPUWriteMemoryFunc * const pmac_ide_write[] = {
b8842209 GH	276	pmac_ide_writeb,
	277	pmac_ide_writew,
	278	pmac_ide_writel,
	279	};
	280
bdae2298	281	static CPUReadMemoryFunc * const pmac_ide_read[] = {
b8842209 GH	282	pmac_ide_readb,
	283	pmac_ide_readw,
	284	pmac_ide_readl,
	285	};
	286
44bfa332 JQ	287	static const VMStateDescription vmstate_pmac = {
	288	.name = "ide",
	289	.version_id = 3,
	290	.minimum_version_id = 0,
	291	.minimum_version_id_old = 0,
	292	.fields = (VMStateField []) {
	293	VMSTATE_IDE_BUS(bus, MACIOIDEState),
	294	VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
	295	VMSTATE_END_OF_LIST()
b8842209	296	}
44bfa332	297	};
b8842209 GH	298
	299	static void pmac_ide_reset(void *opaque)
	300	{
	301	MACIOIDEState *d = opaque;
	302
4a643563	303	ide_bus_reset(&d->bus);
b8842209 GH	304	}
	305
	306	/* hd_table must contain 4 block drivers */
	307	/* PowerMac uses memory mapped registers, not I/O. Return the memory
	308	I/O index to access the ide. */
f455e98c	309	int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
b8842209 GH	310	void *dbdma, int channel, qemu_irq dma_irq)
	311	{
	312	MACIOIDEState *d;
	313	int pmac_ide_memory;
	314
	315	d = qemu_mallocz(sizeof(MACIOIDEState));
57234ee4	316	ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
b8842209 GH	317
	318	if (dbdma)
	319	DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
	320
	321	pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
2507c12a AG	322	pmac_ide_write, d,
2507c12a AG	323	DEVICE_NATIVE_ENDIAN);
0be71e32	324	vmstate_register(NULL, 0, &vmstate_pmac, d);
b8842209	325	qemu_register_reset(pmac_ide_reset, d);
b8842209 GH	326
	327	return pmac_ide_memory;
	328	}