[qemu.git] / hw / ide / macio.c

/*
 * QEMU IDE Emulation: MacIO support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/ppc_mac.h>
#include <hw/mac_dbdma.h>
#include "block.h"
#include "dma.h"

#include <hw/ide/internal.h>

/***********************************************************/
/* MacIO based PowerPC IDE */

typedef struct MACIOIDEState {
    MemoryRegion mem;
    IDEBus bus;
    BlockDriverAIOCB *aiocb;
} MACIOIDEState;

#define MACIO_PAGE_SIZE 4096

static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        ide_atapi_io_error(s, ret);
        goto done;
    }

    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);

        s->packet_transfer_size -= s->io_buffer_size;

        s->io_buffer_index += s->io_buffer_size;
	s->lba += s->io_buffer_index >> 11;
        s->io_buffer_index &= 0x7ff;
    }

    if (s->packet_transfer_size <= 0)
        ide_atapi_cmd_ok(s);

    if (io->len == 0) {
        goto done;
    }

    /* launch next transfer */

    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    m->aiocb = dma_bdrv_read(s->bs, &s->sg,
                             (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
                             pmac_ide_atapi_transfer_cb, io);
    return;

done:
    bdrv_acct_done(s->bs, &s->acct);
    io->dma_end(opaque);
    return;
}

static void pmac_ide_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);
    int n;
    int64_t sector_num;

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
	ide_dma_error(s);
        goto done;
    }

    sector_num = ide_get_sector(s);
    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        n = (s->io_buffer_size + 0x1ff) >> 9;
        sector_num += n;
        ide_set_sector(s, sector_num);
        s->nsector -= n;
    }

    /* end of transfer ? */
    if (s->nsector == 0) {
        s->status = READY_STAT | SEEK_STAT;
        ide_set_irq(s->bus);
    }

    /* end of DMA ? */
    if (io->len == 0) {
        goto done;
    }

    /* launch next transfer */

    s->io_buffer_index = 0;
    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    switch (s->dma_cmd) {
    case IDE_DMA_READ:
        m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
		                 pmac_ide_transfer_cb, io);
        break;
    case IDE_DMA_WRITE:
        m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
		                  pmac_ide_transfer_cb, io);
        break;
    case IDE_DMA_TRIM:
        m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
                               ide_issue_trim, pmac_ide_transfer_cb, s, true);
        break;
    }

    if (!m->aiocb)
        pmac_ide_transfer_cb(io, -1);
    return;
done:
    if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
        bdrv_acct_done(s->bs, &s->acct);
    }
    io->dma_end(io);
}

static void pmac_ide_transfer(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    s->io_buffer_size = 0;
    if (s->drive_kind == IDE_CD) {
        bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
        pmac_ide_atapi_transfer_cb(io, 0);
        return;
    }

    switch (s->dma_cmd) {
    case IDE_DMA_READ:
        bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
        break;
    case IDE_DMA_WRITE:
        bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
        break;
    default:
        break;
    }

    pmac_ide_transfer_cb(io, 0);
}

static void pmac_ide_flush(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;

    if (m->aiocb) {
        bdrv_drain_all();
    }
}

/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        ide_ioport_write(&d->bus, addr, val);
        break;
    case 8:
    case 22:
        ide_cmd_write(&d->bus, 0, val);
        break;
    default:
        break;
    }
}

static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
{
    uint8_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        retval = ide_ioport_read(&d->bus, addr);
        break;
    case 8:
    case 22:
        retval = ide_status_read(&d->bus, 0);
        break;
    default:
        retval = 0xFF;
        break;
    }
    return retval;
}

static void pmac_ide_writew (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap16(val);
    if (addr == 0) {
        ide_data_writew(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
{
    uint16_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readw(&d->bus, 0);
    } else {
        retval = 0xFFFF;
    }
    retval = bswap16(retval);
    return retval;
}

static void pmac_ide_writel (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap32(val);
    if (addr == 0) {
        ide_data_writel(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
{
    uint32_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readl(&d->bus, 0);
    } else {
        retval = 0xFFFFFFFF;
    }
    retval = bswap32(retval);
    return retval;
}

static MemoryRegionOps pmac_ide_ops = {
    .old_mmio = {
        .write = {
            pmac_ide_writeb,
            pmac_ide_writew,
            pmac_ide_writel,
        },
        .read = {
            pmac_ide_readb,
            pmac_ide_readw,
            pmac_ide_readl,
        },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_pmac = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField []) {
        VMSTATE_IDE_BUS(bus, MACIOIDEState),
        VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
        VMSTATE_END_OF_LIST()
    }
};

static void pmac_ide_reset(void *opaque)
{
    MACIOIDEState *d = opaque;

    ide_bus_reset(&d->bus);
}

/* hd_table must contain 4 block drivers */
/* PowerMac uses memory mapped registers, not I/O. Return the memory
   I/O index to access the ide. */
MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
                             void *dbdma, int channel, qemu_irq dma_irq)
{
    MACIOIDEState *d;

    d = g_malloc0(sizeof(MACIOIDEState));
    ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);

    if (dbdma)
        DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);

    memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000);
    vmstate_register(NULL, 0, &vmstate_pmac, d);
    qemu_register_reset(pmac_ide_reset, d);

    return &d->mem;
}
Commit	Line	Data
b8842209 GH	1	/*
	2	* QEMU IDE Emulation: MacIO support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787 GH	25	#include <hw/hw.h>
	26	#include <hw/ppc_mac.h>
	27	#include <hw/mac_dbdma.h>
b8842209	28	#include "block.h"
b8842209	29	#include "dma.h"
59f2a787 GH	30
59f2a787 GH	31	#include <hw/ide/internal.h>
b8842209 GH	32
	33	/***********************************************************/
	34	/* MacIO based PowerPC IDE */
	35
	36	typedef struct MACIOIDEState {
23c5e4ca	37	MemoryRegion mem;
b8842209 GH	38	IDEBus bus;
	39	BlockDriverAIOCB *aiocb;
	40	} MACIOIDEState;
	41
02c7c992 BS	42	#define MACIO_PAGE_SIZE 4096
02c7c992 BS	43
b8842209 GH	44	static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
	45	{
	46	DBDMA_io *io = opaque;
	47	MACIOIDEState *m = io->opaque;
	48	IDEState *s = idebus_active_if(&m->bus);
	49
	50	if (ret < 0) {
	51	m->aiocb = NULL;
	52	qemu_sglist_destroy(&s->sg);
	53	ide_atapi_io_error(s, ret);
a597e79c	54	goto done;
b8842209 GH	55	}
	56
	57	if (s->io_buffer_size > 0) {
	58	m->aiocb = NULL;
	59	qemu_sglist_destroy(&s->sg);
	60
	61	s->packet_transfer_size -= s->io_buffer_size;
	62
	63	s->io_buffer_index += s->io_buffer_size;
	64	s->lba += s->io_buffer_index >> 11;
	65	s->io_buffer_index &= 0x7ff;
	66	}
	67
	68	if (s->packet_transfer_size <= 0)
	69	ide_atapi_cmd_ok(s);
	70
	71	if (io->len == 0) {
a597e79c	72	goto done;
b8842209 GH	73	}
	74
	75	/* launch next transfer */
	76
	77	s->io_buffer_size = io->len;
	78
02c7c992	79	qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
b8842209 GH	80	qemu_sglist_add(&s->sg, io->addr, io->len);
	81	io->addr += io->len;
	82	io->len = 0;
	83
	84	m->aiocb = dma_bdrv_read(s->bs, &s->sg,
	85	(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
	86	pmac_ide_atapi_transfer_cb, io);
a597e79c CH	87	return;
	88
	89	done:
	90	bdrv_acct_done(s->bs, &s->acct);
	91	io->dma_end(opaque);
	92	return;
b8842209 GH	93	}
	94
	95	static void pmac_ide_transfer_cb(void *opaque, int ret)
	96	{
	97	DBDMA_io *io = opaque;
	98	MACIOIDEState *m = io->opaque;
	99	IDEState *s = idebus_active_if(&m->bus);
	100	int n;
	101	int64_t sector_num;
	102
	103	if (ret < 0) {
	104	m->aiocb = NULL;
	105	qemu_sglist_destroy(&s->sg);
	106	ide_dma_error(s);
a597e79c	107	goto done;
b8842209 GH	108	}
	109
	110	sector_num = ide_get_sector(s);
	111	if (s->io_buffer_size > 0) {
	112	m->aiocb = NULL;
	113	qemu_sglist_destroy(&s->sg);
	114	n = (s->io_buffer_size + 0x1ff) >> 9;
	115	sector_num += n;
	116	ide_set_sector(s, sector_num);
	117	s->nsector -= n;
	118	}
	119
	120	/* end of transfer ? */
	121	if (s->nsector == 0) {
	122	s->status = READY_STAT \| SEEK_STAT;
9cdd03a7	123	ide_set_irq(s->bus);
b8842209 GH	124	}
	125
	126	/* end of DMA ? */
b8842209	127	if (io->len == 0) {
a597e79c	128	goto done;
b8842209 GH	129	}
	130
	131	/* launch next transfer */
	132
	133	s->io_buffer_index = 0;
	134	s->io_buffer_size = io->len;
	135
02c7c992	136	qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
b8842209 GH	137	qemu_sglist_add(&s->sg, io->addr, io->len);
	138	io->addr += io->len;
	139	io->len = 0;
	140
4e1e0051 CH	141	switch (s->dma_cmd) {
4e1e0051 CH	142	case IDE_DMA_READ:
b8842209 GH	143	m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
b8842209 GH	144	pmac_ide_transfer_cb, io);
4e1e0051 CH	145	break;
4e1e0051 CH	146	case IDE_DMA_WRITE:
b8842209 GH	147	m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
b8842209 GH	148	pmac_ide_transfer_cb, io);
4e1e0051	149	break;
d353fb72 CH	150	case IDE_DMA_TRIM:
d353fb72 CH	151	m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
bbca72c6	152	ide_issue_trim, pmac_ide_transfer_cb, s, true);
d353fb72	153	break;
4e1e0051 CH	154	}
4e1e0051 CH	155
b8842209 GH	156	if (!m->aiocb)
b8842209 GH	157	pmac_ide_transfer_cb(io, -1);
a597e79c CH	158	return;
	159	done:
	160	if (s->dma_cmd == IDE_DMA_READ \|\| s->dma_cmd == IDE_DMA_WRITE) {
	161	bdrv_acct_done(s->bs, &s->acct);
	162	}
	163	io->dma_end(io);
b8842209 GH	164	}
	165
	166	static void pmac_ide_transfer(DBDMA_io *io)
	167	{
	168	MACIOIDEState *m = io->opaque;
	169	IDEState *s = idebus_active_if(&m->bus);
	170
	171	s->io_buffer_size = 0;
cd8722bb	172	if (s->drive_kind == IDE_CD) {
a597e79c	173	bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
b8842209 GH	174	pmac_ide_atapi_transfer_cb(io, 0);
	175	return;
	176	}
	177
a597e79c CH	178	switch (s->dma_cmd) {
	179	case IDE_DMA_READ:
	180	bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
	181	break;
	182	case IDE_DMA_WRITE:
	183	bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
	184	break;
	185	default:
	186	break;
	187	}
	188
b8842209 GH	189	pmac_ide_transfer_cb(io, 0);
	190	}
	191
	192	static void pmac_ide_flush(DBDMA_io *io)
	193	{
	194	MACIOIDEState *m = io->opaque;
	195
922453bc SH	196	if (m->aiocb) {
	197	bdrv_drain_all();
	198	}
b8842209 GH	199	}
	200
	201	/* PowerMac IDE memory IO */
	202	static void pmac_ide_writeb (void *opaque,
c227f099	203	target_phys_addr_t addr, uint32_t val)
b8842209 GH	204	{
	205	MACIOIDEState *d = opaque;
	206
	207	addr = (addr & 0xFFF) >> 4;
	208	switch (addr) {
	209	case 1 ... 7:
	210	ide_ioport_write(&d->bus, addr, val);
	211	break;
	212	case 8:
	213	case 22:
	214	ide_cmd_write(&d->bus, 0, val);
	215	break;
	216	default:
	217	break;
	218	}
	219	}
	220
c227f099	221	static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
b8842209 GH	222	{
	223	uint8_t retval;
	224	MACIOIDEState *d = opaque;
	225
	226	addr = (addr & 0xFFF) >> 4;
	227	switch (addr) {
	228	case 1 ... 7:
	229	retval = ide_ioport_read(&d->bus, addr);
	230	break;
	231	case 8:
	232	case 22:
	233	retval = ide_status_read(&d->bus, 0);
	234	break;
	235	default:
	236	retval = 0xFF;
	237	break;
	238	}
	239	return retval;
	240	}
	241
	242	static void pmac_ide_writew (void *opaque,
c227f099	243	target_phys_addr_t addr, uint32_t val)
b8842209 GH	244	{
	245	MACIOIDEState *d = opaque;
	246
	247	addr = (addr & 0xFFF) >> 4;
b8842209	248	val = bswap16(val);
b8842209 GH	249	if (addr == 0) {
	250	ide_data_writew(&d->bus, 0, val);
	251	}
	252	}
	253
c227f099	254	static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
b8842209 GH	255	{
	256	uint16_t retval;
	257	MACIOIDEState *d = opaque;
	258
	259	addr = (addr & 0xFFF) >> 4;
	260	if (addr == 0) {
	261	retval = ide_data_readw(&d->bus, 0);
	262	} else {
	263	retval = 0xFFFF;
	264	}
b8842209	265	retval = bswap16(retval);
b8842209 GH	266	return retval;
	267	}
	268
	269	static void pmac_ide_writel (void *opaque,
c227f099	270	target_phys_addr_t addr, uint32_t val)
b8842209 GH	271	{
	272	MACIOIDEState *d = opaque;
	273
	274	addr = (addr & 0xFFF) >> 4;
b8842209	275	val = bswap32(val);
b8842209 GH	276	if (addr == 0) {
	277	ide_data_writel(&d->bus, 0, val);
	278	}
	279	}
	280
c227f099	281	static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
b8842209 GH	282	{
	283	uint32_t retval;
	284	MACIOIDEState *d = opaque;
	285
	286	addr = (addr & 0xFFF) >> 4;
	287	if (addr == 0) {
	288	retval = ide_data_readl(&d->bus, 0);
	289	} else {
	290	retval = 0xFFFFFFFF;
	291	}
b8842209	292	retval = bswap32(retval);
b8842209 GH	293	return retval;
	294	}
	295
23c5e4ca AK	296	static MemoryRegionOps pmac_ide_ops = {
	297	.old_mmio = {
	298	.write = {
	299	pmac_ide_writeb,
	300	pmac_ide_writew,
	301	pmac_ide_writel,
	302	},
	303	.read = {
	304	pmac_ide_readb,
	305	pmac_ide_readw,
	306	pmac_ide_readl,
	307	},
	308	},
	309	.endianness = DEVICE_NATIVE_ENDIAN,
b8842209 GH	310	};
b8842209 GH	311
44bfa332 JQ	312	static const VMStateDescription vmstate_pmac = {
	313	.name = "ide",
	314	.version_id = 3,
	315	.minimum_version_id = 0,
	316	.minimum_version_id_old = 0,
	317	.fields = (VMStateField []) {
	318	VMSTATE_IDE_BUS(bus, MACIOIDEState),
	319	VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
	320	VMSTATE_END_OF_LIST()
b8842209	321	}
44bfa332	322	};
b8842209 GH	323
	324	static void pmac_ide_reset(void *opaque)
	325	{
	326	MACIOIDEState *d = opaque;
	327
4a643563	328	ide_bus_reset(&d->bus);
b8842209 GH	329	}
	330
	331	/* hd_table must contain 4 block drivers */
	332	/* PowerMac uses memory mapped registers, not I/O. Return the memory
	333	I/O index to access the ide. */
23c5e4ca AK	334	MemoryRegion pmac_ide_init (DriveInfo *hd_table, qemu_irq irq,
23c5e4ca AK	335	void *dbdma, int channel, qemu_irq dma_irq)
b8842209 GH	336	{
b8842209 GH	337	MACIOIDEState *d;
b8842209	338
7267c094	339	d = g_malloc0(sizeof(MACIOIDEState));
57234ee4	340	ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
b8842209 GH	341
	342	if (dbdma)
	343	DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
	344
23c5e4ca	345	memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000);
0be71e32	346	vmstate_register(NULL, 0, &vmstate_pmac, d);
b8842209	347	qemu_register_reset(pmac_ide_reset, d);
b8842209	348
23c5e4ca	349	return &d->mem;
b8842209	350	}