[qemu.git] / hw / ide / pci.c

/*
 * QEMU IDE Emulation: PCI Bus support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
#include <hw/isa/isa.h>
#include "block/block.h"
#include "sysemu/dma.h"

#include <hw/ide/pci.h>

#define BMDMA_PAGE_SIZE 4096

static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
                            BlockDriverCompletionFunc *dma_cb)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->unit = s->unit;
    bm->dma_cb = dma_cb;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = ide_get_sector(s);
    bm->nsector = s->nsector;

    if (bm->status & BM_STATUS_DMAING) {
        bm->dma_cb(bmdma_active_if(bm), 0);
    }
}

/* return 0 if buffer completed */
static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    pci_dma_sglist_init(&s->sg, pci_dev,
                        s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
    s->io_buffer_size = 0;
    for(;;) {
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return s->io_buffer_size != 0;
            pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        l = bm->cur_prd_len;
        if (l > 0) {
            qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_size += l;
        }
    }
    return 1;
}

/* return 0 if buffer completed */
static int bmdma_rw_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    for(;;) {
        l = s->io_buffer_size - s->io_buffer_index;
        if (l <= 0)
            break;
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return 0;
            pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        if (l > bm->cur_prd_len)
            l = bm->cur_prd_len;
        if (l > 0) {
            if (is_write) {
                pci_dma_write(pci_dev, bm->cur_prd_addr,
                              s->io_buffer + s->io_buffer_index, l);
            } else {
                pci_dma_read(pci_dev, bm->cur_prd_addr,
                             s->io_buffer + s->io_buffer_index, l);
            }
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_index += l;
        }
    }
    return 1;
}

static int bmdma_set_unit(IDEDMA *dma, int unit)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->unit = unit;

    return 0;
}

static int bmdma_add_status(IDEDMA *dma, int status)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->status |= status;

    return 0;
}

static int bmdma_set_inactive(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->status &= ~BM_STATUS_DMAING;
    bm->dma_cb = NULL;
    bm->unit = -1;

    return 0;
}

static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
{
    IDEState *s = bmdma_active_if(bm);

    ide_set_sector(s, bm->sector_num);
    s->io_buffer_index = 0;
    s->io_buffer_size = 0;
    s->nsector = bm->nsector;
    s->dma_cmd = dma_cmd;
    bm->cur_addr = bm->addr;
    bm->dma_cb = ide_dma_cb;
    bmdma_start_dma(&bm->dma, s, bm->dma_cb);
}

/* TODO This should be common IDE code */
static void bmdma_restart_bh(void *opaque)
{
    BMDMAState *bm = opaque;
    IDEBus *bus = bm->bus;
    bool is_read;
    int error_status;

    qemu_bh_delete(bm->bh);
    bm->bh = NULL;

    if (bm->unit == (uint8_t) -1) {
        return;
    }

    is_read = (bus->error_status & BM_STATUS_RETRY_READ) != 0;

    /* The error status must be cleared before resubmitting the request: The
     * request may fail again, and this case can only be distinguished if the
     * called function can set a new error status. */
    error_status = bus->error_status;
    bus->error_status = 0;

    if (error_status & BM_STATUS_DMA_RETRY) {
        if (error_status & BM_STATUS_RETRY_TRIM) {
            bmdma_restart_dma(bm, IDE_DMA_TRIM);
        } else {
            bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
        }
    } else if (error_status & BM_STATUS_PIO_RETRY) {
        if (is_read) {
            ide_sector_read(bmdma_active_if(bm));
        } else {
            ide_sector_write(bmdma_active_if(bm));
        }
    } else if (error_status & BM_STATUS_RETRY_FLUSH) {
        ide_flush_cache(bmdma_active_if(bm));
    }
}

static void bmdma_restart_cb(void *opaque, int running, RunState state)
{
    IDEDMA *dma = opaque;
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    if (!running)
        return;

    if (!bm->bh) {
        bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
        qemu_bh_schedule(bm->bh);
    }
}

static void bmdma_cancel(BMDMAState *bm)
{
    if (bm->status & BM_STATUS_DMAING) {
        /* cancel DMA request */
        bmdma_set_inactive(&bm->dma);
    }
}

static int bmdma_reset(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

#ifdef DEBUG_IDE
    printf("ide: dma_reset\n");
#endif
    bmdma_cancel(bm);
    bm->cmd = 0;
    bm->status = 0;
    bm->addr = 0;
    bm->cur_addr = 0;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = 0;
    bm->nsector = 0;

    return 0;
}

static int bmdma_start_transfer(IDEDMA *dma)
{
    return 0;
}

static void bmdma_irq(void *opaque, int n, int level)
{
    BMDMAState *bm = opaque;

    if (!level) {
        /* pass through lower */
        qemu_set_irq(bm->irq, level);
        return;
    }

    bm->status |= BM_STATUS_INT;

    /* trigger the real irq */
    qemu_set_irq(bm->irq, level);
}

void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
{
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, val);
#endif

    /* Ignore writes to SSBM if it keeps the old value */
    if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
        if (!(val & BM_CMD_START)) {
            /*
             * We can't cancel Scatter Gather DMA in the middle of the
             * operation or a partial (not full) DMA transfer would reach
             * the storage so we wait for completion instead (we beahve
             * like if the DMA was completed by the time the guest trying
             * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
             * set).
             *
             * In the future we'll be able to safely cancel the I/O if the
             * whole DMA operation will be submitted to disk with a single
             * aio operation with preadv/pwritev.
             */
            if (bm->bus->dma->aiocb) {
                bdrv_drain_all();
                assert(bm->bus->dma->aiocb == NULL);
            }
            bm->status &= ~BM_STATUS_DMAING;
        } else {
            bm->cur_addr = bm->addr;
            if (!(bm->status & BM_STATUS_DMAING)) {
                bm->status |= BM_STATUS_DMAING;
                /* start dma transfer if possible */
                if (bm->dma_cb)
                    bm->dma_cb(bmdma_active_if(bm), 0);
            }
        }
    }

    bm->cmd = val & 0x09;
}

static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
                                unsigned width)
{
    BMDMAState *bm = opaque;
    uint32_t mask = (1ULL << (width * 8)) - 1;
    uint64_t data;

    data = (bm->addr >> (addr * 8)) & mask;
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)data);
#endif
    return data;
}

static void bmdma_addr_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned width)
{
    BMDMAState *bm = opaque;
    int shift = addr * 8;
    uint32_t mask = (1ULL << (width * 8)) - 1;

#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)data);
#endif
    bm->addr &= ~(mask << shift);
    bm->addr |= ((data & mask) << shift) & ~3;
}

MemoryRegionOps bmdma_addr_ioport_ops = {
    .read = bmdma_addr_read,
    .write = bmdma_addr_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static bool ide_bmdma_current_needed(void *opaque)
{
    BMDMAState *bm = opaque;

    return (bm->cur_prd_len != 0);
}

static bool ide_bmdma_status_needed(void *opaque)
{
    BMDMAState *bm = opaque;

    /* Older versions abused some bits in the status register for internal
     * error state. If any of these bits are set, we must add a subsection to
     * transfer the real status register */
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    return ((bm->status & abused_bits) != 0);
}

static void ide_bmdma_pre_save(void *opaque)
{
    BMDMAState *bm = opaque;
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    bm->migration_compat_status =
        (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
}

/* This function accesses bm->bus->error_status which is loaded only after
 * BMDMA itself. This is why the function is called from ide_pci_post_load
 * instead of being registered with VMState where it would run too early. */
static int ide_bmdma_post_load(void *opaque, int version_id)
{
    BMDMAState *bm = opaque;
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    if (bm->status == 0) {
        bm->status = bm->migration_compat_status & ~abused_bits;
        bm->bus->error_status |= bm->migration_compat_status & abused_bits;
    }

    return 0;
}

static const VMStateDescription vmstate_bmdma_current = {
    .name = "ide bmdma_current",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(cur_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_last, BMDMAState),
        VMSTATE_UINT32(cur_prd_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_len, BMDMAState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_bmdma_status = {
    .name ="ide bmdma/status",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField []) {
        VMSTATE_UINT8(status, BMDMAState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_bmdma = {
    .name = "ide bmdma",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .pre_save  = ide_bmdma_pre_save,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(cmd, BMDMAState),
        VMSTATE_UINT8(migration_compat_status, BMDMAState),
        VMSTATE_UINT32(addr, BMDMAState),
        VMSTATE_INT64(sector_num, BMDMAState),
        VMSTATE_UINT32(nsector, BMDMAState),
        VMSTATE_UINT8(unit, BMDMAState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (VMStateSubsection []) {
        {
            .vmsd = &vmstate_bmdma_current,
            .needed = ide_bmdma_current_needed,
        }, {
            .vmsd = &vmstate_bmdma_status,
            .needed = ide_bmdma_status_needed,
        }, {
            /* empty */
        }
    }
};

static int ide_pci_post_load(void *opaque, int version_id)
{
    PCIIDEState *d = opaque;
    int i;

    for(i = 0; i < 2; i++) {
        /* current versions always store 0/1, but older version
           stored bigger values. We only need last bit */
        d->bmdma[i].unit &= 1;
        ide_bmdma_post_load(&d->bmdma[i], -1);
    }

    return 0;
}

const VMStateDescription vmstate_ide_pci = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .post_load = ide_pci_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
        VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
                             vmstate_bmdma, BMDMAState),
        VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
        VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
        VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
        VMSTATE_END_OF_LIST()
    }
};

void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
{
    PCIIDEState *d = PCI_IDE(dev);
    static const int bus[4]  = { 0, 0, 1, 1 };
    static const int unit[4] = { 0, 1, 0, 1 };
    int i;

    for (i = 0; i < 4; i++) {
        if (hd_table[i] == NULL)
            continue;
        ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
    }
}

static const struct IDEDMAOps bmdma_ops = {
    .start_dma = bmdma_start_dma,
    .start_transfer = bmdma_start_transfer,
    .prepare_buf = bmdma_prepare_buf,
    .rw_buf = bmdma_rw_buf,
    .set_unit = bmdma_set_unit,
    .add_status = bmdma_add_status,
    .set_inactive = bmdma_set_inactive,
    .restart_cb = bmdma_restart_cb,
    .reset = bmdma_reset,
};

void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
{
    qemu_irq *irq;

    if (bus->dma == &bm->dma) {
        return;
    }

    bm->dma.ops = &bmdma_ops;
    bus->dma = &bm->dma;
    bm->irq = bus->irq;
    irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
    bus->irq = *irq;
    bm->pci_dev = d;
}

static const TypeInfo pci_ide_type_info = {
    .name = TYPE_PCI_IDE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .abstract = true,
};

static void pci_ide_register_types(void)
{
    type_register_static(&pci_ide_type_info);
}

type_init(pci_ide_register_types)
Commit	Line	Data
977e1244 GH	1	/*
	2	* QEMU IDE Emulation: PCI Bus support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787	25	#include <hw/hw.h>
0d09e41a	26	#include <hw/i386/pc.h>
a2cb15b0	27	#include <hw/pci/pci.h>
0d09e41a	28	#include <hw/isa/isa.h>
737e150e	29	#include "block/block.h"
9c17d615	30	#include "sysemu/dma.h"
59f2a787	31
65c0f135	32	#include <hw/ide/pci.h>
977e1244	33
40a6238a AG	34	#define BMDMA_PAGE_SIZE 4096
	35
	36	static void bmdma_start_dma(IDEDMA dma, IDEState s,
	37	BlockDriverCompletionFunc *dma_cb)
	38	{
	39	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	40
	41	bm->unit = s->unit;
	42	bm->dma_cb = dma_cb;
	43	bm->cur_prd_last = 0;
	44	bm->cur_prd_addr = 0;
	45	bm->cur_prd_len = 0;
	46	bm->sector_num = ide_get_sector(s);
	47	bm->nsector = s->nsector;
	48
	49	if (bm->status & BM_STATUS_DMAING) {
	50	bm->dma_cb(bmdma_active_if(bm), 0);
	51	}
	52	}
	53
	54	/* return 0 if buffer completed */
	55	static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
	56	{
	57	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	58	IDEState *s = bmdma_active_if(bm);
f6c11d56	59	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
40a6238a AG	60	struct {
	61	uint32_t addr;
	62	uint32_t size;
	63	} prd;
	64	int l, len;
	65
f6c11d56	66	pci_dma_sglist_init(&s->sg, pci_dev,
552908fe	67	s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
40a6238a AG	68	s->io_buffer_size = 0;
	69	for(;;) {
	70	if (bm->cur_prd_len == 0) {
	71	/* end of table (with a fail safe of one page) */
	72	if (bm->cur_prd_last \|\|
	73	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
	74	return s->io_buffer_size != 0;
f6c11d56	75	pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
40a6238a AG	76	bm->cur_addr += 8;
	77	prd.addr = le32_to_cpu(prd.addr);
	78	prd.size = le32_to_cpu(prd.size);
	79	len = prd.size & 0xfffe;
	80	if (len == 0)
	81	len = 0x10000;
	82	bm->cur_prd_len = len;
	83	bm->cur_prd_addr = prd.addr;
	84	bm->cur_prd_last = (prd.size & 0x80000000);
	85	}
	86	l = bm->cur_prd_len;
	87	if (l > 0) {
	88	qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
	89	bm->cur_prd_addr += l;
	90	bm->cur_prd_len -= l;
	91	s->io_buffer_size += l;
	92	}
	93	}
	94	return 1;
	95	}
	96
	97	/* return 0 if buffer completed */
	98	static int bmdma_rw_buf(IDEDMA *dma, int is_write)
	99	{
	100	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	101	IDEState *s = bmdma_active_if(bm);
f6c11d56	102	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
40a6238a AG	103	struct {
	104	uint32_t addr;
	105	uint32_t size;
	106	} prd;
	107	int l, len;
	108
	109	for(;;) {
	110	l = s->io_buffer_size - s->io_buffer_index;
	111	if (l <= 0)
	112	break;
	113	if (bm->cur_prd_len == 0) {
	114	/* end of table (with a fail safe of one page) */
	115	if (bm->cur_prd_last \|\|
	116	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
	117	return 0;
f6c11d56	118	pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
40a6238a AG	119	bm->cur_addr += 8;
	120	prd.addr = le32_to_cpu(prd.addr);
	121	prd.size = le32_to_cpu(prd.size);
	122	len = prd.size & 0xfffe;
	123	if (len == 0)
	124	len = 0x10000;
	125	bm->cur_prd_len = len;
	126	bm->cur_prd_addr = prd.addr;
	127	bm->cur_prd_last = (prd.size & 0x80000000);
	128	}
	129	if (l > bm->cur_prd_len)
	130	l = bm->cur_prd_len;
	131	if (l > 0) {
	132	if (is_write) {
f6c11d56	133	pci_dma_write(pci_dev, bm->cur_prd_addr,
552908fe	134	s->io_buffer + s->io_buffer_index, l);
40a6238a	135	} else {
f6c11d56	136	pci_dma_read(pci_dev, bm->cur_prd_addr,
552908fe	137	s->io_buffer + s->io_buffer_index, l);
40a6238a AG	138	}
	139	bm->cur_prd_addr += l;
	140	bm->cur_prd_len -= l;
	141	s->io_buffer_index += l;
	142	}
	143	}
	144	return 1;
	145	}
	146
	147	static int bmdma_set_unit(IDEDMA *dma, int unit)
	148	{
	149	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	150	bm->unit = unit;
	151
	152	return 0;
	153	}
	154
	155	static int bmdma_add_status(IDEDMA *dma, int status)
	156	{
	157	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	158	bm->status \|= status;
	159
	160	return 0;
	161	}
	162
	163	static int bmdma_set_inactive(IDEDMA *dma)
	164	{
	165	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	166
	167	bm->status &= ~BM_STATUS_DMAING;
	168	bm->dma_cb = NULL;
	169	bm->unit = -1;
	170
	171	return 0;
	172	}
	173
4e1e0051	174	static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
40a6238a AG	175	{
	176	IDEState *s = bmdma_active_if(bm);
	177
	178	ide_set_sector(s, bm->sector_num);
	179	s->io_buffer_index = 0;
	180	s->io_buffer_size = 0;
	181	s->nsector = bm->nsector;
4e1e0051	182	s->dma_cmd = dma_cmd;
40a6238a	183	bm->cur_addr = bm->addr;
cd369c46	184	bm->dma_cb = ide_dma_cb;
40a6238a AG	185	bmdma_start_dma(&bm->dma, s, bm->dma_cb);
	186	}
	187
def93791	188	/* TODO This should be common IDE code */
40a6238a AG	189	static void bmdma_restart_bh(void *opaque)
	190	{
	191	BMDMAState *bm = opaque;
def93791	192	IDEBus *bus = bm->bus;
1ceee0d5	193	bool is_read;
ee752da7	194	int error_status;
40a6238a AG	195
	196	qemu_bh_delete(bm->bh);
	197	bm->bh = NULL;
	198
def93791 KW	199	if (bm->unit == (uint8_t) -1) {
	200	return;
	201	}
40a6238a	202
1ceee0d5	203	is_read = (bus->error_status & BM_STATUS_RETRY_READ) != 0;
def93791	204
ee752da7 KW	205	/* The error status must be cleared before resubmitting the request: The
	206	* request may fail again, and this case can only be distinguished if the
	207	* called function can set a new error status. */
	208	error_status = bus->error_status;
	209	bus->error_status = 0;
	210
	211	if (error_status & BM_STATUS_DMA_RETRY) {
	212	if (error_status & BM_STATUS_RETRY_TRIM) {
d353fb72 CH	213	bmdma_restart_dma(bm, IDE_DMA_TRIM);
d353fb72 CH	214	} else {
d353fb72 CH	215	bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
d353fb72 CH	216	}
ee752da7	217	} else if (error_status & BM_STATUS_PIO_RETRY) {
40a6238a AG	218	if (is_read) {
	219	ide_sector_read(bmdma_active_if(bm));
	220	} else {
	221	ide_sector_write(bmdma_active_if(bm));
	222	}
ee752da7	223	} else if (error_status & BM_STATUS_RETRY_FLUSH) {
40a6238a AG	224	ide_flush_cache(bmdma_active_if(bm));
	225	}
	226	}
	227
1dfb4dd9	228	static void bmdma_restart_cb(void *opaque, int running, RunState state)
40a6238a AG	229	{
	230	IDEDMA *dma = opaque;
	231	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	232
	233	if (!running)
	234	return;
	235
	236	if (!bm->bh) {
	237	bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
	238	qemu_bh_schedule(bm->bh);
	239	}
	240	}
	241
	242	static void bmdma_cancel(BMDMAState *bm)
	243	{
	244	if (bm->status & BM_STATUS_DMAING) {
	245	/* cancel DMA request */
	246	bmdma_set_inactive(&bm->dma);
	247	}
	248	}
	249
	250	static int bmdma_reset(IDEDMA *dma)
	251	{
	252	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	253
	254	#ifdef DEBUG_IDE
	255	printf("ide: dma_reset\n");
	256	#endif
	257	bmdma_cancel(bm);
	258	bm->cmd = 0;
	259	bm->status = 0;
	260	bm->addr = 0;
	261	bm->cur_addr = 0;
	262	bm->cur_prd_last = 0;
	263	bm->cur_prd_addr = 0;
	264	bm->cur_prd_len = 0;
	265	bm->sector_num = 0;
	266	bm->nsector = 0;
	267
	268	return 0;
	269	}
	270
	271	static int bmdma_start_transfer(IDEDMA *dma)
	272	{
	273	return 0;
	274	}
	275
	276	static void bmdma_irq(void *opaque, int n, int level)
	277	{
	278	BMDMAState *bm = opaque;
	279
	280	if (!level) {
	281	/* pass through lower */
	282	qemu_set_irq(bm->irq, level);
	283	return;
	284	}
	285
1635eecc	286	bm->status \|= BM_STATUS_INT;
40a6238a AG	287
	288	/* trigger the real irq */
	289	qemu_set_irq(bm->irq, level);
	290	}
	291
a9deb8c6	292	void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
977e1244	293	{
977e1244 GH	294	#ifdef DEBUG_IDE
	295	printf("%s: 0x%08x\n", __func__, val);
	296	#endif
c29947bb KW	297
	298	/* Ignore writes to SSBM if it keeps the old value */
	299	if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
	300	if (!(val & BM_CMD_START)) {
	301	/*
	302	* We can't cancel Scatter Gather DMA in the middle of the
	303	* operation or a partial (not full) DMA transfer would reach
	304	* the storage so we wait for completion instead (we beahve
	305	* like if the DMA was completed by the time the guest trying
	306	* to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
	307	* set).
	308	*
	309	* In the future we'll be able to safely cancel the I/O if the
	310	* whole DMA operation will be submitted to disk with a single
	311	* aio operation with preadv/pwritev.
	312	*/
40a6238a	313	if (bm->bus->dma->aiocb) {
922453bc	314	bdrv_drain_all();
2860e3eb	315	assert(bm->bus->dma->aiocb == NULL);
c29947bb	316	}
b39f9612	317	bm->status &= ~BM_STATUS_DMAING;
c29947bb	318	} else {
b76876e6	319	bm->cur_addr = bm->addr;
c29947bb KW	320	if (!(bm->status & BM_STATUS_DMAING)) {
	321	bm->status \|= BM_STATUS_DMAING;
	322	/* start dma transfer if possible */
	323	if (bm->dma_cb)
40a6238a	324	bm->dma_cb(bmdma_active_if(bm), 0);
c29947bb	325	}
953844d1	326	}
977e1244	327	}
c29947bb KW	328
c29947bb KW	329	bm->cmd = val & 0x09;
977e1244 GH	330	}
977e1244 GH	331
a8170e5e	332	static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
a9deb8c6	333	unsigned width)
977e1244	334	{
a9deb8c6	335	BMDMAState *bm = opaque;
9fbef1ac	336	uint32_t mask = (1ULL << (width * 8)) - 1;
a9deb8c6	337	uint64_t data;
977e1244	338
a9deb8c6	339	data = (bm->addr >> (addr * 8)) & mask;
977e1244	340	#ifdef DEBUG_IDE
cb67be85	341	printf("%s: 0x%08x\n", __func__, (unsigned)data);
977e1244	342	#endif
a9deb8c6	343	return data;
977e1244 GH	344	}
977e1244 GH	345
a8170e5e	346	static void bmdma_addr_write(void *opaque, hwaddr addr,
a9deb8c6	347	uint64_t data, unsigned width)
977e1244	348	{
a9deb8c6	349	BMDMAState *bm = opaque;
9fbef1ac AK	350	int shift = addr * 8;
9fbef1ac AK	351	uint32_t mask = (1ULL << (width * 8)) - 1;
977e1244	352
977e1244	353	#ifdef DEBUG_IDE
9fbef1ac	354	printf("%s: 0x%08x\n", __func__, (unsigned)data);
977e1244	355	#endif
9fbef1ac AK	356	bm->addr &= ~(mask << shift);
9fbef1ac AK	357	bm->addr \|= ((data & mask) << shift) & ~3;
977e1244 GH	358	}
977e1244 GH	359
a9deb8c6	360	MemoryRegionOps bmdma_addr_ioport_ops = {
9fbef1ac AK	361	.read = bmdma_addr_read,
9fbef1ac AK	362	.write = bmdma_addr_write,
a9deb8c6	363	.endianness = DEVICE_LITTLE_ENDIAN,
9fbef1ac	364	};
977e1244	365
5ee84c33 JQ	366	static bool ide_bmdma_current_needed(void *opaque)
	367	{
	368	BMDMAState *bm = opaque;
	369
	370	return (bm->cur_prd_len != 0);
	371	}
	372
def93791 KW	373	static bool ide_bmdma_status_needed(void *opaque)
	374	{
	375	BMDMAState *bm = opaque;
	376
	377	/* Older versions abused some bits in the status register for internal
	378	* error state. If any of these bits are set, we must add a subsection to
	379	* transfer the real status register */
	380	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	381
	382	return ((bm->status & abused_bits) != 0);
	383	}
	384
	385	static void ide_bmdma_pre_save(void *opaque)
	386	{
	387	BMDMAState *bm = opaque;
	388	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	389
	390	bm->migration_compat_status =
	391	(bm->status & ~abused_bits) \| (bm->bus->error_status & abused_bits);
	392	}
	393
	394	/* This function accesses bm->bus->error_status which is loaded only after
	395	* BMDMA itself. This is why the function is called from ide_pci_post_load
	396	* instead of being registered with VMState where it would run too early. */
	397	static int ide_bmdma_post_load(void *opaque, int version_id)
	398	{
	399	BMDMAState *bm = opaque;
	400	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	401
	402	if (bm->status == 0) {
	403	bm->status = bm->migration_compat_status & ~abused_bits;
	404	bm->bus->error_status \|= bm->migration_compat_status & abused_bits;
	405	}
	406
	407	return 0;
	408	}
	409
5ee84c33 JQ	410	static const VMStateDescription vmstate_bmdma_current = {
	411	.name = "ide bmdma_current",
	412	.version_id = 1,
	413	.minimum_version_id = 1,
	414	.minimum_version_id_old = 1,
	415	.fields = (VMStateField []) {
	416	VMSTATE_UINT32(cur_addr, BMDMAState),
	417	VMSTATE_UINT32(cur_prd_last, BMDMAState),
	418	VMSTATE_UINT32(cur_prd_addr, BMDMAState),
	419	VMSTATE_UINT32(cur_prd_len, BMDMAState),
	420	VMSTATE_END_OF_LIST()
	421	}
	422	};
	423
def93791 KW	424	const VMStateDescription vmstate_bmdma_status = {
	425	.name ="ide bmdma/status",
	426	.version_id = 1,
	427	.minimum_version_id = 1,
	428	.minimum_version_id_old = 1,
	429	.fields = (VMStateField []) {
	430	VMSTATE_UINT8(status, BMDMAState),
	431	VMSTATE_END_OF_LIST()
	432	}
	433	};
5ee84c33	434
407a4f30 JQ	435	static const VMStateDescription vmstate_bmdma = {
407a4f30 JQ	436	.name = "ide bmdma",
57338424	437	.version_id = 3,
407a4f30 JQ	438	.minimum_version_id = 0,
407a4f30 JQ	439	.minimum_version_id_old = 0,
def93791	440	.pre_save = ide_bmdma_pre_save,
407a4f30 JQ	441	.fields = (VMStateField []) {
407a4f30 JQ	442	VMSTATE_UINT8(cmd, BMDMAState),
def93791	443	VMSTATE_UINT8(migration_compat_status, BMDMAState),
407a4f30 JQ	444	VMSTATE_UINT32(addr, BMDMAState),
	445	VMSTATE_INT64(sector_num, BMDMAState),
	446	VMSTATE_UINT32(nsector, BMDMAState),
	447	VMSTATE_UINT8(unit, BMDMAState),
	448	VMSTATE_END_OF_LIST()
5ee84c33 JQ	449	},
	450	.subsections = (VMStateSubsection []) {
	451	{
	452	.vmsd = &vmstate_bmdma_current,
	453	.needed = ide_bmdma_current_needed,
def93791 KW	454	}, {
	455	.vmsd = &vmstate_bmdma_status,
	456	.needed = ide_bmdma_status_needed,
5ee84c33 JQ	457	}, {
	458	/* empty */
	459	}
977e1244	460	}
407a4f30	461	};
977e1244	462
407a4f30	463	static int ide_pci_post_load(void *opaque, int version_id)
977e1244 GH	464	{
977e1244 GH	465	PCIIDEState *d = opaque;
407a4f30	466	int i;
977e1244	467
977e1244	468	for(i = 0; i < 2; i++) {
407a4f30 JQ	469	/* current versions always store 0/1, but older version
	470	stored bigger values. We only need last bit */
	471	d->bmdma[i].unit &= 1;
def93791	472	ide_bmdma_post_load(&d->bmdma[i], -1);
977e1244	473	}
def93791	474
977e1244 GH	475	return 0;
	476	}
	477
407a4f30 JQ	478	const VMStateDescription vmstate_ide_pci = {
407a4f30 JQ	479	.name = "ide",
57338424	480	.version_id = 3,
407a4f30 JQ	481	.minimum_version_id = 0,
	482	.minimum_version_id_old = 0,
	483	.post_load = ide_pci_post_load,
	484	.fields = (VMStateField []) {
f6c11d56	485	VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
407a4f30 JQ	486	VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
	487	vmstate_bmdma, BMDMAState),
	488	VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
	489	VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
	490	VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
	491	VMSTATE_END_OF_LIST()
	492	}
	493	};
	494
3e7e1558	495	void pci_ide_create_devs(PCIDevice dev, DriveInfo *hd_table)
feef3102	496	{
f6c11d56	497	PCIIDEState *d = PCI_IDE(dev);
feef3102 GH	498	static const int bus[4] = { 0, 0, 1, 1 };
	499	static const int unit[4] = { 0, 1, 0, 1 };
	500	int i;
	501
	502	for (i = 0; i < 4; i++) {
	503	if (hd_table[i] == NULL)
	504	continue;
1f850f10	505	ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
feef3102 GH	506	}
feef3102 GH	507	}
40a6238a AG	508
	509	static const struct IDEDMAOps bmdma_ops = {
	510	.start_dma = bmdma_start_dma,
	511	.start_transfer = bmdma_start_transfer,
	512	.prepare_buf = bmdma_prepare_buf,
	513	.rw_buf = bmdma_rw_buf,
	514	.set_unit = bmdma_set_unit,
	515	.add_status = bmdma_add_status,
	516	.set_inactive = bmdma_set_inactive,
	517	.restart_cb = bmdma_restart_cb,
	518	.reset = bmdma_reset,
	519	};
	520
a9deb8c6	521	void bmdma_init(IDEBus bus, BMDMAState bm, PCIIDEState *d)
40a6238a AG	522	{
	523	qemu_irq *irq;
	524
	525	if (bus->dma == &bm->dma) {
	526	return;
	527	}
	528
	529	bm->dma.ops = &bmdma_ops;
	530	bus->dma = &bm->dma;
	531	bm->irq = bus->irq;
	532	irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
	533	bus->irq = *irq;
a9deb8c6	534	bm->pci_dev = d;
40a6238a	535	}
f6c11d56 AF	536
	537	static const TypeInfo pci_ide_type_info = {
	538	.name = TYPE_PCI_IDE,
	539	.parent = TYPE_PCI_DEVICE,
	540	.instance_size = sizeof(PCIIDEState),
	541	.abstract = true,
	542	};
	543
	544	static void pci_ide_register_types(void)
	545	{
	546	type_register_static(&pci_ide_type_info);
	547	}
	548
	549	type_init(pci_ide_register_types)