[qemu.git] / hw / ide / pci.c

/*
 * QEMU IDE Emulation: PCI Bus support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/pc.h>
#include <hw/pci.h>
#include <hw/isa.h>
#include "block.h"
#include "block_int.h"
#include "sysemu.h"
#include "dma.h"

#include <hw/ide/pci.h>

#define BMDMA_PAGE_SIZE 4096

static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
                            BlockDriverCompletionFunc *dma_cb)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->unit = s->unit;
    bm->dma_cb = dma_cb;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = ide_get_sector(s);
    bm->nsector = s->nsector;

    if (bm->status & BM_STATUS_DMAING) {
        bm->dma_cb(bmdma_active_if(bm), 0);
    }
}

/* return 0 if buffer completed */
static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    qemu_sglist_init(&s->sg, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
    s->io_buffer_size = 0;
    for(;;) {
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return s->io_buffer_size != 0;
            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        l = bm->cur_prd_len;
        if (l > 0) {
            qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_size += l;
        }
    }
    return 1;
}

/* return 0 if buffer completed */
static int bmdma_rw_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    for(;;) {
        l = s->io_buffer_size - s->io_buffer_index;
        if (l <= 0)
            break;
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return 0;
            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        if (l > bm->cur_prd_len)
            l = bm->cur_prd_len;
        if (l > 0) {
            if (is_write) {
                cpu_physical_memory_write(bm->cur_prd_addr,
                                          s->io_buffer + s->io_buffer_index, l);
            } else {
                cpu_physical_memory_read(bm->cur_prd_addr,
                                          s->io_buffer + s->io_buffer_index, l);
            }
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_index += l;
        }
    }
    return 1;
}

static int bmdma_set_unit(IDEDMA *dma, int unit)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->unit = unit;

    return 0;
}

static int bmdma_add_status(IDEDMA *dma, int status)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->status |= status;

    return 0;
}

static int bmdma_set_inactive(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->status &= ~BM_STATUS_DMAING;
    bm->dma_cb = NULL;
    bm->unit = -1;

    return 0;
}

static void bmdma_restart_dma(BMDMAState *bm, int is_read)
{
    IDEState *s = bmdma_active_if(bm);

    ide_set_sector(s, bm->sector_num);
    s->io_buffer_index = 0;
    s->io_buffer_size = 0;
    s->nsector = bm->nsector;
    bm->cur_addr = bm->addr;

    if (is_read) {
        bm->dma_cb = ide_read_dma_cb;
    } else {
        bm->dma_cb = ide_write_dma_cb;
    }

    bmdma_start_dma(&bm->dma, s, bm->dma_cb);
}

static void bmdma_restart_bh(void *opaque)
{
    BMDMAState *bm = opaque;
    int is_read;

    qemu_bh_delete(bm->bh);
    bm->bh = NULL;

    is_read = !!(bm->status & BM_STATUS_RETRY_READ);

    if (bm->status & BM_STATUS_DMA_RETRY) {
        bm->status &= ~(BM_STATUS_DMA_RETRY | BM_STATUS_RETRY_READ);
        bmdma_restart_dma(bm, is_read);
    } else if (bm->status & BM_STATUS_PIO_RETRY) {
        bm->status &= ~(BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ);
        if (is_read) {
            ide_sector_read(bmdma_active_if(bm));
        } else {
            ide_sector_write(bmdma_active_if(bm));
        }
    } else if (bm->status & BM_STATUS_RETRY_FLUSH) {
        ide_flush_cache(bmdma_active_if(bm));
    }
}

static void bmdma_restart_cb(void *opaque, int running, int reason)
{
    IDEDMA *dma = opaque;
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    if (!running)
        return;

    if (!bm->bh) {
        bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
        qemu_bh_schedule(bm->bh);
    }
}

static void bmdma_cancel(BMDMAState *bm)
{
    if (bm->status & BM_STATUS_DMAING) {
        /* cancel DMA request */
        bmdma_set_inactive(&bm->dma);
    }
}

static int bmdma_reset(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

#ifdef DEBUG_IDE
    printf("ide: dma_reset\n");
#endif
    bmdma_cancel(bm);
    bm->cmd = 0;
    bm->status = 0;
    bm->addr = 0;
    bm->cur_addr = 0;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = 0;
    bm->nsector = 0;

    return 0;
}

static int bmdma_start_transfer(IDEDMA *dma)
{
    return 0;
}

static void bmdma_irq(void *opaque, int n, int level)
{
    BMDMAState *bm = opaque;

    if (!level) {
        /* pass through lower */
        qemu_set_irq(bm->irq, level);
        return;
    }

    if (bm) {
        bm->status |= BM_STATUS_INT;
    }

    /* trigger the real irq */
    qemu_set_irq(bm->irq, level);
}

void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    BMDMAState *bm = opaque;
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, val);
#endif

    /* Ignore writes to SSBM if it keeps the old value */
    if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
        if (!(val & BM_CMD_START)) {
            /*
             * We can't cancel Scatter Gather DMA in the middle of the
             * operation or a partial (not full) DMA transfer would reach
             * the storage so we wait for completion instead (we beahve
             * like if the DMA was completed by the time the guest trying
             * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
             * set).
             *
             * In the future we'll be able to safely cancel the I/O if the
             * whole DMA operation will be submitted to disk with a single
             * aio operation with preadv/pwritev.
             */
            if (bm->bus->dma->aiocb) {
                qemu_aio_flush();
#ifdef DEBUG_IDE
                if (bm->bus->dma->aiocb)
                    printf("ide_dma_cancel: aiocb still pending");
                if (bm->status & BM_STATUS_DMAING)
                    printf("ide_dma_cancel: BM_STATUS_DMAING still pending");
#endif
            }
        } else {
            bm->cur_addr = bm->addr;
            if (!(bm->status & BM_STATUS_DMAING)) {
                bm->status |= BM_STATUS_DMAING;
                /* start dma transfer if possible */
                if (bm->dma_cb)
                    bm->dma_cb(bmdma_active_if(bm), 0);
            }
        }
    }

    bm->cmd = val & 0x09;
}

static void bmdma_addr_read(IORange *ioport, uint64_t addr,
                            unsigned width, uint64_t *data)
{
    BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
    uint32_t mask = (1ULL << (width * 8)) - 1;

    *data = (bm->addr >> (addr * 8)) & mask;
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)*data);
#endif
}

static void bmdma_addr_write(IORange *ioport, uint64_t addr,
                             unsigned width, uint64_t data)
{
    BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
    int shift = addr * 8;
    uint32_t mask = (1ULL << (width * 8)) - 1;

#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)data);
#endif
    bm->addr &= ~(mask << shift);
    bm->addr |= ((data & mask) << shift) & ~3;
}

const IORangeOps bmdma_addr_ioport_ops = {
    .read = bmdma_addr_read,
    .write = bmdma_addr_write,
};

static bool ide_bmdma_current_needed(void *opaque)
{
    BMDMAState *bm = opaque;

    return (bm->cur_prd_len != 0);
}

static const VMStateDescription vmstate_bmdma_current = {
    .name = "ide bmdma_current",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(cur_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_last, BMDMAState),
        VMSTATE_UINT32(cur_prd_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_len, BMDMAState),
        VMSTATE_END_OF_LIST()
    }
};


static const VMStateDescription vmstate_bmdma = {
    .name = "ide bmdma",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(cmd, BMDMAState),
        VMSTATE_UINT8(status, BMDMAState),
        VMSTATE_UINT32(addr, BMDMAState),
        VMSTATE_INT64(sector_num, BMDMAState),
        VMSTATE_UINT32(nsector, BMDMAState),
        VMSTATE_UINT8(unit, BMDMAState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (VMStateSubsection []) {
        {
            .vmsd = &vmstate_bmdma_current,
            .needed = ide_bmdma_current_needed,
        }, {
            /* empty */
        }
    }
};

static int ide_pci_post_load(void *opaque, int version_id)
{
    PCIIDEState *d = opaque;
    int i;

    for(i = 0; i < 2; i++) {
        /* current versions always store 0/1, but older version
           stored bigger values. We only need last bit */
        d->bmdma[i].unit &= 1;
    }
    return 0;
}

const VMStateDescription vmstate_ide_pci = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .post_load = ide_pci_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCIIDEState),
        VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
                             vmstate_bmdma, BMDMAState),
        VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
        VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
        VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
        VMSTATE_END_OF_LIST()
    }
};

void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    static const int bus[4]  = { 0, 0, 1, 1 };
    static const int unit[4] = { 0, 1, 0, 1 };
    int i;

    for (i = 0; i < 4; i++) {
        if (hd_table[i] == NULL)
            continue;
        ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
    }
}

static const struct IDEDMAOps bmdma_ops = {
    .start_dma = bmdma_start_dma,
    .start_transfer = bmdma_start_transfer,
    .prepare_buf = bmdma_prepare_buf,
    .rw_buf = bmdma_rw_buf,
    .set_unit = bmdma_set_unit,
    .add_status = bmdma_add_status,
    .set_inactive = bmdma_set_inactive,
    .restart_cb = bmdma_restart_cb,
    .reset = bmdma_reset,
};

void bmdma_init(IDEBus *bus, BMDMAState *bm)
{
    qemu_irq *irq;

    if (bus->dma == &bm->dma) {
        return;
    }

    bm->dma.ops = &bmdma_ops;
    bus->dma = &bm->dma;
    bm->irq = bus->irq;
    irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
    bus->irq = *irq;
}
Commit	Line	Data
977e1244 GH	1	/*
	2	* QEMU IDE Emulation: PCI Bus support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787 GH	25	#include <hw/hw.h>
	26	#include <hw/pc.h>
	27	#include <hw/pci.h>
feef3102	28	#include <hw/isa.h>
977e1244 GH	29	#include "block.h"
	30	#include "block_int.h"
	31	#include "sysemu.h"
	32	#include "dma.h"
59f2a787	33
65c0f135	34	#include <hw/ide/pci.h>
977e1244	35
40a6238a AG	36	#define BMDMA_PAGE_SIZE 4096
	37
	38	static void bmdma_start_dma(IDEDMA dma, IDEState s,
	39	BlockDriverCompletionFunc *dma_cb)
	40	{
	41	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	42
	43	bm->unit = s->unit;
	44	bm->dma_cb = dma_cb;
	45	bm->cur_prd_last = 0;
	46	bm->cur_prd_addr = 0;
	47	bm->cur_prd_len = 0;
	48	bm->sector_num = ide_get_sector(s);
	49	bm->nsector = s->nsector;
	50
	51	if (bm->status & BM_STATUS_DMAING) {
	52	bm->dma_cb(bmdma_active_if(bm), 0);
	53	}
	54	}
	55
	56	/* return 0 if buffer completed */
	57	static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
	58	{
	59	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	60	IDEState *s = bmdma_active_if(bm);
	61	struct {
	62	uint32_t addr;
	63	uint32_t size;
	64	} prd;
	65	int l, len;
	66
	67	qemu_sglist_init(&s->sg, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
	68	s->io_buffer_size = 0;
	69	for(;;) {
	70	if (bm->cur_prd_len == 0) {
	71	/* end of table (with a fail safe of one page) */
	72	if (bm->cur_prd_last \|\|
	73	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
	74	return s->io_buffer_size != 0;
	75	cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
	76	bm->cur_addr += 8;
	77	prd.addr = le32_to_cpu(prd.addr);
	78	prd.size = le32_to_cpu(prd.size);
	79	len = prd.size & 0xfffe;
	80	if (len == 0)
	81	len = 0x10000;
	82	bm->cur_prd_len = len;
	83	bm->cur_prd_addr = prd.addr;
	84	bm->cur_prd_last = (prd.size & 0x80000000);
	85	}
	86	l = bm->cur_prd_len;
	87	if (l > 0) {
	88	qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
	89	bm->cur_prd_addr += l;
	90	bm->cur_prd_len -= l;
	91	s->io_buffer_size += l;
	92	}
	93	}
	94	return 1;
	95	}
	96
	97	/* return 0 if buffer completed */
	98	static int bmdma_rw_buf(IDEDMA *dma, int is_write)
	99	{
100	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
101	IDEState *s = bmdma_active_if(bm);
102	struct {
103	uint32_t addr;
104	uint32_t size;
105	} prd;
106	int l, len;
107
108	for(;;) {
109	l = s->io_buffer_size - s->io_buffer_index;
110	if (l <= 0)
111	break;
112	if (bm->cur_prd_len == 0) {
113	/* end of table (with a fail safe of one page) */
114	if (bm->cur_prd_last \|\|
115	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
116	return 0;
117	cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
118	bm->cur_addr += 8;
119	prd.addr = le32_to_cpu(prd.addr);
120	prd.size = le32_to_cpu(prd.size);
121	len = prd.size & 0xfffe;
122	if (len == 0)
123	len = 0x10000;
124	bm->cur_prd_len = len;
125	bm->cur_prd_addr = prd.addr;
126	bm->cur_prd_last = (prd.size & 0x80000000);
127	}
128	if (l > bm->cur_prd_len)
129	l = bm->cur_prd_len;
130	if (l > 0) {
131	if (is_write) {
132	cpu_physical_memory_write(bm->cur_prd_addr,
133	s->io_buffer + s->io_buffer_index, l);
134	} else {
135	cpu_physical_memory_read(bm->cur_prd_addr,
136	s->io_buffer + s->io_buffer_index, l);
137	}
138	bm->cur_prd_addr += l;
139	bm->cur_prd_len -= l;
140	s->io_buffer_index += l;
141	}
142	}
143	return 1;
144	}
145
146	static int bmdma_set_unit(IDEDMA *dma, int unit)
147	{
148	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
149	bm->unit = unit;
150
151	return 0;
152	}
153
154	static int bmdma_add_status(IDEDMA *dma, int status)
155	{
156	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
157	bm->status \|= status;
158
159	return 0;
160	}
161
162	static int bmdma_set_inactive(IDEDMA *dma)
163	{
164	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
165
166	bm->status &= ~BM_STATUS_DMAING;
167	bm->dma_cb = NULL;
168	bm->unit = -1;
169
170	return 0;
171	}
172
173	static void bmdma_restart_dma(BMDMAState *bm, int is_read)
174	{
175	IDEState *s = bmdma_active_if(bm);
176
177	ide_set_sector(s, bm->sector_num);
178	s->io_buffer_index = 0;
179	s->io_buffer_size = 0;
180	s->nsector = bm->nsector;
181	bm->cur_addr = bm->addr;
182
183	if (is_read) {
184	bm->dma_cb = ide_read_dma_cb;
185	} else {
186	bm->dma_cb = ide_write_dma_cb;
187	}
188
189	bmdma_start_dma(&bm->dma, s, bm->dma_cb);
190	}
191
192	static void bmdma_restart_bh(void *opaque)
193	{
194	BMDMAState *bm = opaque;
195	int is_read;
196
197	qemu_bh_delete(bm->bh);
198	bm->bh = NULL;
199
200	is_read = !!(bm->status & BM_STATUS_RETRY_READ);
201
202	if (bm->status & BM_STATUS_DMA_RETRY) {
203	bm->status &= ~(BM_STATUS_DMA_RETRY \| BM_STATUS_RETRY_READ);
204	bmdma_restart_dma(bm, is_read);
205	} else if (bm->status & BM_STATUS_PIO_RETRY) {
206	bm->status &= ~(BM_STATUS_PIO_RETRY \| BM_STATUS_RETRY_READ);
207	if (is_read) {
208	ide_sector_read(bmdma_active_if(bm));
209	} else {
210	ide_sector_write(bmdma_active_if(bm));
211	}
212	} else if (bm->status & BM_STATUS_RETRY_FLUSH) {
213	ide_flush_cache(bmdma_active_if(bm));
214	}
215	}
216
217	static void bmdma_restart_cb(void *opaque, int running, int reason)
218	{
219	IDEDMA *dma = opaque;
220	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
221
222	if (!running)
223	return;
224
225	if (!bm->bh) {
226	bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
227	qemu_bh_schedule(bm->bh);
228	}
229	}
230
231	static void bmdma_cancel(BMDMAState *bm)
232	{
233	if (bm->status & BM_STATUS_DMAING) {
234	/* cancel DMA request */
235	bmdma_set_inactive(&bm->dma);
236	}
237	}
238
239	static int bmdma_reset(IDEDMA *dma)
240	{
241	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
242
243	#ifdef DEBUG_IDE
244	printf("ide: dma_reset\n");
245	#endif
246	bmdma_cancel(bm);
247	bm->cmd = 0;
248	bm->status = 0;
249	bm->addr = 0;
250	bm->cur_addr = 0;
251	bm->cur_prd_last = 0;
252	bm->cur_prd_addr = 0;
253	bm->cur_prd_len = 0;
254	bm->sector_num = 0;
255	bm->nsector = 0;
256
257	return 0;
258	}
259
260	static int bmdma_start_transfer(IDEDMA *dma)
261	{
262	return 0;
263	}
264
265	static void bmdma_irq(void *opaque, int n, int level)
266	{
267	BMDMAState *bm = opaque;
268
269	if (!level) {
270	/* pass through lower */
271	qemu_set_irq(bm->irq, level);
272	return;
273	}
274
275	if (bm) {
276	bm->status \|= BM_STATUS_INT;
277	}
278
279	/* trigger the real irq */
280	qemu_set_irq(bm->irq, level);
281	}
282
3e7e1558	283	void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
977e1244 GH	284	{
	285	BMDMAState *bm = opaque;
	286	#ifdef DEBUG_IDE
	287	printf("%s: 0x%08x\n", __func__, val);
	288	#endif
c29947bb KW	289
	290	/* Ignore writes to SSBM if it keeps the old value */
	291	if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
	292	if (!(val & BM_CMD_START)) {
	293	/*
	294	* We can't cancel Scatter Gather DMA in the middle of the
	295	* operation or a partial (not full) DMA transfer would reach
	296	* the storage so we wait for completion instead (we beahve
	297	* like if the DMA was completed by the time the guest trying
	298	* to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
	299	* set).
	300	*
	301	* In the future we'll be able to safely cancel the I/O if the
	302	* whole DMA operation will be submitted to disk with a single
	303	* aio operation with preadv/pwritev.
	304	*/
40a6238a	305	if (bm->bus->dma->aiocb) {
c29947bb	306	qemu_aio_flush();
953844d1	307	#ifdef DEBUG_IDE
40a6238a	308	if (bm->bus->dma->aiocb)
c29947bb KW	309	printf("ide_dma_cancel: aiocb still pending");
	310	if (bm->status & BM_STATUS_DMAING)
	311	printf("ide_dma_cancel: BM_STATUS_DMAING still pending");
953844d1	312	#endif
c29947bb KW	313	}
c29947bb KW	314	} else {
b76876e6	315	bm->cur_addr = bm->addr;
c29947bb KW	316	if (!(bm->status & BM_STATUS_DMAING)) {
	317	bm->status \|= BM_STATUS_DMAING;
	318	/* start dma transfer if possible */
	319	if (bm->dma_cb)
40a6238a	320	bm->dma_cb(bmdma_active_if(bm), 0);
c29947bb	321	}
953844d1	322	}
977e1244	323	}
c29947bb KW	324
c29947bb KW	325	bm->cmd = val & 0x09;
977e1244 GH	326	}
977e1244 GH	327
9fbef1ac AK	328	static void bmdma_addr_read(IORange *ioport, uint64_t addr,
9fbef1ac AK	329	unsigned width, uint64_t *data)
977e1244	330	{
9fbef1ac AK	331	BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
9fbef1ac AK	332	uint32_t mask = (1ULL << (width * 8)) - 1;
977e1244	333
9fbef1ac	334	data = (bm->addr >> (addr 8)) & mask;
977e1244	335	#ifdef DEBUG_IDE
9fbef1ac	336	printf("%s: 0x%08x\n", __func__, (unsigned)*data);
977e1244	337	#endif
977e1244 GH	338	}
977e1244 GH	339
9fbef1ac AK	340	static void bmdma_addr_write(IORange *ioport, uint64_t addr,
9fbef1ac AK	341	unsigned width, uint64_t data)
977e1244	342	{
9fbef1ac AK	343	BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
	344	int shift = addr * 8;
	345	uint32_t mask = (1ULL << (width * 8)) - 1;
977e1244	346
977e1244	347	#ifdef DEBUG_IDE
9fbef1ac	348	printf("%s: 0x%08x\n", __func__, (unsigned)data);
977e1244	349	#endif
9fbef1ac AK	350	bm->addr &= ~(mask << shift);
9fbef1ac AK	351	bm->addr \|= ((data & mask) << shift) & ~3;
977e1244 GH	352	}
977e1244 GH	353
9fbef1ac AK	354	const IORangeOps bmdma_addr_ioport_ops = {
	355	.read = bmdma_addr_read,
	356	.write = bmdma_addr_write,
	357	};
977e1244	358
5ee84c33 JQ	359	static bool ide_bmdma_current_needed(void *opaque)
	360	{
	361	BMDMAState *bm = opaque;
	362
	363	return (bm->cur_prd_len != 0);
	364	}
	365
	366	static const VMStateDescription vmstate_bmdma_current = {
	367	.name = "ide bmdma_current",
	368	.version_id = 1,
	369	.minimum_version_id = 1,
	370	.minimum_version_id_old = 1,
	371	.fields = (VMStateField []) {
	372	VMSTATE_UINT32(cur_addr, BMDMAState),
	373	VMSTATE_UINT32(cur_prd_last, BMDMAState),
	374	VMSTATE_UINT32(cur_prd_addr, BMDMAState),
	375	VMSTATE_UINT32(cur_prd_len, BMDMAState),
	376	VMSTATE_END_OF_LIST()
	377	}
	378	};
	379
	380
407a4f30 JQ	381	static const VMStateDescription vmstate_bmdma = {
407a4f30 JQ	382	.name = "ide bmdma",
57338424	383	.version_id = 3,
407a4f30 JQ	384	.minimum_version_id = 0,
	385	.minimum_version_id_old = 0,
	386	.fields = (VMStateField []) {
	387	VMSTATE_UINT8(cmd, BMDMAState),
	388	VMSTATE_UINT8(status, BMDMAState),
	389	VMSTATE_UINT32(addr, BMDMAState),
	390	VMSTATE_INT64(sector_num, BMDMAState),
	391	VMSTATE_UINT32(nsector, BMDMAState),
	392	VMSTATE_UINT8(unit, BMDMAState),
	393	VMSTATE_END_OF_LIST()
5ee84c33 JQ	394	},
	395	.subsections = (VMStateSubsection []) {
	396	{
	397	.vmsd = &vmstate_bmdma_current,
	398	.needed = ide_bmdma_current_needed,
	399	}, {
	400	/* empty */
	401	}
977e1244	402	}
407a4f30	403	};
977e1244	404
407a4f30	405	static int ide_pci_post_load(void *opaque, int version_id)
977e1244 GH	406	{
977e1244 GH	407	PCIIDEState *d = opaque;
407a4f30	408	int i;
977e1244	409
977e1244	410	for(i = 0; i < 2; i++) {
407a4f30 JQ	411	/* current versions always store 0/1, but older version
	412	stored bigger values. We only need last bit */
	413	d->bmdma[i].unit &= 1;
977e1244 GH	414	}
	415	return 0;
	416	}
	417
407a4f30 JQ	418	const VMStateDescription vmstate_ide_pci = {
407a4f30 JQ	419	.name = "ide",
57338424	420	.version_id = 3,
407a4f30 JQ	421	.minimum_version_id = 0,
	422	.minimum_version_id_old = 0,
	423	.post_load = ide_pci_post_load,
	424	.fields = (VMStateField []) {
	425	VMSTATE_PCI_DEVICE(dev, PCIIDEState),
	426	VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
	427	vmstate_bmdma, BMDMAState),
	428	VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
	429	VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
	430	VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
	431	VMSTATE_END_OF_LIST()
	432	}
	433	};
	434
3e7e1558	435	void pci_ide_create_devs(PCIDevice dev, DriveInfo *hd_table)
feef3102 GH	436	{
	437	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
	438	static const int bus[4] = { 0, 0, 1, 1 };
	439	static const int unit[4] = { 0, 1, 0, 1 };
	440	int i;
	441
	442	for (i = 0; i < 4; i++) {
	443	if (hd_table[i] == NULL)
	444	continue;
1f850f10	445	ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
feef3102 GH	446	}
feef3102 GH	447	}
40a6238a AG	448
	449	static const struct IDEDMAOps bmdma_ops = {
	450	.start_dma = bmdma_start_dma,
	451	.start_transfer = bmdma_start_transfer,
	452	.prepare_buf = bmdma_prepare_buf,
	453	.rw_buf = bmdma_rw_buf,
	454	.set_unit = bmdma_set_unit,
	455	.add_status = bmdma_add_status,
	456	.set_inactive = bmdma_set_inactive,
	457	.restart_cb = bmdma_restart_cb,
	458	.reset = bmdma_reset,
	459	};
	460
	461	void bmdma_init(IDEBus bus, BMDMAState bm)
	462	{
	463	qemu_irq *irq;
	464
	465	if (bus->dma == &bm->dma) {
	466	return;
	467	}
	468
	469	bm->dma.ops = &bmdma_ops;
	470	bus->dma = &bm->dma;
	471	bm->irq = bus->irq;
	472	irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
	473	bus->irq = *irq;
	474	}