[qemu.git] / hw / ide / via.c

/*
 * QEMU IDE Emulation: PCI VIA82C686B support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
#include <hw/isa/isa.h>
#include "block/block.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"

#include <hw/ide/pci.h>

static uint64_t bmdma_read(void *opaque, hwaddr addr,
                           unsigned size)
{
    BMDMAState *bm = opaque;
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch (addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 2:
        val = bm->status;
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
#endif
    return val;
}

static void bmdma_write(void *opaque, hwaddr addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;

    if (size != 1) {
        return;
    }

#ifdef DEBUG_IDE
    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
#endif
    switch (addr & 3) {
    case 0:
        bmdma_cmd_writeb(bm, val);
        break;
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    default:;
    }
}

static const MemoryRegionOps via_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    int i;

    memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
    for(i = 0;i < 2; i++) {
        BMDMAState *bm = &d->bmdma[i];

        memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
                              "via-bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, OBJECT(d),
                              &bmdma_addr_ioport_ops, bm, "bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void via_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    PCIDevice *pd = PCI_DEVICE(d);
    uint8_t *pci_conf = pd->config;
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
                 PCI_STATUS_DEVSEL_MEDIUM);

    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
    pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);

    /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
    pci_set_long(pci_conf + 0x40, 0x0a090600);
    /* IDE misc configuration 1/2/3 */
    pci_set_long(pci_conf + 0x44, 0x00c00068);
    /* IDE Timing control */
    pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
    /* IDE Address Setup Time */
    pci_set_long(pci_conf + 0x4c, 0x000000ff);
    /* UltraDMA Extended Timing Control*/
    pci_set_long(pci_conf + 0x50, 0x07070707);
    /* UltraDMA FIFO Control */
    pci_set_long(pci_conf + 0x54, 0x00000004);
    /* IDE primary sector size */
    pci_set_long(pci_conf + 0x60, 0x00000200);
    /* IDE secondary sector size */
    pci_set_long(pci_conf + 0x68, 0x00000200);
    /* PCI PM Block */
    pci_set_long(pci_conf + 0xc0, 0x00020001);
}

static void vt82c686b_init_ports(PCIIDEState *d) {
    static const struct {
        int iobase;
        int iobase2;
        int isairq;
    } port_info[] = {
        {0x1f0, 0x3f6, 14},
        {0x170, 0x376, 15},
    };
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
        ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
                        port_info[i].iobase2);
        ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }
}

/* via ide func */
static int vt82c686b_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;

    pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);

    qemu_register_reset(via_reset, d);
    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);

    vt82c686b_init_ports(d);

    return 0;
}

static void vt82c686b_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_destroy(&d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
        memory_region_destroy(&d->bmdma[i].addr_ioport);
    }
    memory_region_destroy(&d->bmdma_bar);
}

void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "via-ide");
    pci_ide_create_devs(dev, hd_table);
}

static void via_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = vt82c686b_ide_initfn;
    k->exit = vt82c686b_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_VIA;
    k->device_id = PCI_DEVICE_ID_VIA_IDE;
    k->revision = 0x06;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->no_user = 1;
}

static const TypeInfo via_ide_info = {
    .name          = "via-ide",
    .parent        = TYPE_PCI_IDE,
    .class_init    = via_ide_class_init,
};

static void via_ide_register_types(void)
{
    type_register_static(&via_ide_info);
}

type_init(via_ide_register_types)
Commit	Line	Data
016512f3 HC	1	/*
	2	* QEMU IDE Emulation: PCI VIA82C686B support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	* Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26	#include <hw/hw.h>
0d09e41a	27	#include <hw/i386/pc.h>
a2cb15b0	28	#include <hw/pci/pci.h>
0d09e41a	29	#include <hw/isa/isa.h>
737e150e	30	#include "block/block.h"
9c17d615 PB	31	#include "sysemu/sysemu.h"
9c17d615 PB	32	#include "sysemu/dma.h"
016512f3 HC	33
	34	#include <hw/ide/pci.h>
	35
a8170e5e	36	static uint64_t bmdma_read(void *opaque, hwaddr addr,
a9deb8c6	37	unsigned size)
016512f3 HC	38	{
	39	BMDMAState *bm = opaque;
	40	uint32_t val;
	41
a9deb8c6 AK	42	if (size != 1) {
	43	return ((uint64_t)1 << (size * 8)) - 1;
	44	}
	45
016512f3 HC	46	switch (addr & 3) {
	47	case 0:
	48	val = bm->cmd;
	49	break;
	50	case 2:
	51	val = bm->status;
	52	break;
	53	default:
	54	val = 0xff;
	55	break;
	56	}
	57	#ifdef DEBUG_IDE
08406b03	58	printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
016512f3 HC	59	#endif
	60	return val;
	61	}
	62
a8170e5e	63	static void bmdma_write(void *opaque, hwaddr addr,
a9deb8c6	64	uint64_t val, unsigned size)
016512f3 HC	65	{
016512f3 HC	66	BMDMAState *bm = opaque;
a9deb8c6 AK	67
	68	if (size != 1) {
	69	return;
	70	}
	71
016512f3	72	#ifdef DEBUG_IDE
08406b03	73	printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
016512f3 HC	74	#endif
016512f3 HC	75	switch (addr & 3) {
a9deb8c6	76	case 0:
0ed8b6f6 BS	77	bmdma_cmd_writeb(bm, val);
0ed8b6f6 BS	78	break;
016512f3 HC	79	case 2:
	80	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	81	break;
	82	default:;
	83	}
	84	}
	85
a348f108	86	static const MemoryRegionOps via_bmdma_ops = {
a9deb8c6 AK	87	.read = bmdma_read,
	88	.write = bmdma_write,
	89	};
	90
	91	static void bmdma_setup_bar(PCIIDEState *d)
016512f3	92	{
016512f3 HC	93	int i;
016512f3 HC	94
1437c94b	95	memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
016512f3 HC	96	for(i = 0;i < 2; i++) {
016512f3 HC	97	BMDMAState *bm = &d->bmdma[i];
016512f3	98
1437c94b	99	memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
a9deb8c6 AK	100	"via-bmdma", 4);
a9deb8c6 AK	101	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
1437c94b PB	102	memory_region_init_io(&bm->addr_ioport, OBJECT(d),
1437c94b PB	103	&bmdma_addr_ioport_ops, bm, "bmdma", 4);
a9deb8c6	104	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
016512f3 HC	105	}
	106	}
	107
	108	static void via_reset(void *opaque)
	109	{
	110	PCIIDEState *d = opaque;
f6c11d56 AF	111	PCIDevice *pd = PCI_DEVICE(d);
f6c11d56 AF	112	uint8_t *pci_conf = pd->config;
016512f3 HC	113	int i;
	114
	115	for (i = 0; i < 2; i++) {
	116	ide_bus_reset(&d->bus[i]);
016512f3 HC	117	}
	118
	119	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
	120	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK \|
	121	PCI_STATUS_DEVSEL_MEDIUM);
	122
	123	pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
	124	pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
	125	pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
	126	pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
	127	pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
	128	pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
	129
	130	/* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
	131	pci_set_long(pci_conf + 0x40, 0x0a090600);
	132	/* IDE misc configuration 1/2/3 */
	133	pci_set_long(pci_conf + 0x44, 0x00c00068);
	134	/* IDE Timing control */
	135	pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
	136	/* IDE Address Setup Time */
	137	pci_set_long(pci_conf + 0x4c, 0x000000ff);
	138	/* UltraDMA Extended Timing Control*/
	139	pci_set_long(pci_conf + 0x50, 0x07070707);
	140	/* UltraDMA FIFO Control */
	141	pci_set_long(pci_conf + 0x54, 0x00000004);
	142	/* IDE primary sector size */
	143	pci_set_long(pci_conf + 0x60, 0x00000200);
	144	/* IDE secondary sector size */
	145	pci_set_long(pci_conf + 0x68, 0x00000200);
	146	/* PCI PM Block */
	147	pci_set_long(pci_conf + 0xc0, 0x00020001);
	148	}
	149
61d9d6b0	150	static void vt82c686b_init_ports(PCIIDEState *d) {
4a91d3b3	151	static const struct {
61d9d6b0 SH	152	int iobase;
	153	int iobase2;
	154	int isairq;
	155	} port_info[] = {
	156	{0x1f0, 0x3f6, 14},
	157	{0x170, 0x376, 15},
	158	};
4a91d3b3	159	int i;
61d9d6b0 SH	160
61d9d6b0 SH	161	for (i = 0; i < 2; i++) {
c6baf942	162	ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
4a91d3b3 RH	163	ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
4a91d3b3 RH	164	port_info[i].iobase2);
48a18b3c	165	ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
61d9d6b0	166
a9deb8c6	167	bmdma_init(&d->bus[i], &d->bmdma[i], d);
61d9d6b0 SH	168	d->bmdma[i].bus = &d->bus[i];
61d9d6b0 SH	169	qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
653af235	170	&d->bmdma[i].dma);
61d9d6b0 SH	171	}
	172	}
	173
016512f3 HC	174	/* via ide func */
	175	static int vt82c686b_ide_initfn(PCIDevice *dev)
	176	{
f6c11d56 AF	177	PCIIDEState *d = PCI_IDE(dev);
f6c11d56 AF	178	uint8_t *pci_conf = dev->config;
016512f3	179
016512f3	180	pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
016512f3 HC	181	pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
	182
	183	qemu_register_reset(via_reset, d);
a9deb8c6	184	bmdma_setup_bar(d);
f6c11d56	185	pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
016512f3	186
f6c11d56	187	vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
016512f3	188
61d9d6b0	189	vt82c686b_init_ports(d);
016512f3 HC	190
	191	return 0;
	192	}
	193
f90c2bcd	194	static void vt82c686b_ide_exitfn(PCIDevice *dev)
a9deb8c6	195	{
f6c11d56	196	PCIIDEState *d = PCI_IDE(dev);
a9deb8c6 AK	197	unsigned i;
	198
	199	for (i = 0; i < 2; ++i) {
	200	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
	201	memory_region_destroy(&d->bmdma[i].extra_io);
	202	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
	203	memory_region_destroy(&d->bmdma[i].addr_ioport);
	204	}
	205	memory_region_destroy(&d->bmdma_bar);
a9deb8c6 AK	206	}
a9deb8c6 AK	207
016512f3 HC	208	void vt82c686b_ide_init(PCIBus bus, DriveInfo *hd_table, int devfn)
	209	{
	210	PCIDevice *dev;
	211
	212	dev = pci_create_simple(bus, devfn, "via-ide");
	213	pci_ide_create_devs(dev, hd_table);
	214	}
	215
40021f08 AL	216	static void via_ide_class_init(ObjectClass klass, void data)
40021f08 AL	217	{
39bffca2	218	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	219	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	220
	221	k->init = vt82c686b_ide_initfn;
	222	k->exit = vt82c686b_ide_exitfn;
	223	k->vendor_id = PCI_VENDOR_ID_VIA;
	224	k->device_id = PCI_DEVICE_ID_VIA_IDE;
	225	k->revision = 0x06;
	226	k->class_id = PCI_CLASS_STORAGE_IDE;
125ee0ed	227	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2	228	dc->no_user = 1;
40021f08 AL	229	}
40021f08 AL	230
8c43a6f0	231	static const TypeInfo via_ide_info = {
39bffca2	232	.name = "via-ide",
f6c11d56	233	.parent = TYPE_PCI_IDE,
39bffca2	234	.class_init = via_ide_class_init,
016512f3 HC	235	};
016512f3 HC	236
83f7d43a	237	static void via_ide_register_types(void)
016512f3	238	{
39bffca2	239	type_register_static(&via_ide_info);
016512f3	240	}
83f7d43a AF	241
83f7d43a AF	242	type_init(via_ide_register_types)