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3d2bf4a1 GH |
1 | /* |
2 | * QEMU IDE Emulation: mmio support (for embedded). | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | #include "hw.h" | |
26 | #include "block.h" | |
27 | #include "block_int.h" | |
28 | #include "sysemu.h" | |
29 | #include "dma.h" | |
30 | #include "ide-internal.h" | |
31 | ||
32 | /***********************************************************/ | |
33 | /* MMIO based ide port | |
34 | * This emulates IDE device connected directly to the CPU bus without | |
35 | * dedicated ide controller, which is often seen on embedded boards. | |
36 | */ | |
37 | ||
38 | typedef struct { | |
39 | IDEBus *bus; | |
40 | int shift; | |
41 | } MMIOState; | |
42 | ||
43 | static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) | |
44 | { | |
45 | MMIOState *s = (MMIOState*)opaque; | |
46 | IDEBus *bus = s->bus; | |
47 | addr >>= s->shift; | |
48 | if (addr & 7) | |
49 | return ide_ioport_read(bus, addr); | |
50 | else | |
51 | return ide_data_readw(bus, 0); | |
52 | } | |
53 | ||
54 | static void mmio_ide_write (void *opaque, target_phys_addr_t addr, | |
55 | uint32_t val) | |
56 | { | |
57 | MMIOState *s = (MMIOState*)opaque; | |
58 | IDEBus *bus = s->bus; | |
59 | addr >>= s->shift; | |
60 | if (addr & 7) | |
61 | ide_ioport_write(bus, addr, val); | |
62 | else | |
63 | ide_data_writew(bus, 0, val); | |
64 | } | |
65 | ||
66 | static CPUReadMemoryFunc * const mmio_ide_reads[] = { | |
67 | mmio_ide_read, | |
68 | mmio_ide_read, | |
69 | mmio_ide_read, | |
70 | }; | |
71 | ||
72 | static CPUWriteMemoryFunc * const mmio_ide_writes[] = { | |
73 | mmio_ide_write, | |
74 | mmio_ide_write, | |
75 | mmio_ide_write, | |
76 | }; | |
77 | ||
78 | static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) | |
79 | { | |
80 | MMIOState *s= (MMIOState*)opaque; | |
81 | IDEBus *bus = s->bus; | |
82 | return ide_status_read(bus, 0); | |
83 | } | |
84 | ||
85 | static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, | |
86 | uint32_t val) | |
87 | { | |
88 | MMIOState *s = (MMIOState*)opaque; | |
89 | IDEBus *bus = s->bus; | |
90 | ide_cmd_write(bus, 0, val); | |
91 | } | |
92 | ||
93 | static CPUReadMemoryFunc * const mmio_ide_status[] = { | |
94 | mmio_ide_status_read, | |
95 | mmio_ide_status_read, | |
96 | mmio_ide_status_read, | |
97 | }; | |
98 | ||
99 | static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { | |
100 | mmio_ide_cmd_write, | |
101 | mmio_ide_cmd_write, | |
102 | mmio_ide_cmd_write, | |
103 | }; | |
104 | ||
105 | void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, | |
106 | qemu_irq irq, int shift, | |
107 | BlockDriverState *hd0, BlockDriverState *hd1) | |
108 | { | |
109 | MMIOState *s = qemu_mallocz(sizeof(MMIOState)); | |
110 | IDEBus *bus = qemu_mallocz(sizeof(*bus)); | |
111 | int mem1, mem2; | |
112 | ||
113 | ide_init2(bus, hd0, hd1, irq); | |
114 | ||
115 | s->bus = bus; | |
116 | s->shift = shift; | |
117 | ||
118 | mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); | |
119 | mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); | |
120 | cpu_register_physical_memory(membase, 16 << shift, mem1); | |
121 | cpu_register_physical_memory(membase2, 2 << shift, mem2); | |
122 | } | |
123 |