[qemu.git] / hw / input / pckbd.c

/*
 * QEMU PC keyboard emulation
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/isa/isa.h"
#include "hw/i386/pc.h"
#include "hw/input/ps2.h"
#include "sysemu/sysemu.h"

/* debug PC keyboard */
//#define DEBUG_KBD
#ifdef DEBUG_KBD
#define DPRINTF(fmt, ...)                                       \
    do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

/*	Keyboard Controller Commands */
#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
#define KBD_CCMD_READ_INPORT    0xC0    /* read input port */
#define KBD_CCMD_READ_OUTPORT	0xD0    /* read output port */
#define KBD_CCMD_WRITE_OUTPORT	0xD1    /* write output port */
#define KBD_CCMD_WRITE_OBUF	0xD2
#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
					   initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
#define KBD_CCMD_DISABLE_A20    0xDD    /* HP vectra only ? */
#define KBD_CCMD_ENABLE_A20     0xDF    /* HP vectra only ? */
#define KBD_CCMD_PULSE_BITS_3_0 0xF0    /* Pulse bits 3-0 of the output port P2. */
#define KBD_CCMD_RESET          0xFE    /* Pulse bit 0 of the output port P2 = CPU reset. */
#define KBD_CCMD_NO_OP          0xFF    /* Pulse no bits of the output port P2. */

/* Keyboard Commands */
#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
#define KBD_CMD_ECHO     	0xEE
#define KBD_CMD_GET_ID 	        0xF2	/* get keyboard ID */
#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
#define KBD_CMD_RESET_DISABLE	0xF5	/* reset and disable scanning */
#define KBD_CMD_RESET_ENABLE   	0xF6    /* reset and enable scanning */
#define KBD_CMD_RESET		0xFF	/* Reset */

/* Keyboard Replies */
#define KBD_REPLY_POR		0xAA	/* Power on reset */
#define KBD_REPLY_ACK		0xFA	/* Command ACK */
#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */

/* Status Register Bits */
#define KBD_STAT_OBF 		0x01	/* Keyboard output buffer full */
#define KBD_STAT_IBF 		0x02	/* Keyboard input buffer full */
#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
#define KBD_STAT_GTO 		0x40	/* General receive/xmit timeout */
#define KBD_STAT_PERR 		0x80	/* Parity error */

/* Controller Mode Register Bits */
#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
#define KBD_MODE_SYS 		0x04	/* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
#define KBD_MODE_KCC 		0x40	/* Scan code conversion to PC format */
#define KBD_MODE_RFU		0x80

/* Output Port Bits */
#define KBD_OUT_RESET           0x01    /* 1=normal mode, 0=reset */
#define KBD_OUT_A20             0x02    /* x86 only */
#define KBD_OUT_OBF             0x10    /* Keyboard output buffer full */
#define KBD_OUT_MOUSE_OBF       0x20    /* Mouse output buffer full */

/* Mouse Commands */
#define AUX_SET_SCALE11		0xE6	/* Set 1:1 scaling */
#define AUX_SET_SCALE21		0xE7	/* Set 2:1 scaling */
#define AUX_SET_RES		0xE8	/* Set resolution */
#define AUX_GET_SCALE		0xE9	/* Get scaling factor */
#define AUX_SET_STREAM		0xEA	/* Set stream mode */
#define AUX_POLL		0xEB	/* Poll */
#define AUX_RESET_WRAP		0xEC	/* Reset wrap mode */
#define AUX_SET_WRAP		0xEE	/* Set wrap mode */
#define AUX_SET_REMOTE		0xF0	/* Set remote mode */
#define AUX_GET_TYPE		0xF2	/* Get type */
#define AUX_SET_SAMPLE		0xF3	/* Set sample rate */
#define AUX_ENABLE_DEV		0xF4	/* Enable aux device */
#define AUX_DISABLE_DEV		0xF5	/* Disable aux device */
#define AUX_SET_DEFAULT		0xF6
#define AUX_RESET		0xFF	/* Reset aux device */
#define AUX_ACK			0xFA	/* Command byte ACK. */

#define MOUSE_STATUS_REMOTE     0x40
#define MOUSE_STATUS_ENABLED    0x20
#define MOUSE_STATUS_SCALE21    0x10

#define KBD_PENDING_KBD         1
#define KBD_PENDING_AUX         2

typedef struct KBDState {
    uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
    uint8_t status;
    uint8_t mode;
    uint8_t outport;
    /* Bitmask of devices with data available.  */
    uint8_t pending;
    void *kbd;
    void *mouse;

    qemu_irq irq_kbd;
    qemu_irq irq_mouse;
    qemu_irq *a20_out;
    hwaddr mask;
} KBDState;

/* update irq and KBD_STAT_[MOUSE_]OBF */
/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
   incorrect, but it avoids having to simulate exact delays */
static void kbd_update_irq(KBDState *s)
{
    int irq_kbd_level, irq_mouse_level;

    irq_kbd_level = 0;
    irq_mouse_level = 0;
    s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
    s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
    if (s->pending) {
        s->status |= KBD_STAT_OBF;
        s->outport |= KBD_OUT_OBF;
        /* kbd data takes priority over aux data.  */
        if (s->pending == KBD_PENDING_AUX) {
            s->status |= KBD_STAT_MOUSE_OBF;
            s->outport |= KBD_OUT_MOUSE_OBF;
            if (s->mode & KBD_MODE_MOUSE_INT)
                irq_mouse_level = 1;
        } else {
            if ((s->mode & KBD_MODE_KBD_INT) &&
                !(s->mode & KBD_MODE_DISABLE_KBD))
                irq_kbd_level = 1;
        }
    }
    qemu_set_irq(s->irq_kbd, irq_kbd_level);
    qemu_set_irq(s->irq_mouse, irq_mouse_level);
}

static void kbd_update_kbd_irq(void *opaque, int level)
{
    KBDState *s = (KBDState *)opaque;

    if (level)
        s->pending |= KBD_PENDING_KBD;
    else
        s->pending &= ~KBD_PENDING_KBD;
    kbd_update_irq(s);
}

static void kbd_update_aux_irq(void *opaque, int level)
{
    KBDState *s = (KBDState *)opaque;

    if (level)
        s->pending |= KBD_PENDING_AUX;
    else
        s->pending &= ~KBD_PENDING_AUX;
    kbd_update_irq(s);
}

static uint64_t kbd_read_status(void *opaque, hwaddr addr,
                                unsigned size)
{
    KBDState *s = opaque;
    int val;
    val = s->status;
    DPRINTF("kbd: read status=0x%02x\n", val);
    return val;
}

static void kbd_queue(KBDState *s, int b, int aux)
{
    if (aux)
        ps2_queue(s->mouse, b);
    else
        ps2_queue(s->kbd, b);
}

static void outport_write(KBDState *s, uint32_t val)
{
    DPRINTF("kbd: write outport=0x%02x\n", val);
    s->outport = val;
    if (s->a20_out) {
        qemu_set_irq(*s->a20_out, (val >> 1) & 1);
    }
    if (!(val & 1)) {
        qemu_system_reset_request();
    }
}

static void kbd_write_command(void *opaque, hwaddr addr,
                              uint64_t val, unsigned size)
{
    KBDState *s = opaque;

    DPRINTF("kbd: write cmd=0x%02x\n", val);

    /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
     * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
     * command specify the output port bits to be pulsed.
     * 0: Bit should be pulsed. 1: Bit should not be modified.
     * The only useful version of this command is pulsing bit 0,
     * which does a CPU reset.
     */
    if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
        if(!(val & 1))
            val = KBD_CCMD_RESET;
        else
            val = KBD_CCMD_NO_OP;
    }

    switch(val) {
    case KBD_CCMD_READ_MODE:
        kbd_queue(s, s->mode, 0);
        break;
    case KBD_CCMD_WRITE_MODE:
    case KBD_CCMD_WRITE_OBUF:
    case KBD_CCMD_WRITE_AUX_OBUF:
    case KBD_CCMD_WRITE_MOUSE:
    case KBD_CCMD_WRITE_OUTPORT:
        s->write_cmd = val;
        break;
    case KBD_CCMD_MOUSE_DISABLE:
        s->mode |= KBD_MODE_DISABLE_MOUSE;
        break;
    case KBD_CCMD_MOUSE_ENABLE:
        s->mode &= ~KBD_MODE_DISABLE_MOUSE;
        break;
    case KBD_CCMD_TEST_MOUSE:
        kbd_queue(s, 0x00, 0);
        break;
    case KBD_CCMD_SELF_TEST:
        s->status |= KBD_STAT_SELFTEST;
        kbd_queue(s, 0x55, 0);
        break;
    case KBD_CCMD_KBD_TEST:
        kbd_queue(s, 0x00, 0);
        break;
    case KBD_CCMD_KBD_DISABLE:
        s->mode |= KBD_MODE_DISABLE_KBD;
        kbd_update_irq(s);
        break;
    case KBD_CCMD_KBD_ENABLE:
        s->mode &= ~KBD_MODE_DISABLE_KBD;
        kbd_update_irq(s);
        break;
    case KBD_CCMD_READ_INPORT:
        kbd_queue(s, 0x00, 0);
        break;
    case KBD_CCMD_READ_OUTPORT:
        kbd_queue(s, s->outport, 0);
        break;
    case KBD_CCMD_ENABLE_A20:
        if (s->a20_out) {
            qemu_irq_raise(*s->a20_out);
        }
        s->outport |= KBD_OUT_A20;
        break;
    case KBD_CCMD_DISABLE_A20:
        if (s->a20_out) {
            qemu_irq_lower(*s->a20_out);
        }
        s->outport &= ~KBD_OUT_A20;
        break;
    case KBD_CCMD_RESET:
        qemu_system_reset_request();
        break;
    case KBD_CCMD_NO_OP:
        /* ignore that */
        break;
    default:
        fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", (int)val);
        break;
    }
}

static uint64_t kbd_read_data(void *opaque, hwaddr addr,
                              unsigned size)
{
    KBDState *s = opaque;
    uint32_t val;

    if (s->pending == KBD_PENDING_AUX)
        val = ps2_read_data(s->mouse);
    else
        val = ps2_read_data(s->kbd);

    DPRINTF("kbd: read data=0x%02x\n", val);
    return val;
}

static void kbd_write_data(void *opaque, hwaddr addr,
                           uint64_t val, unsigned size)
{
    KBDState *s = opaque;

    DPRINTF("kbd: write data=0x%02x\n", val);

    switch(s->write_cmd) {
    case 0:
        ps2_write_keyboard(s->kbd, val);
        break;
    case KBD_CCMD_WRITE_MODE:
        s->mode = val;
        ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
        /* ??? */
        kbd_update_irq(s);
        break;
    case KBD_CCMD_WRITE_OBUF:
        kbd_queue(s, val, 0);
        break;
    case KBD_CCMD_WRITE_AUX_OBUF:
        kbd_queue(s, val, 1);
        break;
    case KBD_CCMD_WRITE_OUTPORT:
        outport_write(s, val);
        break;
    case KBD_CCMD_WRITE_MOUSE:
        ps2_write_mouse(s->mouse, val);
        break;
    default:
        break;
    }
    s->write_cmd = 0;
}

static void kbd_reset(void *opaque)
{
    KBDState *s = opaque;

    s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
    s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
    s->outport = KBD_OUT_RESET | KBD_OUT_A20;
}

static const VMStateDescription vmstate_kbd = {
    .name = "pckbd",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(write_cmd, KBDState),
        VMSTATE_UINT8(status, KBDState),
        VMSTATE_UINT8(mode, KBDState),
        VMSTATE_UINT8(pending, KBDState),
        VMSTATE_END_OF_LIST()
    }
};

/* Memory mapped interface */
static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
{
    KBDState *s = opaque;

    if (addr & s->mask)
        return kbd_read_status(s, 0, 1) & 0xff;
    else
        return kbd_read_data(s, 0, 1) & 0xff;
}

static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
{
    KBDState *s = opaque;

    if (addr & s->mask)
        kbd_write_command(s, 0, value & 0xff, 1);
    else
        kbd_write_data(s, 0, value & 0xff, 1);
}

static const MemoryRegionOps i8042_mmio_ops = {
    .endianness = DEVICE_NATIVE_ENDIAN,
    .old_mmio = {
        .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
        .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
    },
};

void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   hwaddr mask)
{
    KBDState *s = g_malloc0(sizeof(KBDState));

    s->irq_kbd = kbd_irq;
    s->irq_mouse = mouse_irq;
    s->mask = mask;

    vmstate_register(NULL, 0, &vmstate_kbd, s);

    memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);

    s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
    s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
    qemu_register_reset(kbd_reset, s);
}

#define TYPE_I8042 "i8042"
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)

typedef struct ISAKBDState {
    ISADevice parent_obj;

    KBDState kbd;
    MemoryRegion io[2];
} ISAKBDState;

void i8042_isa_mouse_fake_event(void *opaque)
{
    ISADevice *dev = opaque;
    ISAKBDState *isa = I8042(dev);
    KBDState *s = &isa->kbd;

    ps2_mouse_fake_event(s->mouse);
}

void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
{
    ISAKBDState *isa = I8042(dev);
    KBDState *s = &isa->kbd;

    s->a20_out = a20_out;
}

static const VMStateDescription vmstate_kbd_isa = {
    .name = "pckbd",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
        VMSTATE_END_OF_LIST()
    }
};

static const MemoryRegionOps i8042_data_ops = {
    .read = kbd_read_data,
    .write = kbd_write_data,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static const MemoryRegionOps i8042_cmd_ops = {
    .read = kbd_read_status,
    .write = kbd_write_command,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void i8042_initfn(Object *obj)
{
    ISAKBDState *isa_s = I8042(obj);
    KBDState *s = &isa_s->kbd;

    memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
                          "i8042-data", 1);
    memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
                          "i8042-cmd", 1);
}

static void i8042_realizefn(DeviceState *dev, Error **errp)
{
    ISADevice *isadev = ISA_DEVICE(dev);
    ISAKBDState *isa_s = I8042(dev);
    KBDState *s = &isa_s->kbd;

    isa_init_irq(isadev, &s->irq_kbd, 1);
    isa_init_irq(isadev, &s->irq_mouse, 12);

    isa_register_ioport(isadev, isa_s->io + 0, 0x60);
    isa_register_ioport(isadev, isa_s->io + 1, 0x64);

    s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
    s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
    qemu_register_reset(kbd_reset, s);
}

static void i8042_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = i8042_realizefn;
    dc->no_user = 1;
    dc->vmsd = &vmstate_kbd_isa;
}

static const TypeInfo i8042_info = {
    .name          = TYPE_I8042,
    .parent        = TYPE_ISA_DEVICE,
    .instance_size = sizeof(ISAKBDState),
    .instance_init = i8042_initfn,
    .class_init    = i8042_class_initfn,
};

static void i8042_register_types(void)
{
    type_register_static(&i8042_info);
}

type_init(i8042_register_types)
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU PC keyboard emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
83c9f4ca	24	#include "hw/hw.h"
0d09e41a PB	25	#include "hw/isa/isa.h"
	26	#include "hw/i386/pc.h"
	27	#include "hw/input/ps2.h"
9c17d615	28	#include "sysemu/sysemu.h"
80cabfad FB	29
	30	/* debug PC keyboard */
	31	//#define DEBUG_KBD
c86d2c23 BS	32	#ifdef DEBUG_KBD
	33	#define DPRINTF(fmt, ...) \
	34	do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
	35	#else
	36	#define DPRINTF(fmt, ...)
	37	#endif
80cabfad	38
80cabfad FB	39	/* Keyboard Controller Commands */
	40	#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
	41	#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
	42	#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
	43	#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
	44	#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
	45	#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
	46	#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
	47	#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
	48	#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
	49	#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
	50	#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
	51	#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
	52	#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
	53	#define KBD_CCMD_WRITE_OBUF 0xD2
	54	#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
	55	initiated by the auxiliary device */
	56	#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
	57	#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
	58	#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
5ccaa4ce BK	59	#define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */
	60	#define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */
	61	#define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */
80cabfad FB	62
	63	/* Keyboard Commands */
	64	#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
	65	#define KBD_CMD_ECHO 0xEE
	66	#define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
	67	#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
	68	#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
	69	#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
	70	#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
	71	#define KBD_CMD_RESET 0xFF /* Reset */
	72
	73	/* Keyboard Replies */
	74	#define KBD_REPLY_POR 0xAA /* Power on reset */
	75	#define KBD_REPLY_ACK 0xFA /* Command ACK */
	76	#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
	77
	78	/* Status Register Bits */
	79	#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
	80	#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
	81	#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
	82	#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
	83	#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
	84	#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
	85	#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
	86	#define KBD_STAT_PERR 0x80 /* Parity error */
	87
	88	/* Controller Mode Register Bits */
	89	#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
	90	#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
	91	#define KBD_MODE_SYS 0x04 /* The system flag (?) */
	92	#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
	93	#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
	94	#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
	95	#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
	96	#define KBD_MODE_RFU 0x80
	97
956a3e6b BS	98	/* Output Port Bits */
	99	#define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
	100	#define KBD_OUT_A20 0x02 /* x86 only */
	101	#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
	102	#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
	103
80cabfad FB	104	/* Mouse Commands */
	105	#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
	106	#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
	107	#define AUX_SET_RES 0xE8 /* Set resolution */
	108	#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
	109	#define AUX_SET_STREAM 0xEA /* Set stream mode */
	110	#define AUX_POLL 0xEB /* Poll */
	111	#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
	112	#define AUX_SET_WRAP 0xEE /* Set wrap mode */
	113	#define AUX_SET_REMOTE 0xF0 /* Set remote mode */
	114	#define AUX_GET_TYPE 0xF2 /* Get type */
	115	#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
	116	#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
	117	#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
	118	#define AUX_SET_DEFAULT 0xF6
	119	#define AUX_RESET 0xFF /* Reset aux device */
	120	#define AUX_ACK 0xFA /* Command byte ACK. */
	121
	122	#define MOUSE_STATUS_REMOTE 0x40
	123	#define MOUSE_STATUS_ENABLED 0x20
	124	#define MOUSE_STATUS_SCALE21 0x10
	125
daa57963 FB	126	#define KBD_PENDING_KBD 1
daa57963 FB	127	#define KBD_PENDING_AUX 2
80cabfad FB	128
80cabfad FB	129	typedef struct KBDState {
80cabfad FB	130	uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
	131	uint8_t status;
	132	uint8_t mode;
956a3e6b	133	uint8_t outport;
daa57963	134	/* Bitmask of devices with data available. */
7783e9f0	135	uint8_t pending;
daa57963 FB	136	void *kbd;
daa57963 FB	137	void *mouse;
b7678d96	138
d537cf6c PB	139	qemu_irq irq_kbd;
d537cf6c PB	140	qemu_irq irq_mouse;
956a3e6b	141	qemu_irq *a20_out;
a8170e5e	142	hwaddr mask;
80cabfad FB	143	} KBDState;
80cabfad FB	144
80cabfad FB	145	/* update irq and KBD_STAT_[MOUSE_]OBF */
	146	/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
	147	incorrect, but it avoids having to simulate exact delays */
	148	static void kbd_update_irq(KBDState *s)
	149	{
b7678d96	150	int irq_kbd_level, irq_mouse_level;
80cabfad	151
b7678d96 TS	152	irq_kbd_level = 0;
b7678d96 TS	153	irq_mouse_level = 0;
80cabfad	154	s->status &= ~(KBD_STAT_OBF \| KBD_STAT_MOUSE_OBF);
956a3e6b	155	s->outport &= ~(KBD_OUT_OBF \| KBD_OUT_MOUSE_OBF);
daa57963	156	if (s->pending) {
80cabfad	157	s->status \|= KBD_STAT_OBF;
956a3e6b	158	s->outport \|= KBD_OUT_OBF;
b92bb99b	159	/* kbd data takes priority over aux data. */
daa57963	160	if (s->pending == KBD_PENDING_AUX) {
80cabfad	161	s->status \|= KBD_STAT_MOUSE_OBF;
956a3e6b	162	s->outport \|= KBD_OUT_MOUSE_OBF;
80cabfad	163	if (s->mode & KBD_MODE_MOUSE_INT)
b7678d96	164	irq_mouse_level = 1;
80cabfad	165	} else {
5fafdf24	166	if ((s->mode & KBD_MODE_KBD_INT) &&
80cabfad	167	!(s->mode & KBD_MODE_DISABLE_KBD))
b7678d96	168	irq_kbd_level = 1;
80cabfad FB	169	}
80cabfad FB	170	}
d537cf6c PB	171	qemu_set_irq(s->irq_kbd, irq_kbd_level);
d537cf6c PB	172	qemu_set_irq(s->irq_mouse, irq_mouse_level);
80cabfad FB	173	}
80cabfad FB	174
daa57963	175	static void kbd_update_kbd_irq(void *opaque, int level)
80cabfad	176	{
daa57963	177	KBDState s = (KBDState )opaque;
80cabfad	178
daa57963 FB	179	if (level)
daa57963 FB	180	s->pending \|= KBD_PENDING_KBD;
80cabfad	181	else
daa57963	182	s->pending &= ~KBD_PENDING_KBD;
80cabfad FB	183	kbd_update_irq(s);
	184	}
	185
daa57963	186	static void kbd_update_aux_irq(void *opaque, int level)
80cabfad	187	{
daa57963 FB	188	KBDState s = (KBDState )opaque;
	189
	190	if (level)
	191	s->pending \|= KBD_PENDING_AUX;
	192	else
	193	s->pending &= ~KBD_PENDING_AUX;
	194	kbd_update_irq(s);
80cabfad FB	195	}
80cabfad FB	196
d540bfe0 AG	197	static uint64_t kbd_read_status(void *opaque, hwaddr addr,
d540bfe0 AG	198	unsigned size)
80cabfad	199	{
b41a2cd1	200	KBDState *s = opaque;
80cabfad FB	201	int val;
80cabfad FB	202	val = s->status;
c86d2c23	203	DPRINTF("kbd: read status=0x%02x\n", val);
80cabfad FB	204	return val;
	205	}
	206
daa57963 FB	207	static void kbd_queue(KBDState *s, int b, int aux)
	208	{
	209	if (aux)
	210	ps2_queue(s->mouse, b);
	211	else
	212	ps2_queue(s->kbd, b);
	213	}
	214
4b78a802	215	static void outport_write(KBDState *s, uint32_t val)
956a3e6b	216	{
c86d2c23	217	DPRINTF("kbd: write outport=0x%02x\n", val);
956a3e6b BS	218	s->outport = val;
	219	if (s->a20_out) {
	220	qemu_set_irq(*s->a20_out, (val >> 1) & 1);
	221	}
	222	if (!(val & 1)) {
	223	qemu_system_reset_request();
	224	}
	225	}
	226
d540bfe0 AG	227	static void kbd_write_command(void *opaque, hwaddr addr,
d540bfe0 AG	228	uint64_t val, unsigned size)
80cabfad	229	{
b41a2cd1	230	KBDState *s = opaque;
80cabfad	231
c86d2c23	232	DPRINTF("kbd: write cmd=0x%02x\n", val);
5ccaa4ce BK	233
	234	/* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
	235	* low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
	236	* command specify the output port bits to be pulsed.
	237	* 0: Bit should be pulsed. 1: Bit should not be modified.
	238	* The only useful version of this command is pulsing bit 0,
	239	* which does a CPU reset.
	240	*/
	241	if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
	242	if(!(val & 1))
	243	val = KBD_CCMD_RESET;
	244	else
	245	val = KBD_CCMD_NO_OP;
	246	}
	247
80cabfad FB	248	switch(val) {
80cabfad FB	249	case KBD_CCMD_READ_MODE:
889bec69	250	kbd_queue(s, s->mode, 0);
80cabfad FB	251	break;
	252	case KBD_CCMD_WRITE_MODE:
	253	case KBD_CCMD_WRITE_OBUF:
	254	case KBD_CCMD_WRITE_AUX_OBUF:
	255	case KBD_CCMD_WRITE_MOUSE:
	256	case KBD_CCMD_WRITE_OUTPORT:
	257	s->write_cmd = val;
	258	break;
	259	case KBD_CCMD_MOUSE_DISABLE:
	260	s->mode \|= KBD_MODE_DISABLE_MOUSE;
	261	break;
	262	case KBD_CCMD_MOUSE_ENABLE:
	263	s->mode &= ~KBD_MODE_DISABLE_MOUSE;
	264	break;
	265	case KBD_CCMD_TEST_MOUSE:
	266	kbd_queue(s, 0x00, 0);
	267	break;
	268	case KBD_CCMD_SELF_TEST:
	269	s->status \|= KBD_STAT_SELFTEST;
	270	kbd_queue(s, 0x55, 0);
	271	break;
	272	case KBD_CCMD_KBD_TEST:
	273	kbd_queue(s, 0x00, 0);
	274	break;
	275	case KBD_CCMD_KBD_DISABLE:
	276	s->mode \|= KBD_MODE_DISABLE_KBD;
	277	kbd_update_irq(s);
	278	break;
	279	case KBD_CCMD_KBD_ENABLE:
	280	s->mode &= ~KBD_MODE_DISABLE_KBD;
	281	kbd_update_irq(s);
	282	break;
	283	case KBD_CCMD_READ_INPORT:
	284	kbd_queue(s, 0x00, 0);
	285	break;
	286	case KBD_CCMD_READ_OUTPORT:
956a3e6b	287	kbd_queue(s, s->outport, 0);
80cabfad	288	break;
80cabfad	289	case KBD_CCMD_ENABLE_A20:
956a3e6b BS	290	if (s->a20_out) {
	291	qemu_irq_raise(*s->a20_out);
	292	}
	293	s->outport \|= KBD_OUT_A20;
80cabfad FB	294	break;
80cabfad FB	295	case KBD_CCMD_DISABLE_A20:
956a3e6b BS	296	if (s->a20_out) {
	297	qemu_irq_lower(*s->a20_out);
	298	}
	299	s->outport &= ~KBD_OUT_A20;
80cabfad	300	break;
80cabfad	301	case KBD_CCMD_RESET:
d7d02e3c	302	qemu_system_reset_request();
80cabfad	303	break;
5ccaa4ce BK	304	case KBD_CCMD_NO_OP:
5ccaa4ce BK	305	/* ignore that */
80cabfad FB	306	break;
80cabfad FB	307	default:
d540bfe0	308	fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", (int)val);
80cabfad FB	309	break;
	310	}
	311	}
	312
d540bfe0 AG	313	static uint64_t kbd_read_data(void *opaque, hwaddr addr,
d540bfe0 AG	314	unsigned size)
80cabfad	315	{
63066f4f	316	KBDState *s = opaque;
e41c0f26	317	uint32_t val;
80cabfad	318
daa57963	319	if (s->pending == KBD_PENDING_AUX)
e41c0f26 AZ	320	val = ps2_read_data(s->mouse);
	321	else
	322	val = ps2_read_data(s->kbd);
80cabfad	323
c86d2c23	324	DPRINTF("kbd: read data=0x%02x\n", val);
e41c0f26	325	return val;
80cabfad FB	326	}
80cabfad FB	327
d540bfe0 AG	328	static void kbd_write_data(void *opaque, hwaddr addr,
d540bfe0 AG	329	uint64_t val, unsigned size)
80cabfad	330	{
b41a2cd1	331	KBDState *s = opaque;
80cabfad	332
c86d2c23	333	DPRINTF("kbd: write data=0x%02x\n", val);
80cabfad FB	334
	335	switch(s->write_cmd) {
	336	case 0:
daa57963	337	ps2_write_keyboard(s->kbd, val);
80cabfad FB	338	break;
	339	case KBD_CCMD_WRITE_MODE:
	340	s->mode = val;
f94f5d71	341	ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
daa57963	342	/* ??? */
80cabfad FB	343	kbd_update_irq(s);
	344	break;
	345	case KBD_CCMD_WRITE_OBUF:
	346	kbd_queue(s, val, 0);
	347	break;
	348	case KBD_CCMD_WRITE_AUX_OBUF:
	349	kbd_queue(s, val, 1);
	350	break;
	351	case KBD_CCMD_WRITE_OUTPORT:
4b78a802	352	outport_write(s, val);
80cabfad FB	353	break;
80cabfad FB	354	case KBD_CCMD_WRITE_MOUSE:
daa57963	355	ps2_write_mouse(s->mouse, val);
80cabfad FB	356	break;
	357	default:
	358	break;
	359	}
	360	s->write_cmd = 0;
	361	}
	362
d7d02e3c	363	static void kbd_reset(void *opaque)
80cabfad	364	{
d7d02e3c	365	KBDState *s = opaque;
80cabfad	366
80cabfad FB	367	s->mode = KBD_MODE_KBD_INT \| KBD_MODE_MOUSE_INT;
80cabfad FB	368	s->status = KBD_STAT_CMD \| KBD_STAT_UNLOCKED;
956a3e6b	369	s->outport = KBD_OUT_RESET \| KBD_OUT_A20;
80cabfad FB	370	}
80cabfad FB	371
3c619b59 JQ	372	static const VMStateDescription vmstate_kbd = {
	373	.name = "pckbd",
	374	.version_id = 3,
	375	.minimum_version_id = 3,
	376	.minimum_version_id_old = 3,
	377	.fields = (VMStateField []) {
	378	VMSTATE_UINT8(write_cmd, KBDState),
	379	VMSTATE_UINT8(status, KBDState),
	380	VMSTATE_UINT8(mode, KBDState),
	381	VMSTATE_UINT8(pending, KBDState),
	382	VMSTATE_END_OF_LIST()
	383	}
	384	};
675376f2	385
b92bb99b	386	/* Memory mapped interface */
a8170e5e	387	static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
b92bb99b TS	388	{
	389	KBDState *s = opaque;
	390
4efbe58f	391	if (addr & s->mask)
d540bfe0	392	return kbd_read_status(s, 0, 1) & 0xff;
4efbe58f	393	else
d540bfe0	394	return kbd_read_data(s, 0, 1) & 0xff;
b92bb99b TS	395	}
b92bb99b TS	396
a8170e5e	397	static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
b92bb99b TS	398	{
	399	KBDState *s = opaque;
	400
4efbe58f	401	if (addr & s->mask)
d540bfe0	402	kbd_write_command(s, 0, value & 0xff, 1);
4efbe58f	403	else
d540bfe0	404	kbd_write_data(s, 0, value & 0xff, 1);
b92bb99b TS	405	}
b92bb99b TS	406
dbff76ac RH	407	static const MemoryRegionOps i8042_mmio_ops = {
	408	.endianness = DEVICE_NATIVE_ENDIAN,
	409	.old_mmio = {
	410	.read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
	411	.write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
	412	},
b92bb99b TS	413	};
b92bb99b TS	414
71db710f	415	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
dbff76ac	416	MemoryRegion *region, ram_addr_t size,
a8170e5e	417	hwaddr mask)
b92bb99b	418	{
7267c094	419	KBDState *s = g_malloc0(sizeof(KBDState));
b92bb99b TS	420
	421	s->irq_kbd = kbd_irq;
	422	s->irq_mouse = mouse_irq;
4efbe58f	423	s->mask = mask;
b92bb99b	424
0be71e32	425	vmstate_register(NULL, 0, &vmstate_kbd, s);
dbff76ac	426
2c9b15ca	427	memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
b92bb99b TS	428
	429	s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
	430	s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
a08d4367	431	qemu_register_reset(kbd_reset, s);
b92bb99b	432	}
da85ccfb	433
a2e0b863 AF	434	#define TYPE_I8042 "i8042"
	435	#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
	436
da85ccfb	437	typedef struct ISAKBDState {
a2e0b863 AF	438	ISADevice parent_obj;
a2e0b863 AF	439
dbff76ac RH	440	KBDState kbd;
dbff76ac RH	441	MemoryRegion io[2];
da85ccfb GH	442	} ISAKBDState;
da85ccfb GH	443
956a3e6b BS	444	void i8042_isa_mouse_fake_event(void *opaque)
	445	{
	446	ISADevice *dev = opaque;
a2e0b863 AF	447	ISAKBDState *isa = I8042(dev);
a2e0b863 AF	448	KBDState *s = &isa->kbd;
956a3e6b BS	449
	450	ps2_mouse_fake_event(s->mouse);
	451	}
	452
	453	void i8042_setup_a20_line(ISADevice dev, qemu_irq a20_out)
	454	{
a2e0b863 AF	455	ISAKBDState *isa = I8042(dev);
a2e0b863 AF	456	KBDState *s = &isa->kbd;
956a3e6b BS	457
	458	s->a20_out = a20_out;
	459	}
	460
d05ac8fa	461	static const VMStateDescription vmstate_kbd_isa = {
be73cfe2 JQ	462	.name = "pckbd",
	463	.version_id = 3,
	464	.minimum_version_id = 3,
	465	.minimum_version_id_old = 3,
	466	.fields = (VMStateField []) {
	467	VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
	468	VMSTATE_END_OF_LIST()
	469	}
	470	};
	471
dbff76ac	472	static const MemoryRegionOps i8042_data_ops = {
d540bfe0 AG	473	.read = kbd_read_data,
	474	.write = kbd_write_data,
	475	.impl = {
	476	.min_access_size = 1,
	477	.max_access_size = 1,
	478	},
	479	.endianness = DEVICE_LITTLE_ENDIAN,
dbff76ac RH	480	};
	481
	482	static const MemoryRegionOps i8042_cmd_ops = {
d540bfe0 AG	483	.read = kbd_read_status,
	484	.write = kbd_write_command,
	485	.impl = {
	486	.min_access_size = 1,
	487	.max_access_size = 1,
	488	},
	489	.endianness = DEVICE_LITTLE_ENDIAN,
dbff76ac RH	490	};
dbff76ac RH	491
db895a1e	492	static void i8042_initfn(Object *obj)
da85ccfb	493	{
db895a1e	494	ISAKBDState *isa_s = I8042(obj);
dbff76ac	495	KBDState *s = &isa_s->kbd;
da85ccfb	496
1437c94b PB	497	memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
	498	"i8042-data", 1);
	499	memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
	500	"i8042-cmd", 1);
db895a1e AF	501	}
	502
	503	static void i8042_realizefn(DeviceState dev, Error *errp)
	504	{
	505	ISADevice *isadev = ISA_DEVICE(dev);
	506	ISAKBDState *isa_s = I8042(dev);
	507	KBDState *s = &isa_s->kbd;
	508
	509	isa_init_irq(isadev, &s->irq_kbd, 1);
	510	isa_init_irq(isadev, &s->irq_mouse, 12);
	511
	512	isa_register_ioport(isadev, isa_s->io + 0, 0x60);
	513	isa_register_ioport(isadev, isa_s->io + 1, 0x64);
da85ccfb GH	514
	515	s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
	516	s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
da85ccfb GH	517	qemu_register_reset(kbd_reset, s);
	518	}
	519
8f04ee08 AL	520	static void i8042_class_initfn(ObjectClass klass, void data)
8f04ee08 AL	521	{
39bffca2	522	DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e AF	523
db895a1e AF	524	dc->realize = i8042_realizefn;
39bffca2 AL	525	dc->no_user = 1;
39bffca2 AL	526	dc->vmsd = &vmstate_kbd_isa;
8f04ee08 AL	527	}
8f04ee08 AL	528
8c43a6f0	529	static const TypeInfo i8042_info = {
a2e0b863	530	.name = TYPE_I8042,
39bffca2 AL	531	.parent = TYPE_ISA_DEVICE,
39bffca2 AL	532	.instance_size = sizeof(ISAKBDState),
db895a1e	533	.instance_init = i8042_initfn,
39bffca2	534	.class_init = i8042_class_initfn,
da85ccfb GH	535	};
da85ccfb GH	536
83f7d43a	537	static void i8042_register_types(void)
da85ccfb	538	{
39bffca2	539	type_register_static(&i8042_info);
da85ccfb	540	}
83f7d43a AF	541
83f7d43a AF	542	type_init(i8042_register_types)