]>
Commit | Line | Data |
---|---|---|
dae01685 JK |
1 | /* |
2 | * APIC support - common bits of emulated and KVM kernel model | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * Copyright (c) 2011 Jan Kiszka, Siemens AG | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
19 | */ | |
0d09e41a PB |
20 | #include "hw/i386/apic.h" |
21 | #include "hw/i386/apic_internal.h" | |
dae01685 | 22 | #include "trace.h" |
9c17d615 | 23 | #include "sysemu/kvm.h" |
53a89e26 IM |
24 | #include "hw/qdev.h" |
25 | #include "hw/sysbus.h" | |
dae01685 JK |
26 | |
27 | static int apic_irq_delivered; | |
e5ad936b | 28 | bool apic_report_tpr_access; |
dae01685 JK |
29 | |
30 | void cpu_set_apic_base(DeviceState *d, uint64_t val) | |
31 | { | |
dae01685 JK |
32 | trace_cpu_set_apic_base(val); |
33 | ||
999e12bb AL |
34 | if (d) { |
35 | APICCommonState *s = APIC_COMMON(d); | |
36 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
dae01685 JK |
37 | info->set_base(s, val); |
38 | } | |
39 | } | |
40 | ||
41 | uint64_t cpu_get_apic_base(DeviceState *d) | |
42 | { | |
999e12bb AL |
43 | if (d) { |
44 | APICCommonState *s = APIC_COMMON(d); | |
45 | trace_cpu_get_apic_base((uint64_t)s->apicbase); | |
46 | return s->apicbase; | |
47 | } else { | |
dd673288 IM |
48 | trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); |
49 | return MSR_IA32_APICBASE_BSP; | |
999e12bb | 50 | } |
dae01685 JK |
51 | } |
52 | ||
53 | void cpu_set_apic_tpr(DeviceState *d, uint8_t val) | |
54 | { | |
999e12bb AL |
55 | APICCommonState *s; |
56 | APICCommonClass *info; | |
dae01685 | 57 | |
999e12bb AL |
58 | if (!d) { |
59 | return; | |
dae01685 | 60 | } |
999e12bb AL |
61 | |
62 | s = APIC_COMMON(d); | |
63 | info = APIC_COMMON_GET_CLASS(s); | |
64 | ||
65 | info->set_tpr(s, val); | |
dae01685 JK |
66 | } |
67 | ||
68 | uint8_t cpu_get_apic_tpr(DeviceState *d) | |
e5ad936b JK |
69 | { |
70 | APICCommonState *s; | |
71 | APICCommonClass *info; | |
72 | ||
73 | if (!d) { | |
74 | return 0; | |
75 | } | |
76 | ||
77 | s = APIC_COMMON(d); | |
78 | info = APIC_COMMON_GET_CLASS(s); | |
79 | ||
80 | return info->get_tpr(s); | |
81 | } | |
82 | ||
83 | void apic_enable_tpr_access_reporting(DeviceState *d, bool enable) | |
84 | { | |
85 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
86 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
87 | ||
88 | apic_report_tpr_access = enable; | |
89 | if (info->enable_tpr_reporting) { | |
90 | info->enable_tpr_reporting(s, enable); | |
91 | } | |
92 | } | |
93 | ||
a8170e5e | 94 | void apic_enable_vapic(DeviceState *d, hwaddr paddr) |
dae01685 JK |
95 | { |
96 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
e5ad936b | 97 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 | 98 | |
e5ad936b JK |
99 | s->vapic_paddr = paddr; |
100 | info->vapic_base_update(s); | |
dae01685 JK |
101 | } |
102 | ||
d362e757 JK |
103 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
104 | TPRAccess access) | |
105 | { | |
e5ad936b JK |
106 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
107 | ||
d77953b9 | 108 | vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); |
d362e757 JK |
109 | } |
110 | ||
dae01685 JK |
111 | void apic_report_irq_delivered(int delivered) |
112 | { | |
113 | apic_irq_delivered += delivered; | |
114 | ||
115 | trace_apic_report_irq_delivered(apic_irq_delivered); | |
116 | } | |
117 | ||
118 | void apic_reset_irq_delivered(void) | |
119 | { | |
120 | trace_apic_reset_irq_delivered(apic_irq_delivered); | |
121 | ||
122 | apic_irq_delivered = 0; | |
123 | } | |
124 | ||
125 | int apic_get_irq_delivered(void) | |
126 | { | |
127 | trace_apic_get_irq_delivered(apic_irq_delivered); | |
128 | ||
129 | return apic_irq_delivered; | |
130 | } | |
131 | ||
132 | void apic_deliver_nmi(DeviceState *d) | |
133 | { | |
999e12bb AL |
134 | APICCommonState *s = APIC_COMMON(d); |
135 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
dae01685 | 136 | |
dae01685 JK |
137 | info->external_nmi(s); |
138 | } | |
139 | ||
7a380ca3 JK |
140 | bool apic_next_timer(APICCommonState *s, int64_t current_time) |
141 | { | |
142 | int64_t d; | |
143 | ||
144 | /* We need to store the timer state separately to support APIC | |
145 | * implementations that maintain a non-QEMU timer, e.g. inside the | |
146 | * host kernel. This open-coded state allows us to migrate between | |
147 | * both models. */ | |
148 | s->timer_expiry = -1; | |
149 | ||
150 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { | |
151 | return false; | |
152 | } | |
153 | ||
154 | d = (current_time - s->initial_count_load_time) >> s->count_shift; | |
155 | ||
156 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
157 | if (!s->initial_count) { | |
158 | return false; | |
159 | } | |
160 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * | |
161 | ((uint64_t)s->initial_count + 1); | |
162 | } else { | |
163 | if (d >= s->initial_count) { | |
164 | return false; | |
165 | } | |
166 | d = (uint64_t)s->initial_count + 1; | |
167 | } | |
168 | s->next_time = s->initial_count_load_time + (d << s->count_shift); | |
169 | s->timer_expiry = s->next_time; | |
170 | return true; | |
171 | } | |
172 | ||
dae01685 JK |
173 | void apic_init_reset(DeviceState *d) |
174 | { | |
175 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
176 | int i; | |
177 | ||
178 | if (!s) { | |
179 | return; | |
180 | } | |
181 | s->tpr = 0; | |
182 | s->spurious_vec = 0xff; | |
183 | s->log_dest = 0; | |
184 | s->dest_mode = 0xf; | |
185 | memset(s->isr, 0, sizeof(s->isr)); | |
186 | memset(s->tmr, 0, sizeof(s->tmr)); | |
187 | memset(s->irr, 0, sizeof(s->irr)); | |
188 | for (i = 0; i < APIC_LVT_NB; i++) { | |
189 | s->lvt[i] = APIC_LVT_MASKED; | |
190 | } | |
191 | s->esr = 0; | |
192 | memset(s->icr, 0, sizeof(s->icr)); | |
193 | s->divide_conf = 0; | |
194 | s->count_shift = 0; | |
195 | s->initial_count = 0; | |
196 | s->initial_count_load_time = 0; | |
197 | s->next_time = 0; | |
198 | s->wait_for_sipi = 1; | |
199 | ||
7a380ca3 | 200 | if (s->timer) { |
bc72ad67 | 201 | timer_del(s->timer); |
7a380ca3 JK |
202 | } |
203 | s->timer_expiry = -1; | |
dae01685 JK |
204 | } |
205 | ||
dd673288 IM |
206 | void apic_designate_bsp(DeviceState *d) |
207 | { | |
208 | if (d == NULL) { | |
209 | return; | |
210 | } | |
211 | ||
212 | APICCommonState *s = APIC_COMMON(d); | |
213 | s->apicbase |= MSR_IA32_APICBASE_BSP; | |
214 | } | |
215 | ||
dae01685 JK |
216 | static void apic_reset_common(DeviceState *d) |
217 | { | |
218 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
e5ad936b | 219 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 JK |
220 | bool bsp; |
221 | ||
60671e58 | 222 | bsp = cpu_is_bsp(s->cpu); |
dab86234 | 223 | s->apicbase = APIC_DEFAULT_ADDRESS | |
dae01685 JK |
224 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; |
225 | ||
e5ad936b JK |
226 | s->vapic_paddr = 0; |
227 | info->vapic_base_update(s); | |
228 | ||
dae01685 JK |
229 | apic_init_reset(d); |
230 | ||
231 | if (bsp) { | |
232 | /* | |
233 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
234 | * time typically by BIOS, so PIC interrupt can be delivered to the | |
235 | * processor when local APIC is enabled. | |
236 | */ | |
237 | s->lvt[APIC_LVT_LINT0] = 0x700; | |
238 | } | |
239 | } | |
240 | ||
241 | /* This function is only used for old state version 1 and 2 */ | |
242 | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) | |
243 | { | |
244 | APICCommonState *s = opaque; | |
a4aecd28 | 245 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 JK |
246 | int i; |
247 | ||
248 | if (version_id > 2) { | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | /* XXX: what if the base changes? (registered memory regions) */ | |
253 | qemu_get_be32s(f, &s->apicbase); | |
254 | qemu_get_8s(f, &s->id); | |
255 | qemu_get_8s(f, &s->arb_id); | |
256 | qemu_get_8s(f, &s->tpr); | |
257 | qemu_get_be32s(f, &s->spurious_vec); | |
258 | qemu_get_8s(f, &s->log_dest); | |
259 | qemu_get_8s(f, &s->dest_mode); | |
260 | for (i = 0; i < 8; i++) { | |
261 | qemu_get_be32s(f, &s->isr[i]); | |
262 | qemu_get_be32s(f, &s->tmr[i]); | |
263 | qemu_get_be32s(f, &s->irr[i]); | |
264 | } | |
265 | for (i = 0; i < APIC_LVT_NB; i++) { | |
266 | qemu_get_be32s(f, &s->lvt[i]); | |
267 | } | |
268 | qemu_get_be32s(f, &s->esr); | |
269 | qemu_get_be32s(f, &s->icr[0]); | |
270 | qemu_get_be32s(f, &s->icr[1]); | |
271 | qemu_get_be32s(f, &s->divide_conf); | |
272 | s->count_shift = qemu_get_be32(f); | |
273 | qemu_get_be32s(f, &s->initial_count); | |
274 | s->initial_count_load_time = qemu_get_be64(f); | |
275 | s->next_time = qemu_get_be64(f); | |
276 | ||
277 | if (version_id >= 2) { | |
a4aecd28 JK |
278 | s->timer_expiry = qemu_get_be64(f); |
279 | } | |
280 | ||
281 | if (info->post_load) { | |
282 | info->post_load(s); | |
dae01685 JK |
283 | } |
284 | return 0; | |
285 | } | |
286 | ||
53a89e26 | 287 | static int apic_init_common(ICCDevice *dev) |
dae01685 | 288 | { |
999e12bb AL |
289 | APICCommonState *s = APIC_COMMON(dev); |
290 | APICCommonClass *info; | |
e5ad936b | 291 | static DeviceState *vapic; |
dae01685 | 292 | static int apic_no; |
53a89e26 | 293 | static bool mmio_registered; |
dae01685 JK |
294 | |
295 | if (apic_no >= MAX_APICS) { | |
296 | return -1; | |
297 | } | |
298 | s->idx = apic_no++; | |
299 | ||
999e12bb | 300 | info = APIC_COMMON_GET_CLASS(s); |
dae01685 | 301 | info->init(s); |
53a89e26 IM |
302 | if (!mmio_registered) { |
303 | ICCBus *b = ICC_BUS(qdev_get_parent_bus(DEVICE(dev))); | |
304 | memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory); | |
305 | mmio_registered = true; | |
306 | } | |
e5ad936b | 307 | |
a9605e03 JK |
308 | /* Note: We need at least 1M to map the VAPIC option ROM */ |
309 | if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && | |
310 | ram_size >= 1024 * 1024) { | |
e5ad936b JK |
311 | vapic = sysbus_create_simple("kvmvapic", -1, NULL); |
312 | } | |
313 | s->vapic = vapic; | |
314 | if (apic_report_tpr_access && info->enable_tpr_reporting) { | |
315 | info->enable_tpr_reporting(s, true); | |
316 | } | |
317 | ||
dae01685 JK |
318 | return 0; |
319 | } | |
320 | ||
e5ad936b JK |
321 | static void apic_dispatch_pre_save(void *opaque) |
322 | { | |
323 | APICCommonState *s = APIC_COMMON(opaque); | |
324 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
325 | ||
326 | if (info->pre_save) { | |
327 | info->pre_save(s); | |
328 | } | |
329 | } | |
330 | ||
7a380ca3 JK |
331 | static int apic_dispatch_post_load(void *opaque, int version_id) |
332 | { | |
999e12bb AL |
333 | APICCommonState *s = APIC_COMMON(opaque); |
334 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
7a380ca3 JK |
335 | |
336 | if (info->post_load) { | |
337 | info->post_load(s); | |
338 | } | |
339 | return 0; | |
340 | } | |
341 | ||
dae01685 JK |
342 | static const VMStateDescription vmstate_apic_common = { |
343 | .name = "apic", | |
344 | .version_id = 3, | |
345 | .minimum_version_id = 3, | |
346 | .minimum_version_id_old = 1, | |
347 | .load_state_old = apic_load_old, | |
e5ad936b | 348 | .pre_save = apic_dispatch_pre_save, |
7a380ca3 | 349 | .post_load = apic_dispatch_post_load, |
dae01685 JK |
350 | .fields = (VMStateField[]) { |
351 | VMSTATE_UINT32(apicbase, APICCommonState), | |
352 | VMSTATE_UINT8(id, APICCommonState), | |
353 | VMSTATE_UINT8(arb_id, APICCommonState), | |
354 | VMSTATE_UINT8(tpr, APICCommonState), | |
355 | VMSTATE_UINT32(spurious_vec, APICCommonState), | |
356 | VMSTATE_UINT8(log_dest, APICCommonState), | |
357 | VMSTATE_UINT8(dest_mode, APICCommonState), | |
358 | VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), | |
359 | VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), | |
360 | VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), | |
361 | VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), | |
362 | VMSTATE_UINT32(esr, APICCommonState), | |
363 | VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), | |
364 | VMSTATE_UINT32(divide_conf, APICCommonState), | |
365 | VMSTATE_INT32(count_shift, APICCommonState), | |
366 | VMSTATE_UINT32(initial_count, APICCommonState), | |
367 | VMSTATE_INT64(initial_count_load_time, APICCommonState), | |
368 | VMSTATE_INT64(next_time, APICCommonState), | |
7a380ca3 JK |
369 | VMSTATE_INT64(timer_expiry, |
370 | APICCommonState), /* open-coded timer state */ | |
dae01685 JK |
371 | VMSTATE_END_OF_LIST() |
372 | } | |
373 | }; | |
374 | ||
375 | static Property apic_properties_common[] = { | |
376 | DEFINE_PROP_UINT8("id", APICCommonState, id, -1), | |
e5ad936b JK |
377 | DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, |
378 | true), | |
dae01685 JK |
379 | DEFINE_PROP_END_OF_LIST(), |
380 | }; | |
381 | ||
999e12bb AL |
382 | static void apic_common_class_init(ObjectClass *klass, void *data) |
383 | { | |
53a89e26 | 384 | ICCDeviceClass *idc = ICC_DEVICE_CLASS(klass); |
39bffca2 | 385 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 386 | |
39bffca2 AL |
387 | dc->vmsd = &vmstate_apic_common; |
388 | dc->reset = apic_reset_common; | |
389 | dc->no_user = 1; | |
390 | dc->props = apic_properties_common; | |
53a89e26 | 391 | idc->init = apic_init_common; |
999e12bb | 392 | } |
dae01685 | 393 | |
8c43a6f0 | 394 | static const TypeInfo apic_common_type = { |
999e12bb | 395 | .name = TYPE_APIC_COMMON, |
53a89e26 | 396 | .parent = TYPE_ICC_DEVICE, |
999e12bb AL |
397 | .instance_size = sizeof(APICCommonState), |
398 | .class_size = sizeof(APICCommonClass), | |
399 | .class_init = apic_common_class_init, | |
400 | .abstract = true, | |
401 | }; | |
402 | ||
83f7d43a | 403 | static void register_types(void) |
999e12bb AL |
404 | { |
405 | type_register_static(&apic_common_type); | |
406 | } | |
407 | ||
83f7d43a | 408 | type_init(register_types) |