[qemu.git] / hw / intc / imx_avic.c

/*
 * i.MX31 Vectored Interrupt Controller
 *
 * Note this is NOT the PL192 provided by ARM, but
 * a custom implementation by Freescale.
 *
 * Copyright (c) 2008 OKL
 * Copyright (c) 2011 NICTA Pty Ltd
 * Originally written by Hans Jiang
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 *
 * TODO: implement vectors.
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/host-utils.h"

#define DEBUG_INT 1
#undef DEBUG_INT /* comment out for debugging */

#ifdef DEBUG_INT
#define DPRINTF(fmt, args...) \
do { printf("imx_avic: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif

/*
 * Define to 1 for messages about attempts to
 * access unimplemented registers or similar.
 */
#define DEBUG_IMPLEMENTATION 1
#if DEBUG_IMPLEMENTATION
#  define IPRINTF(fmt, args...) \
    do  { fprintf(stderr, "imx_avic: " fmt, ##args); } while (0)
#else
#  define IPRINTF(fmt, args...) do {} while (0)
#endif

#define IMX_AVIC_NUM_IRQS 64

/* Interrupt Control Bits */
#define ABFLAG (1<<25)
#define ABFEN (1<<24)
#define NIDIS (1<<22) /* Normal Interrupt disable */
#define FIDIS (1<<21) /* Fast interrupt disable */
#define NIAD  (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
#define FIAD  (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
#define NM    (1<<18) /* Normal interrupt mode */


#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)

#define TYPE_IMX_AVIC "imx_avic"
#define IMX_AVIC(obj) \
    OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)

typedef struct IMXAVICState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint64_t pending;
    uint64_t enabled;
    uint64_t is_fiq;
    uint32_t intcntl;
    uint32_t intmask;
    qemu_irq irq;
    qemu_irq fiq;
    uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
} IMXAVICState;

static const VMStateDescription vmstate_imx_avic = {
    .name = "imx-avic",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(pending, IMXAVICState),
        VMSTATE_UINT64(enabled, IMXAVICState),
        VMSTATE_UINT64(is_fiq, IMXAVICState),
        VMSTATE_UINT32(intcntl, IMXAVICState),
        VMSTATE_UINT32(intmask, IMXAVICState),
        VMSTATE_UINT32_ARRAY(prio, IMXAVICState, PRIO_WORDS),
        VMSTATE_END_OF_LIST()
    },
};


static inline int imx_avic_prio(IMXAVICState *s, int irq)
{
    uint32_t word = irq / PRIO_PER_WORD;
    uint32_t part = 4 * (irq % PRIO_PER_WORD);
    return 0xf & (s->prio[word] >> part);
}

static inline void imx_avic_set_prio(IMXAVICState *s, int irq, int prio)
{
    uint32_t word = irq / PRIO_PER_WORD;
    uint32_t part = 4 * (irq % PRIO_PER_WORD);
    uint32_t mask = ~(0xf << part);
    s->prio[word] &= mask;
    s->prio[word] |= prio << part;
}

/* Update interrupts.  */
static void imx_avic_update(IMXAVICState *s)
{
    int i;
    uint64_t new = s->pending & s->enabled;
    uint64_t flags;

    flags = new & s->is_fiq;
    qemu_set_irq(s->fiq, !!flags);

    flags = new & ~s->is_fiq;
    if (!flags || (s->intmask == 0x1f)) {
        qemu_set_irq(s->irq, !!flags);
        return;
    }

    /*
     * Take interrupt if there's a pending interrupt with
     * priority higher than the value of intmask
     */
    for (i = 0; i < IMX_AVIC_NUM_IRQS; i++) {
        if (flags & (1UL << i)) {
            if (imx_avic_prio(s, i) > s->intmask) {
                qemu_set_irq(s->irq, 1);
                return;
            }
        }
    }
    qemu_set_irq(s->irq, 0);
}

static void imx_avic_set_irq(void *opaque, int irq, int level)
{
    IMXAVICState *s = (IMXAVICState *)opaque;

    if (level) {
        DPRINTF("Raising IRQ %d, prio %d\n",
                irq, imx_avic_prio(s, irq));
        s->pending |= (1ULL << irq);
    } else {
        DPRINTF("Clearing IRQ %d, prio %d\n",
                irq, imx_avic_prio(s, irq));
        s->pending &= ~(1ULL << irq);
    }

    imx_avic_update(s);
}


static uint64_t imx_avic_read(void *opaque,
                             hwaddr offset, unsigned size)
{
    IMXAVICState *s = (IMXAVICState *)opaque;


    DPRINTF("read(offset = 0x%x)\n", offset >> 2);
    switch (offset >> 2) {
    case 0: /* INTCNTL */
        return s->intcntl;

    case 1: /* Normal Interrupt Mask Register, NIMASK */
        return s->intmask;

    case 2: /* Interrupt Enable Number Register, INTENNUM */
    case 3: /* Interrupt Disable Number Register, INTDISNUM */
        return 0;

    case 4: /* Interrupt Enabled Number Register High */
        return s->enabled >> 32;

    case 5: /* Interrupt Enabled Number Register Low */
        return s->enabled & 0xffffffffULL;

    case 6: /* Interrupt Type Register High */
        return s->is_fiq >> 32;

    case 7: /* Interrupt Type Register Low */
        return s->is_fiq & 0xffffffffULL;

    case 8: /* Normal Interrupt Priority Register 7 */
    case 9: /* Normal Interrupt Priority Register 6 */
    case 10:/* Normal Interrupt Priority Register 5 */
    case 11:/* Normal Interrupt Priority Register 4 */
    case 12:/* Normal Interrupt Priority Register 3 */
    case 13:/* Normal Interrupt Priority Register 2 */
    case 14:/* Normal Interrupt Priority Register 1 */
    case 15:/* Normal Interrupt Priority Register 0 */
        return s->prio[15-(offset>>2)];

    case 16: /* Normal interrupt vector and status register */
    {
        /*
         * This returns the highest priority
         * outstanding interrupt.  Where there is more than
         * one pending IRQ with the same priority,
         * take the highest numbered one.
         */
        uint64_t flags = s->pending & s->enabled & ~s->is_fiq;
        int i;
        int prio = -1;
        int irq = -1;
        for (i = 63; i >= 0; --i) {
            if (flags & (1ULL<<i)) {
                int irq_prio = imx_avic_prio(s, i);
                if (irq_prio > prio) {
                    irq = i;
                    prio = irq_prio;
                }
            }
        }
        if (irq >= 0) {
            imx_avic_set_irq(s, irq, 0);
            return irq << 16 | prio;
        }
        return 0xffffffffULL;
    }
    case 17:/* Fast Interrupt vector and status register */
    {
        uint64_t flags = s->pending & s->enabled & s->is_fiq;
        int i = ctz64(flags);
        if (i < 64) {
            imx_avic_set_irq(opaque, i, 0);
            return i;
        }
        return 0xffffffffULL;
    }
    case 18:/* Interrupt source register high */
        return s->pending >> 32;

    case 19:/* Interrupt source register low */
        return s->pending & 0xffffffffULL;

    case 20:/* Interrupt Force Register high */
    case 21:/* Interrupt Force Register low */
        return 0;

    case 22:/* Normal Interrupt Pending Register High */
        return (s->pending & s->enabled & ~s->is_fiq) >> 32;

    case 23:/* Normal Interrupt Pending Register Low */
        return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL;

    case 24: /* Fast Interrupt Pending Register High  */
        return (s->pending & s->enabled & s->is_fiq) >> 32;

    case 25: /* Fast Interrupt Pending Register Low  */
        return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL;

    case 0x40:            /* AVIC vector 0, use for WFI WAR */
        return 0x4;

    default:
        IPRINTF("imx_avic_read: Bad offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void imx_avic_write(void *opaque, hwaddr offset,
                          uint64_t val, unsigned size)
{
    IMXAVICState *s = (IMXAVICState *)opaque;

    /* Vector Registers not yet supported */
    if (offset >= 0x100 && offset <= 0x2fc) {
        IPRINTF("imx_avic_write to vector register %d ignored\n",
                (unsigned int)((offset - 0x100) >> 2));
        return;
    }

    DPRINTF("imx_avic_write(0x%x) = %x\n",
            (unsigned int)offset>>2, (unsigned int)val);
    switch (offset >> 2) {
    case 0: /* Interrupt Control Register, INTCNTL */
        s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM);
        if (s->intcntl & ABFEN) {
            s->intcntl &= ~(val & ABFLAG);
        }
        break;

    case 1: /* Normal Interrupt Mask Register, NIMASK */
        s->intmask = val & 0x1f;
        break;

    case 2: /* Interrupt Enable Number Register, INTENNUM */
        DPRINTF("enable(%d)\n", (int)val);
        val &= 0x3f;
        s->enabled |= (1ULL << val);
        break;

    case 3: /* Interrupt Disable Number Register, INTDISNUM */
        DPRINTF("disable(%d)\n", (int)val);
        val &= 0x3f;
        s->enabled &= ~(1ULL << val);
        break;

    case 4: /* Interrupt Enable Number Register High */
        s->enabled = (s->enabled & 0xffffffffULL) | (val << 32);
        break;

    case 5: /* Interrupt Enable Number Register Low */
        s->enabled = (s->enabled & 0xffffffff00000000ULL) | val;
        break;

    case 6: /* Interrupt Type Register High */
        s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32);
        break;

    case 7: /* Interrupt Type Register Low */
        s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) | val;
        break;

    case 8: /* Normal Interrupt Priority Register 7 */
    case 9: /* Normal Interrupt Priority Register 6 */
    case 10:/* Normal Interrupt Priority Register 5 */
    case 11:/* Normal Interrupt Priority Register 4 */
    case 12:/* Normal Interrupt Priority Register 3 */
    case 13:/* Normal Interrupt Priority Register 2 */
    case 14:/* Normal Interrupt Priority Register 1 */
    case 15:/* Normal Interrupt Priority Register 0 */
        s->prio[15-(offset>>2)] = val;
        break;

        /* Read-only registers, writes ignored */
    case 16:/* Normal Interrupt Vector and Status register */
    case 17:/* Fast Interrupt vector and status register */
    case 18:/* Interrupt source register high */
    case 19:/* Interrupt source register low */
        return;

    case 20:/* Interrupt Force Register high */
        s->pending = (s->pending & 0xffffffffULL) | (val << 32);
        break;

    case 21:/* Interrupt Force Register low */
        s->pending = (s->pending & 0xffffffff00000000ULL) | val;
        break;

    case 22:/* Normal Interrupt Pending Register High */
    case 23:/* Normal Interrupt Pending Register Low */
    case 24: /* Fast Interrupt Pending Register High  */
    case 25: /* Fast Interrupt Pending Register Low  */
        return;

    default:
        IPRINTF("imx_avic_write: Bad offset %x\n", (int)offset);
    }
    imx_avic_update(s);
}

static const MemoryRegionOps imx_avic_ops = {
    .read = imx_avic_read,
    .write = imx_avic_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void imx_avic_reset(DeviceState *dev)
{
    IMXAVICState *s = IMX_AVIC(dev);

    s->pending = 0;
    s->enabled = 0;
    s->is_fiq = 0;
    s->intmask = 0x1f;
    s->intcntl = 0;
    memset(s->prio, 0, sizeof s->prio);
}

static int imx_avic_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    IMXAVICState *s = IMX_AVIC(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s,
                          "imx_avic", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);

    qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
    sysbus_init_irq(sbd, &s->irq);
    sysbus_init_irq(sbd, &s->fiq);

    return 0;
}


static void imx_avic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
    k->init = imx_avic_init;
    dc->vmsd = &vmstate_imx_avic;
    dc->reset = imx_avic_reset;
    dc->desc = "i.MX Advanced Vector Interrupt Controller";
}

static const TypeInfo imx_avic_info = {
    .name = TYPE_IMX_AVIC,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IMXAVICState),
    .class_init = imx_avic_class_init,
};

static void imx_avic_register_types(void)
{
    type_register_static(&imx_avic_info);
}

type_init(imx_avic_register_types)
Commit	Line	Data
ff53d4c6 PC	1	/*
	2	* i.MX31 Vectored Interrupt Controller
	3	*
	4	* Note this is NOT the PL192 provided by ARM, but
	5	* a custom implementation by Freescale.
	6	*
	7	* Copyright (c) 2008 OKL
	8	* Copyright (c) 2011 NICTA Pty Ltd
aade7b91	9	* Originally written by Hans Jiang
ff53d4c6	10	*
aade7b91	11	* This code is licensed under the GPL version 2 or later. See
ff53d4c6 PC	12	* the COPYING file in the top-level directory.
	13	*
	14	* TODO: implement vectors.
	15	*/
	16
83c9f4ca PB	17	#include "hw/hw.h"
83c9f4ca PB	18	#include "hw/sysbus.h"
1de7afc9	19	#include "qemu/host-utils.h"
ff53d4c6 PC	20
	21	#define DEBUG_INT 1
	22	#undef DEBUG_INT /* comment out for debugging */
	23
	24	#ifdef DEBUG_INT
	25	#define DPRINTF(fmt, args...) \
	26	do { printf("imx_avic: " fmt , ##args); } while (0)
	27	#else
	28	#define DPRINTF(fmt, args...) do {} while (0)
	29	#endif
	30
	31	/*
	32	* Define to 1 for messages about attempts to
	33	* access unimplemented registers or similar.
	34	*/
	35	#define DEBUG_IMPLEMENTATION 1
	36	#if DEBUG_IMPLEMENTATION
	37	# define IPRINTF(fmt, args...) \
	38	do { fprintf(stderr, "imx_avic: " fmt, ##args); } while (0)
	39	#else
	40	# define IPRINTF(fmt, args...) do {} while (0)
	41	#endif
	42
	43	#define IMX_AVIC_NUM_IRQS 64
	44
	45	/* Interrupt Control Bits */
	46	#define ABFLAG (1<<25)
	47	#define ABFEN (1<<24)
	48	#define NIDIS (1<<22) /* Normal Interrupt disable */
	49	#define FIDIS (1<<21) /* Fast interrupt disable */
	50	#define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
	51	#define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
	52	#define NM (1<<18) /* Normal interrupt mode */
	53
	54
	55	#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
	56	#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
	57
5ff94a61 AF	58	#define TYPE_IMX_AVIC "imx_avic"
	59	#define IMX_AVIC(obj) \
	60	OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
	61
	62	typedef struct IMXAVICState {
	63	SysBusDevice parent_obj;
	64
ff53d4c6 PC	65	MemoryRegion iomem;
	66	uint64_t pending;
	67	uint64_t enabled;
	68	uint64_t is_fiq;
	69	uint32_t intcntl;
	70	uint32_t intmask;
	71	qemu_irq irq;
	72	qemu_irq fiq;
	73	uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
	74	} IMXAVICState;
	75
	76	static const VMStateDescription vmstate_imx_avic = {
	77	.name = "imx-avic",
	78	.version_id = 1,
	79	.minimum_version_id = 1,
	80	.minimum_version_id_old = 1,
	81	.fields = (VMStateField[]) {
	82	VMSTATE_UINT64(pending, IMXAVICState),
	83	VMSTATE_UINT64(enabled, IMXAVICState),
	84	VMSTATE_UINT64(is_fiq, IMXAVICState),
	85	VMSTATE_UINT32(intcntl, IMXAVICState),
	86	VMSTATE_UINT32(intmask, IMXAVICState),
	87	VMSTATE_UINT32_ARRAY(prio, IMXAVICState, PRIO_WORDS),
	88	VMSTATE_END_OF_LIST()
	89	},
	90	};
	91
	92
	93
	94	static inline int imx_avic_prio(IMXAVICState *s, int irq)
	95	{
	96	uint32_t word = irq / PRIO_PER_WORD;
	97	uint32_t part = 4 * (irq % PRIO_PER_WORD);
	98	return 0xf & (s->prio[word] >> part);
	99	}
	100
	101	static inline void imx_avic_set_prio(IMXAVICState *s, int irq, int prio)
	102	{
	103	uint32_t word = irq / PRIO_PER_WORD;
	104	uint32_t part = 4 * (irq % PRIO_PER_WORD);
	105	uint32_t mask = ~(0xf << part);
	106	s->prio[word] &= mask;
	107	s->prio[word] \|= prio << part;
	108	}
	109
	110	/* Update interrupts. */
	111	static void imx_avic_update(IMXAVICState *s)
	112	{
	113	int i;
	114	uint64_t new = s->pending & s->enabled;
	115	uint64_t flags;
	116
	117	flags = new & s->is_fiq;
	118	qemu_set_irq(s->fiq, !!flags);
	119
	120	flags = new & ~s->is_fiq;
	121	if (!flags \|\| (s->intmask == 0x1f)) {
	122	qemu_set_irq(s->irq, !!flags);
	123	return;
	124	}
	125
	126	/*
	127	* Take interrupt if there's a pending interrupt with
	128	* priority higher than the value of intmask
129	*/
130	for (i = 0; i < IMX_AVIC_NUM_IRQS; i++) {
131	if (flags & (1UL << i)) {
132	if (imx_avic_prio(s, i) > s->intmask) {
133	qemu_set_irq(s->irq, 1);
134	return;
135	}
136	}
137	}
138	qemu_set_irq(s->irq, 0);
139	}
140
141	static void imx_avic_set_irq(void *opaque, int irq, int level)
142	{
143	IMXAVICState s = (IMXAVICState )opaque;
144
145	if (level) {
146	DPRINTF("Raising IRQ %d, prio %d\n",
147	irq, imx_avic_prio(s, irq));
148	s->pending \|= (1ULL << irq);
149	} else {
150	DPRINTF("Clearing IRQ %d, prio %d\n",
151	irq, imx_avic_prio(s, irq));
152	s->pending &= ~(1ULL << irq);
153	}
154
155	imx_avic_update(s);
156	}
157
158
159	static uint64_t imx_avic_read(void *opaque,
a8170e5e	160	hwaddr offset, unsigned size)
ff53d4c6 PC	161	{
	162	IMXAVICState s = (IMXAVICState )opaque;
	163
	164
	165	DPRINTF("read(offset = 0x%x)\n", offset >> 2);
	166	switch (offset >> 2) {
	167	case 0: /* INTCNTL */
	168	return s->intcntl;
	169
	170	case 1: /* Normal Interrupt Mask Register, NIMASK */
	171	return s->intmask;
	172
	173	case 2: /* Interrupt Enable Number Register, INTENNUM */
	174	case 3: /* Interrupt Disable Number Register, INTDISNUM */
	175	return 0;
	176
	177	case 4: /* Interrupt Enabled Number Register High */
	178	return s->enabled >> 32;
	179
	180	case 5: /* Interrupt Enabled Number Register Low */
	181	return s->enabled & 0xffffffffULL;
	182
	183	case 6: /* Interrupt Type Register High */
	184	return s->is_fiq >> 32;
	185
	186	case 7: /* Interrupt Type Register Low */
	187	return s->is_fiq & 0xffffffffULL;
	188
	189	case 8: /* Normal Interrupt Priority Register 7 */
	190	case 9: /* Normal Interrupt Priority Register 6 */
	191	case 10:/* Normal Interrupt Priority Register 5 */
	192	case 11:/* Normal Interrupt Priority Register 4 */
	193	case 12:/* Normal Interrupt Priority Register 3 */
	194	case 13:/* Normal Interrupt Priority Register 2 */
	195	case 14:/* Normal Interrupt Priority Register 1 */
	196	case 15:/* Normal Interrupt Priority Register 0 */
	197	return s->prio[15-(offset>>2)];
	198
	199	case 16: /* Normal interrupt vector and status register */
	200	{
	201	/*
	202	* This returns the highest priority
	203	* outstanding interrupt. Where there is more than
	204	* one pending IRQ with the same priority,
	205	* take the highest numbered one.
	206	*/
	207	uint64_t flags = s->pending & s->enabled & ~s->is_fiq;
	208	int i;
	209	int prio = -1;
	210	int irq = -1;
	211	for (i = 63; i >= 0; --i) {
	212	if (flags & (1ULL<<i)) {
	213	int irq_prio = imx_avic_prio(s, i);
	214	if (irq_prio > prio) {
	215	irq = i;
	216	prio = irq_prio;
	217	}
	218	}
	219	}
	220	if (irq >= 0) {
	221	imx_avic_set_irq(s, irq, 0);
	222	return irq << 16 \| prio;
	223	}
	224	return 0xffffffffULL;
225	}
226	case 17:/* Fast Interrupt vector and status register */
227	{
228	uint64_t flags = s->pending & s->enabled & s->is_fiq;
229	int i = ctz64(flags);
230	if (i < 64) {
231	imx_avic_set_irq(opaque, i, 0);
232	return i;
233	}
234	return 0xffffffffULL;
235	}
236	case 18:/* Interrupt source register high */
237	return s->pending >> 32;
238
239	case 19:/* Interrupt source register low */
240	return s->pending & 0xffffffffULL;
241
242	case 20:/* Interrupt Force Register high */
243	case 21:/* Interrupt Force Register low */
244	return 0;
245
246	case 22:/* Normal Interrupt Pending Register High */
247	return (s->pending & s->enabled & ~s->is_fiq) >> 32;
248
249	case 23:/* Normal Interrupt Pending Register Low */
250	return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL;
251
252	case 24: /* Fast Interrupt Pending Register High */
253	return (s->pending & s->enabled & s->is_fiq) >> 32;
254
255	case 25: /* Fast Interrupt Pending Register Low */
256	return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL;
257
258	case 0x40: /* AVIC vector 0, use for WFI WAR */
259	return 0x4;
260
261	default:
262	IPRINTF("imx_avic_read: Bad offset 0x%x\n", (int)offset);
263	return 0;
264	}
265	}
266
a8170e5e	267	static void imx_avic_write(void *opaque, hwaddr offset,
ff53d4c6 PC	268	uint64_t val, unsigned size)
	269	{
	270	IMXAVICState s = (IMXAVICState )opaque;
	271
	272	/* Vector Registers not yet supported */
	273	if (offset >= 0x100 && offset <= 0x2fc) {
	274	IPRINTF("imx_avic_write to vector register %d ignored\n",
40291d61	275	(unsigned int)((offset - 0x100) >> 2));
ff53d4c6 PC	276	return;
	277	}
	278
	279	DPRINTF("imx_avic_write(0x%x) = %x\n",
	280	(unsigned int)offset>>2, (unsigned int)val);
	281	switch (offset >> 2) {
	282	case 0: /* Interrupt Control Register, INTCNTL */
	283	s->intcntl = val & (ABFEN \| NIDIS \| FIDIS \| NIAD \| FIAD \| NM);
	284	if (s->intcntl & ABFEN) {
	285	s->intcntl &= ~(val & ABFLAG);
	286	}
	287	break;
	288
	289	case 1: /* Normal Interrupt Mask Register, NIMASK */
	290	s->intmask = val & 0x1f;
	291	break;
	292
	293	case 2: /* Interrupt Enable Number Register, INTENNUM */
	294	DPRINTF("enable(%d)\n", (int)val);
	295	val &= 0x3f;
	296	s->enabled \|= (1ULL << val);
	297	break;
	298
	299	case 3: /* Interrupt Disable Number Register, INTDISNUM */
	300	DPRINTF("disable(%d)\n", (int)val);
	301	val &= 0x3f;
	302	s->enabled &= ~(1ULL << val);
	303	break;
	304
	305	case 4: /* Interrupt Enable Number Register High */
	306	s->enabled = (s->enabled & 0xffffffffULL) \| (val << 32);
	307	break;
	308
	309	case 5: /* Interrupt Enable Number Register Low */
	310	s->enabled = (s->enabled & 0xffffffff00000000ULL) \| val;
	311	break;
	312
	313	case 6: /* Interrupt Type Register High */
	314	s->is_fiq = (s->is_fiq & 0xffffffffULL) \| (val << 32);
	315	break;
	316
	317	case 7: /* Interrupt Type Register Low */
	318	s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) \| val;
	319	break;
	320
	321	case 8: /* Normal Interrupt Priority Register 7 */
	322	case 9: /* Normal Interrupt Priority Register 6 */
	323	case 10:/* Normal Interrupt Priority Register 5 */
	324	case 11:/* Normal Interrupt Priority Register 4 */
	325	case 12:/* Normal Interrupt Priority Register 3 */
	326	case 13:/* Normal Interrupt Priority Register 2 */
	327	case 14:/* Normal Interrupt Priority Register 1 */
	328	case 15:/* Normal Interrupt Priority Register 0 */
	329	s->prio[15-(offset>>2)] = val;
	330	break;
	331
	332	/* Read-only registers, writes ignored */
	333	case 16:/* Normal Interrupt Vector and Status register */
	334	case 17:/* Fast Interrupt vector and status register */
	335	case 18:/* Interrupt source register high */
	336	case 19:/* Interrupt source register low */
	337	return;
	338
	339	case 20:/* Interrupt Force Register high */
340	s->pending = (s->pending & 0xffffffffULL) \| (val << 32);
341	break;
342
343	case 21:/* Interrupt Force Register low */
344	s->pending = (s->pending & 0xffffffff00000000ULL) \| val;
345	break;
346
347	case 22:/* Normal Interrupt Pending Register High */
348	case 23:/* Normal Interrupt Pending Register Low */
349	case 24: /* Fast Interrupt Pending Register High */
350	case 25: /* Fast Interrupt Pending Register Low */
351	return;
352
353	default:
354	IPRINTF("imx_avic_write: Bad offset %x\n", (int)offset);
355	}
356	imx_avic_update(s);
357	}
358
359	static const MemoryRegionOps imx_avic_ops = {
360	.read = imx_avic_read,
361	.write = imx_avic_write,
362	.endianness = DEVICE_NATIVE_ENDIAN,
363	};
364
365	static void imx_avic_reset(DeviceState *dev)
366	{
5ff94a61 AF	367	IMXAVICState *s = IMX_AVIC(dev);
5ff94a61 AF	368
ff53d4c6 PC	369	s->pending = 0;
	370	s->enabled = 0;
	371	s->is_fiq = 0;
	372	s->intmask = 0x1f;
	373	s->intcntl = 0;
	374	memset(s->prio, 0, sizeof s->prio);
	375	}
	376
5ff94a61	377	static int imx_avic_init(SysBusDevice *sbd)
ff53d4c6	378	{
5ff94a61 AF	379	DeviceState *dev = DEVICE(sbd);
5ff94a61 AF	380	IMXAVICState *s = IMX_AVIC(dev);
ff53d4c6	381
1437c94b PB	382	memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s,
1437c94b PB	383	"imx_avic", 0x1000);
5ff94a61	384	sysbus_init_mmio(sbd, &s->iomem);
ff53d4c6	385
5ff94a61 AF	386	qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
	387	sysbus_init_irq(sbd, &s->irq);
	388	sysbus_init_irq(sbd, &s->fiq);
ff53d4c6 PC	389
	390	return 0;
	391	}
	392
	393
	394	static void imx_avic_class_init(ObjectClass klass, void data)
	395	{
	396	DeviceClass *dc = DEVICE_CLASS(klass);
	397	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	398	k->init = imx_avic_init;
	399	dc->vmsd = &vmstate_imx_avic;
	400	dc->reset = imx_avic_reset;
	401	dc->desc = "i.MX Advanced Vector Interrupt Controller";
	402	}
	403
	404	static const TypeInfo imx_avic_info = {
5ff94a61	405	.name = TYPE_IMX_AVIC,
ff53d4c6 PC	406	.parent = TYPE_SYS_BUS_DEVICE,
	407	.instance_size = sizeof(IMXAVICState),
	408	.class_init = imx_avic_class_init,
	409	};
	410
	411	static void imx_avic_register_types(void)
	412	{
	413	type_register_static(&imx_avic_info);
	414	}
	415
	416	type_init(imx_avic_register_types)