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610626af
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1/*
2 * ioapic.c IOAPIC emulation logic
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 *
6 * Split the ioapic logic from apic.c
7 * Xiantao Zhang <xiantao.zhang@intel.com>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
8167ee88 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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21 */
22
83c9f4ca 23#include "hw/hw.h"
0d09e41a 24#include "hw/i386/pc.h"
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25#include "hw/i386/ioapic.h"
26#include "hw/i386/ioapic_internal.h"
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27
28//#define DEBUG_IOAPIC
29
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30#ifdef DEBUG_IOAPIC
31#define DPRINTF(fmt, ...) \
32 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
33#else
34#define DPRINTF(fmt, ...)
35#endif
36
244ac3af 37static IOAPICCommonState *ioapics[MAX_IOAPICS];
0280b571 38
244ac3af 39static void ioapic_service(IOAPICCommonState *s)
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40{
41 uint8_t i;
42 uint8_t trig_mode;
43 uint8_t vector;
44 uint8_t delivery_mode;
45 uint32_t mask;
46 uint64_t entry;
47 uint8_t dest;
48 uint8_t dest_mode;
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49
50 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
51 mask = 1 << i;
52 if (s->irr & mask) {
53 entry = s->ioredtbl[i];
54 if (!(entry & IOAPIC_LVT_MASKED)) {
1f5e71a8
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55 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
56 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
57 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
58 delivery_mode =
59 (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
0280b571 60 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
610626af 61 s->irr &= ~mask;
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62 } else {
63 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
64 }
1f5e71a8 65 if (delivery_mode == IOAPIC_DM_EXTINT) {
610626af 66 vector = pic_read_irq(isa_pic);
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67 } else {
68 vector = entry & IOAPIC_VECTOR_MASK;
69 }
610626af 70 apic_deliver_irq(dest, dest_mode, delivery_mode,
1f6f408c 71 vector, trig_mode);
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72 }
73 }
74 }
75}
76
7d0500c4 77static void ioapic_set_irq(void *opaque, int vector, int level)
610626af 78{
244ac3af 79 IOAPICCommonState *s = opaque;
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80
81 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
82 * to GSI 2. GSI maps to ioapic 1-1. This is not
83 * the cleanest way of doing it but it should work. */
84
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85 DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
86 if (vector == 0) {
610626af 87 vector = 2;
1f5e71a8 88 }
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89 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
90 uint32_t mask = 1 << vector;
91 uint64_t entry = s->ioredtbl[vector];
92
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93 if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) {
94 level = !level;
95 }
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96 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
97 IOAPIC_TRIGGER_LEVEL) {
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98 /* level triggered */
99 if (level) {
100 s->irr |= mask;
101 ioapic_service(s);
102 } else {
103 s->irr &= ~mask;
104 }
105 } else {
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106 /* According to the 82093AA manual, we must ignore edge requests
107 * if the input pin is masked. */
108 if (level && !(entry & IOAPIC_LVT_MASKED)) {
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109 s->irr |= mask;
110 ioapic_service(s);
111 }
112 }
113 }
114}
115
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116void ioapic_eoi_broadcast(int vector)
117{
244ac3af 118 IOAPICCommonState *s;
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119 uint64_t entry;
120 int i, n;
121
122 for (i = 0; i < MAX_IOAPICS; i++) {
123 s = ioapics[i];
124 if (!s) {
125 continue;
126 }
127 for (n = 0; n < IOAPIC_NUM_PINS; n++) {
128 entry = s->ioredtbl[n];
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129 if ((entry & IOAPIC_LVT_REMOTE_IRR)
130 && (entry & IOAPIC_VECTOR_MASK) == vector) {
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131 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
132 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
133 ioapic_service(s);
134 }
135 }
136 }
137 }
138}
139
4d5bf5f6 140static uint64_t
a8170e5e 141ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
610626af 142{
244ac3af 143 IOAPICCommonState *s = opaque;
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144 int index;
145 uint32_t val = 0;
146
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147 switch (addr & 0xff) {
148 case IOAPIC_IOREGSEL:
610626af 149 val = s->ioregsel;
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150 break;
151 case IOAPIC_IOWIN:
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152 if (size != 4) {
153 break;
154 }
610626af 155 switch (s->ioregsel) {
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156 case IOAPIC_REG_ID:
157 val = s->id << IOAPIC_ID_SHIFT;
158 break;
159 case IOAPIC_REG_VER:
160 val = IOAPIC_VERSION |
161 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
162 break;
163 case IOAPIC_REG_ARB:
164 val = 0;
165 break;
166 default:
167 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
168 if (index >= 0 && index < IOAPIC_NUM_PINS) {
169 if (s->ioregsel & 1) {
170 val = s->ioredtbl[index] >> 32;
171 } else {
172 val = s->ioredtbl[index] & 0xffffffff;
610626af 173 }
1f5e71a8 174 }
610626af 175 }
9af9b330 176 DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
1f5e71a8 177 break;
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178 }
179 return val;
180}
181
1f5e71a8 182static void
a8170e5e 183ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
4d5bf5f6 184 unsigned int size)
610626af 185{
244ac3af 186 IOAPICCommonState *s = opaque;
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187 int index;
188
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189 switch (addr & 0xff) {
190 case IOAPIC_IOREGSEL:
610626af 191 s->ioregsel = val;
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192 break;
193 case IOAPIC_IOWIN:
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194 if (size != 4) {
195 break;
196 }
0c1f781b 197 DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
610626af 198 switch (s->ioregsel) {
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199 case IOAPIC_REG_ID:
200 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
201 break;
202 case IOAPIC_REG_VER:
203 case IOAPIC_REG_ARB:
204 break;
205 default:
206 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
207 if (index >= 0 && index < IOAPIC_NUM_PINS) {
208 if (s->ioregsel & 1) {
209 s->ioredtbl[index] &= 0xffffffff;
210 s->ioredtbl[index] |= (uint64_t)val << 32;
211 } else {
212 s->ioredtbl[index] &= ~0xffffffffULL;
213 s->ioredtbl[index] |= val;
610626af 214 }
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215 ioapic_service(s);
216 }
610626af 217 }
1f5e71a8 218 break;
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219 }
220}
221
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222static const MemoryRegionOps ioapic_io_ops = {
223 .read = ioapic_mem_read,
224 .write = ioapic_mem_write,
225 .endianness = DEVICE_NATIVE_ENDIAN,
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226};
227
244ac3af 228static void ioapic_init(IOAPICCommonState *s, int instance_no)
610626af 229{
4d5bf5f6 230 memory_region_init_io(&s->io_memory, &ioapic_io_ops, s, "ioapic", 0x1000);
610626af 231
244ac3af 232 qdev_init_gpio_in(&s->busdev.qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
0280b571 233
244ac3af 234 ioapics[instance_no] = s;
610626af 235}
96051119 236
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237static void ioapic_class_init(ObjectClass *klass, void *data)
238{
239 IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
39bffca2 240 DeviceClass *dc = DEVICE_CLASS(klass);
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241
242 k->init = ioapic_init;
39bffca2 243 dc->reset = ioapic_reset_common;
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244}
245
8c43a6f0 246static const TypeInfo ioapic_info = {
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247 .name = "ioapic",
248 .parent = TYPE_IOAPIC_COMMON,
249 .instance_size = sizeof(IOAPICCommonState),
250 .class_init = ioapic_class_init,
96051119
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251};
252
83f7d43a 253static void ioapic_register_types(void)
96051119 254{
39bffca2 255 type_register_static(&ioapic_info);
96051119
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256}
257
83f7d43a 258type_init(ioapic_register_types)