[qemu.git] / hw / intc / omap_intc.c

/*
 * TI OMAP interrupt controller emulation.
 *
 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "hw/hw.h"
#include "hw/arm/omap.h"
#include "hw/sysbus.h"

/* Interrupt Handlers */
struct omap_intr_handler_bank_s {
    uint32_t irqs;
    uint32_t inputs;
    uint32_t mask;
    uint32_t fiq;
    uint32_t sens_edge;
    uint32_t swi;
    unsigned char priority[32];
};

#define TYPE_OMAP_INTC "common-omap-intc"
#define OMAP_INTC(obj) \
    OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)

struct omap_intr_handler_s {
    SysBusDevice parent_obj;

    qemu_irq *pins;
    qemu_irq parent_intr[2];
    MemoryRegion mmio;
    void *iclk;
    void *fclk;
    unsigned char nbanks;
    int level_only;
    uint32_t size;

    uint8_t revision;

    /* state */
    uint32_t new_agr[2];
    int sir_intr[2];
    int autoidle;
    uint32_t mask;
    struct omap_intr_handler_bank_s bank[3];
};

static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
{
    int i, j, sir_intr, p_intr, p, f;
    uint32_t level;
    sir_intr = 0;
    p_intr = 255;

    /* Find the interrupt line with the highest dynamic priority.
     * Note: 0 denotes the hightest priority.
     * If all interrupts have the same priority, the default order is IRQ_N,
     * IRQ_N-1,...,IRQ_0. */
    for (j = 0; j < s->nbanks; ++j) {
        level = s->bank[j].irqs & ~s->bank[j].mask &
                (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
        for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
                        level >>= f) {
            p = s->bank[j].priority[i];
            if (p <= p_intr) {
                p_intr = p;
                sir_intr = 32 * j + i;
            }
            f = ffs(level >> 1);
        }
    }
    s->sir_intr[is_fiq] = sir_intr;
}

static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
{
    int i;
    uint32_t has_intr = 0;

    for (i = 0; i < s->nbanks; ++i)
        has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
                (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);

    if (s->new_agr[is_fiq] & has_intr & s->mask) {
        s->new_agr[is_fiq] = 0;
        omap_inth_sir_update(s, is_fiq);
        qemu_set_irq(s->parent_intr[is_fiq], 1);
    }
}

#define INT_FALLING_EDGE	0
#define INT_LOW_LEVEL		1

static void omap_set_intr(void *opaque, int irq, int req)
{
    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
    uint32_t rise;

    struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
    int n = irq & 31;

    if (req) {
        rise = ~bank->irqs & (1 << n);
        if (~bank->sens_edge & (1 << n))
            rise &= ~bank->inputs;

        bank->inputs |= (1 << n);
        if (rise) {
            bank->irqs |= rise;
            omap_inth_update(ih, 0);
            omap_inth_update(ih, 1);
        }
    } else {
        rise = bank->sens_edge & bank->irqs & (1 << n);
        bank->irqs &= ~rise;
        bank->inputs &= ~(1 << n);
    }
}

/* Simplified version with no edge detection */
static void omap_set_intr_noedge(void *opaque, int irq, int req)
{
    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
    uint32_t rise;

    struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
    int n = irq & 31;

    if (req) {
        rise = ~bank->inputs & (1 << n);
        if (rise) {
            bank->irqs |= bank->inputs |= rise;
            omap_inth_update(ih, 0);
            omap_inth_update(ih, 1);
        }
    } else
        bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}

static uint64_t omap_inth_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int i, offset = addr;
    int bank_no = offset >> 8;
    int line_no;
    struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
    offset &= 0xff;

    switch (offset) {
    case 0x00:	/* ITR */
        return bank->irqs;

    case 0x04:	/* MIR */
        return bank->mask;

    case 0x10:	/* SIR_IRQ_CODE */
    case 0x14:  /* SIR_FIQ_CODE */
        if (bank_no != 0)
            break;
        line_no = s->sir_intr[(offset - 0x10) >> 2];
        bank = &s->bank[line_no >> 5];
        i = line_no & 31;
        if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
            bank->irqs &= ~(1 << i);
        return line_no;

    case 0x18:	/* CONTROL_REG */
        if (bank_no != 0)
            break;
        return 0;

    case 0x1c:	/* ILR0 */
    case 0x20:	/* ILR1 */
    case 0x24:	/* ILR2 */
    case 0x28:	/* ILR3 */
    case 0x2c:	/* ILR4 */
    case 0x30:	/* ILR5 */
    case 0x34:	/* ILR6 */
    case 0x38:	/* ILR7 */
    case 0x3c:	/* ILR8 */
    case 0x40:	/* ILR9 */
    case 0x44:	/* ILR10 */
    case 0x48:	/* ILR11 */
    case 0x4c:	/* ILR12 */
    case 0x50:	/* ILR13 */
    case 0x54:	/* ILR14 */
    case 0x58:	/* ILR15 */
    case 0x5c:	/* ILR16 */
    case 0x60:	/* ILR17 */
    case 0x64:	/* ILR18 */
    case 0x68:	/* ILR19 */
    case 0x6c:	/* ILR20 */
    case 0x70:	/* ILR21 */
    case 0x74:	/* ILR22 */
    case 0x78:	/* ILR23 */
    case 0x7c:	/* ILR24 */
    case 0x80:	/* ILR25 */
    case 0x84:	/* ILR26 */
    case 0x88:	/* ILR27 */
    case 0x8c:	/* ILR28 */
    case 0x90:	/* ILR29 */
    case 0x94:	/* ILR30 */
    case 0x98:	/* ILR31 */
        i = (offset - 0x1c) >> 2;
        return (bank->priority[i] << 2) |
                (((bank->sens_edge >> i) & 1) << 1) |
                ((bank->fiq >> i) & 1);

    case 0x9c:	/* ISR */
        return 0x00000000;

    }
    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_inth_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int i, offset = addr;
    int bank_no = offset >> 8;
    struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
    offset &= 0xff;

    switch (offset) {
    case 0x00:	/* ITR */
        /* Important: ignore the clearing if the IRQ is level-triggered and
           the input bit is 1 */
        bank->irqs &= value | (bank->inputs & bank->sens_edge);
        return;

    case 0x04:	/* MIR */
        bank->mask = value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x10:	/* SIR_IRQ_CODE */
    case 0x14:	/* SIR_FIQ_CODE */
        OMAP_RO_REG(addr);
        break;

    case 0x18:	/* CONTROL_REG */
        if (bank_no != 0)
            break;
        if (value & 2) {
            qemu_set_irq(s->parent_intr[1], 0);
            s->new_agr[1] = ~0;
            omap_inth_update(s, 1);
        }
        if (value & 1) {
            qemu_set_irq(s->parent_intr[0], 0);
            s->new_agr[0] = ~0;
            omap_inth_update(s, 0);
        }
        return;

    case 0x1c:	/* ILR0 */
    case 0x20:	/* ILR1 */
    case 0x24:	/* ILR2 */
    case 0x28:	/* ILR3 */
    case 0x2c:	/* ILR4 */
    case 0x30:	/* ILR5 */
    case 0x34:	/* ILR6 */
    case 0x38:	/* ILR7 */
    case 0x3c:	/* ILR8 */
    case 0x40:	/* ILR9 */
    case 0x44:	/* ILR10 */
    case 0x48:	/* ILR11 */
    case 0x4c:	/* ILR12 */
    case 0x50:	/* ILR13 */
    case 0x54:	/* ILR14 */
    case 0x58:	/* ILR15 */
    case 0x5c:	/* ILR16 */
    case 0x60:	/* ILR17 */
    case 0x64:	/* ILR18 */
    case 0x68:	/* ILR19 */
    case 0x6c:	/* ILR20 */
    case 0x70:	/* ILR21 */
    case 0x74:	/* ILR22 */
    case 0x78:	/* ILR23 */
    case 0x7c:	/* ILR24 */
    case 0x80:	/* ILR25 */
    case 0x84:	/* ILR26 */
    case 0x88:	/* ILR27 */
    case 0x8c:	/* ILR28 */
    case 0x90:	/* ILR29 */
    case 0x94:	/* ILR30 */
    case 0x98:	/* ILR31 */
        i = (offset - 0x1c) >> 2;
        bank->priority[i] = (value >> 2) & 0x1f;
        bank->sens_edge &= ~(1 << i);
        bank->sens_edge |= ((value >> 1) & 1) << i;
        bank->fiq &= ~(1 << i);
        bank->fiq |= (value & 1) << i;
        return;

    case 0x9c:	/* ISR */
        for (i = 0; i < 32; i ++)
            if (value & (1 << i)) {
                omap_set_intr(s, 32 * bank_no + i, 1);
                return;
            }
        return;
    }
    OMAP_BAD_REG(addr);
}

static const MemoryRegionOps omap_inth_mem_ops = {
    .read = omap_inth_read,
    .write = omap_inth_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void omap_inth_reset(DeviceState *dev)
{
    struct omap_intr_handler_s *s = OMAP_INTC(dev);
    int i;

    for (i = 0; i < s->nbanks; ++i){
        s->bank[i].irqs = 0x00000000;
        s->bank[i].mask = 0xffffffff;
        s->bank[i].sens_edge = 0x00000000;
        s->bank[i].fiq = 0x00000000;
        s->bank[i].inputs = 0x00000000;
        s->bank[i].swi = 0x00000000;
        memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));

        if (s->level_only)
            s->bank[i].sens_edge = 0xffffffff;
    }

    s->new_agr[0] = ~0;
    s->new_agr[1] = ~0;
    s->sir_intr[0] = 0;
    s->sir_intr[1] = 0;
    s->autoidle = 0;
    s->mask = ~0;

    qemu_set_irq(s->parent_intr[0], 0);
    qemu_set_irq(s->parent_intr[1], 0);
}

static int omap_intc_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    struct omap_intr_handler_s *s = OMAP_INTC(dev);

    if (!s->iclk) {
        hw_error("omap-intc: clk not connected\n");
    }
    s->nbanks = 1;
    sysbus_init_irq(sbd, &s->parent_intr[0]);
    sysbus_init_irq(sbd, &s->parent_intr[1]);
    qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
    memory_region_init_io(&s->mmio, OBJECT(s), &omap_inth_mem_ops, s,
                          "omap-intc", s->size);
    sysbus_init_mmio(sbd, &s->mmio);
    return 0;
}

static Property omap_intc_properties[] = {
    DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
    DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
    DEFINE_PROP_END_OF_LIST(),
};

static void omap_intc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = omap_intc_init;
    dc->reset = omap_inth_reset;
    dc->props = omap_intc_properties;
}

static const TypeInfo omap_intc_info = {
    .name          = "omap-intc",
    .parent        = TYPE_OMAP_INTC,
    .class_init    = omap_intc_class_init,
};

static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int offset = addr;
    int bank_no, line_no;
    struct omap_intr_handler_bank_s *bank = NULL;

    if ((offset & 0xf80) == 0x80) {
        bank_no = (offset & 0x60) >> 5;
        if (bank_no < s->nbanks) {
            offset &= ~0x60;
            bank = &s->bank[bank_no];
        } else {
            OMAP_BAD_REG(addr);
            return 0;
        }
    }

    switch (offset) {
    case 0x00:	/* INTC_REVISION */
        return s->revision;

    case 0x10:	/* INTC_SYSCONFIG */
        return (s->autoidle >> 2) & 1;

    case 0x14:	/* INTC_SYSSTATUS */
        return 1;						/* RESETDONE */

    case 0x40:	/* INTC_SIR_IRQ */
        return s->sir_intr[0];

    case 0x44:	/* INTC_SIR_FIQ */
        return s->sir_intr[1];

    case 0x48:	/* INTC_CONTROL */
        return (!s->mask) << 2;					/* GLOBALMASK */

    case 0x4c:	/* INTC_PROTECTION */
        return 0;

    case 0x50:	/* INTC_IDLE */
        return s->autoidle & 3;

    /* Per-bank registers */
    case 0x80:	/* INTC_ITR */
        return bank->inputs;

    case 0x84:	/* INTC_MIR */
        return bank->mask;

    case 0x88:	/* INTC_MIR_CLEAR */
    case 0x8c:	/* INTC_MIR_SET */
        return 0;

    case 0x90:	/* INTC_ISR_SET */
        return bank->swi;

    case 0x94:	/* INTC_ISR_CLEAR */
        return 0;

    case 0x98:	/* INTC_PENDING_IRQ */
        return bank->irqs & ~bank->mask & ~bank->fiq;

    case 0x9c:	/* INTC_PENDING_FIQ */
        return bank->irqs & ~bank->mask & bank->fiq;

    /* Per-line registers */
    case 0x100 ... 0x300:	/* INTC_ILR */
        bank_no = (offset - 0x100) >> 7;
        if (bank_no > s->nbanks)
            break;
        bank = &s->bank[bank_no];
        line_no = (offset & 0x7f) >> 2;
        return (bank->priority[line_no] << 2) |
                ((bank->fiq >> line_no) & 1);
    }
    OMAP_BAD_REG(addr);
    return 0;
}

static void omap2_inth_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
    int offset = addr;
    int bank_no, line_no;
    struct omap_intr_handler_bank_s *bank = NULL;

    if ((offset & 0xf80) == 0x80) {
        bank_no = (offset & 0x60) >> 5;
        if (bank_no < s->nbanks) {
            offset &= ~0x60;
            bank = &s->bank[bank_no];
        } else {
            OMAP_BAD_REG(addr);
            return;
        }
    }

    switch (offset) {
    case 0x10:	/* INTC_SYSCONFIG */
        s->autoidle &= 4;
        s->autoidle |= (value & 1) << 2;
        if (value & 2) {                                        /* SOFTRESET */
            omap_inth_reset(DEVICE(s));
        }
        return;

    case 0x48:	/* INTC_CONTROL */
        s->mask = (value & 4) ? 0 : ~0;				/* GLOBALMASK */
        if (value & 2) {					/* NEWFIQAGR */
            qemu_set_irq(s->parent_intr[1], 0);
            s->new_agr[1] = ~0;
            omap_inth_update(s, 1);
        }
        if (value & 1) {					/* NEWIRQAGR */
            qemu_set_irq(s->parent_intr[0], 0);
            s->new_agr[0] = ~0;
            omap_inth_update(s, 0);
        }
        return;

    case 0x4c:	/* INTC_PROTECTION */
        /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
         * for every register, see Chapter 3 and 4 for privileged mode.  */
        if (value & 1)
            fprintf(stderr, "%s: protection mode enable attempt\n",
                            __FUNCTION__);
        return;

    case 0x50:	/* INTC_IDLE */
        s->autoidle &= ~3;
        s->autoidle |= value & 3;
        return;

    /* Per-bank registers */
    case 0x84:	/* INTC_MIR */
        bank->mask = value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x88:	/* INTC_MIR_CLEAR */
        bank->mask &= ~value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x8c:	/* INTC_MIR_SET */
        bank->mask |= value;
        return;

    case 0x90:	/* INTC_ISR_SET */
        bank->irqs |= bank->swi |= value;
        omap_inth_update(s, 0);
        omap_inth_update(s, 1);
        return;

    case 0x94:	/* INTC_ISR_CLEAR */
        bank->swi &= ~value;
        bank->irqs = bank->swi & bank->inputs;
        return;

    /* Per-line registers */
    case 0x100 ... 0x300:	/* INTC_ILR */
        bank_no = (offset - 0x100) >> 7;
        if (bank_no > s->nbanks)
            break;
        bank = &s->bank[bank_no];
        line_no = (offset & 0x7f) >> 2;
        bank->priority[line_no] = (value >> 2) & 0x3f;
        bank->fiq &= ~(1 << line_no);
        bank->fiq |= (value & 1) << line_no;
        return;

    case 0x00:	/* INTC_REVISION */
    case 0x14:	/* INTC_SYSSTATUS */
    case 0x40:	/* INTC_SIR_IRQ */
    case 0x44:	/* INTC_SIR_FIQ */
    case 0x80:	/* INTC_ITR */
    case 0x98:	/* INTC_PENDING_IRQ */
    case 0x9c:	/* INTC_PENDING_FIQ */
        OMAP_RO_REG(addr);
        return;
    }
    OMAP_BAD_REG(addr);
}

static const MemoryRegionOps omap2_inth_mem_ops = {
    .read = omap2_inth_read,
    .write = omap2_inth_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static int omap2_intc_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    struct omap_intr_handler_s *s = OMAP_INTC(dev);

    if (!s->iclk) {
        hw_error("omap2-intc: iclk not connected\n");
    }
    if (!s->fclk) {
        hw_error("omap2-intc: fclk not connected\n");
    }
    s->level_only = 1;
    s->nbanks = 3;
    sysbus_init_irq(sbd, &s->parent_intr[0]);
    sysbus_init_irq(sbd, &s->parent_intr[1]);
    qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
    memory_region_init_io(&s->mmio, OBJECT(s), &omap2_inth_mem_ops, s,
                          "omap2-intc", 0x1000);
    sysbus_init_mmio(sbd, &s->mmio);
    return 0;
}

static Property omap2_intc_properties[] = {
    DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
    revision, 0x21),
    DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
    DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
    DEFINE_PROP_END_OF_LIST(),
};

static void omap2_intc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = omap2_intc_init;
    dc->reset = omap_inth_reset;
    dc->props = omap2_intc_properties;
}

static const TypeInfo omap2_intc_info = {
    .name          = "omap2-intc",
    .parent        = TYPE_OMAP_INTC,
    .class_init    = omap2_intc_class_init,
};

static const TypeInfo omap_intc_type_info = {
    .name          = TYPE_OMAP_INTC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(struct omap_intr_handler_s),
    .abstract      = true,
};

static void omap_intc_register_types(void)
{
    type_register_static(&omap_intc_type_info);
    type_register_static(&omap_intc_info);
    type_register_static(&omap2_intc_info);
}

type_init(omap_intc_register_types)
Commit	Line	Data
7f132a21	1	/*
	2	* TI OMAP interrupt controller emulation.
	3	*
	4	* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
	5	* Copyright (C) 2007-2008 Nokia Corporation
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 or
	10	* (at your option) version 3 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
	19	*/
83c9f4ca	20	#include "hw/hw.h"
0d09e41a	21	#include "hw/arm/omap.h"
83c9f4ca	22	#include "hw/sysbus.h"
7f132a21	23
	24	/* Interrupt Handlers */
	25	struct omap_intr_handler_bank_s {
	26	uint32_t irqs;
	27	uint32_t inputs;
	28	uint32_t mask;
	29	uint32_t fiq;
	30	uint32_t sens_edge;
	31	uint32_t swi;
	32	unsigned char priority[32];
	33	};
	34
47edc5a4 AF	35	#define TYPE_OMAP_INTC "common-omap-intc"
	36	#define OMAP_INTC(obj) \
	37	OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
	38
7f132a21	39	struct omap_intr_handler_s {
47edc5a4 AF	40	SysBusDevice parent_obj;
47edc5a4 AF	41
7f132a21	42	qemu_irq *pins;
7f132a21	43	qemu_irq parent_intr[2];
53bb614e	44	MemoryRegion mmio;
0919ac78 PM	45	void *iclk;
0919ac78 PM	46	void *fclk;
7f132a21	47	unsigned char nbanks;
7f132a21	48	int level_only;
0919ac78 PM	49	uint32_t size;
	50
	51	uint8_t revision;
7f132a21	52
	53	/* state */
	54	uint32_t new_agr[2];
	55	int sir_intr[2];
	56	int autoidle;
	57	uint32_t mask;
0919ac78	58	struct omap_intr_handler_bank_s bank[3];
7f132a21	59	};
7f132a21	60
7f132a21	61	static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
	62	{
	63	int i, j, sir_intr, p_intr, p, f;
	64	uint32_t level;
	65	sir_intr = 0;
	66	p_intr = 255;
	67
	68	/* Find the interrupt line with the highest dynamic priority.
	69	* Note: 0 denotes the hightest priority.
	70	* If all interrupts have the same priority, the default order is IRQ_N,
	71	* IRQ_N-1,...,IRQ_0. */
	72	for (j = 0; j < s->nbanks; ++j) {
	73	level = s->bank[j].irqs & ~s->bank[j].mask &
	74	(is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
	75	for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
	76	level >>= f) {
	77	p = s->bank[j].priority[i];
	78	if (p <= p_intr) {
	79	p_intr = p;
	80	sir_intr = 32 * j + i;
	81	}
	82	f = ffs(level >> 1);
	83	}
	84	}
	85	s->sir_intr[is_fiq] = sir_intr;
	86	}
	87
	88	static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
	89	{
	90	int i;
	91	uint32_t has_intr = 0;
	92
	93	for (i = 0; i < s->nbanks; ++i)
	94	has_intr \|= s->bank[i].irqs & ~s->bank[i].mask &
	95	(is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
	96
	97	if (s->new_agr[is_fiq] & has_intr & s->mask) {
	98	s->new_agr[is_fiq] = 0;
	99	omap_inth_sir_update(s, is_fiq);
	100	qemu_set_irq(s->parent_intr[is_fiq], 1);
	101	}
	102	}
	103
	104	#define INT_FALLING_EDGE 0
	105	#define INT_LOW_LEVEL 1
	106
	107	static void omap_set_intr(void *opaque, int irq, int req)
	108	{
	109	struct omap_intr_handler_s ih = (struct omap_intr_handler_s ) opaque;
	110	uint32_t rise;
	111
	112	struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
	113	int n = irq & 31;
	114
	115	if (req) {
	116	rise = ~bank->irqs & (1 << n);
	117	if (~bank->sens_edge & (1 << n))
	118	rise &= ~bank->inputs;
	119
	120	bank->inputs \|= (1 << n);
	121	if (rise) {
	122	bank->irqs \|= rise;
	123	omap_inth_update(ih, 0);
	124	omap_inth_update(ih, 1);
125	}
126	} else {
127	rise = bank->sens_edge & bank->irqs & (1 << n);
128	bank->irqs &= ~rise;
129	bank->inputs &= ~(1 << n);
130	}
131	}
132
133	/* Simplified version with no edge detection */
134	static void omap_set_intr_noedge(void *opaque, int irq, int req)
135	{
136	struct omap_intr_handler_s ih = (struct omap_intr_handler_s ) opaque;
137	uint32_t rise;
138
139	struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
140	int n = irq & 31;
141
142	if (req) {
143	rise = ~bank->inputs & (1 << n);
144	if (rise) {
145	bank->irqs \|= bank->inputs \|= rise;
146	omap_inth_update(ih, 0);
147	omap_inth_update(ih, 1);
148	}
149	} else
150	bank->irqs = (bank->inputs &= ~(1 << n)) \| bank->swi;
151	}
152
a8170e5e	153	static uint64_t omap_inth_read(void *opaque, hwaddr addr,
53bb614e	154	unsigned size)
7f132a21	155	{
	156	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	157	int i, offset = addr;
	158	int bank_no = offset >> 8;
	159	int line_no;
	160	struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
	161	offset &= 0xff;
	162
	163	switch (offset) {
	164	case 0x00: /* ITR */
	165	return bank->irqs;
	166
	167	case 0x04: /* MIR */
	168	return bank->mask;
	169
	170	case 0x10: /* SIR_IRQ_CODE */
	171	case 0x14: /* SIR_FIQ_CODE */
	172	if (bank_no != 0)
	173	break;
	174	line_no = s->sir_intr[(offset - 0x10) >> 2];
	175	bank = &s->bank[line_no >> 5];
	176	i = line_no & 31;
	177	if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
	178	bank->irqs &= ~(1 << i);
	179	return line_no;
	180
	181	case 0x18: /* CONTROL_REG */
	182	if (bank_no != 0)
	183	break;
	184	return 0;
	185
	186	case 0x1c: /* ILR0 */
	187	case 0x20: /* ILR1 */
	188	case 0x24: /* ILR2 */
	189	case 0x28: /* ILR3 */
	190	case 0x2c: /* ILR4 */
	191	case 0x30: /* ILR5 */
	192	case 0x34: /* ILR6 */
	193	case 0x38: /* ILR7 */
	194	case 0x3c: /* ILR8 */
	195	case 0x40: /* ILR9 */
	196	case 0x44: /* ILR10 */
	197	case 0x48: /* ILR11 */
	198	case 0x4c: /* ILR12 */
	199	case 0x50: /* ILR13 */
	200	case 0x54: /* ILR14 */
	201	case 0x58: /* ILR15 */
	202	case 0x5c: /* ILR16 */
	203	case 0x60: /* ILR17 */
	204	case 0x64: /* ILR18 */
	205	case 0x68: /* ILR19 */
	206	case 0x6c: /* ILR20 */
	207	case 0x70: /* ILR21 */
	208	case 0x74: /* ILR22 */
	209	case 0x78: /* ILR23 */
	210	case 0x7c: /* ILR24 */
	211	case 0x80: /* ILR25 */
	212	case 0x84: /* ILR26 */
	213	case 0x88: /* ILR27 */
	214	case 0x8c: /* ILR28 */
	215	case 0x90: /* ILR29 */
	216	case 0x94: /* ILR30 */
	217	case 0x98: /* ILR31 */
	218	i = (offset - 0x1c) >> 2;
219	return (bank->priority[i] << 2) \|
220	(((bank->sens_edge >> i) & 1) << 1) \|
221	((bank->fiq >> i) & 1);
222
223	case 0x9c: /* ISR */
224	return 0x00000000;
225
226	}
227	OMAP_BAD_REG(addr);
228	return 0;
229	}
230
a8170e5e	231	static void omap_inth_write(void *opaque, hwaddr addr,
53bb614e	232	uint64_t value, unsigned size)
7f132a21	233	{
	234	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	235	int i, offset = addr;
	236	int bank_no = offset >> 8;
	237	struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
	238	offset &= 0xff;
	239
	240	switch (offset) {
	241	case 0x00: /* ITR */
	242	/* Important: ignore the clearing if the IRQ is level-triggered and
	243	the input bit is 1 */
	244	bank->irqs &= value \| (bank->inputs & bank->sens_edge);
	245	return;
	246
	247	case 0x04: /* MIR */
	248	bank->mask = value;
	249	omap_inth_update(s, 0);
	250	omap_inth_update(s, 1);
	251	return;
	252
	253	case 0x10: /* SIR_IRQ_CODE */
	254	case 0x14: /* SIR_FIQ_CODE */
	255	OMAP_RO_REG(addr);
	256	break;
	257
	258	case 0x18: /* CONTROL_REG */
	259	if (bank_no != 0)
	260	break;
	261	if (value & 2) {
	262	qemu_set_irq(s->parent_intr[1], 0);
	263	s->new_agr[1] = ~0;
	264	omap_inth_update(s, 1);
	265	}
	266	if (value & 1) {
	267	qemu_set_irq(s->parent_intr[0], 0);
	268	s->new_agr[0] = ~0;
	269	omap_inth_update(s, 0);
	270	}
	271	return;
	272
	273	case 0x1c: /* ILR0 */
	274	case 0x20: /* ILR1 */
	275	case 0x24: /* ILR2 */
	276	case 0x28: /* ILR3 */
	277	case 0x2c: /* ILR4 */
	278	case 0x30: /* ILR5 */
	279	case 0x34: /* ILR6 */
	280	case 0x38: /* ILR7 */
	281	case 0x3c: /* ILR8 */
	282	case 0x40: /* ILR9 */
	283	case 0x44: /* ILR10 */
	284	case 0x48: /* ILR11 */
	285	case 0x4c: /* ILR12 */
	286	case 0x50: /* ILR13 */
	287	case 0x54: /* ILR14 */
	288	case 0x58: /* ILR15 */
	289	case 0x5c: /* ILR16 */
	290	case 0x60: /* ILR17 */
	291	case 0x64: /* ILR18 */
	292	case 0x68: /* ILR19 */
	293	case 0x6c: /* ILR20 */
	294	case 0x70: /* ILR21 */
	295	case 0x74: /* ILR22 */
	296	case 0x78: /* ILR23 */
297	case 0x7c: /* ILR24 */
298	case 0x80: /* ILR25 */
299	case 0x84: /* ILR26 */
300	case 0x88: /* ILR27 */
301	case 0x8c: /* ILR28 */
302	case 0x90: /* ILR29 */
303	case 0x94: /* ILR30 */
304	case 0x98: /* ILR31 */
305	i = (offset - 0x1c) >> 2;
306	bank->priority[i] = (value >> 2) & 0x1f;
307	bank->sens_edge &= ~(1 << i);
308	bank->sens_edge \|= ((value >> 1) & 1) << i;
309	bank->fiq &= ~(1 << i);
310	bank->fiq \|= (value & 1) << i;
311	return;
312
313	case 0x9c: /* ISR */
314	for (i = 0; i < 32; i ++)
315	if (value & (1 << i)) {
316	omap_set_intr(s, 32 * bank_no + i, 1);
317	return;
318	}
319	return;
320	}
321	OMAP_BAD_REG(addr);
322	}
323
53bb614e PM	324	static const MemoryRegionOps omap_inth_mem_ops = {
	325	.read = omap_inth_read,
	326	.write = omap_inth_write,
	327	.endianness = DEVICE_NATIVE_ENDIAN,
	328	.valid = {
	329	.min_access_size = 4,
	330	.max_access_size = 4,
	331	},
7f132a21	332	};
7f132a21	333
0919ac78	334	static void omap_inth_reset(DeviceState *dev)
7f132a21	335	{
47edc5a4	336	struct omap_intr_handler_s *s = OMAP_INTC(dev);
7f132a21	337	int i;
	338
	339	for (i = 0; i < s->nbanks; ++i){
	340	s->bank[i].irqs = 0x00000000;
	341	s->bank[i].mask = 0xffffffff;
	342	s->bank[i].sens_edge = 0x00000000;
	343	s->bank[i].fiq = 0x00000000;
	344	s->bank[i].inputs = 0x00000000;
	345	s->bank[i].swi = 0x00000000;
	346	memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
	347
	348	if (s->level_only)
	349	s->bank[i].sens_edge = 0xffffffff;
	350	}
	351
	352	s->new_agr[0] = ~0;
	353	s->new_agr[1] = ~0;
	354	s->sir_intr[0] = 0;
	355	s->sir_intr[1] = 0;
	356	s->autoidle = 0;
	357	s->mask = ~0;
	358
	359	qemu_set_irq(s->parent_intr[0], 0);
	360	qemu_set_irq(s->parent_intr[1], 0);
	361	}
	362
47edc5a4	363	static int omap_intc_init(SysBusDevice *sbd)
7f132a21	364	{
47edc5a4 AF	365	DeviceState *dev = DEVICE(sbd);
	366	struct omap_intr_handler_s *s = OMAP_INTC(dev);
	367
0919ac78 PM	368	if (!s->iclk) {
	369	hw_error("omap-intc: clk not connected\n");
	370	}
	371	s->nbanks = 1;
47edc5a4 AF	372	sysbus_init_irq(sbd, &s->parent_intr[0]);
	373	sysbus_init_irq(sbd, &s->parent_intr[1]);
	374	qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
1437c94b	375	memory_region_init_io(&s->mmio, OBJECT(s), &omap_inth_mem_ops, s,
0919ac78	376	"omap-intc", s->size);
47edc5a4	377	sysbus_init_mmio(sbd, &s->mmio);
0919ac78	378	return 0;
7f132a21	379	}
7f132a21	380
999e12bb AL	381	static Property omap_intc_properties[] = {
	382	DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
	383	DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
	384	DEFINE_PROP_END_OF_LIST(),
	385	};
	386
	387	static void omap_intc_class_init(ObjectClass klass, void data)
	388	{
39bffca2	389	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	390	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	391
	392	k->init = omap_intc_init;
39bffca2 AL	393	dc->reset = omap_inth_reset;
39bffca2 AL	394	dc->props = omap_intc_properties;
999e12bb AL	395	}
999e12bb AL	396
8c43a6f0	397	static const TypeInfo omap_intc_info = {
39bffca2	398	.name = "omap-intc",
47edc5a4	399	.parent = TYPE_OMAP_INTC,
39bffca2	400	.class_init = omap_intc_class_init,
0919ac78 PM	401	};
0919ac78 PM	402
a8170e5e	403	static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
53bb614e	404	unsigned size)
7f132a21	405	{
	406	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	407	int offset = addr;
	408	int bank_no, line_no;
	409	struct omap_intr_handler_bank_s *bank = NULL;
	410
	411	if ((offset & 0xf80) == 0x80) {
	412	bank_no = (offset & 0x60) >> 5;
	413	if (bank_no < s->nbanks) {
	414	offset &= ~0x60;
	415	bank = &s->bank[bank_no];
096685fc PM	416	} else {
	417	OMAP_BAD_REG(addr);
	418	return 0;
7f132a21	419	}
	420	}
	421
	422	switch (offset) {
	423	case 0x00: /* INTC_REVISION */
0919ac78	424	return s->revision;
7f132a21	425
	426	case 0x10: /* INTC_SYSCONFIG */
	427	return (s->autoidle >> 2) & 1;
	428
	429	case 0x14: /* INTC_SYSSTATUS */
	430	return 1; /* RESETDONE */
	431
	432	case 0x40: /* INTC_SIR_IRQ */
	433	return s->sir_intr[0];
	434
	435	case 0x44: /* INTC_SIR_FIQ */
	436	return s->sir_intr[1];
	437
	438	case 0x48: /* INTC_CONTROL */
	439	return (!s->mask) << 2; /* GLOBALMASK */
	440
	441	case 0x4c: /* INTC_PROTECTION */
	442	return 0;
	443
	444	case 0x50: /* INTC_IDLE */
	445	return s->autoidle & 3;
	446
	447	/* Per-bank registers */
	448	case 0x80: /* INTC_ITR */
	449	return bank->inputs;
	450
	451	case 0x84: /* INTC_MIR */
	452	return bank->mask;
	453
	454	case 0x88: /* INTC_MIR_CLEAR */
	455	case 0x8c: /* INTC_MIR_SET */
	456	return 0;
	457
	458	case 0x90: /* INTC_ISR_SET */
	459	return bank->swi;
	460
	461	case 0x94: /* INTC_ISR_CLEAR */
	462	return 0;
	463
	464	case 0x98: /* INTC_PENDING_IRQ */
	465	return bank->irqs & ~bank->mask & ~bank->fiq;
	466
	467	case 0x9c: /* INTC_PENDING_FIQ */
	468	return bank->irqs & ~bank->mask & bank->fiq;
	469
	470	/* Per-line registers */
	471	case 0x100 ... 0x300: /* INTC_ILR */
	472	bank_no = (offset - 0x100) >> 7;
	473	if (bank_no > s->nbanks)
	474	break;
	475	bank = &s->bank[bank_no];
	476	line_no = (offset & 0x7f) >> 2;
	477	return (bank->priority[line_no] << 2) \|
	478	((bank->fiq >> line_no) & 1);
	479	}
	480	OMAP_BAD_REG(addr);
	481	return 0;
	482	}
	483
a8170e5e	484	static void omap2_inth_write(void *opaque, hwaddr addr,
53bb614e	485	uint64_t value, unsigned size)
7f132a21	486	{
	487	struct omap_intr_handler_s s = (struct omap_intr_handler_s ) opaque;
	488	int offset = addr;
	489	int bank_no, line_no;
	490	struct omap_intr_handler_bank_s *bank = NULL;
	491
	492	if ((offset & 0xf80) == 0x80) {
	493	bank_no = (offset & 0x60) >> 5;
	494	if (bank_no < s->nbanks) {
	495	offset &= ~0x60;
	496	bank = &s->bank[bank_no];
096685fc PM	497	} else {
	498	OMAP_BAD_REG(addr);
	499	return;
7f132a21	500	}
	501	}
	502
	503	switch (offset) {
	504	case 0x10: /* INTC_SYSCONFIG */
	505	s->autoidle &= 4;
	506	s->autoidle \|= (value & 1) << 2;
47edc5a4 AF	507	if (value & 2) { /* SOFTRESET */
	508	omap_inth_reset(DEVICE(s));
	509	}
7f132a21	510	return;
	511
	512	case 0x48: /* INTC_CONTROL */
	513	s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
	514	if (value & 2) { /* NEWFIQAGR */
	515	qemu_set_irq(s->parent_intr[1], 0);
	516	s->new_agr[1] = ~0;
	517	omap_inth_update(s, 1);
	518	}
	519	if (value & 1) { /* NEWIRQAGR */
	520	qemu_set_irq(s->parent_intr[0], 0);
	521	s->new_agr[0] = ~0;
	522	omap_inth_update(s, 0);
	523	}
	524	return;
	525
	526	case 0x4c: /* INTC_PROTECTION */
	527	/* TODO: Make a bitmap (or sizeof(char)map) of access privileges
	528	* for every register, see Chapter 3 and 4 for privileged mode. */
	529	if (value & 1)
	530	fprintf(stderr, "%s: protection mode enable attempt\n",
	531	__FUNCTION__);
	532	return;
	533
	534	case 0x50: /* INTC_IDLE */
	535	s->autoidle &= ~3;
	536	s->autoidle \|= value & 3;
	537	return;
	538
	539	/* Per-bank registers */
	540	case 0x84: /* INTC_MIR */
	541	bank->mask = value;
	542	omap_inth_update(s, 0);
	543	omap_inth_update(s, 1);
	544	return;
	545
	546	case 0x88: /* INTC_MIR_CLEAR */
	547	bank->mask &= ~value;
	548	omap_inth_update(s, 0);
	549	omap_inth_update(s, 1);
	550	return;
	551
	552	case 0x8c: /* INTC_MIR_SET */
	553	bank->mask \|= value;
	554	return;
	555
	556	case 0x90: /* INTC_ISR_SET */
	557	bank->irqs \|= bank->swi \|= value;
	558	omap_inth_update(s, 0);
	559	omap_inth_update(s, 1);
	560	return;
	561
	562	case 0x94: /* INTC_ISR_CLEAR */
	563	bank->swi &= ~value;
	564	bank->irqs = bank->swi & bank->inputs;
	565	return;
	566
	567	/* Per-line registers */
	568	case 0x100 ... 0x300: /* INTC_ILR */
	569	bank_no = (offset - 0x100) >> 7;
	570	if (bank_no > s->nbanks)
	571	break;
	572	bank = &s->bank[bank_no];
	573	line_no = (offset & 0x7f) >> 2;
574	bank->priority[line_no] = (value >> 2) & 0x3f;
575	bank->fiq &= ~(1 << line_no);
576	bank->fiq \|= (value & 1) << line_no;
577	return;
578
579	case 0x00: /* INTC_REVISION */
580	case 0x14: /* INTC_SYSSTATUS */
581	case 0x40: /* INTC_SIR_IRQ */
582	case 0x44: /* INTC_SIR_FIQ */
583	case 0x80: /* INTC_ITR */
584	case 0x98: /* INTC_PENDING_IRQ */
585	case 0x9c: /* INTC_PENDING_FIQ */
586	OMAP_RO_REG(addr);
587	return;
588	}
589	OMAP_BAD_REG(addr);
590	}
591
53bb614e PM	592	static const MemoryRegionOps omap2_inth_mem_ops = {
	593	.read = omap2_inth_read,
	594	.write = omap2_inth_write,
	595	.endianness = DEVICE_NATIVE_ENDIAN,
	596	.valid = {
	597	.min_access_size = 4,
	598	.max_access_size = 4,
	599	},
7f132a21	600	};
7f132a21	601
47edc5a4	602	static int omap2_intc_init(SysBusDevice *sbd)
7f132a21	603	{
47edc5a4 AF	604	DeviceState *dev = DEVICE(sbd);
	605	struct omap_intr_handler_s *s = OMAP_INTC(dev);
	606
0919ac78 PM	607	if (!s->iclk) {
	608	hw_error("omap2-intc: iclk not connected\n");
	609	}
	610	if (!s->fclk) {
	611	hw_error("omap2-intc: fclk not connected\n");
	612	}
7f132a21	613	s->level_only = 1;
0919ac78	614	s->nbanks = 3;
47edc5a4 AF	615	sysbus_init_irq(sbd, &s->parent_intr[0]);
	616	sysbus_init_irq(sbd, &s->parent_intr[1]);
	617	qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
1437c94b	618	memory_region_init_io(&s->mmio, OBJECT(s), &omap2_inth_mem_ops, s,
0919ac78	619	"omap2-intc", 0x1000);
47edc5a4	620	sysbus_init_mmio(sbd, &s->mmio);
0919ac78 PM	621	return 0;
0919ac78 PM	622	}
7f132a21	623
999e12bb AL	624	static Property omap2_intc_properties[] = {
	625	DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
	626	revision, 0x21),
	627	DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
	628	DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
	629	DEFINE_PROP_END_OF_LIST(),
	630	};
	631
	632	static void omap2_intc_class_init(ObjectClass klass, void data)
	633	{
39bffca2	634	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	635	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	636
	637	k->init = omap2_intc_init;
39bffca2 AL	638	dc->reset = omap_inth_reset;
39bffca2 AL	639	dc->props = omap2_intc_properties;
999e12bb AL	640	}
999e12bb AL	641
8c43a6f0	642	static const TypeInfo omap2_intc_info = {
39bffca2	643	.name = "omap2-intc",
47edc5a4 AF	644	.parent = TYPE_OMAP_INTC,
	645	.class_init = omap2_intc_class_init,
	646	};
	647
	648	static const TypeInfo omap_intc_type_info = {
	649	.name = TYPE_OMAP_INTC,
39bffca2 AL	650	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	651	.instance_size = sizeof(struct omap_intr_handler_s),
47edc5a4	652	.abstract = true,
0919ac78	653	};
7f132a21	654
83f7d43a	655	static void omap_intc_register_types(void)
0919ac78	656	{
47edc5a4	657	type_register_static(&omap_intc_type_info);
39bffca2 AL	658	type_register_static(&omap_intc_info);
39bffca2 AL	659	type_register_static(&omap2_intc_info);
7f132a21	660	}
0919ac78	661
83f7d43a	662	type_init(omap_intc_register_types)