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dbda808a FB |
1 | /* |
2 | * OpenPIC emulation | |
5fafdf24 | 3 | * |
dbda808a | 4 | * Copyright (c) 2004 Jocelyn Mayer |
704c7e5d | 5 | * 2011 Alexander Graf |
5fafdf24 | 6 | * |
dbda808a FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | /* | |
26 | * | |
27 | * Based on OpenPic implementations: | |
67b55785 | 28 | * - Intel GW80314 I/O companion chip developer's manual |
dbda808a FB |
29 | * - Motorola MPC8245 & MPC8540 user manuals. |
30 | * - Motorola MCP750 (aka Raven) programmer manual. | |
31 | * - Motorola Harrier programmer manuel | |
32 | * | |
33 | * Serial interrupts, as implemented in Raven chipset are not supported yet. | |
5fafdf24 | 34 | * |
dbda808a | 35 | */ |
83c9f4ca PB |
36 | #include "hw/hw.h" |
37 | #include "hw/ppc/mac.h" | |
38 | #include "hw/pci/pci.h" | |
0d09e41a | 39 | #include "hw/ppc/openpic.h" |
2b927571 | 40 | #include "hw/ppc/ppc_e500.h" |
83c9f4ca PB |
41 | #include "hw/sysbus.h" |
42 | #include "hw/pci/msi.h" | |
e69a17f6 | 43 | #include "qemu/bitops.h" |
dbda808a | 44 | |
611493d9 | 45 | //#define DEBUG_OPENPIC |
dbda808a FB |
46 | |
47 | #ifdef DEBUG_OPENPIC | |
4c4f0e48 | 48 | static const int debug_openpic = 1; |
dbda808a | 49 | #else |
4c4f0e48 | 50 | static const int debug_openpic = 0; |
dbda808a | 51 | #endif |
dbda808a | 52 | |
4c4f0e48 SW |
53 | #define DPRINTF(fmt, ...) do { \ |
54 | if (debug_openpic) { \ | |
55 | printf(fmt , ## __VA_ARGS__); \ | |
56 | } \ | |
57 | } while (0) | |
58 | ||
e0dfe5b1 | 59 | #define MAX_CPU 32 |
732aa6ec | 60 | #define MAX_MSI 8 |
dbda808a | 61 | #define VID 0x03 /* MPIC version ID */ |
dbda808a | 62 | |
d0b72631 | 63 | /* OpenPIC capability flags */ |
be7c236f | 64 | #define OPENPIC_FLAG_IDR_CRIT (1 << 0) |
e0dfe5b1 | 65 | #define OPENPIC_FLAG_ILR (2 << 0) |
dbda808a | 66 | |
d0b72631 | 67 | /* OpenPIC address map */ |
780d16b7 AG |
68 | #define OPENPIC_GLB_REG_START 0x0 |
69 | #define OPENPIC_GLB_REG_SIZE 0x10F0 | |
70 | #define OPENPIC_TMR_REG_START 0x10F0 | |
71 | #define OPENPIC_TMR_REG_SIZE 0x220 | |
732aa6ec AG |
72 | #define OPENPIC_MSI_REG_START 0x1600 |
73 | #define OPENPIC_MSI_REG_SIZE 0x200 | |
e0dfe5b1 SW |
74 | #define OPENPIC_SUMMARY_REG_START 0x3800 |
75 | #define OPENPIC_SUMMARY_REG_SIZE 0x800 | |
780d16b7 | 76 | #define OPENPIC_SRC_REG_START 0x10000 |
8935a442 | 77 | #define OPENPIC_SRC_REG_SIZE (OPENPIC_MAX_SRC * 0x20) |
780d16b7 AG |
78 | #define OPENPIC_CPU_REG_START 0x20000 |
79 | #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) | |
80 | ||
d0b72631 AG |
81 | /* Raven */ |
82 | #define RAVEN_MAX_CPU 2 | |
83 | #define RAVEN_MAX_EXT 48 | |
84 | #define RAVEN_MAX_IRQ 64 | |
8935a442 SW |
85 | #define RAVEN_MAX_TMR OPENPIC_MAX_TMR |
86 | #define RAVEN_MAX_IPI OPENPIC_MAX_IPI | |
d0b72631 AG |
87 | |
88 | /* Interrupt definitions */ | |
89 | #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ | |
90 | #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ | |
91 | #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ | |
92 | #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ | |
93 | /* First doorbell IRQ */ | |
94 | #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) | |
95 | ||
e0dfe5b1 SW |
96 | typedef struct FslMpicInfo { |
97 | int max_ext; | |
98 | } FslMpicInfo; | |
dbda808a | 99 | |
e0dfe5b1 SW |
100 | static FslMpicInfo fsl_mpic_20 = { |
101 | .max_ext = 12, | |
102 | }; | |
b7169916 | 103 | |
e0dfe5b1 SW |
104 | static FslMpicInfo fsl_mpic_42 = { |
105 | .max_ext = 12, | |
106 | }; | |
3e772232 | 107 | |
be7c236f SW |
108 | #define FRR_NIRQ_SHIFT 16 |
109 | #define FRR_NCPU_SHIFT 8 | |
110 | #define FRR_VID_SHIFT 0 | |
825463b3 AG |
111 | |
112 | #define VID_REVISION_1_2 2 | |
d0b72631 | 113 | #define VID_REVISION_1_3 3 |
825463b3 | 114 | |
be7c236f | 115 | #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ |
825463b3 | 116 | |
be7c236f | 117 | #define GCR_RESET 0x80000000 |
68c2dd70 AG |
118 | #define GCR_MODE_PASS 0x00000000 |
119 | #define GCR_MODE_MIXED 0x20000000 | |
120 | #define GCR_MODE_PROXY 0x60000000 | |
71c6cacb | 121 | |
be7c236f SW |
122 | #define TBCR_CI 0x80000000 /* count inhibit */ |
123 | #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ | |
825463b3 | 124 | |
1945dbc1 AG |
125 | #define IDR_EP_SHIFT 31 |
126 | #define IDR_EP_MASK (1 << IDR_EP_SHIFT) | |
127 | #define IDR_CI0_SHIFT 30 | |
128 | #define IDR_CI1_SHIFT 29 | |
129 | #define IDR_P1_SHIFT 1 | |
130 | #define IDR_P0_SHIFT 0 | |
b7169916 | 131 | |
e0dfe5b1 SW |
132 | #define ILR_INTTGT_MASK 0x000000ff |
133 | #define ILR_INTTGT_INT 0x00 | |
134 | #define ILR_INTTGT_CINT 0x01 /* critical */ | |
135 | #define ILR_INTTGT_MCP 0x02 /* machine check */ | |
136 | ||
137 | /* The currently supported INTTGT values happen to be the same as QEMU's | |
138 | * openpic output codes, but don't depend on this. The output codes | |
139 | * could change (unlikely, but...) or support could be added for | |
140 | * more INTTGT values. | |
141 | */ | |
142 | static const int inttgt_output[][2] = { | |
143 | { ILR_INTTGT_INT, OPENPIC_OUTPUT_INT }, | |
144 | { ILR_INTTGT_CINT, OPENPIC_OUTPUT_CINT }, | |
145 | { ILR_INTTGT_MCP, OPENPIC_OUTPUT_MCK }, | |
146 | }; | |
147 | ||
148 | static int inttgt_to_output(int inttgt) | |
149 | { | |
150 | int i; | |
151 | ||
152 | for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) { | |
153 | if (inttgt_output[i][0] == inttgt) { | |
154 | return inttgt_output[i][1]; | |
155 | } | |
156 | } | |
157 | ||
158 | fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt); | |
159 | return OPENPIC_OUTPUT_INT; | |
160 | } | |
161 | ||
162 | static int output_to_inttgt(int output) | |
163 | { | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) { | |
167 | if (inttgt_output[i][1] == output) { | |
168 | return inttgt_output[i][0]; | |
169 | } | |
170 | } | |
171 | ||
172 | abort(); | |
173 | } | |
174 | ||
732aa6ec AG |
175 | #define MSIIR_OFFSET 0x140 |
176 | #define MSIIR_SRS_SHIFT 29 | |
177 | #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT) | |
178 | #define MSIIR_IBS_SHIFT 24 | |
179 | #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT) | |
180 | ||
704c7e5d AG |
181 | static int get_current_cpu(void) |
182 | { | |
4917cf44 | 183 | if (!current_cpu) { |
c3203fa5 SW |
184 | return -1; |
185 | } | |
186 | ||
4917cf44 | 187 | return current_cpu->cpu_index; |
704c7e5d AG |
188 | } |
189 | ||
a8170e5e | 190 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 191 | int idx); |
a8170e5e | 192 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d AG |
193 | uint32_t val, int idx); |
194 | ||
6c5e84c2 SW |
195 | typedef enum IRQType { |
196 | IRQ_TYPE_NORMAL = 0, | |
197 | IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ | |
198 | IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ | |
199 | } IRQType; | |
200 | ||
af7e9e74 | 201 | typedef struct IRQQueue { |
e69a17f6 SW |
202 | /* Round up to the nearest 64 IRQs so that the queue length |
203 | * won't change when moving between 32 and 64 bit hosts. | |
204 | */ | |
8935a442 | 205 | unsigned long queue[BITS_TO_LONGS((OPENPIC_MAX_IRQ + 63) & ~63)]; |
dbda808a FB |
206 | int next; |
207 | int priority; | |
af7e9e74 | 208 | } IRQQueue; |
dbda808a | 209 | |
af7e9e74 | 210 | typedef struct IRQSource { |
be7c236f SW |
211 | uint32_t ivpr; /* IRQ vector/priority register */ |
212 | uint32_t idr; /* IRQ destination register */ | |
5e22c276 | 213 | uint32_t destmask; /* bitmap of CPU destinations */ |
dbda808a | 214 | int last_cpu; |
5e22c276 | 215 | int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ |
611493d9 | 216 | int pending; /* TRUE if IRQ is pending */ |
6c5e84c2 SW |
217 | IRQType type; |
218 | bool level:1; /* level-triggered */ | |
72c1da2c | 219 | bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ |
af7e9e74 | 220 | } IRQSource; |
dbda808a | 221 | |
be7c236f SW |
222 | #define IVPR_MASK_SHIFT 31 |
223 | #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) | |
224 | #define IVPR_ACTIVITY_SHIFT 30 | |
225 | #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT) | |
226 | #define IVPR_MODE_SHIFT 29 | |
227 | #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT) | |
228 | #define IVPR_POLARITY_SHIFT 23 | |
229 | #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT) | |
230 | #define IVPR_SENSE_SHIFT 22 | |
231 | #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT) | |
232 | ||
233 | #define IVPR_PRIORITY_MASK (0xF << 16) | |
234 | #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) | |
235 | #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) | |
236 | ||
237 | /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ | |
238 | #define IDR_EP 0x80000000 /* external pin */ | |
239 | #define IDR_CI 0x40000000 /* critical interrupt */ | |
71c6cacb | 240 | |
af7e9e74 | 241 | typedef struct IRQDest { |
eb438427 | 242 | int32_t ctpr; /* CPU current task priority */ |
af7e9e74 AG |
243 | IRQQueue raised; |
244 | IRQQueue servicing; | |
e9df014c | 245 | qemu_irq *irqs; |
9f1d4b1d SW |
246 | |
247 | /* Count of IRQ sources asserting on non-INT outputs */ | |
248 | uint32_t outputs_active[OPENPIC_OUTPUT_NB]; | |
af7e9e74 | 249 | } IRQDest; |
dbda808a | 250 | |
e1766344 AF |
251 | #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC) |
252 | ||
6d544ee8 | 253 | typedef struct OpenPICState { |
e1766344 AF |
254 | /*< private >*/ |
255 | SysBusDevice parent_obj; | |
256 | /*< public >*/ | |
257 | ||
23c5e4ca | 258 | MemoryRegion mem; |
71cf9e62 | 259 | |
5861a338 | 260 | /* Behavior control */ |
e0dfe5b1 | 261 | FslMpicInfo *fsl; |
d0b72631 | 262 | uint32_t model; |
5861a338 | 263 | uint32_t flags; |
825463b3 AG |
264 | uint32_t nb_irqs; |
265 | uint32_t vid; | |
be7c236f | 266 | uint32_t vir; /* Vendor identification register */ |
0fe04622 | 267 | uint32_t vector_mask; |
be7c236f SW |
268 | uint32_t tfrr_reset; |
269 | uint32_t ivpr_reset; | |
270 | uint32_t idr_reset; | |
dbbbfd60 | 271 | uint32_t brr1; |
68c2dd70 | 272 | uint32_t mpic_mode_mask; |
5861a338 | 273 | |
71cf9e62 | 274 | /* Sub-regions */ |
e0dfe5b1 | 275 | MemoryRegion sub_io_mem[6]; |
71cf9e62 | 276 | |
dbda808a | 277 | /* Global registers */ |
be7c236f SW |
278 | uint32_t frr; /* Feature reporting register */ |
279 | uint32_t gcr; /* Global configuration register */ | |
280 | uint32_t pir; /* Processor initialization register */ | |
dbda808a | 281 | uint32_t spve; /* Spurious vector register */ |
be7c236f | 282 | uint32_t tfrr; /* Timer frequency reporting register */ |
dbda808a | 283 | /* Source registers */ |
8935a442 | 284 | IRQSource src[OPENPIC_MAX_IRQ]; |
dbda808a | 285 | /* Local registers per output pin */ |
af7e9e74 | 286 | IRQDest dst[MAX_CPU]; |
d0b72631 | 287 | uint32_t nb_cpus; |
dbda808a FB |
288 | /* Timer registers */ |
289 | struct { | |
be7c236f SW |
290 | uint32_t tccr; /* Global timer current count register */ |
291 | uint32_t tbcr; /* Global timer base count register */ | |
8935a442 | 292 | } timers[OPENPIC_MAX_TMR]; |
732aa6ec AG |
293 | /* Shared MSI registers */ |
294 | struct { | |
295 | uint32_t msir; /* Shared Message Signaled Interrupt Register */ | |
296 | } msi[MAX_MSI]; | |
d0b72631 AG |
297 | uint32_t max_irq; |
298 | uint32_t irq_ipi0; | |
299 | uint32_t irq_tim0; | |
732aa6ec | 300 | uint32_t irq_msi; |
6d544ee8 | 301 | } OpenPICState; |
dbda808a | 302 | |
af7e9e74 | 303 | static inline void IRQ_setbit(IRQQueue *q, int n_IRQ) |
dbda808a | 304 | { |
e69a17f6 | 305 | set_bit(n_IRQ, q->queue); |
dbda808a FB |
306 | } |
307 | ||
af7e9e74 | 308 | static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ) |
dbda808a | 309 | { |
e69a17f6 | 310 | clear_bit(n_IRQ, q->queue); |
dbda808a FB |
311 | } |
312 | ||
af7e9e74 | 313 | static inline int IRQ_testbit(IRQQueue *q, int n_IRQ) |
dbda808a | 314 | { |
e69a17f6 | 315 | return test_bit(n_IRQ, q->queue); |
dbda808a FB |
316 | } |
317 | ||
af7e9e74 | 318 | static void IRQ_check(OpenPICState *opp, IRQQueue *q) |
dbda808a | 319 | { |
4417c733 SW |
320 | int irq = -1; |
321 | int next = -1; | |
322 | int priority = -1; | |
323 | ||
324 | for (;;) { | |
325 | irq = find_next_bit(q->queue, opp->max_irq, irq + 1); | |
326 | if (irq == opp->max_irq) { | |
327 | break; | |
328 | } | |
76aec1f8 | 329 | |
4417c733 SW |
330 | DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n", |
331 | irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); | |
76aec1f8 | 332 | |
4417c733 SW |
333 | if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { |
334 | next = irq; | |
335 | priority = IVPR_PRIORITY(opp->src[irq].ivpr); | |
060fbfe1 | 336 | } |
dbda808a | 337 | } |
76aec1f8 | 338 | |
dbda808a FB |
339 | q->next = next; |
340 | q->priority = priority; | |
341 | } | |
342 | ||
af7e9e74 | 343 | static int IRQ_get_next(OpenPICState *opp, IRQQueue *q) |
dbda808a | 344 | { |
3c94378e SW |
345 | /* XXX: optimize */ |
346 | IRQ_check(opp, q); | |
dbda808a FB |
347 | |
348 | return q->next; | |
349 | } | |
350 | ||
9f1d4b1d SW |
351 | static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, |
352 | bool active, bool was_active) | |
dbda808a | 353 | { |
af7e9e74 AG |
354 | IRQDest *dst; |
355 | IRQSource *src; | |
dbda808a FB |
356 | int priority; |
357 | ||
358 | dst = &opp->dst[n_CPU]; | |
359 | src = &opp->src[n_IRQ]; | |
5e22c276 | 360 | |
9f1d4b1d SW |
361 | DPRINTF("%s: IRQ %d active %d was %d\n", |
362 | __func__, n_IRQ, active, was_active); | |
363 | ||
5e22c276 | 364 | if (src->output != OPENPIC_OUTPUT_INT) { |
9f1d4b1d SW |
365 | DPRINTF("%s: output %d irq %d active %d was %d count %d\n", |
366 | __func__, src->output, n_IRQ, active, was_active, | |
367 | dst->outputs_active[src->output]); | |
368 | ||
5e22c276 SW |
369 | /* On Freescale MPIC, critical interrupts ignore priority, |
370 | * IACK, EOI, etc. Before MPIC v4.1 they also ignore | |
371 | * masking. | |
372 | */ | |
9f1d4b1d SW |
373 | if (active) { |
374 | if (!was_active && dst->outputs_active[src->output]++ == 0) { | |
375 | DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n", | |
376 | __func__, src->output, n_CPU, n_IRQ); | |
377 | qemu_irq_raise(dst->irqs[src->output]); | |
378 | } | |
379 | } else { | |
380 | if (was_active && --dst->outputs_active[src->output] == 0) { | |
381 | DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n", | |
382 | __func__, src->output, n_CPU, n_IRQ); | |
383 | qemu_irq_lower(dst->irqs[src->output]); | |
384 | } | |
385 | } | |
386 | ||
060fbfe1 | 387 | return; |
dbda808a | 388 | } |
5e22c276 | 389 | |
be7c236f | 390 | priority = IVPR_PRIORITY(src->ivpr); |
9f1d4b1d SW |
391 | |
392 | /* Even if the interrupt doesn't have enough priority, | |
393 | * it is still raised, in case ctpr is lowered later. | |
394 | */ | |
395 | if (active) { | |
396 | IRQ_setbit(&dst->raised, n_IRQ); | |
397 | } else { | |
398 | IRQ_resetbit(&dst->raised, n_IRQ); | |
dbda808a | 399 | } |
9f1d4b1d | 400 | |
3c94378e | 401 | IRQ_check(opp, &dst->raised); |
9f1d4b1d SW |
402 | |
403 | if (active && priority <= dst->ctpr) { | |
404 | DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", | |
405 | __func__, n_IRQ, priority, dst->ctpr, n_CPU); | |
406 | active = 0; | |
e9df014c | 407 | } |
9f1d4b1d SW |
408 | |
409 | if (active) { | |
410 | if (IRQ_get_next(opp, &dst->servicing) >= 0 && | |
411 | priority <= dst->servicing.priority) { | |
412 | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", | |
413 | __func__, n_IRQ, dst->servicing.next, n_CPU); | |
414 | } else { | |
415 | DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", | |
416 | __func__, n_CPU, n_IRQ, dst->raised.next); | |
417 | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); | |
418 | } | |
419 | } else { | |
420 | IRQ_get_next(opp, &dst->servicing); | |
421 | if (dst->raised.priority > dst->ctpr && | |
422 | dst->raised.priority > dst->servicing.priority) { | |
423 | DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n", | |
424 | __func__, n_IRQ, dst->raised.next, dst->raised.priority, | |
425 | dst->ctpr, dst->servicing.priority, n_CPU); | |
426 | /* IRQ line stays asserted */ | |
427 | } else { | |
428 | DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", | |
429 | __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU); | |
430 | qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); | |
431 | } | |
dbda808a FB |
432 | } |
433 | } | |
434 | ||
611493d9 | 435 | /* update pic state because registers for n_IRQ have changed value */ |
6d544ee8 | 436 | static void openpic_update_irq(OpenPICState *opp, int n_IRQ) |
dbda808a | 437 | { |
af7e9e74 | 438 | IRQSource *src; |
9f1d4b1d | 439 | bool active, was_active; |
dbda808a FB |
440 | int i; |
441 | ||
442 | src = &opp->src[n_IRQ]; | |
9f1d4b1d | 443 | active = src->pending; |
611493d9 | 444 | |
72c1da2c | 445 | if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { |
060fbfe1 | 446 | /* Interrupt source is disabled */ |
e9df014c | 447 | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); |
9f1d4b1d | 448 | active = false; |
dbda808a | 449 | } |
9f1d4b1d SW |
450 | |
451 | was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); | |
452 | ||
453 | /* | |
454 | * We don't have a similar check for already-active because | |
455 | * ctpr may have changed and we need to withdraw the interrupt. | |
456 | */ | |
457 | if (!active && !was_active) { | |
458 | DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ); | |
060fbfe1 | 459 | return; |
dbda808a | 460 | } |
9f1d4b1d SW |
461 | |
462 | if (active) { | |
463 | src->ivpr |= IVPR_ACTIVITY_MASK; | |
464 | } else { | |
465 | src->ivpr &= ~IVPR_ACTIVITY_MASK; | |
611493d9 | 466 | } |
9f1d4b1d | 467 | |
f40c360c | 468 | if (src->destmask == 0) { |
060fbfe1 | 469 | /* No target */ |
e9df014c | 470 | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); |
060fbfe1 | 471 | return; |
dbda808a | 472 | } |
611493d9 | 473 | |
f40c360c | 474 | if (src->destmask == (1 << src->last_cpu)) { |
e9df014c | 475 | /* Only one CPU is allowed to receive this IRQ */ |
9f1d4b1d | 476 | IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); |
be7c236f | 477 | } else if (!(src->ivpr & IVPR_MODE_MASK)) { |
611493d9 FB |
478 | /* Directed delivery mode */ |
479 | for (i = 0; i < opp->nb_cpus; i++) { | |
5e22c276 | 480 | if (src->destmask & (1 << i)) { |
9f1d4b1d | 481 | IRQ_local_pipe(opp, i, n_IRQ, active, was_active); |
1945dbc1 | 482 | } |
611493d9 | 483 | } |
dbda808a | 484 | } else { |
611493d9 | 485 | /* Distributed delivery mode */ |
e9df014c | 486 | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
af7e9e74 | 487 | if (i == opp->nb_cpus) { |
611493d9 | 488 | i = 0; |
af7e9e74 | 489 | } |
5e22c276 | 490 | if (src->destmask & (1 << i)) { |
9f1d4b1d | 491 | IRQ_local_pipe(opp, i, n_IRQ, active, was_active); |
611493d9 FB |
492 | src->last_cpu = i; |
493 | break; | |
494 | } | |
495 | } | |
496 | } | |
497 | } | |
498 | ||
d537cf6c | 499 | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
611493d9 | 500 | { |
6d544ee8 | 501 | OpenPICState *opp = opaque; |
af7e9e74 | 502 | IRQSource *src; |
611493d9 | 503 | |
8935a442 | 504 | if (n_IRQ >= OPENPIC_MAX_IRQ) { |
65b9d0d5 SW |
505 | fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ); |
506 | abort(); | |
507 | } | |
611493d9 FB |
508 | |
509 | src = &opp->src[n_IRQ]; | |
be7c236f SW |
510 | DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n", |
511 | n_IRQ, level, src->ivpr); | |
6c5e84c2 | 512 | if (src->level) { |
611493d9 FB |
513 | /* level-sensitive irq */ |
514 | src->pending = level; | |
9f1d4b1d | 515 | openpic_update_irq(opp, n_IRQ); |
611493d9 FB |
516 | } else { |
517 | /* edge-sensitive irq */ | |
af7e9e74 | 518 | if (level) { |
611493d9 | 519 | src->pending = 1; |
9f1d4b1d SW |
520 | openpic_update_irq(opp, n_IRQ); |
521 | } | |
522 | ||
523 | if (src->output != OPENPIC_OUTPUT_INT) { | |
524 | /* Edge-triggered interrupts shouldn't be used | |
525 | * with non-INT delivery, but just in case, | |
526 | * try to make it do something sane rather than | |
527 | * cause an interrupt storm. This is close to | |
528 | * what you'd probably see happen in real hardware. | |
529 | */ | |
530 | src->pending = 0; | |
531 | openpic_update_irq(opp, n_IRQ); | |
af7e9e74 | 532 | } |
dbda808a FB |
533 | } |
534 | } | |
535 | ||
d0b72631 | 536 | static void openpic_reset(DeviceState *d) |
dbda808a | 537 | { |
e1766344 | 538 | OpenPICState *opp = OPENPIC(d); |
dbda808a FB |
539 | int i; |
540 | ||
be7c236f | 541 | opp->gcr = GCR_RESET; |
f8407028 | 542 | /* Initialise controller registers */ |
be7c236f SW |
543 | opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) | |
544 | ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) | | |
545 | (opp->vid << FRR_VID_SHIFT); | |
825463b3 | 546 | |
be7c236f | 547 | opp->pir = 0; |
0fe04622 | 548 | opp->spve = -1 & opp->vector_mask; |
be7c236f | 549 | opp->tfrr = opp->tfrr_reset; |
dbda808a | 550 | /* Initialise IRQ sources */ |
b7169916 | 551 | for (i = 0; i < opp->max_irq; i++) { |
be7c236f SW |
552 | opp->src[i].ivpr = opp->ivpr_reset; |
553 | opp->src[i].idr = opp->idr_reset; | |
6c5e84c2 SW |
554 | |
555 | switch (opp->src[i].type) { | |
556 | case IRQ_TYPE_NORMAL: | |
557 | opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK); | |
558 | break; | |
559 | ||
560 | case IRQ_TYPE_FSLINT: | |
561 | opp->src[i].ivpr |= IVPR_POLARITY_MASK; | |
562 | break; | |
563 | ||
564 | case IRQ_TYPE_FSLSPECIAL: | |
565 | break; | |
566 | } | |
dbda808a FB |
567 | } |
568 | /* Initialise IRQ destinations */ | |
e9df014c | 569 | for (i = 0; i < MAX_CPU; i++) { |
be7c236f | 570 | opp->dst[i].ctpr = 15; |
af7e9e74 | 571 | memset(&opp->dst[i].raised, 0, sizeof(IRQQueue)); |
d14ed254 | 572 | opp->dst[i].raised.next = -1; |
af7e9e74 | 573 | memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue)); |
d14ed254 | 574 | opp->dst[i].servicing.next = -1; |
dbda808a FB |
575 | } |
576 | /* Initialise timers */ | |
8935a442 | 577 | for (i = 0; i < OPENPIC_MAX_TMR; i++) { |
be7c236f SW |
578 | opp->timers[i].tccr = 0; |
579 | opp->timers[i].tbcr = TBCR_CI; | |
dbda808a | 580 | } |
dbda808a | 581 | /* Go out of RESET state */ |
be7c236f | 582 | opp->gcr = 0; |
dbda808a FB |
583 | } |
584 | ||
be7c236f | 585 | static inline uint32_t read_IRQreg_idr(OpenPICState *opp, int n_IRQ) |
dbda808a | 586 | { |
be7c236f | 587 | return opp->src[n_IRQ].idr; |
8d3a8c1e | 588 | } |
dbda808a | 589 | |
e0dfe5b1 SW |
590 | static inline uint32_t read_IRQreg_ilr(OpenPICState *opp, int n_IRQ) |
591 | { | |
592 | if (opp->flags & OPENPIC_FLAG_ILR) { | |
593 | return output_to_inttgt(opp->src[n_IRQ].output); | |
594 | } | |
595 | ||
596 | return 0xffffffff; | |
597 | } | |
598 | ||
be7c236f | 599 | static inline uint32_t read_IRQreg_ivpr(OpenPICState *opp, int n_IRQ) |
8d3a8c1e | 600 | { |
be7c236f | 601 | return opp->src[n_IRQ].ivpr; |
dbda808a FB |
602 | } |
603 | ||
be7c236f | 604 | static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val) |
dbda808a | 605 | { |
5e22c276 SW |
606 | IRQSource *src = &opp->src[n_IRQ]; |
607 | uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; | |
608 | uint32_t crit_mask = 0; | |
609 | uint32_t mask = normal_mask; | |
610 | int crit_shift = IDR_EP_SHIFT - opp->nb_cpus; | |
611 | int i; | |
612 | ||
613 | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { | |
614 | crit_mask = mask << crit_shift; | |
615 | mask |= crit_mask | IDR_EP; | |
616 | } | |
617 | ||
618 | src->idr = val & mask; | |
619 | DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); | |
620 | ||
621 | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { | |
622 | if (src->idr & crit_mask) { | |
623 | if (src->idr & normal_mask) { | |
624 | DPRINTF("%s: IRQ configured for multiple output types, using " | |
625 | "critical\n", __func__); | |
626 | } | |
dbda808a | 627 | |
5e22c276 | 628 | src->output = OPENPIC_OUTPUT_CINT; |
72c1da2c | 629 | src->nomask = true; |
5e22c276 SW |
630 | src->destmask = 0; |
631 | ||
632 | for (i = 0; i < opp->nb_cpus; i++) { | |
633 | int n_ci = IDR_CI0_SHIFT - i; | |
dbda808a | 634 | |
5e22c276 SW |
635 | if (src->idr & (1UL << n_ci)) { |
636 | src->destmask |= 1UL << i; | |
637 | } | |
638 | } | |
639 | } else { | |
640 | src->output = OPENPIC_OUTPUT_INT; | |
72c1da2c | 641 | src->nomask = false; |
5e22c276 SW |
642 | src->destmask = src->idr & normal_mask; |
643 | } | |
644 | } else { | |
645 | src->destmask = src->idr; | |
646 | } | |
11de8b71 AG |
647 | } |
648 | ||
e0dfe5b1 SW |
649 | static inline void write_IRQreg_ilr(OpenPICState *opp, int n_IRQ, uint32_t val) |
650 | { | |
651 | if (opp->flags & OPENPIC_FLAG_ILR) { | |
652 | IRQSource *src = &opp->src[n_IRQ]; | |
653 | ||
654 | src->output = inttgt_to_output(val & ILR_INTTGT_MASK); | |
655 | DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, | |
656 | src->output); | |
657 | ||
658 | /* TODO: on MPIC v4.0 only, set nomask for non-INT */ | |
659 | } | |
660 | } | |
661 | ||
be7c236f | 662 | static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) |
11de8b71 | 663 | { |
6c5e84c2 SW |
664 | uint32_t mask; |
665 | ||
666 | /* NOTE when implementing newer FSL MPIC models: starting with v4.0, | |
667 | * the polarity bit is read-only on internal interrupts. | |
668 | */ | |
669 | mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK | | |
670 | IVPR_POLARITY_MASK | opp->vector_mask; | |
671 | ||
11de8b71 | 672 | /* ACTIVITY bit is read-only */ |
6c5e84c2 SW |
673 | opp->src[n_IRQ].ivpr = |
674 | (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); | |
675 | ||
676 | /* For FSL internal interrupts, The sense bit is reserved and zero, | |
677 | * and the interrupt is always level-triggered. Timers and IPIs | |
678 | * have no sense or polarity bits, and are edge-triggered. | |
679 | */ | |
680 | switch (opp->src[n_IRQ].type) { | |
681 | case IRQ_TYPE_NORMAL: | |
682 | opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); | |
683 | break; | |
684 | ||
685 | case IRQ_TYPE_FSLINT: | |
686 | opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; | |
687 | break; | |
688 | ||
689 | case IRQ_TYPE_FSLSPECIAL: | |
690 | opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); | |
691 | break; | |
692 | } | |
693 | ||
11de8b71 | 694 | openpic_update_irq(opp, n_IRQ); |
be7c236f SW |
695 | DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, |
696 | opp->src[n_IRQ].ivpr); | |
dbda808a FB |
697 | } |
698 | ||
7f11573b AG |
699 | static void openpic_gcr_write(OpenPICState *opp, uint64_t val) |
700 | { | |
e49798b1 | 701 | bool mpic_proxy = false; |
1ac3d713 | 702 | |
7f11573b | 703 | if (val & GCR_RESET) { |
e1766344 | 704 | openpic_reset(DEVICE(opp)); |
1ac3d713 AG |
705 | return; |
706 | } | |
7f11573b | 707 | |
1ac3d713 AG |
708 | opp->gcr &= ~opp->mpic_mode_mask; |
709 | opp->gcr |= val & opp->mpic_mode_mask; | |
7f11573b | 710 | |
1ac3d713 AG |
711 | /* Set external proxy mode */ |
712 | if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { | |
e49798b1 | 713 | mpic_proxy = true; |
7f11573b | 714 | } |
e49798b1 AG |
715 | |
716 | ppce500_set_mpic_proxy(mpic_proxy); | |
7f11573b AG |
717 | } |
718 | ||
b9b2aaa3 AG |
719 | static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, |
720 | unsigned len) | |
dbda808a | 721 | { |
6d544ee8 | 722 | OpenPICState *opp = opaque; |
af7e9e74 | 723 | IRQDest *dst; |
e9df014c | 724 | int idx; |
dbda808a | 725 | |
4c4f0e48 SW |
726 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
727 | __func__, addr, val); | |
af7e9e74 | 728 | if (addr & 0xF) { |
dbda808a | 729 | return; |
af7e9e74 | 730 | } |
dbda808a | 731 | switch (addr) { |
3e772232 BB |
732 | case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ |
733 | break; | |
704c7e5d AG |
734 | case 0x40: |
735 | case 0x50: | |
736 | case 0x60: | |
737 | case 0x70: | |
738 | case 0x80: | |
739 | case 0x90: | |
740 | case 0xA0: | |
741 | case 0xB0: | |
742 | openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); | |
dbda808a | 743 | break; |
be7c236f | 744 | case 0x1000: /* FRR */ |
dbda808a | 745 | break; |
be7c236f | 746 | case 0x1020: /* GCR */ |
7f11573b | 747 | openpic_gcr_write(opp, val); |
060fbfe1 | 748 | break; |
be7c236f | 749 | case 0x1080: /* VIR */ |
060fbfe1 | 750 | break; |
be7c236f | 751 | case 0x1090: /* PIR */ |
e9df014c | 752 | for (idx = 0; idx < opp->nb_cpus; idx++) { |
be7c236f | 753 | if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { |
e9df014c JM |
754 | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); |
755 | dst = &opp->dst[idx]; | |
756 | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
be7c236f | 757 | } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { |
e9df014c JM |
758 | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); |
759 | dst = &opp->dst[idx]; | |
760 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
761 | } | |
dbda808a | 762 | } |
be7c236f | 763 | opp->pir = val; |
060fbfe1 | 764 | break; |
be7c236f | 765 | case 0x10A0: /* IPI_IVPR */ |
704c7e5d AG |
766 | case 0x10B0: |
767 | case 0x10C0: | |
768 | case 0x10D0: | |
dbda808a FB |
769 | { |
770 | int idx; | |
704c7e5d | 771 | idx = (addr - 0x10A0) >> 4; |
be7c236f | 772 | write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); |
dbda808a FB |
773 | } |
774 | break; | |
704c7e5d | 775 | case 0x10E0: /* SPVE */ |
0fe04622 | 776 | opp->spve = val & opp->vector_mask; |
dbda808a | 777 | break; |
dbda808a FB |
778 | default: |
779 | break; | |
780 | } | |
781 | } | |
782 | ||
b9b2aaa3 | 783 | static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 784 | { |
6d544ee8 | 785 | OpenPICState *opp = opaque; |
dbda808a FB |
786 | uint32_t retval; |
787 | ||
4c4f0e48 | 788 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
dbda808a | 789 | retval = 0xFFFFFFFF; |
af7e9e74 | 790 | if (addr & 0xF) { |
dbda808a | 791 | return retval; |
af7e9e74 | 792 | } |
dbda808a | 793 | switch (addr) { |
be7c236f SW |
794 | case 0x1000: /* FRR */ |
795 | retval = opp->frr; | |
dbda808a | 796 | break; |
be7c236f SW |
797 | case 0x1020: /* GCR */ |
798 | retval = opp->gcr; | |
060fbfe1 | 799 | break; |
be7c236f SW |
800 | case 0x1080: /* VIR */ |
801 | retval = opp->vir; | |
060fbfe1 | 802 | break; |
be7c236f | 803 | case 0x1090: /* PIR */ |
dbda808a | 804 | retval = 0x00000000; |
060fbfe1 | 805 | break; |
3e772232 | 806 | case 0x00: /* Block Revision Register1 (BRR1) */ |
0d404683 SW |
807 | retval = opp->brr1; |
808 | break; | |
704c7e5d AG |
809 | case 0x40: |
810 | case 0x50: | |
811 | case 0x60: | |
812 | case 0x70: | |
813 | case 0x80: | |
814 | case 0x90: | |
815 | case 0xA0: | |
dbda808a | 816 | case 0xB0: |
704c7e5d AG |
817 | retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); |
818 | break; | |
be7c236f | 819 | case 0x10A0: /* IPI_IVPR */ |
704c7e5d AG |
820 | case 0x10B0: |
821 | case 0x10C0: | |
822 | case 0x10D0: | |
dbda808a FB |
823 | { |
824 | int idx; | |
704c7e5d | 825 | idx = (addr - 0x10A0) >> 4; |
be7c236f | 826 | retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx); |
dbda808a | 827 | } |
060fbfe1 | 828 | break; |
704c7e5d | 829 | case 0x10E0: /* SPVE */ |
dbda808a FB |
830 | retval = opp->spve; |
831 | break; | |
dbda808a FB |
832 | default: |
833 | break; | |
834 | } | |
4c4f0e48 | 835 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
836 | |
837 | return retval; | |
838 | } | |
839 | ||
6d544ee8 | 840 | static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, |
b9b2aaa3 | 841 | unsigned len) |
dbda808a | 842 | { |
6d544ee8 | 843 | OpenPICState *opp = opaque; |
dbda808a FB |
844 | int idx; |
845 | ||
03274d44 SW |
846 | addr += 0x10f0; |
847 | ||
4c4f0e48 SW |
848 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
849 | __func__, addr, val); | |
af7e9e74 | 850 | if (addr & 0xF) { |
dbda808a | 851 | return; |
af7e9e74 | 852 | } |
c38c0b8a | 853 | |
03274d44 | 854 | if (addr == 0x10f0) { |
be7c236f SW |
855 | /* TFRR */ |
856 | opp->tfrr = val; | |
c38c0b8a AG |
857 | return; |
858 | } | |
03274d44 SW |
859 | |
860 | idx = (addr >> 6) & 0x3; | |
861 | addr = addr & 0x30; | |
862 | ||
c38c0b8a | 863 | switch (addr & 0x30) { |
be7c236f | 864 | case 0x00: /* TCCR */ |
dbda808a | 865 | break; |
be7c236f SW |
866 | case 0x10: /* TBCR */ |
867 | if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && | |
868 | (val & TBCR_CI) == 0 && | |
869 | (opp->timers[idx].tbcr & TBCR_CI) != 0) { | |
870 | opp->timers[idx].tccr &= ~TCCR_TOG; | |
71c6cacb | 871 | } |
be7c236f | 872 | opp->timers[idx].tbcr = val; |
060fbfe1 | 873 | break; |
be7c236f SW |
874 | case 0x20: /* TVPR */ |
875 | write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val); | |
060fbfe1 | 876 | break; |
be7c236f SW |
877 | case 0x30: /* TDR */ |
878 | write_IRQreg_idr(opp, opp->irq_tim0 + idx, val); | |
060fbfe1 | 879 | break; |
dbda808a FB |
880 | } |
881 | } | |
882 | ||
6d544ee8 | 883 | static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 884 | { |
6d544ee8 | 885 | OpenPICState *opp = opaque; |
c38c0b8a | 886 | uint32_t retval = -1; |
dbda808a FB |
887 | int idx; |
888 | ||
4c4f0e48 | 889 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
c38c0b8a AG |
890 | if (addr & 0xF) { |
891 | goto out; | |
892 | } | |
893 | idx = (addr >> 6) & 0x3; | |
894 | if (addr == 0x0) { | |
be7c236f SW |
895 | /* TFRR */ |
896 | retval = opp->tfrr; | |
c38c0b8a AG |
897 | goto out; |
898 | } | |
899 | switch (addr & 0x30) { | |
be7c236f SW |
900 | case 0x00: /* TCCR */ |
901 | retval = opp->timers[idx].tccr; | |
dbda808a | 902 | break; |
be7c236f SW |
903 | case 0x10: /* TBCR */ |
904 | retval = opp->timers[idx].tbcr; | |
060fbfe1 | 905 | break; |
be7c236f SW |
906 | case 0x20: /* TIPV */ |
907 | retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); | |
060fbfe1 | 908 | break; |
c38c0b8a | 909 | case 0x30: /* TIDE (TIDR) */ |
be7c236f | 910 | retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx); |
060fbfe1 | 911 | break; |
dbda808a | 912 | } |
c38c0b8a AG |
913 | |
914 | out: | |
4c4f0e48 | 915 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
916 | |
917 | return retval; | |
918 | } | |
919 | ||
b9b2aaa3 AG |
920 | static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, |
921 | unsigned len) | |
dbda808a | 922 | { |
6d544ee8 | 923 | OpenPICState *opp = opaque; |
dbda808a FB |
924 | int idx; |
925 | ||
4c4f0e48 SW |
926 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
927 | __func__, addr, val); | |
e0dfe5b1 SW |
928 | |
929 | addr = addr & 0xffff; | |
dbda808a | 930 | idx = addr >> 5; |
e0dfe5b1 SW |
931 | |
932 | switch (addr & 0x1f) { | |
933 | case 0x00: | |
be7c236f | 934 | write_IRQreg_ivpr(opp, idx, val); |
e0dfe5b1 SW |
935 | break; |
936 | case 0x10: | |
937 | write_IRQreg_idr(opp, idx, val); | |
938 | break; | |
939 | case 0x18: | |
940 | write_IRQreg_ilr(opp, idx, val); | |
941 | break; | |
dbda808a FB |
942 | } |
943 | } | |
944 | ||
b9b2aaa3 | 945 | static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) |
dbda808a | 946 | { |
6d544ee8 | 947 | OpenPICState *opp = opaque; |
dbda808a FB |
948 | uint32_t retval; |
949 | int idx; | |
950 | ||
4c4f0e48 | 951 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
dbda808a | 952 | retval = 0xFFFFFFFF; |
e0dfe5b1 SW |
953 | |
954 | addr = addr & 0xffff; | |
dbda808a | 955 | idx = addr >> 5; |
e0dfe5b1 SW |
956 | |
957 | switch (addr & 0x1f) { | |
958 | case 0x00: | |
be7c236f | 959 | retval = read_IRQreg_ivpr(opp, idx); |
e0dfe5b1 SW |
960 | break; |
961 | case 0x10: | |
962 | retval = read_IRQreg_idr(opp, idx); | |
963 | break; | |
964 | case 0x18: | |
965 | retval = read_IRQreg_ilr(opp, idx); | |
966 | break; | |
dbda808a | 967 | } |
dbda808a | 968 | |
e0dfe5b1 | 969 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
970 | return retval; |
971 | } | |
972 | ||
732aa6ec AG |
973 | static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, |
974 | unsigned size) | |
975 | { | |
976 | OpenPICState *opp = opaque; | |
977 | int idx = opp->irq_msi; | |
978 | int srs, ibs; | |
979 | ||
4c4f0e48 SW |
980 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", |
981 | __func__, addr, val); | |
732aa6ec AG |
982 | if (addr & 0xF) { |
983 | return; | |
984 | } | |
985 | ||
986 | switch (addr) { | |
987 | case MSIIR_OFFSET: | |
988 | srs = val >> MSIIR_SRS_SHIFT; | |
989 | idx += srs; | |
990 | ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT; | |
991 | opp->msi[srs].msir |= 1 << ibs; | |
992 | openpic_set_irq(opp, idx, 1); | |
993 | break; | |
994 | default: | |
995 | /* most registers are read-only, thus ignored */ | |
996 | break; | |
997 | } | |
998 | } | |
999 | ||
1000 | static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) | |
1001 | { | |
1002 | OpenPICState *opp = opaque; | |
1003 | uint64_t r = 0; | |
1004 | int i, srs; | |
1005 | ||
4c4f0e48 | 1006 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
732aa6ec AG |
1007 | if (addr & 0xF) { |
1008 | return -1; | |
1009 | } | |
1010 | ||
1011 | srs = addr >> 4; | |
1012 | ||
1013 | switch (addr) { | |
1014 | case 0x00: | |
1015 | case 0x10: | |
1016 | case 0x20: | |
1017 | case 0x30: | |
1018 | case 0x40: | |
1019 | case 0x50: | |
1020 | case 0x60: | |
1021 | case 0x70: /* MSIRs */ | |
1022 | r = opp->msi[srs].msir; | |
1023 | /* Clear on read */ | |
1024 | opp->msi[srs].msir = 0; | |
e99fd8af | 1025 | openpic_set_irq(opp, opp->irq_msi + srs, 0); |
732aa6ec AG |
1026 | break; |
1027 | case 0x120: /* MSISR */ | |
1028 | for (i = 0; i < MAX_MSI; i++) { | |
1029 | r |= (opp->msi[i].msir ? 1 : 0) << i; | |
1030 | } | |
1031 | break; | |
1032 | } | |
1033 | ||
1034 | return r; | |
1035 | } | |
1036 | ||
e0dfe5b1 SW |
1037 | static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size) |
1038 | { | |
1039 | uint64_t r = 0; | |
1040 | ||
1041 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); | |
1042 | ||
1043 | /* TODO: EISR/EIMR */ | |
1044 | ||
1045 | return r; | |
1046 | } | |
1047 | ||
1048 | static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val, | |
1049 | unsigned size) | |
1050 | { | |
1051 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", | |
1052 | __func__, addr, val); | |
1053 | ||
1054 | /* TODO: EISR/EIMR */ | |
1055 | } | |
1056 | ||
a8170e5e | 1057 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d | 1058 | uint32_t val, int idx) |
dbda808a | 1059 | { |
6d544ee8 | 1060 | OpenPICState *opp = opaque; |
af7e9e74 AG |
1061 | IRQSource *src; |
1062 | IRQDest *dst; | |
704c7e5d | 1063 | int s_IRQ, n_IRQ; |
dbda808a | 1064 | |
4c4f0e48 | 1065 | DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx, |
704c7e5d | 1066 | addr, val); |
c3203fa5 SW |
1067 | |
1068 | if (idx < 0) { | |
dbda808a | 1069 | return; |
c3203fa5 SW |
1070 | } |
1071 | ||
af7e9e74 | 1072 | if (addr & 0xF) { |
dbda808a | 1073 | return; |
af7e9e74 | 1074 | } |
dbda808a FB |
1075 | dst = &opp->dst[idx]; |
1076 | addr &= 0xFF0; | |
1077 | switch (addr) { | |
704c7e5d | 1078 | case 0x40: /* IPIDR */ |
dbda808a FB |
1079 | case 0x50: |
1080 | case 0x60: | |
1081 | case 0x70: | |
1082 | idx = (addr - 0x40) >> 4; | |
a675155e | 1083 | /* we use IDE as mask which CPUs to deliver the IPI to still. */ |
f40c360c | 1084 | opp->src[opp->irq_ipi0 + idx].destmask |= val; |
b7169916 AJ |
1085 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); |
1086 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); | |
dbda808a | 1087 | break; |
be7c236f SW |
1088 | case 0x80: /* CTPR */ |
1089 | dst->ctpr = val & 0x0000000F; | |
9f1d4b1d SW |
1090 | |
1091 | DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", | |
1092 | __func__, idx, dst->ctpr, dst->raised.priority, | |
1093 | dst->servicing.priority); | |
1094 | ||
1095 | if (dst->raised.priority <= dst->ctpr) { | |
1096 | DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", | |
1097 | __func__, idx); | |
1098 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); | |
1099 | } else if (dst->raised.priority > dst->servicing.priority) { | |
1100 | DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n", | |
1101 | __func__, idx, dst->raised.next); | |
1102 | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); | |
1103 | } | |
1104 | ||
060fbfe1 | 1105 | break; |
dbda808a | 1106 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
1107 | /* Read-only register */ |
1108 | break; | |
be7c236f | 1109 | case 0xA0: /* IACK */ |
060fbfe1 AJ |
1110 | /* Read-only register */ |
1111 | break; | |
be7c236f SW |
1112 | case 0xB0: /* EOI */ |
1113 | DPRINTF("EOI\n"); | |
060fbfe1 | 1114 | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
65b9d0d5 SW |
1115 | |
1116 | if (s_IRQ < 0) { | |
1117 | DPRINTF("%s: EOI with no interrupt in service\n", __func__); | |
1118 | break; | |
1119 | } | |
1120 | ||
060fbfe1 | 1121 | IRQ_resetbit(&dst->servicing, s_IRQ); |
060fbfe1 AJ |
1122 | /* Set up next servicing IRQ */ |
1123 | s_IRQ = IRQ_get_next(opp, &dst->servicing); | |
e9df014c JM |
1124 | /* Check queued interrupts. */ |
1125 | n_IRQ = IRQ_get_next(opp, &dst->raised); | |
1126 | src = &opp->src[n_IRQ]; | |
1127 | if (n_IRQ != -1 && | |
1128 | (s_IRQ == -1 || | |
be7c236f | 1129 | IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { |
e9df014c JM |
1130 | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", |
1131 | idx, n_IRQ); | |
5e22c276 | 1132 | qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]); |
e9df014c | 1133 | } |
060fbfe1 | 1134 | break; |
dbda808a FB |
1135 | default: |
1136 | break; | |
1137 | } | |
1138 | } | |
1139 | ||
b9b2aaa3 AG |
1140 | static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, |
1141 | unsigned len) | |
704c7e5d AG |
1142 | { |
1143 | openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); | |
1144 | } | |
1145 | ||
a898a8fc SW |
1146 | |
1147 | static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu) | |
1148 | { | |
1149 | IRQSource *src; | |
1150 | int retval, irq; | |
1151 | ||
1152 | DPRINTF("Lower OpenPIC INT output\n"); | |
1153 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); | |
1154 | ||
1155 | irq = IRQ_get_next(opp, &dst->raised); | |
1156 | DPRINTF("IACK: irq=%d\n", irq); | |
1157 | ||
1158 | if (irq == -1) { | |
1159 | /* No more interrupt pending */ | |
1160 | return opp->spve; | |
1161 | } | |
1162 | ||
1163 | src = &opp->src[irq]; | |
1164 | if (!(src->ivpr & IVPR_ACTIVITY_MASK) || | |
1165 | !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { | |
9f1d4b1d SW |
1166 | fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", |
1167 | __func__, irq, dst->ctpr, src->ivpr); | |
1168 | openpic_update_irq(opp, irq); | |
a898a8fc SW |
1169 | retval = opp->spve; |
1170 | } else { | |
1171 | /* IRQ enter servicing state */ | |
1172 | IRQ_setbit(&dst->servicing, irq); | |
1173 | retval = IVPR_VECTOR(opp, src->ivpr); | |
1174 | } | |
9f1d4b1d | 1175 | |
a898a8fc SW |
1176 | if (!src->level) { |
1177 | /* edge-sensitive IRQ */ | |
1178 | src->ivpr &= ~IVPR_ACTIVITY_MASK; | |
1179 | src->pending = 0; | |
9f1d4b1d | 1180 | IRQ_resetbit(&dst->raised, irq); |
a898a8fc SW |
1181 | } |
1182 | ||
8935a442 | 1183 | if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + OPENPIC_MAX_IPI))) { |
f40c360c SW |
1184 | src->destmask &= ~(1 << cpu); |
1185 | if (src->destmask && !src->level) { | |
a898a8fc SW |
1186 | /* trigger on CPUs that didn't know about it yet */ |
1187 | openpic_set_irq(opp, irq, 1); | |
1188 | openpic_set_irq(opp, irq, 0); | |
1189 | /* if all CPUs knew about it, set active bit again */ | |
1190 | src->ivpr |= IVPR_ACTIVITY_MASK; | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | return retval; | |
1195 | } | |
1196 | ||
a8170e5e | 1197 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 1198 | int idx) |
dbda808a | 1199 | { |
6d544ee8 | 1200 | OpenPICState *opp = opaque; |
af7e9e74 | 1201 | IRQDest *dst; |
dbda808a | 1202 | uint32_t retval; |
3b46e624 | 1203 | |
4c4f0e48 | 1204 | DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); |
dbda808a | 1205 | retval = 0xFFFFFFFF; |
c3203fa5 SW |
1206 | |
1207 | if (idx < 0) { | |
1208 | return retval; | |
1209 | } | |
1210 | ||
af7e9e74 | 1211 | if (addr & 0xF) { |
dbda808a | 1212 | return retval; |
af7e9e74 | 1213 | } |
dbda808a FB |
1214 | dst = &opp->dst[idx]; |
1215 | addr &= 0xFF0; | |
1216 | switch (addr) { | |
be7c236f SW |
1217 | case 0x80: /* CTPR */ |
1218 | retval = dst->ctpr; | |
060fbfe1 | 1219 | break; |
dbda808a | 1220 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
1221 | retval = idx; |
1222 | break; | |
be7c236f | 1223 | case 0xA0: /* IACK */ |
a898a8fc | 1224 | retval = openpic_iack(opp, dst, idx); |
060fbfe1 | 1225 | break; |
be7c236f | 1226 | case 0xB0: /* EOI */ |
060fbfe1 AJ |
1227 | retval = 0; |
1228 | break; | |
dbda808a FB |
1229 | default: |
1230 | break; | |
1231 | } | |
4c4f0e48 | 1232 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
1233 | |
1234 | return retval; | |
1235 | } | |
1236 | ||
b9b2aaa3 | 1237 | static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) |
704c7e5d AG |
1238 | { |
1239 | return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); | |
1240 | } | |
1241 | ||
35732cb4 | 1242 | static const MemoryRegionOps openpic_glb_ops_le = { |
780d16b7 AG |
1243 | .write = openpic_gbl_write, |
1244 | .read = openpic_gbl_read, | |
1245 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1246 | .impl = { | |
1247 | .min_access_size = 4, | |
1248 | .max_access_size = 4, | |
1249 | }, | |
1250 | }; | |
dbda808a | 1251 | |
35732cb4 AG |
1252 | static const MemoryRegionOps openpic_glb_ops_be = { |
1253 | .write = openpic_gbl_write, | |
1254 | .read = openpic_gbl_read, | |
1255 | .endianness = DEVICE_BIG_ENDIAN, | |
1256 | .impl = { | |
1257 | .min_access_size = 4, | |
1258 | .max_access_size = 4, | |
1259 | }, | |
1260 | }; | |
1261 | ||
1262 | static const MemoryRegionOps openpic_tmr_ops_le = { | |
6d544ee8 AG |
1263 | .write = openpic_tmr_write, |
1264 | .read = openpic_tmr_read, | |
780d16b7 AG |
1265 | .endianness = DEVICE_LITTLE_ENDIAN, |
1266 | .impl = { | |
1267 | .min_access_size = 4, | |
1268 | .max_access_size = 4, | |
1269 | }, | |
1270 | }; | |
dbda808a | 1271 | |
35732cb4 | 1272 | static const MemoryRegionOps openpic_tmr_ops_be = { |
6d544ee8 AG |
1273 | .write = openpic_tmr_write, |
1274 | .read = openpic_tmr_read, | |
35732cb4 AG |
1275 | .endianness = DEVICE_BIG_ENDIAN, |
1276 | .impl = { | |
1277 | .min_access_size = 4, | |
1278 | .max_access_size = 4, | |
1279 | }, | |
1280 | }; | |
1281 | ||
1282 | static const MemoryRegionOps openpic_cpu_ops_le = { | |
780d16b7 AG |
1283 | .write = openpic_cpu_write, |
1284 | .read = openpic_cpu_read, | |
1285 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1286 | .impl = { | |
1287 | .min_access_size = 4, | |
1288 | .max_access_size = 4, | |
1289 | }, | |
1290 | }; | |
dbda808a | 1291 | |
35732cb4 AG |
1292 | static const MemoryRegionOps openpic_cpu_ops_be = { |
1293 | .write = openpic_cpu_write, | |
1294 | .read = openpic_cpu_read, | |
1295 | .endianness = DEVICE_BIG_ENDIAN, | |
1296 | .impl = { | |
1297 | .min_access_size = 4, | |
1298 | .max_access_size = 4, | |
1299 | }, | |
1300 | }; | |
1301 | ||
1302 | static const MemoryRegionOps openpic_src_ops_le = { | |
780d16b7 AG |
1303 | .write = openpic_src_write, |
1304 | .read = openpic_src_read, | |
23c5e4ca | 1305 | .endianness = DEVICE_LITTLE_ENDIAN, |
b9b2aaa3 AG |
1306 | .impl = { |
1307 | .min_access_size = 4, | |
1308 | .max_access_size = 4, | |
1309 | }, | |
23c5e4ca AK |
1310 | }; |
1311 | ||
35732cb4 AG |
1312 | static const MemoryRegionOps openpic_src_ops_be = { |
1313 | .write = openpic_src_write, | |
1314 | .read = openpic_src_read, | |
1315 | .endianness = DEVICE_BIG_ENDIAN, | |
1316 | .impl = { | |
1317 | .min_access_size = 4, | |
1318 | .max_access_size = 4, | |
1319 | }, | |
1320 | }; | |
1321 | ||
e0dfe5b1 | 1322 | static const MemoryRegionOps openpic_msi_ops_be = { |
732aa6ec AG |
1323 | .read = openpic_msi_read, |
1324 | .write = openpic_msi_write, | |
e0dfe5b1 | 1325 | .endianness = DEVICE_BIG_ENDIAN, |
732aa6ec AG |
1326 | .impl = { |
1327 | .min_access_size = 4, | |
1328 | .max_access_size = 4, | |
1329 | }, | |
1330 | }; | |
1331 | ||
e0dfe5b1 SW |
1332 | static const MemoryRegionOps openpic_summary_ops_be = { |
1333 | .read = openpic_summary_read, | |
1334 | .write = openpic_summary_write, | |
732aa6ec AG |
1335 | .endianness = DEVICE_BIG_ENDIAN, |
1336 | .impl = { | |
1337 | .min_access_size = 4, | |
1338 | .max_access_size = 4, | |
1339 | }, | |
1340 | }; | |
1341 | ||
af7e9e74 | 1342 | static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q) |
67b55785 BS |
1343 | { |
1344 | unsigned int i; | |
1345 | ||
e69a17f6 SW |
1346 | for (i = 0; i < ARRAY_SIZE(q->queue); i++) { |
1347 | /* Always put the lower half of a 64-bit long first, in case we | |
1348 | * restore on a 32-bit host. The least significant bits correspond | |
1349 | * to lower IRQ numbers in the bitmap. | |
1350 | */ | |
1351 | qemu_put_be32(f, (uint32_t)q->queue[i]); | |
1352 | #if LONG_MAX > 0x7FFFFFFF | |
1353 | qemu_put_be32(f, (uint32_t)(q->queue[i] >> 32)); | |
1354 | #endif | |
1355 | } | |
67b55785 BS |
1356 | |
1357 | qemu_put_sbe32s(f, &q->next); | |
1358 | qemu_put_sbe32s(f, &q->priority); | |
1359 | } | |
1360 | ||
1361 | static void openpic_save(QEMUFile* f, void *opaque) | |
1362 | { | |
6d544ee8 | 1363 | OpenPICState *opp = (OpenPICState *)opaque; |
67b55785 BS |
1364 | unsigned int i; |
1365 | ||
be7c236f SW |
1366 | qemu_put_be32s(f, &opp->gcr); |
1367 | qemu_put_be32s(f, &opp->vir); | |
1368 | qemu_put_be32s(f, &opp->pir); | |
67b55785 | 1369 | qemu_put_be32s(f, &opp->spve); |
be7c236f | 1370 | qemu_put_be32s(f, &opp->tfrr); |
67b55785 | 1371 | |
d0b72631 | 1372 | qemu_put_be32s(f, &opp->nb_cpus); |
b7169916 AJ |
1373 | |
1374 | for (i = 0; i < opp->nb_cpus; i++) { | |
eb438427 | 1375 | qemu_put_sbe32s(f, &opp->dst[i].ctpr); |
67b55785 BS |
1376 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1377 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); | |
9f1d4b1d SW |
1378 | qemu_put_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, |
1379 | sizeof(opp->dst[i].outputs_active)); | |
67b55785 BS |
1380 | } |
1381 | ||
8935a442 | 1382 | for (i = 0; i < OPENPIC_MAX_TMR; i++) { |
be7c236f SW |
1383 | qemu_put_be32s(f, &opp->timers[i].tccr); |
1384 | qemu_put_be32s(f, &opp->timers[i].tbcr); | |
67b55785 | 1385 | } |
5e22c276 SW |
1386 | |
1387 | for (i = 0; i < opp->max_irq; i++) { | |
1388 | qemu_put_be32s(f, &opp->src[i].ivpr); | |
1389 | qemu_put_be32s(f, &opp->src[i].idr); | |
f40c360c | 1390 | qemu_get_be32s(f, &opp->src[i].destmask); |
5e22c276 SW |
1391 | qemu_put_sbe32s(f, &opp->src[i].last_cpu); |
1392 | qemu_put_sbe32s(f, &opp->src[i].pending); | |
67b55785 | 1393 | } |
67b55785 BS |
1394 | } |
1395 | ||
af7e9e74 | 1396 | static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q) |
67b55785 BS |
1397 | { |
1398 | unsigned int i; | |
1399 | ||
e69a17f6 SW |
1400 | for (i = 0; i < ARRAY_SIZE(q->queue); i++) { |
1401 | unsigned long val; | |
1402 | ||
1403 | val = qemu_get_be32(f); | |
1404 | #if LONG_MAX > 0x7FFFFFFF | |
1405 | val <<= 32; | |
1406 | val |= qemu_get_be32(f); | |
1407 | #endif | |
1408 | ||
1409 | q->queue[i] = val; | |
1410 | } | |
67b55785 BS |
1411 | |
1412 | qemu_get_sbe32s(f, &q->next); | |
1413 | qemu_get_sbe32s(f, &q->priority); | |
1414 | } | |
1415 | ||
1416 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) | |
1417 | { | |
6d544ee8 | 1418 | OpenPICState *opp = (OpenPICState *)opaque; |
67b55785 BS |
1419 | unsigned int i; |
1420 | ||
af7e9e74 | 1421 | if (version_id != 1) { |
67b55785 | 1422 | return -EINVAL; |
af7e9e74 | 1423 | } |
67b55785 | 1424 | |
be7c236f SW |
1425 | qemu_get_be32s(f, &opp->gcr); |
1426 | qemu_get_be32s(f, &opp->vir); | |
1427 | qemu_get_be32s(f, &opp->pir); | |
67b55785 | 1428 | qemu_get_be32s(f, &opp->spve); |
be7c236f | 1429 | qemu_get_be32s(f, &opp->tfrr); |
67b55785 | 1430 | |
d0b72631 | 1431 | qemu_get_be32s(f, &opp->nb_cpus); |
b7169916 AJ |
1432 | |
1433 | for (i = 0; i < opp->nb_cpus; i++) { | |
eb438427 | 1434 | qemu_get_sbe32s(f, &opp->dst[i].ctpr); |
67b55785 BS |
1435 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1436 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); | |
9f1d4b1d SW |
1437 | qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, |
1438 | sizeof(opp->dst[i].outputs_active)); | |
67b55785 BS |
1439 | } |
1440 | ||
8935a442 | 1441 | for (i = 0; i < OPENPIC_MAX_TMR; i++) { |
be7c236f SW |
1442 | qemu_get_be32s(f, &opp->timers[i].tccr); |
1443 | qemu_get_be32s(f, &opp->timers[i].tbcr); | |
67b55785 BS |
1444 | } |
1445 | ||
5e22c276 SW |
1446 | for (i = 0; i < opp->max_irq; i++) { |
1447 | uint32_t val; | |
67b55785 | 1448 | |
5e22c276 SW |
1449 | val = qemu_get_be32(f); |
1450 | write_IRQreg_idr(opp, i, val); | |
1451 | val = qemu_get_be32(f); | |
1452 | write_IRQreg_ivpr(opp, i, val); | |
5861a338 | 1453 | |
5e22c276 SW |
1454 | qemu_get_be32s(f, &opp->src[i].ivpr); |
1455 | qemu_get_be32s(f, &opp->src[i].idr); | |
f40c360c | 1456 | qemu_get_be32s(f, &opp->src[i].destmask); |
5e22c276 SW |
1457 | qemu_get_sbe32s(f, &opp->src[i].last_cpu); |
1458 | qemu_get_sbe32s(f, &opp->src[i].pending); | |
5861a338 | 1459 | } |
5e22c276 SW |
1460 | |
1461 | return 0; | |
b7169916 AJ |
1462 | } |
1463 | ||
af7e9e74 | 1464 | typedef struct MemReg { |
d0b72631 AG |
1465 | const char *name; |
1466 | MemoryRegionOps const *ops; | |
1467 | hwaddr start_addr; | |
1468 | ram_addr_t size; | |
af7e9e74 | 1469 | } MemReg; |
d0b72631 | 1470 | |
e0dfe5b1 SW |
1471 | static void fsl_common_init(OpenPICState *opp) |
1472 | { | |
1473 | int i; | |
8935a442 | 1474 | int virq = OPENPIC_MAX_SRC; |
e0dfe5b1 SW |
1475 | |
1476 | opp->vid = VID_REVISION_1_2; | |
1477 | opp->vir = VIR_GENERIC; | |
1478 | opp->vector_mask = 0xFFFF; | |
1479 | opp->tfrr_reset = 0; | |
1480 | opp->ivpr_reset = IVPR_MASK_MASK; | |
1481 | opp->idr_reset = 1 << 0; | |
8935a442 | 1482 | opp->max_irq = OPENPIC_MAX_IRQ; |
e0dfe5b1 SW |
1483 | |
1484 | opp->irq_ipi0 = virq; | |
8935a442 | 1485 | virq += OPENPIC_MAX_IPI; |
e0dfe5b1 | 1486 | opp->irq_tim0 = virq; |
8935a442 | 1487 | virq += OPENPIC_MAX_TMR; |
e0dfe5b1 | 1488 | |
8935a442 | 1489 | assert(virq <= OPENPIC_MAX_IRQ); |
e0dfe5b1 SW |
1490 | |
1491 | opp->irq_msi = 224; | |
1492 | ||
1493 | msi_supported = true; | |
1494 | for (i = 0; i < opp->fsl->max_ext; i++) { | |
1495 | opp->src[i].level = false; | |
1496 | } | |
1497 | ||
1498 | /* Internal interrupts, including message and MSI */ | |
8935a442 | 1499 | for (i = 16; i < OPENPIC_MAX_SRC; i++) { |
e0dfe5b1 SW |
1500 | opp->src[i].type = IRQ_TYPE_FSLINT; |
1501 | opp->src[i].level = true; | |
1502 | } | |
1503 | ||
1504 | /* timers and IPIs */ | |
8935a442 | 1505 | for (i = OPENPIC_MAX_SRC; i < virq; i++) { |
e0dfe5b1 SW |
1506 | opp->src[i].type = IRQ_TYPE_FSLSPECIAL; |
1507 | opp->src[i].level = false; | |
1508 | } | |
1509 | } | |
1510 | ||
1511 | static void map_list(OpenPICState *opp, const MemReg *list, int *count) | |
1512 | { | |
1513 | while (list->name) { | |
1514 | assert(*count < ARRAY_SIZE(opp->sub_io_mem)); | |
1515 | ||
1437c94b PB |
1516 | memory_region_init_io(&opp->sub_io_mem[*count], OBJECT(opp), list->ops, |
1517 | opp, list->name, list->size); | |
e0dfe5b1 SW |
1518 | |
1519 | memory_region_add_subregion(&opp->mem, list->start_addr, | |
1520 | &opp->sub_io_mem[*count]); | |
1521 | ||
1522 | (*count)++; | |
1523 | list++; | |
1524 | } | |
1525 | } | |
1526 | ||
cbe72019 | 1527 | static void openpic_init(Object *obj) |
dbda808a | 1528 | { |
cbe72019 AF |
1529 | OpenPICState *opp = OPENPIC(obj); |
1530 | ||
1437c94b | 1531 | memory_region_init(&opp->mem, obj, "openpic", 0x40000); |
cbe72019 AF |
1532 | } |
1533 | ||
1534 | static void openpic_realize(DeviceState *dev, Error **errp) | |
1535 | { | |
1536 | SysBusDevice *d = SYS_BUS_DEVICE(dev); | |
e1766344 | 1537 | OpenPICState *opp = OPENPIC(dev); |
d0b72631 | 1538 | int i, j; |
e0dfe5b1 SW |
1539 | int list_count = 0; |
1540 | static const MemReg list_le[] = { | |
1541 | {"glb", &openpic_glb_ops_le, | |
732aa6ec | 1542 | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, |
e0dfe5b1 | 1543 | {"tmr", &openpic_tmr_ops_le, |
732aa6ec | 1544 | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, |
e0dfe5b1 | 1545 | {"src", &openpic_src_ops_le, |
732aa6ec | 1546 | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, |
e0dfe5b1 | 1547 | {"cpu", &openpic_cpu_ops_le, |
732aa6ec | 1548 | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, |
e0dfe5b1 | 1549 | {NULL} |
780d16b7 | 1550 | }; |
e0dfe5b1 SW |
1551 | static const MemReg list_be[] = { |
1552 | {"glb", &openpic_glb_ops_be, | |
732aa6ec | 1553 | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, |
e0dfe5b1 | 1554 | {"tmr", &openpic_tmr_ops_be, |
732aa6ec | 1555 | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, |
e0dfe5b1 | 1556 | {"src", &openpic_src_ops_be, |
732aa6ec | 1557 | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, |
e0dfe5b1 | 1558 | {"cpu", &openpic_cpu_ops_be, |
732aa6ec | 1559 | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, |
e0dfe5b1 | 1560 | {NULL} |
d0b72631 | 1561 | }; |
e0dfe5b1 SW |
1562 | static const MemReg list_fsl[] = { |
1563 | {"msi", &openpic_msi_ops_be, | |
1564 | OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, | |
1565 | {"summary", &openpic_summary_ops_be, | |
1566 | OPENPIC_SUMMARY_REG_START, OPENPIC_SUMMARY_REG_SIZE}, | |
1567 | {NULL} | |
1568 | }; | |
1569 | ||
d0b72631 AG |
1570 | switch (opp->model) { |
1571 | case OPENPIC_MODEL_FSL_MPIC_20: | |
1572 | default: | |
e0dfe5b1 SW |
1573 | opp->fsl = &fsl_mpic_20; |
1574 | opp->brr1 = 0x00400200; | |
be7c236f | 1575 | opp->flags |= OPENPIC_FLAG_IDR_CRIT; |
d0b72631 | 1576 | opp->nb_irqs = 80; |
e0dfe5b1 | 1577 | opp->mpic_mode_mask = GCR_MODE_MIXED; |
68c2dd70 | 1578 | |
e0dfe5b1 SW |
1579 | fsl_common_init(opp); |
1580 | map_list(opp, list_be, &list_count); | |
1581 | map_list(opp, list_fsl, &list_count); | |
6c5e84c2 | 1582 | |
e0dfe5b1 | 1583 | break; |
6c5e84c2 | 1584 | |
e0dfe5b1 SW |
1585 | case OPENPIC_MODEL_FSL_MPIC_42: |
1586 | opp->fsl = &fsl_mpic_42; | |
1587 | opp->brr1 = 0x00400402; | |
1588 | opp->flags |= OPENPIC_FLAG_ILR; | |
1589 | opp->nb_irqs = 196; | |
1590 | opp->mpic_mode_mask = GCR_MODE_PROXY; | |
6c5e84c2 | 1591 | |
e0dfe5b1 SW |
1592 | fsl_common_init(opp); |
1593 | map_list(opp, list_be, &list_count); | |
1594 | map_list(opp, list_fsl, &list_count); | |
6c5e84c2 | 1595 | |
d0b72631 | 1596 | break; |
6c5e84c2 | 1597 | |
d0b72631 AG |
1598 | case OPENPIC_MODEL_RAVEN: |
1599 | opp->nb_irqs = RAVEN_MAX_EXT; | |
1600 | opp->vid = VID_REVISION_1_3; | |
be7c236f | 1601 | opp->vir = VIR_GENERIC; |
0fe04622 | 1602 | opp->vector_mask = 0xFF; |
be7c236f SW |
1603 | opp->tfrr_reset = 4160000; |
1604 | opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK; | |
1605 | opp->idr_reset = 0; | |
d0b72631 AG |
1606 | opp->max_irq = RAVEN_MAX_IRQ; |
1607 | opp->irq_ipi0 = RAVEN_IPI_IRQ; | |
1608 | opp->irq_tim0 = RAVEN_TMR_IRQ; | |
dbbbfd60 | 1609 | opp->brr1 = -1; |
86e56a88 | 1610 | opp->mpic_mode_mask = GCR_MODE_MIXED; |
d0b72631 | 1611 | |
d0b72631 | 1612 | if (opp->nb_cpus != 1) { |
cbe72019 AF |
1613 | error_setg(errp, "Only UP supported today"); |
1614 | return; | |
d0b72631 | 1615 | } |
780d16b7 | 1616 | |
e0dfe5b1 SW |
1617 | map_list(opp, list_le, &list_count); |
1618 | break; | |
780d16b7 | 1619 | } |
3b46e624 | 1620 | |
d0b72631 AG |
1621 | for (i = 0; i < opp->nb_cpus; i++) { |
1622 | opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB); | |
1623 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
cbe72019 | 1624 | sysbus_init_irq(d, &opp->dst[i].irqs[j]); |
d0b72631 AG |
1625 | } |
1626 | } | |
1627 | ||
cbe72019 | 1628 | register_savevm(dev, "openpic", 0, 2, |
0be71e32 | 1629 | openpic_save, openpic_load, opp); |
b7169916 | 1630 | |
cbe72019 AF |
1631 | sysbus_init_mmio(d, &opp->mem); |
1632 | qdev_init_gpio_in(dev, openpic_set_irq, opp->max_irq); | |
b7169916 AJ |
1633 | } |
1634 | ||
d0b72631 AG |
1635 | static Property openpic_properties[] = { |
1636 | DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20), | |
1637 | DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1), | |
1638 | DEFINE_PROP_END_OF_LIST(), | |
1639 | }; | |
71cf9e62 | 1640 | |
cbe72019 | 1641 | static void openpic_class_init(ObjectClass *oc, void *data) |
d0b72631 | 1642 | { |
cbe72019 | 1643 | DeviceClass *dc = DEVICE_CLASS(oc); |
b7169916 | 1644 | |
cbe72019 | 1645 | dc->realize = openpic_realize; |
d0b72631 AG |
1646 | dc->props = openpic_properties; |
1647 | dc->reset = openpic_reset; | |
1648 | } | |
71cf9e62 | 1649 | |
8c43a6f0 | 1650 | static const TypeInfo openpic_info = { |
e1766344 | 1651 | .name = TYPE_OPENPIC, |
d0b72631 AG |
1652 | .parent = TYPE_SYS_BUS_DEVICE, |
1653 | .instance_size = sizeof(OpenPICState), | |
cbe72019 | 1654 | .instance_init = openpic_init, |
d0b72631 AG |
1655 | .class_init = openpic_class_init, |
1656 | }; | |
b7169916 | 1657 | |
d0b72631 AG |
1658 | static void openpic_register_types(void) |
1659 | { | |
1660 | type_register_static(&openpic_info); | |
dbda808a | 1661 | } |
d0b72631 AG |
1662 | |
1663 | type_init(openpic_register_types) |