]>
Commit | Line | Data |
---|---|---|
b5cec4c5 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics | |
5 | * | |
6 | * Copyright (c) 2010,2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
83c9f4ca | 28 | #include "hw/hw.h" |
500efa23 | 29 | #include "trace.h" |
0d09e41a PB |
30 | #include "hw/ppc/spapr.h" |
31 | #include "hw/ppc/xics.h" | |
9ccff2a4 | 32 | #include "qemu/error-report.h" |
b5cec4c5 | 33 | |
8ffe04ed AK |
34 | void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) |
35 | { | |
36 | CPUState *cs = CPU(cpu); | |
37 | CPUPPCState *env = &cpu->env; | |
38 | ICPState *ss = &icp->ss[cs->cpu_index]; | |
39 | ||
40 | assert(cs->cpu_index < icp->nr_servers); | |
41 | ||
42 | switch (PPC_INPUT(env)) { | |
43 | case PPC_FLAGS_INPUT_POWER7: | |
44 | ss->output = env->irq_inputs[POWER7_INPUT_INT]; | |
45 | break; | |
46 | ||
47 | case PPC_FLAGS_INPUT_970: | |
48 | ss->output = env->irq_inputs[PPC970_INPUT_INT]; | |
49 | break; | |
50 | ||
51 | default: | |
9ccff2a4 AK |
52 | error_report("XICS interrupt controller does not support this CPU " |
53 | "bus model"); | |
8ffe04ed AK |
54 | abort(); |
55 | } | |
56 | } | |
57 | ||
58 | static void xics_reset(DeviceState *d) | |
59 | { | |
60 | XICSState *icp = XICS(d); | |
61 | int i; | |
62 | ||
63 | for (i = 0; i < icp->nr_servers; i++) { | |
64 | device_reset(DEVICE(&icp->ss[i])); | |
65 | } | |
66 | ||
67 | device_reset(DEVICE(icp->ics)); | |
68 | } | |
69 | ||
b5cec4c5 DG |
70 | /* |
71 | * ICP: Presentation layer | |
72 | */ | |
73 | ||
b5cec4c5 DG |
74 | #define XISR_MASK 0x00ffffff |
75 | #define CPPR_MASK 0xff000000 | |
76 | ||
77 | #define XISR(ss) (((ss)->xirr) & XISR_MASK) | |
78 | #define CPPR(ss) (((ss)->xirr) >> 24) | |
79 | ||
c04d6cfa AL |
80 | static void ics_reject(ICSState *ics, int nr); |
81 | static void ics_resend(ICSState *ics); | |
82 | static void ics_eoi(ICSState *ics, int nr); | |
b5cec4c5 | 83 | |
c04d6cfa | 84 | static void icp_check_ipi(XICSState *icp, int server) |
b5cec4c5 | 85 | { |
c04d6cfa | 86 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
87 | |
88 | if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) { | |
89 | return; | |
90 | } | |
91 | ||
500efa23 DG |
92 | trace_xics_icp_check_ipi(server, ss->mfrr); |
93 | ||
b5cec4c5 DG |
94 | if (XISR(ss)) { |
95 | ics_reject(icp->ics, XISR(ss)); | |
96 | } | |
97 | ||
98 | ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI; | |
99 | ss->pending_priority = ss->mfrr; | |
100 | qemu_irq_raise(ss->output); | |
101 | } | |
102 | ||
c04d6cfa | 103 | static void icp_resend(XICSState *icp, int server) |
b5cec4c5 | 104 | { |
c04d6cfa | 105 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
106 | |
107 | if (ss->mfrr < CPPR(ss)) { | |
108 | icp_check_ipi(icp, server); | |
109 | } | |
110 | ics_resend(icp->ics); | |
111 | } | |
112 | ||
c04d6cfa | 113 | static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr) |
b5cec4c5 | 114 | { |
c04d6cfa | 115 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
116 | uint8_t old_cppr; |
117 | uint32_t old_xisr; | |
118 | ||
119 | old_cppr = CPPR(ss); | |
120 | ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24); | |
121 | ||
122 | if (cppr < old_cppr) { | |
123 | if (XISR(ss) && (cppr <= ss->pending_priority)) { | |
124 | old_xisr = XISR(ss); | |
125 | ss->xirr &= ~XISR_MASK; /* Clear XISR */ | |
e03c902c | 126 | ss->pending_priority = 0xff; |
b5cec4c5 DG |
127 | qemu_irq_lower(ss->output); |
128 | ics_reject(icp->ics, old_xisr); | |
129 | } | |
130 | } else { | |
131 | if (!XISR(ss)) { | |
132 | icp_resend(icp, server); | |
133 | } | |
134 | } | |
135 | } | |
136 | ||
c04d6cfa | 137 | static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr) |
b5cec4c5 | 138 | { |
c04d6cfa | 139 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
140 | |
141 | ss->mfrr = mfrr; | |
142 | if (mfrr < CPPR(ss)) { | |
bf0175de | 143 | icp_check_ipi(icp, server); |
b5cec4c5 DG |
144 | } |
145 | } | |
146 | ||
c04d6cfa | 147 | static uint32_t icp_accept(ICPState *ss) |
b5cec4c5 | 148 | { |
500efa23 | 149 | uint32_t xirr = ss->xirr; |
b5cec4c5 DG |
150 | |
151 | qemu_irq_lower(ss->output); | |
b5cec4c5 | 152 | ss->xirr = ss->pending_priority << 24; |
e03c902c | 153 | ss->pending_priority = 0xff; |
500efa23 DG |
154 | |
155 | trace_xics_icp_accept(xirr, ss->xirr); | |
156 | ||
b5cec4c5 DG |
157 | return xirr; |
158 | } | |
159 | ||
c04d6cfa | 160 | static void icp_eoi(XICSState *icp, int server, uint32_t xirr) |
b5cec4c5 | 161 | { |
c04d6cfa | 162 | ICPState *ss = icp->ss + server; |
b5cec4c5 | 163 | |
b5cec4c5 DG |
164 | /* Send EOI -> ICS */ |
165 | ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); | |
500efa23 | 166 | trace_xics_icp_eoi(server, xirr, ss->xirr); |
d07fee7e | 167 | ics_eoi(icp->ics, xirr & XISR_MASK); |
b5cec4c5 DG |
168 | if (!XISR(ss)) { |
169 | icp_resend(icp, server); | |
170 | } | |
171 | } | |
172 | ||
c04d6cfa | 173 | static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority) |
b5cec4c5 | 174 | { |
c04d6cfa | 175 | ICPState *ss = icp->ss + server; |
b5cec4c5 | 176 | |
500efa23 DG |
177 | trace_xics_icp_irq(server, nr, priority); |
178 | ||
b5cec4c5 DG |
179 | if ((priority >= CPPR(ss)) |
180 | || (XISR(ss) && (ss->pending_priority <= priority))) { | |
181 | ics_reject(icp->ics, nr); | |
182 | } else { | |
183 | if (XISR(ss)) { | |
184 | ics_reject(icp->ics, XISR(ss)); | |
185 | } | |
186 | ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK); | |
187 | ss->pending_priority = priority; | |
500efa23 | 188 | trace_xics_icp_raise(ss->xirr, ss->pending_priority); |
b5cec4c5 DG |
189 | qemu_irq_raise(ss->output); |
190 | } | |
191 | } | |
192 | ||
d1b5682d AK |
193 | static void icp_dispatch_pre_save(void *opaque) |
194 | { | |
195 | ICPState *ss = opaque; | |
196 | ICPStateClass *info = ICP_GET_CLASS(ss); | |
197 | ||
198 | if (info->pre_save) { | |
199 | info->pre_save(ss); | |
200 | } | |
201 | } | |
202 | ||
203 | static int icp_dispatch_post_load(void *opaque, int version_id) | |
204 | { | |
205 | ICPState *ss = opaque; | |
206 | ICPStateClass *info = ICP_GET_CLASS(ss); | |
207 | ||
208 | if (info->post_load) { | |
209 | return info->post_load(ss, version_id); | |
210 | } | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
c04d6cfa AL |
215 | static const VMStateDescription vmstate_icp_server = { |
216 | .name = "icp/server", | |
217 | .version_id = 1, | |
218 | .minimum_version_id = 1, | |
219 | .minimum_version_id_old = 1, | |
d1b5682d AK |
220 | .pre_save = icp_dispatch_pre_save, |
221 | .post_load = icp_dispatch_post_load, | |
c04d6cfa AL |
222 | .fields = (VMStateField []) { |
223 | /* Sanity check */ | |
224 | VMSTATE_UINT32(xirr, ICPState), | |
225 | VMSTATE_UINT8(pending_priority, ICPState), | |
226 | VMSTATE_UINT8(mfrr, ICPState), | |
227 | VMSTATE_END_OF_LIST() | |
228 | }, | |
b5cec4c5 DG |
229 | }; |
230 | ||
c04d6cfa AL |
231 | static void icp_reset(DeviceState *dev) |
232 | { | |
233 | ICPState *icp = ICP(dev); | |
234 | ||
235 | icp->xirr = 0; | |
236 | icp->pending_priority = 0xff; | |
237 | icp->mfrr = 0xff; | |
238 | ||
239 | /* Make all outputs are deasserted */ | |
240 | qemu_set_irq(icp->output, 0); | |
241 | } | |
242 | ||
243 | static void icp_class_init(ObjectClass *klass, void *data) | |
244 | { | |
245 | DeviceClass *dc = DEVICE_CLASS(klass); | |
246 | ||
247 | dc->reset = icp_reset; | |
248 | dc->vmsd = &vmstate_icp_server; | |
249 | } | |
250 | ||
251 | static TypeInfo icp_info = { | |
252 | .name = TYPE_ICP, | |
253 | .parent = TYPE_DEVICE, | |
254 | .instance_size = sizeof(ICPState), | |
255 | .class_init = icp_class_init, | |
d1b5682d | 256 | .class_size = sizeof(ICPStateClass), |
b5cec4c5 DG |
257 | }; |
258 | ||
c04d6cfa AL |
259 | /* |
260 | * ICS: Source layer | |
261 | */ | |
262 | static int ics_valid_irq(ICSState *ics, uint32_t nr) | |
b5cec4c5 DG |
263 | { |
264 | return (nr >= ics->offset) | |
265 | && (nr < (ics->offset + ics->nr_irqs)); | |
266 | } | |
267 | ||
c04d6cfa | 268 | static void resend_msi(ICSState *ics, int srcno) |
d07fee7e | 269 | { |
c04d6cfa | 270 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e DG |
271 | |
272 | /* FIXME: filter by server#? */ | |
98ca8c02 DG |
273 | if (irq->status & XICS_STATUS_REJECTED) { |
274 | irq->status &= ~XICS_STATUS_REJECTED; | |
d07fee7e DG |
275 | if (irq->priority != 0xff) { |
276 | icp_irq(ics->icp, irq->server, srcno + ics->offset, | |
277 | irq->priority); | |
278 | } | |
279 | } | |
280 | } | |
281 | ||
c04d6cfa | 282 | static void resend_lsi(ICSState *ics, int srcno) |
d07fee7e | 283 | { |
c04d6cfa | 284 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 285 | |
98ca8c02 DG |
286 | if ((irq->priority != 0xff) |
287 | && (irq->status & XICS_STATUS_ASSERTED) | |
288 | && !(irq->status & XICS_STATUS_SENT)) { | |
289 | irq->status |= XICS_STATUS_SENT; | |
d07fee7e DG |
290 | icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority); |
291 | } | |
292 | } | |
293 | ||
c04d6cfa | 294 | static void set_irq_msi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 295 | { |
c04d6cfa | 296 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 297 | |
500efa23 DG |
298 | trace_xics_set_irq_msi(srcno, srcno + ics->offset); |
299 | ||
b5cec4c5 DG |
300 | if (val) { |
301 | if (irq->priority == 0xff) { | |
98ca8c02 | 302 | irq->status |= XICS_STATUS_MASKED_PENDING; |
500efa23 | 303 | trace_xics_masked_pending(); |
b5cec4c5 | 304 | } else { |
cc67b9c8 | 305 | icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
306 | } |
307 | } | |
308 | } | |
309 | ||
c04d6cfa | 310 | static void set_irq_lsi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 311 | { |
c04d6cfa | 312 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 313 | |
500efa23 | 314 | trace_xics_set_irq_lsi(srcno, srcno + ics->offset); |
98ca8c02 DG |
315 | if (val) { |
316 | irq->status |= XICS_STATUS_ASSERTED; | |
317 | } else { | |
318 | irq->status &= ~XICS_STATUS_ASSERTED; | |
319 | } | |
d07fee7e | 320 | resend_lsi(ics, srcno); |
b5cec4c5 DG |
321 | } |
322 | ||
d07fee7e | 323 | static void ics_set_irq(void *opaque, int srcno, int val) |
b5cec4c5 | 324 | { |
c04d6cfa | 325 | ICSState *ics = (ICSState *)opaque; |
b5cec4c5 | 326 | |
22a2611c | 327 | if (ics->islsi[srcno]) { |
d07fee7e DG |
328 | set_irq_lsi(ics, srcno, val); |
329 | } else { | |
330 | set_irq_msi(ics, srcno, val); | |
331 | } | |
332 | } | |
b5cec4c5 | 333 | |
c04d6cfa | 334 | static void write_xive_msi(ICSState *ics, int srcno) |
d07fee7e | 335 | { |
c04d6cfa | 336 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 337 | |
98ca8c02 DG |
338 | if (!(irq->status & XICS_STATUS_MASKED_PENDING) |
339 | || (irq->priority == 0xff)) { | |
d07fee7e | 340 | return; |
b5cec4c5 | 341 | } |
d07fee7e | 342 | |
98ca8c02 | 343 | irq->status &= ~XICS_STATUS_MASKED_PENDING; |
d07fee7e | 344 | icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
345 | } |
346 | ||
c04d6cfa | 347 | static void write_xive_lsi(ICSState *ics, int srcno) |
b5cec4c5 | 348 | { |
d07fee7e DG |
349 | resend_lsi(ics, srcno); |
350 | } | |
351 | ||
c04d6cfa | 352 | static void ics_write_xive(ICSState *ics, int nr, int server, |
3fe719f4 | 353 | uint8_t priority, uint8_t saved_priority) |
d07fee7e DG |
354 | { |
355 | int srcno = nr - ics->offset; | |
c04d6cfa | 356 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 DG |
357 | |
358 | irq->server = server; | |
359 | irq->priority = priority; | |
3fe719f4 | 360 | irq->saved_priority = saved_priority; |
b5cec4c5 | 361 | |
500efa23 DG |
362 | trace_xics_ics_write_xive(nr, srcno, server, priority); |
363 | ||
22a2611c | 364 | if (ics->islsi[srcno]) { |
d07fee7e DG |
365 | write_xive_lsi(ics, srcno); |
366 | } else { | |
367 | write_xive_msi(ics, srcno); | |
b5cec4c5 | 368 | } |
b5cec4c5 DG |
369 | } |
370 | ||
c04d6cfa | 371 | static void ics_reject(ICSState *ics, int nr) |
b5cec4c5 | 372 | { |
c04d6cfa | 373 | ICSIRQState *irq = ics->irqs + nr - ics->offset; |
d07fee7e | 374 | |
500efa23 | 375 | trace_xics_ics_reject(nr, nr - ics->offset); |
98ca8c02 DG |
376 | irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */ |
377 | irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */ | |
b5cec4c5 DG |
378 | } |
379 | ||
c04d6cfa | 380 | static void ics_resend(ICSState *ics) |
b5cec4c5 | 381 | { |
d07fee7e DG |
382 | int i; |
383 | ||
384 | for (i = 0; i < ics->nr_irqs; i++) { | |
d07fee7e | 385 | /* FIXME: filter by server#? */ |
22a2611c | 386 | if (ics->islsi[i]) { |
d07fee7e DG |
387 | resend_lsi(ics, i); |
388 | } else { | |
389 | resend_msi(ics, i); | |
390 | } | |
391 | } | |
b5cec4c5 DG |
392 | } |
393 | ||
c04d6cfa | 394 | static void ics_eoi(ICSState *ics, int nr) |
b5cec4c5 | 395 | { |
d07fee7e | 396 | int srcno = nr - ics->offset; |
c04d6cfa | 397 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 398 | |
500efa23 DG |
399 | trace_xics_ics_eoi(nr); |
400 | ||
22a2611c | 401 | if (ics->islsi[srcno]) { |
98ca8c02 | 402 | irq->status &= ~XICS_STATUS_SENT; |
d07fee7e | 403 | } |
b5cec4c5 DG |
404 | } |
405 | ||
c04d6cfa AL |
406 | static void ics_reset(DeviceState *dev) |
407 | { | |
408 | ICSState *ics = ICS(dev); | |
409 | int i; | |
410 | ||
411 | memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); | |
412 | for (i = 0; i < ics->nr_irqs; i++) { | |
413 | ics->irqs[i].priority = 0xff; | |
414 | ics->irqs[i].saved_priority = 0xff; | |
415 | } | |
416 | } | |
417 | ||
d1b5682d | 418 | static int ics_post_load(ICSState *ics, int version_id) |
c04d6cfa AL |
419 | { |
420 | int i; | |
c04d6cfa AL |
421 | |
422 | for (i = 0; i < ics->icp->nr_servers; i++) { | |
423 | icp_resend(ics->icp, i); | |
424 | } | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
d1b5682d AK |
429 | static void ics_dispatch_pre_save(void *opaque) |
430 | { | |
431 | ICSState *ics = opaque; | |
432 | ICSStateClass *info = ICS_GET_CLASS(ics); | |
433 | ||
434 | if (info->pre_save) { | |
435 | info->pre_save(ics); | |
436 | } | |
437 | } | |
438 | ||
439 | static int ics_dispatch_post_load(void *opaque, int version_id) | |
440 | { | |
441 | ICSState *ics = opaque; | |
442 | ICSStateClass *info = ICS_GET_CLASS(ics); | |
443 | ||
444 | if (info->post_load) { | |
445 | return info->post_load(ics, version_id); | |
446 | } | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
c04d6cfa AL |
451 | static const VMStateDescription vmstate_ics_irq = { |
452 | .name = "ics/irq", | |
453 | .version_id = 1, | |
454 | .minimum_version_id = 1, | |
455 | .minimum_version_id_old = 1, | |
456 | .fields = (VMStateField []) { | |
457 | VMSTATE_UINT32(server, ICSIRQState), | |
458 | VMSTATE_UINT8(priority, ICSIRQState), | |
459 | VMSTATE_UINT8(saved_priority, ICSIRQState), | |
460 | VMSTATE_UINT8(status, ICSIRQState), | |
461 | VMSTATE_END_OF_LIST() | |
462 | }, | |
463 | }; | |
464 | ||
465 | static const VMStateDescription vmstate_ics = { | |
466 | .name = "ics", | |
467 | .version_id = 1, | |
468 | .minimum_version_id = 1, | |
469 | .minimum_version_id_old = 1, | |
d1b5682d AK |
470 | .pre_save = ics_dispatch_pre_save, |
471 | .post_load = ics_dispatch_post_load, | |
c04d6cfa AL |
472 | .fields = (VMStateField []) { |
473 | /* Sanity check */ | |
474 | VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), | |
475 | ||
476 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, | |
477 | vmstate_ics_irq, ICSIRQState), | |
478 | VMSTATE_END_OF_LIST() | |
479 | }, | |
480 | }; | |
481 | ||
482 | static int ics_realize(DeviceState *dev) | |
483 | { | |
484 | ICSState *ics = ICS(dev); | |
485 | ||
486 | ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); | |
487 | ics->islsi = g_malloc0(ics->nr_irqs * sizeof(bool)); | |
488 | ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static void ics_class_init(ObjectClass *klass, void *data) | |
494 | { | |
495 | DeviceClass *dc = DEVICE_CLASS(klass); | |
d1b5682d | 496 | ICSStateClass *isc = ICS_CLASS(klass); |
c04d6cfa AL |
497 | |
498 | dc->init = ics_realize; | |
499 | dc->vmsd = &vmstate_ics; | |
500 | dc->reset = ics_reset; | |
d1b5682d | 501 | isc->post_load = ics_post_load; |
c04d6cfa AL |
502 | } |
503 | ||
504 | static TypeInfo ics_info = { | |
505 | .name = TYPE_ICS, | |
506 | .parent = TYPE_DEVICE, | |
507 | .instance_size = sizeof(ICSState), | |
508 | .class_init = ics_class_init, | |
d1b5682d | 509 | .class_size = sizeof(ICSStateClass), |
c04d6cfa AL |
510 | }; |
511 | ||
b5cec4c5 DG |
512 | /* |
513 | * Exported functions | |
514 | */ | |
515 | ||
c04d6cfa | 516 | qemu_irq xics_get_qirq(XICSState *icp, int irq) |
b5cec4c5 | 517 | { |
1ecbbab4 | 518 | if (!ics_valid_irq(icp->ics, irq)) { |
b5cec4c5 DG |
519 | return NULL; |
520 | } | |
521 | ||
a307d594 AK |
522 | return icp->ics->qirqs[irq - icp->ics->offset]; |
523 | } | |
524 | ||
c04d6cfa | 525 | void xics_set_irq_type(XICSState *icp, int irq, bool lsi) |
a307d594 | 526 | { |
1ecbbab4 | 527 | assert(ics_valid_irq(icp->ics, irq)); |
d07fee7e | 528 | |
22a2611c | 529 | icp->ics->islsi[irq - icp->ics->offset] = lsi; |
b5cec4c5 DG |
530 | } |
531 | ||
c04d6cfa AL |
532 | /* |
533 | * Guest interfaces | |
534 | */ | |
535 | ||
b13ce26d | 536 | static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
b5cec4c5 DG |
537 | target_ulong opcode, target_ulong *args) |
538 | { | |
55e5c285 | 539 | CPUState *cs = CPU(cpu); |
b5cec4c5 DG |
540 | target_ulong cppr = args[0]; |
541 | ||
55e5c285 | 542 | icp_set_cppr(spapr->icp, cs->cpu_index, cppr); |
b5cec4c5 DG |
543 | return H_SUCCESS; |
544 | } | |
545 | ||
b13ce26d | 546 | static target_ulong h_ipi(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
b5cec4c5 DG |
547 | target_ulong opcode, target_ulong *args) |
548 | { | |
549 | target_ulong server = args[0]; | |
550 | target_ulong mfrr = args[1]; | |
551 | ||
552 | if (server >= spapr->icp->nr_servers) { | |
553 | return H_PARAMETER; | |
554 | } | |
555 | ||
556 | icp_set_mfrr(spapr->icp, server, mfrr); | |
557 | return H_SUCCESS; | |
b5cec4c5 DG |
558 | } |
559 | ||
b13ce26d | 560 | static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
b5cec4c5 DG |
561 | target_ulong opcode, target_ulong *args) |
562 | { | |
55e5c285 AF |
563 | CPUState *cs = CPU(cpu); |
564 | uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index); | |
b5cec4c5 DG |
565 | |
566 | args[0] = xirr; | |
567 | return H_SUCCESS; | |
568 | } | |
569 | ||
b13ce26d | 570 | static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
b5cec4c5 DG |
571 | target_ulong opcode, target_ulong *args) |
572 | { | |
55e5c285 | 573 | CPUState *cs = CPU(cpu); |
b5cec4c5 DG |
574 | target_ulong xirr = args[0]; |
575 | ||
55e5c285 | 576 | icp_eoi(spapr->icp, cs->cpu_index, xirr); |
b5cec4c5 DG |
577 | return H_SUCCESS; |
578 | } | |
579 | ||
210b580b AL |
580 | static void rtas_set_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
581 | uint32_t token, | |
b5cec4c5 DG |
582 | uint32_t nargs, target_ulong args, |
583 | uint32_t nret, target_ulong rets) | |
584 | { | |
c04d6cfa | 585 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
586 | uint32_t nr, server, priority; |
587 | ||
588 | if ((nargs != 3) || (nret != 1)) { | |
589 | rtas_st(rets, 0, -3); | |
590 | return; | |
591 | } | |
592 | ||
593 | nr = rtas_ld(args, 0); | |
594 | server = rtas_ld(args, 1); | |
595 | priority = rtas_ld(args, 2); | |
596 | ||
597 | if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers) | |
598 | || (priority > 0xff)) { | |
599 | rtas_st(rets, 0, -3); | |
600 | return; | |
601 | } | |
602 | ||
3fe719f4 | 603 | ics_write_xive(ics, nr, server, priority, priority); |
b5cec4c5 DG |
604 | |
605 | rtas_st(rets, 0, 0); /* Success */ | |
606 | } | |
607 | ||
210b580b AL |
608 | static void rtas_get_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
609 | uint32_t token, | |
b5cec4c5 DG |
610 | uint32_t nargs, target_ulong args, |
611 | uint32_t nret, target_ulong rets) | |
612 | { | |
c04d6cfa | 613 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
614 | uint32_t nr; |
615 | ||
616 | if ((nargs != 1) || (nret != 3)) { | |
617 | rtas_st(rets, 0, -3); | |
618 | return; | |
619 | } | |
620 | ||
621 | nr = rtas_ld(args, 0); | |
622 | ||
623 | if (!ics_valid_irq(ics, nr)) { | |
624 | rtas_st(rets, 0, -3); | |
625 | return; | |
626 | } | |
627 | ||
628 | rtas_st(rets, 0, 0); /* Success */ | |
629 | rtas_st(rets, 1, ics->irqs[nr - ics->offset].server); | |
630 | rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority); | |
631 | } | |
632 | ||
210b580b AL |
633 | static void rtas_int_off(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
634 | uint32_t token, | |
b5cec4c5 DG |
635 | uint32_t nargs, target_ulong args, |
636 | uint32_t nret, target_ulong rets) | |
637 | { | |
c04d6cfa | 638 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
639 | uint32_t nr; |
640 | ||
641 | if ((nargs != 1) || (nret != 1)) { | |
642 | rtas_st(rets, 0, -3); | |
643 | return; | |
644 | } | |
645 | ||
646 | nr = rtas_ld(args, 0); | |
647 | ||
648 | if (!ics_valid_irq(ics, nr)) { | |
649 | rtas_st(rets, 0, -3); | |
650 | return; | |
651 | } | |
652 | ||
3fe719f4 DG |
653 | ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff, |
654 | ics->irqs[nr - ics->offset].priority); | |
b5cec4c5 DG |
655 | |
656 | rtas_st(rets, 0, 0); /* Success */ | |
657 | } | |
658 | ||
210b580b AL |
659 | static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
660 | uint32_t token, | |
b5cec4c5 DG |
661 | uint32_t nargs, target_ulong args, |
662 | uint32_t nret, target_ulong rets) | |
663 | { | |
c04d6cfa | 664 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
665 | uint32_t nr; |
666 | ||
667 | if ((nargs != 1) || (nret != 1)) { | |
668 | rtas_st(rets, 0, -3); | |
669 | return; | |
670 | } | |
671 | ||
672 | nr = rtas_ld(args, 0); | |
673 | ||
674 | if (!ics_valid_irq(ics, nr)) { | |
675 | rtas_st(rets, 0, -3); | |
676 | return; | |
677 | } | |
678 | ||
3fe719f4 DG |
679 | ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, |
680 | ics->irqs[nr - ics->offset].saved_priority, | |
681 | ics->irqs[nr - ics->offset].saved_priority); | |
b5cec4c5 DG |
682 | |
683 | rtas_st(rets, 0, 0); /* Success */ | |
684 | } | |
685 | ||
c04d6cfa AL |
686 | /* |
687 | * XICS | |
688 | */ | |
689 | ||
c04d6cfa | 690 | static void xics_realize(DeviceState *dev, Error **errp) |
7b565160 | 691 | { |
c04d6cfa AL |
692 | XICSState *icp = XICS(dev); |
693 | ICSState *ics = icp->ics; | |
694 | int i; | |
b5cec4c5 | 695 | |
33a0e5d8 AK |
696 | /* Registration of global state belongs into realize */ |
697 | spapr_rtas_register("ibm,set-xive", rtas_set_xive); | |
698 | spapr_rtas_register("ibm,get-xive", rtas_get_xive); | |
699 | spapr_rtas_register("ibm,int-off", rtas_int_off); | |
700 | spapr_rtas_register("ibm,int-on", rtas_int_on); | |
701 | ||
702 | spapr_register_hypercall(H_CPPR, h_cppr); | |
703 | spapr_register_hypercall(H_IPI, h_ipi); | |
704 | spapr_register_hypercall(H_XIRR, h_xirr); | |
705 | spapr_register_hypercall(H_EOI, h_eoi); | |
706 | ||
c04d6cfa | 707 | ics->nr_irqs = icp->nr_irqs; |
bf3bc4c4 | 708 | ics->offset = XICS_IRQ_BASE; |
b5cec4c5 | 709 | ics->icp = icp; |
c04d6cfa | 710 | qdev_init_nofail(DEVICE(ics)); |
b5cec4c5 | 711 | |
c04d6cfa AL |
712 | icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState)); |
713 | for (i = 0; i < icp->nr_servers; i++) { | |
714 | char buffer[32]; | |
213f0c4f | 715 | object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); |
c04d6cfa AL |
716 | snprintf(buffer, sizeof(buffer), "icp[%d]", i); |
717 | object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), NULL); | |
718 | qdev_init_nofail(DEVICE(&icp->ss[i])); | |
719 | } | |
720 | } | |
b5cec4c5 | 721 | |
c04d6cfa AL |
722 | static void xics_initfn(Object *obj) |
723 | { | |
724 | XICSState *xics = XICS(obj); | |
725 | ||
726 | xics->ics = ICS(object_new(TYPE_ICS)); | |
727 | object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); | |
728 | } | |
729 | ||
730 | static Property xics_properties[] = { | |
731 | DEFINE_PROP_UINT32("nr_servers", XICSState, nr_servers, -1), | |
732 | DEFINE_PROP_UINT32("nr_irqs", XICSState, nr_irqs, -1), | |
733 | DEFINE_PROP_END_OF_LIST(), | |
734 | }; | |
735 | ||
736 | static void xics_class_init(ObjectClass *oc, void *data) | |
737 | { | |
738 | DeviceClass *dc = DEVICE_CLASS(oc); | |
739 | ||
740 | dc->realize = xics_realize; | |
741 | dc->props = xics_properties; | |
742 | dc->reset = xics_reset; | |
c04d6cfa AL |
743 | } |
744 | ||
745 | static const TypeInfo xics_info = { | |
746 | .name = TYPE_XICS, | |
747 | .parent = TYPE_SYS_BUS_DEVICE, | |
748 | .instance_size = sizeof(XICSState), | |
749 | .class_init = xics_class_init, | |
750 | .instance_init = xics_initfn, | |
751 | }; | |
256b408a | 752 | |
c04d6cfa AL |
753 | static void xics_register_types(void) |
754 | { | |
755 | type_register_static(&xics_info); | |
756 | type_register_static(&ics_info); | |
757 | type_register_static(&icp_info); | |
b5cec4c5 | 758 | } |
c04d6cfa AL |
759 | |
760 | type_init(xics_register_types) |