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Commit | Line | Data |
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5fafdf24 | 1 | /* |
b5ff1b31 FB |
2 | * ARM Integrator CP System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2005-2007 CodeSourcery. |
b5ff1b31 FB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This code is licenced under the GPL | |
8 | */ | |
9 | ||
2e9bdce5 | 10 | #include "sysbus.h" |
87ecb68b PB |
11 | #include "primecell.h" |
12 | #include "devices.h" | |
13 | #include "sysemu.h" | |
14 | #include "boards.h" | |
15 | #include "arm-misc.h" | |
16 | #include "net.h" | |
b5ff1b31 | 17 | |
b5ff1b31 | 18 | typedef struct { |
a7086888 | 19 | SysBusDevice busdev; |
ee6847d1 | 20 | uint32_t memsz; |
b5ff1b31 FB |
21 | uint32_t flash_offset; |
22 | uint32_t cm_osc; | |
23 | uint32_t cm_ctrl; | |
24 | uint32_t cm_lock; | |
25 | uint32_t cm_auxosc; | |
26 | uint32_t cm_sdram; | |
27 | uint32_t cm_init; | |
28 | uint32_t cm_flags; | |
29 | uint32_t cm_nvflags; | |
30 | uint32_t int_level; | |
31 | uint32_t irq_enabled; | |
32 | uint32_t fiq_enabled; | |
33 | } integratorcm_state; | |
34 | ||
35 | static uint8_t integrator_spd[128] = { | |
36 | 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, | |
37 | 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 | |
38 | }; | |
39 | ||
40 | static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) | |
41 | { | |
42 | integratorcm_state *s = (integratorcm_state *)opaque; | |
b5ff1b31 FB |
43 | if (offset >= 0x100 && offset < 0x200) { |
44 | /* CM_SPD */ | |
45 | if (offset >= 0x180) | |
46 | return 0; | |
47 | return integrator_spd[offset >> 2]; | |
48 | } | |
49 | switch (offset >> 2) { | |
50 | case 0: /* CM_ID */ | |
51 | return 0x411a3001; | |
52 | case 1: /* CM_PROC */ | |
53 | return 0; | |
54 | case 2: /* CM_OSC */ | |
55 | return s->cm_osc; | |
56 | case 3: /* CM_CTRL */ | |
57 | return s->cm_ctrl; | |
58 | case 4: /* CM_STAT */ | |
59 | return 0x00100000; | |
60 | case 5: /* CM_LOCK */ | |
61 | if (s->cm_lock == 0xa05f) { | |
62 | return 0x1a05f; | |
63 | } else { | |
64 | return s->cm_lock; | |
65 | } | |
66 | case 6: /* CM_LMBUSCNT */ | |
67 | /* ??? High frequency timer. */ | |
2ac71179 | 68 | hw_error("integratorcm_read: CM_LMBUSCNT"); |
b5ff1b31 FB |
69 | case 7: /* CM_AUXOSC */ |
70 | return s->cm_auxosc; | |
71 | case 8: /* CM_SDRAM */ | |
72 | return s->cm_sdram; | |
73 | case 9: /* CM_INIT */ | |
74 | return s->cm_init; | |
75 | case 10: /* CM_REFCT */ | |
76 | /* ??? High frequency timer. */ | |
2ac71179 | 77 | hw_error("integratorcm_read: CM_REFCT"); |
b5ff1b31 FB |
78 | case 12: /* CM_FLAGS */ |
79 | return s->cm_flags; | |
80 | case 14: /* CM_NVFLAGS */ | |
81 | return s->cm_nvflags; | |
82 | case 16: /* CM_IRQ_STAT */ | |
83 | return s->int_level & s->irq_enabled; | |
84 | case 17: /* CM_IRQ_RSTAT */ | |
85 | return s->int_level; | |
86 | case 18: /* CM_IRQ_ENSET */ | |
87 | return s->irq_enabled; | |
88 | case 20: /* CM_SOFT_INTSET */ | |
89 | return s->int_level & 1; | |
90 | case 24: /* CM_FIQ_STAT */ | |
91 | return s->int_level & s->fiq_enabled; | |
92 | case 25: /* CM_FIQ_RSTAT */ | |
93 | return s->int_level; | |
94 | case 26: /* CM_FIQ_ENSET */ | |
95 | return s->fiq_enabled; | |
96 | case 32: /* CM_VOLTAGE_CTL0 */ | |
97 | case 33: /* CM_VOLTAGE_CTL1 */ | |
98 | case 34: /* CM_VOLTAGE_CTL2 */ | |
99 | case 35: /* CM_VOLTAGE_CTL3 */ | |
100 | /* ??? Voltage control unimplemented. */ | |
101 | return 0; | |
102 | default: | |
2ac71179 PB |
103 | hw_error("integratorcm_read: Unimplemented offset 0x%x\n", |
104 | (int)offset); | |
b5ff1b31 FB |
105 | return 0; |
106 | } | |
107 | } | |
108 | ||
109 | static void integratorcm_do_remap(integratorcm_state *s, int flash) | |
110 | { | |
111 | if (flash) { | |
112 | cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM); | |
113 | } else { | |
114 | cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM); | |
115 | } | |
116 | //??? tlb_flush (cpu_single_env, 1); | |
117 | } | |
118 | ||
119 | static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value) | |
120 | { | |
121 | if (value & 8) { | |
2ac71179 | 122 | hw_error("Board reset\n"); |
b5ff1b31 FB |
123 | } |
124 | if ((s->cm_init ^ value) & 4) { | |
125 | integratorcm_do_remap(s, (value & 4) == 0); | |
126 | } | |
127 | if ((s->cm_init ^ value) & 1) { | |
128 | printf("Green LED %s\n", (value & 1) ? "on" : "off"); | |
129 | } | |
130 | s->cm_init = (s->cm_init & ~ 5) | (value ^ 5); | |
131 | } | |
132 | ||
133 | static void integratorcm_update(integratorcm_state *s) | |
134 | { | |
135 | /* ??? The CPU irq/fiq is raised when either the core module or base PIC | |
136 | are active. */ | |
137 | if (s->int_level & (s->irq_enabled | s->fiq_enabled)) | |
2ac71179 | 138 | hw_error("Core module interrupt\n"); |
b5ff1b31 FB |
139 | } |
140 | ||
141 | static void integratorcm_write(void *opaque, target_phys_addr_t offset, | |
142 | uint32_t value) | |
143 | { | |
144 | integratorcm_state *s = (integratorcm_state *)opaque; | |
b5ff1b31 FB |
145 | switch (offset >> 2) { |
146 | case 2: /* CM_OSC */ | |
147 | if (s->cm_lock == 0xa05f) | |
148 | s->cm_osc = value; | |
149 | break; | |
150 | case 3: /* CM_CTRL */ | |
151 | integratorcm_set_ctrl(s, value); | |
152 | break; | |
153 | case 5: /* CM_LOCK */ | |
154 | s->cm_lock = value & 0xffff; | |
155 | break; | |
156 | case 7: /* CM_AUXOSC */ | |
157 | if (s->cm_lock == 0xa05f) | |
158 | s->cm_auxosc = value; | |
159 | break; | |
160 | case 8: /* CM_SDRAM */ | |
161 | s->cm_sdram = value; | |
162 | break; | |
163 | case 9: /* CM_INIT */ | |
164 | /* ??? This can change the memory bus frequency. */ | |
165 | s->cm_init = value; | |
166 | break; | |
167 | case 12: /* CM_FLAGSS */ | |
168 | s->cm_flags |= value; | |
169 | break; | |
170 | case 13: /* CM_FLAGSC */ | |
171 | s->cm_flags &= ~value; | |
172 | break; | |
173 | case 14: /* CM_NVFLAGSS */ | |
174 | s->cm_nvflags |= value; | |
175 | break; | |
176 | case 15: /* CM_NVFLAGSS */ | |
177 | s->cm_nvflags &= ~value; | |
178 | break; | |
179 | case 18: /* CM_IRQ_ENSET */ | |
180 | s->irq_enabled |= value; | |
181 | integratorcm_update(s); | |
182 | break; | |
183 | case 19: /* CM_IRQ_ENCLR */ | |
184 | s->irq_enabled &= ~value; | |
185 | integratorcm_update(s); | |
186 | break; | |
187 | case 20: /* CM_SOFT_INTSET */ | |
188 | s->int_level |= (value & 1); | |
189 | integratorcm_update(s); | |
190 | break; | |
191 | case 21: /* CM_SOFT_INTCLR */ | |
192 | s->int_level &= ~(value & 1); | |
193 | integratorcm_update(s); | |
194 | break; | |
195 | case 26: /* CM_FIQ_ENSET */ | |
196 | s->fiq_enabled |= value; | |
197 | integratorcm_update(s); | |
198 | break; | |
199 | case 27: /* CM_FIQ_ENCLR */ | |
200 | s->fiq_enabled &= ~value; | |
201 | integratorcm_update(s); | |
202 | break; | |
203 | case 32: /* CM_VOLTAGE_CTL0 */ | |
204 | case 33: /* CM_VOLTAGE_CTL1 */ | |
205 | case 34: /* CM_VOLTAGE_CTL2 */ | |
206 | case 35: /* CM_VOLTAGE_CTL3 */ | |
207 | /* ??? Voltage control unimplemented. */ | |
208 | break; | |
209 | default: | |
2ac71179 PB |
210 | hw_error("integratorcm_write: Unimplemented offset 0x%x\n", |
211 | (int)offset); | |
b5ff1b31 FB |
212 | break; |
213 | } | |
214 | } | |
215 | ||
216 | /* Integrator/CM control registers. */ | |
217 | ||
218 | static CPUReadMemoryFunc *integratorcm_readfn[] = { | |
219 | integratorcm_read, | |
220 | integratorcm_read, | |
221 | integratorcm_read | |
222 | }; | |
223 | ||
224 | static CPUWriteMemoryFunc *integratorcm_writefn[] = { | |
225 | integratorcm_write, | |
226 | integratorcm_write, | |
227 | integratorcm_write | |
228 | }; | |
229 | ||
a7086888 | 230 | static void integratorcm_init(SysBusDevice *dev) |
b5ff1b31 FB |
231 | { |
232 | int iomemtype; | |
a7086888 | 233 | integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev); |
b5ff1b31 | 234 | |
b5ff1b31 FB |
235 | s->cm_osc = 0x01000048; |
236 | /* ??? What should the high bits of this value be? */ | |
237 | s->cm_auxosc = 0x0007feff; | |
238 | s->cm_sdram = 0x00011122; | |
ee6847d1 | 239 | if (s->memsz >= 256) { |
b5ff1b31 FB |
240 | integrator_spd[31] = 64; |
241 | s->cm_sdram |= 0x10; | |
ee6847d1 | 242 | } else if (s->memsz >= 128) { |
b5ff1b31 FB |
243 | integrator_spd[31] = 32; |
244 | s->cm_sdram |= 0x0c; | |
ee6847d1 | 245 | } else if (s->memsz >= 64) { |
b5ff1b31 FB |
246 | integrator_spd[31] = 16; |
247 | s->cm_sdram |= 0x08; | |
ee6847d1 | 248 | } else if (s->memsz >= 32) { |
b5ff1b31 FB |
249 | integrator_spd[31] = 4; |
250 | s->cm_sdram |= 0x04; | |
251 | } else { | |
252 | integrator_spd[31] = 2; | |
253 | } | |
254 | memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); | |
255 | s->cm_init = 0x00000112; | |
7fb4fdcf | 256 | s->flash_offset = qemu_ram_alloc(0x100000); |
b5ff1b31 | 257 | |
1eed09cb | 258 | iomemtype = cpu_register_io_memory(integratorcm_readfn, |
b5ff1b31 | 259 | integratorcm_writefn, s); |
a7086888 | 260 | sysbus_init_mmio(dev, 0x00800000, iomemtype); |
b5ff1b31 FB |
261 | integratorcm_do_remap(s, 1); |
262 | /* ??? Save/restore. */ | |
263 | } | |
264 | ||
265 | /* Integrator/CP hardware emulation. */ | |
266 | /* Primary interrupt controller. */ | |
267 | ||
268 | typedef struct icp_pic_state | |
269 | { | |
a7086888 | 270 | SysBusDevice busdev; |
b5ff1b31 FB |
271 | uint32_t level; |
272 | uint32_t irq_enabled; | |
273 | uint32_t fiq_enabled; | |
d537cf6c PB |
274 | qemu_irq parent_irq; |
275 | qemu_irq parent_fiq; | |
b5ff1b31 FB |
276 | } icp_pic_state; |
277 | ||
b5ff1b31 FB |
278 | static void icp_pic_update(icp_pic_state *s) |
279 | { | |
cdbdb648 | 280 | uint32_t flags; |
b5ff1b31 | 281 | |
d537cf6c PB |
282 | flags = (s->level & s->irq_enabled); |
283 | qemu_set_irq(s->parent_irq, flags != 0); | |
284 | flags = (s->level & s->fiq_enabled); | |
285 | qemu_set_irq(s->parent_fiq, flags != 0); | |
b5ff1b31 FB |
286 | } |
287 | ||
cdbdb648 | 288 | static void icp_pic_set_irq(void *opaque, int irq, int level) |
b5ff1b31 | 289 | { |
80337b66 | 290 | icp_pic_state *s = (icp_pic_state *)opaque; |
b5ff1b31 | 291 | if (level) |
80337b66 | 292 | s->level |= 1 << irq; |
b5ff1b31 | 293 | else |
80337b66 | 294 | s->level &= ~(1 << irq); |
b5ff1b31 FB |
295 | icp_pic_update(s); |
296 | } | |
297 | ||
298 | static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) | |
299 | { | |
300 | icp_pic_state *s = (icp_pic_state *)opaque; | |
301 | ||
b5ff1b31 FB |
302 | switch (offset >> 2) { |
303 | case 0: /* IRQ_STATUS */ | |
304 | return s->level & s->irq_enabled; | |
305 | case 1: /* IRQ_RAWSTAT */ | |
306 | return s->level; | |
307 | case 2: /* IRQ_ENABLESET */ | |
308 | return s->irq_enabled; | |
309 | case 4: /* INT_SOFTSET */ | |
310 | return s->level & 1; | |
311 | case 8: /* FRQ_STATUS */ | |
312 | return s->level & s->fiq_enabled; | |
313 | case 9: /* FRQ_RAWSTAT */ | |
314 | return s->level; | |
315 | case 10: /* FRQ_ENABLESET */ | |
316 | return s->fiq_enabled; | |
317 | case 3: /* IRQ_ENABLECLR */ | |
318 | case 5: /* INT_SOFTCLR */ | |
319 | case 11: /* FRQ_ENABLECLR */ | |
320 | default: | |
29bfb117 | 321 | printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
322 | return 0; |
323 | } | |
324 | } | |
325 | ||
326 | static void icp_pic_write(void *opaque, target_phys_addr_t offset, | |
327 | uint32_t value) | |
328 | { | |
329 | icp_pic_state *s = (icp_pic_state *)opaque; | |
b5ff1b31 FB |
330 | |
331 | switch (offset >> 2) { | |
332 | case 2: /* IRQ_ENABLESET */ | |
333 | s->irq_enabled |= value; | |
334 | break; | |
335 | case 3: /* IRQ_ENABLECLR */ | |
336 | s->irq_enabled &= ~value; | |
337 | break; | |
338 | case 4: /* INT_SOFTSET */ | |
339 | if (value & 1) | |
d537cf6c | 340 | icp_pic_set_irq(s, 0, 1); |
b5ff1b31 FB |
341 | break; |
342 | case 5: /* INT_SOFTCLR */ | |
343 | if (value & 1) | |
d537cf6c | 344 | icp_pic_set_irq(s, 0, 0); |
b5ff1b31 FB |
345 | break; |
346 | case 10: /* FRQ_ENABLESET */ | |
347 | s->fiq_enabled |= value; | |
348 | break; | |
349 | case 11: /* FRQ_ENABLECLR */ | |
350 | s->fiq_enabled &= ~value; | |
351 | break; | |
352 | case 0: /* IRQ_STATUS */ | |
353 | case 1: /* IRQ_RAWSTAT */ | |
354 | case 8: /* FRQ_STATUS */ | |
355 | case 9: /* FRQ_RAWSTAT */ | |
356 | default: | |
29bfb117 | 357 | printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
358 | return; |
359 | } | |
360 | icp_pic_update(s); | |
361 | } | |
362 | ||
363 | static CPUReadMemoryFunc *icp_pic_readfn[] = { | |
364 | icp_pic_read, | |
365 | icp_pic_read, | |
366 | icp_pic_read | |
367 | }; | |
368 | ||
369 | static CPUWriteMemoryFunc *icp_pic_writefn[] = { | |
370 | icp_pic_write, | |
371 | icp_pic_write, | |
372 | icp_pic_write | |
373 | }; | |
374 | ||
a7086888 | 375 | static void icp_pic_init(SysBusDevice *dev) |
b5ff1b31 | 376 | { |
a7086888 | 377 | icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev); |
b5ff1b31 FB |
378 | int iomemtype; |
379 | ||
067a3ddc | 380 | qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32); |
a7086888 PB |
381 | sysbus_init_irq(dev, &s->parent_irq); |
382 | sysbus_init_irq(dev, &s->parent_fiq); | |
1eed09cb | 383 | iomemtype = cpu_register_io_memory(icp_pic_readfn, |
b5ff1b31 | 384 | icp_pic_writefn, s); |
a7086888 | 385 | sysbus_init_mmio(dev, 0x00800000, iomemtype); |
b5ff1b31 FB |
386 | } |
387 | ||
b5ff1b31 | 388 | /* CP control registers. */ |
b5ff1b31 FB |
389 | static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) |
390 | { | |
b5ff1b31 FB |
391 | switch (offset >> 2) { |
392 | case 0: /* CP_IDFIELD */ | |
393 | return 0x41034003; | |
394 | case 1: /* CP_FLASHPROG */ | |
395 | return 0; | |
396 | case 2: /* CP_INTREG */ | |
397 | return 0; | |
398 | case 3: /* CP_DECODE */ | |
399 | return 0x11; | |
400 | default: | |
2ac71179 | 401 | hw_error("icp_control_read: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
402 | return 0; |
403 | } | |
404 | } | |
405 | ||
406 | static void icp_control_write(void *opaque, target_phys_addr_t offset, | |
407 | uint32_t value) | |
408 | { | |
b5ff1b31 FB |
409 | switch (offset >> 2) { |
410 | case 1: /* CP_FLASHPROG */ | |
411 | case 2: /* CP_INTREG */ | |
412 | case 3: /* CP_DECODE */ | |
413 | /* Nothing interesting implemented yet. */ | |
414 | break; | |
415 | default: | |
2ac71179 | 416 | hw_error("icp_control_write: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
417 | } |
418 | } | |
419 | static CPUReadMemoryFunc *icp_control_readfn[] = { | |
420 | icp_control_read, | |
421 | icp_control_read, | |
422 | icp_control_read | |
423 | }; | |
424 | ||
425 | static CPUWriteMemoryFunc *icp_control_writefn[] = { | |
426 | icp_control_write, | |
427 | icp_control_write, | |
428 | icp_control_write | |
429 | }; | |
430 | ||
431 | static void icp_control_init(uint32_t base) | |
432 | { | |
433 | int iomemtype; | |
b5ff1b31 | 434 | |
1eed09cb | 435 | iomemtype = cpu_register_io_memory(icp_control_readfn, |
8da3ff18 | 436 | icp_control_writefn, NULL); |
187337f8 | 437 | cpu_register_physical_memory(base, 0x00800000, iomemtype); |
b5ff1b31 FB |
438 | /* ??? Save/restore. */ |
439 | } | |
440 | ||
441 | ||
b5ff1b31 FB |
442 | /* Board init. */ |
443 | ||
f93eb9ff AZ |
444 | static struct arm_boot_info integrator_binfo = { |
445 | .loader_start = 0x0, | |
446 | .board_id = 0x113, | |
447 | }; | |
448 | ||
fbe1b595 | 449 | static void integratorcp_init(ram_addr_t ram_size, |
3023f332 | 450 | const char *boot_device, |
b5ff1b31 | 451 | const char *kernel_filename, const char *kernel_cmdline, |
3371d272 | 452 | const char *initrd_filename, const char *cpu_model) |
b5ff1b31 FB |
453 | { |
454 | CPUState *env; | |
7ffab4d7 | 455 | ram_addr_t ram_offset; |
a7086888 | 456 | qemu_irq pic[32]; |
d537cf6c | 457 | qemu_irq *cpu_pic; |
a7086888 PB |
458 | DeviceState *dev; |
459 | int i; | |
b5ff1b31 | 460 | |
3371d272 PB |
461 | if (!cpu_model) |
462 | cpu_model = "arm926"; | |
aaed909a FB |
463 | env = cpu_init(cpu_model); |
464 | if (!env) { | |
465 | fprintf(stderr, "Unable to find CPU definition\n"); | |
466 | exit(1); | |
467 | } | |
7fb4fdcf | 468 | ram_offset = qemu_ram_alloc(ram_size); |
b5ff1b31 | 469 | /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ |
1235fc06 | 470 | /* ??? RAM should repeat to fill physical memory space. */ |
b5ff1b31 | 471 | /* SDRAM at address zero*/ |
7fb4fdcf | 472 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); |
b5ff1b31 | 473 | /* And again at address 0x80000000 */ |
7fb4fdcf | 474 | cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM); |
b5ff1b31 | 475 | |
a7086888 | 476 | dev = qdev_create(NULL, "integrator_core"); |
ee6847d1 | 477 | qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); |
a7086888 PB |
478 | qdev_init(dev); |
479 | sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); | |
480 | ||
cdbdb648 | 481 | cpu_pic = arm_pic_init_cpu(env); |
a7086888 PB |
482 | dev = sysbus_create_varargs("integrator_pic", 0x14000000, |
483 | cpu_pic[ARM_PIC_CPU_IRQ], | |
484 | cpu_pic[ARM_PIC_CPU_FIQ], NULL); | |
485 | for (i = 0; i < 32; i++) { | |
067a3ddc | 486 | pic[i] = qdev_get_gpio_in(dev, i); |
a7086888 | 487 | } |
6a824ec3 PB |
488 | sysbus_create_simple("integrator_pic", 0xca000000, pic[26]); |
489 | sysbus_create_varargs("integrator_pit", 0x13000000, | |
490 | pic[5], pic[6], pic[7], NULL); | |
a63bdb31 | 491 | sysbus_create_simple("pl031", 0x15000000, pic[8]); |
a7d518a6 PB |
492 | sysbus_create_simple("pl011", 0x16000000, pic[1]); |
493 | sysbus_create_simple("pl011", 0x17000000, pic[2]); | |
b5ff1b31 | 494 | icp_control_init(0xcb000000); |
86394e96 PB |
495 | sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); |
496 | sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); | |
aa9311d8 | 497 | sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); |
0ae18cee AL |
498 | if (nd_table[0].vlan) |
499 | smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); | |
2e9bdce5 PB |
500 | |
501 | sysbus_create_simple("pl110", 0xc0000000, pic[22]); | |
b5ff1b31 | 502 | |
f93eb9ff AZ |
503 | integrator_binfo.ram_size = ram_size; |
504 | integrator_binfo.kernel_filename = kernel_filename; | |
505 | integrator_binfo.kernel_cmdline = kernel_cmdline; | |
506 | integrator_binfo.initrd_filename = initrd_filename; | |
507 | arm_load_kernel(env, &integrator_binfo); | |
b5ff1b31 FB |
508 | } |
509 | ||
f80f9ec9 | 510 | static QEMUMachine integratorcp_machine = { |
4b32e168 AL |
511 | .name = "integratorcp", |
512 | .desc = "ARM Integrator/CP (ARM926EJ-S)", | |
513 | .init = integratorcp_init, | |
0c257437 | 514 | .is_default = 1, |
b5ff1b31 | 515 | }; |
a7086888 | 516 | |
f80f9ec9 AL |
517 | static void integratorcp_machine_init(void) |
518 | { | |
519 | qemu_register_machine(&integratorcp_machine); | |
520 | } | |
521 | ||
522 | machine_init(integratorcp_machine_init); | |
523 | ||
ee6847d1 GH |
524 | static SysBusDeviceInfo core_info = { |
525 | .init = integratorcm_init, | |
526 | .qdev.name = "integrator_core", | |
527 | .qdev.size = sizeof(integratorcm_state), | |
528 | .qdev.props = (Property[]) { | |
529 | { | |
530 | .name = "memsz", | |
531 | .info = &qdev_prop_uint32, | |
532 | .offset = offsetof(integratorcm_state, memsz), | |
533 | }, | |
534 | {/* end of list */} | |
535 | } | |
536 | }; | |
537 | ||
a7086888 PB |
538 | static void integratorcp_register_devices(void) |
539 | { | |
540 | sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init); | |
ee6847d1 | 541 | sysbus_register_withprop(&core_info); |
a7086888 PB |
542 | } |
543 | ||
544 | device_init(integratorcp_register_devices) |