]>
Commit | Line | Data |
---|---|---|
5fafdf24 | 1 | /* |
b5ff1b31 FB |
2 | * ARM Integrator CP System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2005-2007 CodeSourcery. |
b5ff1b31 FB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL |
b5ff1b31 FB |
8 | */ |
9 | ||
2e9bdce5 | 10 | #include "sysbus.h" |
87ecb68b PB |
11 | #include "primecell.h" |
12 | #include "devices.h" | |
87ecb68b PB |
13 | #include "boards.h" |
14 | #include "arm-misc.h" | |
15 | #include "net.h" | |
211adf4d | 16 | #include "exec-memory.h" |
df3f457b | 17 | #include "sysemu.h" |
b5ff1b31 | 18 | |
b5ff1b31 | 19 | typedef struct { |
a7086888 | 20 | SysBusDevice busdev; |
71d9bc50 | 21 | MemoryRegion iomem; |
ee6847d1 | 22 | uint32_t memsz; |
211adf4d AK |
23 | MemoryRegion flash; |
24 | bool flash_mapped; | |
b5ff1b31 FB |
25 | uint32_t cm_osc; |
26 | uint32_t cm_ctrl; | |
27 | uint32_t cm_lock; | |
28 | uint32_t cm_auxosc; | |
29 | uint32_t cm_sdram; | |
30 | uint32_t cm_init; | |
31 | uint32_t cm_flags; | |
32 | uint32_t cm_nvflags; | |
33 | uint32_t int_level; | |
34 | uint32_t irq_enabled; | |
35 | uint32_t fiq_enabled; | |
36 | } integratorcm_state; | |
37 | ||
38 | static uint8_t integrator_spd[128] = { | |
39 | 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, | |
40 | 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 | |
41 | }; | |
42 | ||
71d9bc50 BC |
43 | static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset, |
44 | unsigned size) | |
b5ff1b31 FB |
45 | { |
46 | integratorcm_state *s = (integratorcm_state *)opaque; | |
b5ff1b31 FB |
47 | if (offset >= 0x100 && offset < 0x200) { |
48 | /* CM_SPD */ | |
49 | if (offset >= 0x180) | |
50 | return 0; | |
51 | return integrator_spd[offset >> 2]; | |
52 | } | |
53 | switch (offset >> 2) { | |
54 | case 0: /* CM_ID */ | |
55 | return 0x411a3001; | |
56 | case 1: /* CM_PROC */ | |
57 | return 0; | |
58 | case 2: /* CM_OSC */ | |
59 | return s->cm_osc; | |
60 | case 3: /* CM_CTRL */ | |
61 | return s->cm_ctrl; | |
62 | case 4: /* CM_STAT */ | |
63 | return 0x00100000; | |
64 | case 5: /* CM_LOCK */ | |
65 | if (s->cm_lock == 0xa05f) { | |
66 | return 0x1a05f; | |
67 | } else { | |
68 | return s->cm_lock; | |
69 | } | |
70 | case 6: /* CM_LMBUSCNT */ | |
71 | /* ??? High frequency timer. */ | |
2ac71179 | 72 | hw_error("integratorcm_read: CM_LMBUSCNT"); |
b5ff1b31 FB |
73 | case 7: /* CM_AUXOSC */ |
74 | return s->cm_auxosc; | |
75 | case 8: /* CM_SDRAM */ | |
76 | return s->cm_sdram; | |
77 | case 9: /* CM_INIT */ | |
78 | return s->cm_init; | |
79 | case 10: /* CM_REFCT */ | |
80 | /* ??? High frequency timer. */ | |
2ac71179 | 81 | hw_error("integratorcm_read: CM_REFCT"); |
b5ff1b31 FB |
82 | case 12: /* CM_FLAGS */ |
83 | return s->cm_flags; | |
84 | case 14: /* CM_NVFLAGS */ | |
85 | return s->cm_nvflags; | |
86 | case 16: /* CM_IRQ_STAT */ | |
87 | return s->int_level & s->irq_enabled; | |
88 | case 17: /* CM_IRQ_RSTAT */ | |
89 | return s->int_level; | |
90 | case 18: /* CM_IRQ_ENSET */ | |
91 | return s->irq_enabled; | |
92 | case 20: /* CM_SOFT_INTSET */ | |
93 | return s->int_level & 1; | |
94 | case 24: /* CM_FIQ_STAT */ | |
95 | return s->int_level & s->fiq_enabled; | |
96 | case 25: /* CM_FIQ_RSTAT */ | |
97 | return s->int_level; | |
98 | case 26: /* CM_FIQ_ENSET */ | |
99 | return s->fiq_enabled; | |
100 | case 32: /* CM_VOLTAGE_CTL0 */ | |
101 | case 33: /* CM_VOLTAGE_CTL1 */ | |
102 | case 34: /* CM_VOLTAGE_CTL2 */ | |
103 | case 35: /* CM_VOLTAGE_CTL3 */ | |
104 | /* ??? Voltage control unimplemented. */ | |
105 | return 0; | |
106 | default: | |
2ac71179 PB |
107 | hw_error("integratorcm_read: Unimplemented offset 0x%x\n", |
108 | (int)offset); | |
b5ff1b31 FB |
109 | return 0; |
110 | } | |
111 | } | |
112 | ||
113 | static void integratorcm_do_remap(integratorcm_state *s, int flash) | |
114 | { | |
4753dea8 | 115 | if (!flash) { |
211adf4d AK |
116 | if (s->flash_mapped) { |
117 | sysbus_del_memory(&s->busdev, &s->flash); | |
118 | s->flash_mapped = false; | |
119 | } | |
b5ff1b31 | 120 | } else { |
211adf4d AK |
121 | if (!s->flash_mapped) { |
122 | sysbus_add_memory_overlap(&s->busdev, 0, &s->flash, 1); | |
123 | s->flash_mapped = true; | |
124 | } | |
b5ff1b31 FB |
125 | } |
126 | //??? tlb_flush (cpu_single_env, 1); | |
127 | } | |
128 | ||
129 | static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value) | |
130 | { | |
131 | if (value & 8) { | |
df3f457b | 132 | qemu_system_reset_request(); |
b5ff1b31 | 133 | } |
df3f457b | 134 | if ((s->cm_ctrl ^ value) & 4) { |
b5ff1b31 FB |
135 | integratorcm_do_remap(s, (value & 4) == 0); |
136 | } | |
df3f457b PM |
137 | if ((s->cm_ctrl ^ value) & 1) { |
138 | /* (value & 1) != 0 means the green "MISC LED" is lit. | |
139 | * We don't have any nice place to display LEDs. printf is a bad | |
140 | * idea because Linux uses the LED as a heartbeat and the output | |
141 | * will swamp anything else on the terminal. | |
142 | */ | |
b5ff1b31 | 143 | } |
df3f457b PM |
144 | /* Note that the RESET bit [3] always reads as zero */ |
145 | s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); | |
b5ff1b31 FB |
146 | } |
147 | ||
148 | static void integratorcm_update(integratorcm_state *s) | |
149 | { | |
150 | /* ??? The CPU irq/fiq is raised when either the core module or base PIC | |
151 | are active. */ | |
152 | if (s->int_level & (s->irq_enabled | s->fiq_enabled)) | |
2ac71179 | 153 | hw_error("Core module interrupt\n"); |
b5ff1b31 FB |
154 | } |
155 | ||
c227f099 | 156 | static void integratorcm_write(void *opaque, target_phys_addr_t offset, |
71d9bc50 | 157 | uint64_t value, unsigned size) |
b5ff1b31 FB |
158 | { |
159 | integratorcm_state *s = (integratorcm_state *)opaque; | |
b5ff1b31 FB |
160 | switch (offset >> 2) { |
161 | case 2: /* CM_OSC */ | |
162 | if (s->cm_lock == 0xa05f) | |
163 | s->cm_osc = value; | |
164 | break; | |
165 | case 3: /* CM_CTRL */ | |
166 | integratorcm_set_ctrl(s, value); | |
167 | break; | |
168 | case 5: /* CM_LOCK */ | |
169 | s->cm_lock = value & 0xffff; | |
170 | break; | |
171 | case 7: /* CM_AUXOSC */ | |
172 | if (s->cm_lock == 0xa05f) | |
173 | s->cm_auxosc = value; | |
174 | break; | |
175 | case 8: /* CM_SDRAM */ | |
176 | s->cm_sdram = value; | |
177 | break; | |
178 | case 9: /* CM_INIT */ | |
179 | /* ??? This can change the memory bus frequency. */ | |
180 | s->cm_init = value; | |
181 | break; | |
182 | case 12: /* CM_FLAGSS */ | |
183 | s->cm_flags |= value; | |
184 | break; | |
185 | case 13: /* CM_FLAGSC */ | |
186 | s->cm_flags &= ~value; | |
187 | break; | |
188 | case 14: /* CM_NVFLAGSS */ | |
189 | s->cm_nvflags |= value; | |
190 | break; | |
191 | case 15: /* CM_NVFLAGSS */ | |
192 | s->cm_nvflags &= ~value; | |
193 | break; | |
194 | case 18: /* CM_IRQ_ENSET */ | |
195 | s->irq_enabled |= value; | |
196 | integratorcm_update(s); | |
197 | break; | |
198 | case 19: /* CM_IRQ_ENCLR */ | |
199 | s->irq_enabled &= ~value; | |
200 | integratorcm_update(s); | |
201 | break; | |
202 | case 20: /* CM_SOFT_INTSET */ | |
203 | s->int_level |= (value & 1); | |
204 | integratorcm_update(s); | |
205 | break; | |
206 | case 21: /* CM_SOFT_INTCLR */ | |
207 | s->int_level &= ~(value & 1); | |
208 | integratorcm_update(s); | |
209 | break; | |
210 | case 26: /* CM_FIQ_ENSET */ | |
211 | s->fiq_enabled |= value; | |
212 | integratorcm_update(s); | |
213 | break; | |
214 | case 27: /* CM_FIQ_ENCLR */ | |
215 | s->fiq_enabled &= ~value; | |
216 | integratorcm_update(s); | |
217 | break; | |
218 | case 32: /* CM_VOLTAGE_CTL0 */ | |
219 | case 33: /* CM_VOLTAGE_CTL1 */ | |
220 | case 34: /* CM_VOLTAGE_CTL2 */ | |
221 | case 35: /* CM_VOLTAGE_CTL3 */ | |
222 | /* ??? Voltage control unimplemented. */ | |
223 | break; | |
224 | default: | |
2ac71179 PB |
225 | hw_error("integratorcm_write: Unimplemented offset 0x%x\n", |
226 | (int)offset); | |
b5ff1b31 FB |
227 | break; |
228 | } | |
229 | } | |
230 | ||
231 | /* Integrator/CM control registers. */ | |
232 | ||
71d9bc50 BC |
233 | static const MemoryRegionOps integratorcm_ops = { |
234 | .read = integratorcm_read, | |
235 | .write = integratorcm_write, | |
236 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
237 | }; |
238 | ||
81a322d4 | 239 | static int integratorcm_init(SysBusDevice *dev) |
b5ff1b31 | 240 | { |
a7086888 | 241 | integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev); |
b5ff1b31 | 242 | |
b5ff1b31 FB |
243 | s->cm_osc = 0x01000048; |
244 | /* ??? What should the high bits of this value be? */ | |
245 | s->cm_auxosc = 0x0007feff; | |
246 | s->cm_sdram = 0x00011122; | |
ee6847d1 | 247 | if (s->memsz >= 256) { |
b5ff1b31 FB |
248 | integrator_spd[31] = 64; |
249 | s->cm_sdram |= 0x10; | |
ee6847d1 | 250 | } else if (s->memsz >= 128) { |
b5ff1b31 FB |
251 | integrator_spd[31] = 32; |
252 | s->cm_sdram |= 0x0c; | |
ee6847d1 | 253 | } else if (s->memsz >= 64) { |
b5ff1b31 FB |
254 | integrator_spd[31] = 16; |
255 | s->cm_sdram |= 0x08; | |
ee6847d1 | 256 | } else if (s->memsz >= 32) { |
b5ff1b31 FB |
257 | integrator_spd[31] = 4; |
258 | s->cm_sdram |= 0x04; | |
259 | } else { | |
260 | integrator_spd[31] = 2; | |
261 | } | |
262 | memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); | |
263 | s->cm_init = 0x00000112; | |
c5705a77 AK |
264 | memory_region_init_ram(&s->flash, "integrator.flash", 0x100000); |
265 | vmstate_register_ram_global(&s->flash); | |
211adf4d | 266 | s->flash_mapped = false; |
b5ff1b31 | 267 | |
71d9bc50 BC |
268 | memory_region_init_io(&s->iomem, &integratorcm_ops, s, |
269 | "integratorcm", 0x00800000); | |
750ecd44 | 270 | sysbus_init_mmio(dev, &s->iomem); |
71d9bc50 | 271 | |
b5ff1b31 FB |
272 | integratorcm_do_remap(s, 1); |
273 | /* ??? Save/restore. */ | |
81a322d4 | 274 | return 0; |
b5ff1b31 FB |
275 | } |
276 | ||
277 | /* Integrator/CP hardware emulation. */ | |
278 | /* Primary interrupt controller. */ | |
279 | ||
280 | typedef struct icp_pic_state | |
281 | { | |
a7086888 | 282 | SysBusDevice busdev; |
61074e46 | 283 | MemoryRegion iomem; |
b5ff1b31 FB |
284 | uint32_t level; |
285 | uint32_t irq_enabled; | |
286 | uint32_t fiq_enabled; | |
d537cf6c PB |
287 | qemu_irq parent_irq; |
288 | qemu_irq parent_fiq; | |
b5ff1b31 FB |
289 | } icp_pic_state; |
290 | ||
b5ff1b31 FB |
291 | static void icp_pic_update(icp_pic_state *s) |
292 | { | |
cdbdb648 | 293 | uint32_t flags; |
b5ff1b31 | 294 | |
d537cf6c PB |
295 | flags = (s->level & s->irq_enabled); |
296 | qemu_set_irq(s->parent_irq, flags != 0); | |
297 | flags = (s->level & s->fiq_enabled); | |
298 | qemu_set_irq(s->parent_fiq, flags != 0); | |
b5ff1b31 FB |
299 | } |
300 | ||
cdbdb648 | 301 | static void icp_pic_set_irq(void *opaque, int irq, int level) |
b5ff1b31 | 302 | { |
80337b66 | 303 | icp_pic_state *s = (icp_pic_state *)opaque; |
b5ff1b31 | 304 | if (level) |
80337b66 | 305 | s->level |= 1 << irq; |
b5ff1b31 | 306 | else |
80337b66 | 307 | s->level &= ~(1 << irq); |
b5ff1b31 FB |
308 | icp_pic_update(s); |
309 | } | |
310 | ||
61074e46 BC |
311 | static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset, |
312 | unsigned size) | |
b5ff1b31 FB |
313 | { |
314 | icp_pic_state *s = (icp_pic_state *)opaque; | |
315 | ||
b5ff1b31 FB |
316 | switch (offset >> 2) { |
317 | case 0: /* IRQ_STATUS */ | |
318 | return s->level & s->irq_enabled; | |
319 | case 1: /* IRQ_RAWSTAT */ | |
320 | return s->level; | |
321 | case 2: /* IRQ_ENABLESET */ | |
322 | return s->irq_enabled; | |
323 | case 4: /* INT_SOFTSET */ | |
324 | return s->level & 1; | |
325 | case 8: /* FRQ_STATUS */ | |
326 | return s->level & s->fiq_enabled; | |
327 | case 9: /* FRQ_RAWSTAT */ | |
328 | return s->level; | |
329 | case 10: /* FRQ_ENABLESET */ | |
330 | return s->fiq_enabled; | |
331 | case 3: /* IRQ_ENABLECLR */ | |
332 | case 5: /* INT_SOFTCLR */ | |
333 | case 11: /* FRQ_ENABLECLR */ | |
334 | default: | |
29bfb117 | 335 | printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
336 | return 0; |
337 | } | |
338 | } | |
339 | ||
c227f099 | 340 | static void icp_pic_write(void *opaque, target_phys_addr_t offset, |
61074e46 | 341 | uint64_t value, unsigned size) |
b5ff1b31 FB |
342 | { |
343 | icp_pic_state *s = (icp_pic_state *)opaque; | |
b5ff1b31 FB |
344 | |
345 | switch (offset >> 2) { | |
346 | case 2: /* IRQ_ENABLESET */ | |
347 | s->irq_enabled |= value; | |
348 | break; | |
349 | case 3: /* IRQ_ENABLECLR */ | |
350 | s->irq_enabled &= ~value; | |
351 | break; | |
352 | case 4: /* INT_SOFTSET */ | |
353 | if (value & 1) | |
d537cf6c | 354 | icp_pic_set_irq(s, 0, 1); |
b5ff1b31 FB |
355 | break; |
356 | case 5: /* INT_SOFTCLR */ | |
357 | if (value & 1) | |
d537cf6c | 358 | icp_pic_set_irq(s, 0, 0); |
b5ff1b31 FB |
359 | break; |
360 | case 10: /* FRQ_ENABLESET */ | |
361 | s->fiq_enabled |= value; | |
362 | break; | |
363 | case 11: /* FRQ_ENABLECLR */ | |
364 | s->fiq_enabled &= ~value; | |
365 | break; | |
366 | case 0: /* IRQ_STATUS */ | |
367 | case 1: /* IRQ_RAWSTAT */ | |
368 | case 8: /* FRQ_STATUS */ | |
369 | case 9: /* FRQ_RAWSTAT */ | |
370 | default: | |
29bfb117 | 371 | printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
372 | return; |
373 | } | |
374 | icp_pic_update(s); | |
375 | } | |
376 | ||
61074e46 BC |
377 | static const MemoryRegionOps icp_pic_ops = { |
378 | .read = icp_pic_read, | |
379 | .write = icp_pic_write, | |
380 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
381 | }; |
382 | ||
81a322d4 | 383 | static int icp_pic_init(SysBusDevice *dev) |
b5ff1b31 | 384 | { |
a7086888 | 385 | icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev); |
b5ff1b31 | 386 | |
067a3ddc | 387 | qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32); |
a7086888 PB |
388 | sysbus_init_irq(dev, &s->parent_irq); |
389 | sysbus_init_irq(dev, &s->parent_fiq); | |
61074e46 | 390 | memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000); |
750ecd44 | 391 | sysbus_init_mmio(dev, &s->iomem); |
81a322d4 | 392 | return 0; |
b5ff1b31 FB |
393 | } |
394 | ||
b5ff1b31 | 395 | /* CP control registers. */ |
0c36493e BC |
396 | |
397 | static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset, | |
398 | unsigned size) | |
b5ff1b31 | 399 | { |
b5ff1b31 FB |
400 | switch (offset >> 2) { |
401 | case 0: /* CP_IDFIELD */ | |
402 | return 0x41034003; | |
403 | case 1: /* CP_FLASHPROG */ | |
404 | return 0; | |
405 | case 2: /* CP_INTREG */ | |
406 | return 0; | |
407 | case 3: /* CP_DECODE */ | |
408 | return 0x11; | |
409 | default: | |
2ac71179 | 410 | hw_error("icp_control_read: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
411 | return 0; |
412 | } | |
413 | } | |
414 | ||
c227f099 | 415 | static void icp_control_write(void *opaque, target_phys_addr_t offset, |
0c36493e | 416 | uint64_t value, unsigned size) |
b5ff1b31 | 417 | { |
b5ff1b31 FB |
418 | switch (offset >> 2) { |
419 | case 1: /* CP_FLASHPROG */ | |
420 | case 2: /* CP_INTREG */ | |
421 | case 3: /* CP_DECODE */ | |
422 | /* Nothing interesting implemented yet. */ | |
423 | break; | |
424 | default: | |
2ac71179 | 425 | hw_error("icp_control_write: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
426 | } |
427 | } | |
b5ff1b31 | 428 | |
0c36493e BC |
429 | static const MemoryRegionOps icp_control_ops = { |
430 | .read = icp_control_read, | |
431 | .write = icp_control_write, | |
432 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
433 | }; |
434 | ||
0c36493e | 435 | static void icp_control_init(target_phys_addr_t base) |
b5ff1b31 | 436 | { |
0c36493e | 437 | MemoryRegion *io; |
b5ff1b31 | 438 | |
0c36493e BC |
439 | io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion)); |
440 | memory_region_init_io(io, &icp_control_ops, NULL, | |
441 | "control", 0x00800000); | |
442 | memory_region_add_subregion(get_system_memory(), base, io); | |
b5ff1b31 FB |
443 | /* ??? Save/restore. */ |
444 | } | |
445 | ||
446 | ||
b5ff1b31 FB |
447 | /* Board init. */ |
448 | ||
f93eb9ff AZ |
449 | static struct arm_boot_info integrator_binfo = { |
450 | .loader_start = 0x0, | |
451 | .board_id = 0x113, | |
452 | }; | |
453 | ||
c227f099 | 454 | static void integratorcp_init(ram_addr_t ram_size, |
3023f332 | 455 | const char *boot_device, |
b5ff1b31 | 456 | const char *kernel_filename, const char *kernel_cmdline, |
3371d272 | 457 | const char *initrd_filename, const char *cpu_model) |
b5ff1b31 FB |
458 | { |
459 | CPUState *env; | |
211adf4d AK |
460 | MemoryRegion *address_space_mem = get_system_memory(); |
461 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
462 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); | |
a7086888 | 463 | qemu_irq pic[32]; |
d537cf6c | 464 | qemu_irq *cpu_pic; |
a7086888 PB |
465 | DeviceState *dev; |
466 | int i; | |
b5ff1b31 | 467 | |
3371d272 PB |
468 | if (!cpu_model) |
469 | cpu_model = "arm926"; | |
aaed909a FB |
470 | env = cpu_init(cpu_model); |
471 | if (!env) { | |
472 | fprintf(stderr, "Unable to find CPU definition\n"); | |
473 | exit(1); | |
474 | } | |
c5705a77 AK |
475 | memory_region_init_ram(ram, "integrator.ram", ram_size); |
476 | vmstate_register_ram_global(ram); | |
b5ff1b31 | 477 | /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ |
1235fc06 | 478 | /* ??? RAM should repeat to fill physical memory space. */ |
b5ff1b31 | 479 | /* SDRAM at address zero*/ |
211adf4d | 480 | memory_region_add_subregion(address_space_mem, 0, ram); |
b5ff1b31 | 481 | /* And again at address 0x80000000 */ |
211adf4d AK |
482 | memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size); |
483 | memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); | |
b5ff1b31 | 484 | |
a7086888 | 485 | dev = qdev_create(NULL, "integrator_core"); |
ee6847d1 | 486 | qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); |
e23a1b33 | 487 | qdev_init_nofail(dev); |
a7086888 PB |
488 | sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); |
489 | ||
cdbdb648 | 490 | cpu_pic = arm_pic_init_cpu(env); |
a7086888 PB |
491 | dev = sysbus_create_varargs("integrator_pic", 0x14000000, |
492 | cpu_pic[ARM_PIC_CPU_IRQ], | |
493 | cpu_pic[ARM_PIC_CPU_FIQ], NULL); | |
494 | for (i = 0; i < 32; i++) { | |
067a3ddc | 495 | pic[i] = qdev_get_gpio_in(dev, i); |
a7086888 | 496 | } |
6a824ec3 PB |
497 | sysbus_create_simple("integrator_pic", 0xca000000, pic[26]); |
498 | sysbus_create_varargs("integrator_pit", 0x13000000, | |
499 | pic[5], pic[6], pic[7], NULL); | |
a63bdb31 | 500 | sysbus_create_simple("pl031", 0x15000000, pic[8]); |
a7d518a6 PB |
501 | sysbus_create_simple("pl011", 0x16000000, pic[1]); |
502 | sysbus_create_simple("pl011", 0x17000000, pic[2]); | |
b5ff1b31 | 503 | icp_control_init(0xcb000000); |
86394e96 PB |
504 | sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); |
505 | sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); | |
aa9311d8 | 506 | sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); |
0ae18cee AL |
507 | if (nd_table[0].vlan) |
508 | smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); | |
2e9bdce5 PB |
509 | |
510 | sysbus_create_simple("pl110", 0xc0000000, pic[22]); | |
b5ff1b31 | 511 | |
f93eb9ff AZ |
512 | integrator_binfo.ram_size = ram_size; |
513 | integrator_binfo.kernel_filename = kernel_filename; | |
514 | integrator_binfo.kernel_cmdline = kernel_cmdline; | |
515 | integrator_binfo.initrd_filename = initrd_filename; | |
516 | arm_load_kernel(env, &integrator_binfo); | |
b5ff1b31 FB |
517 | } |
518 | ||
f80f9ec9 | 519 | static QEMUMachine integratorcp_machine = { |
4b32e168 AL |
520 | .name = "integratorcp", |
521 | .desc = "ARM Integrator/CP (ARM926EJ-S)", | |
522 | .init = integratorcp_init, | |
0c257437 | 523 | .is_default = 1, |
b5ff1b31 | 524 | }; |
a7086888 | 525 | |
f80f9ec9 AL |
526 | static void integratorcp_machine_init(void) |
527 | { | |
528 | qemu_register_machine(&integratorcp_machine); | |
529 | } | |
530 | ||
531 | machine_init(integratorcp_machine_init); | |
532 | ||
ee6847d1 GH |
533 | static SysBusDeviceInfo core_info = { |
534 | .init = integratorcm_init, | |
535 | .qdev.name = "integrator_core", | |
536 | .qdev.size = sizeof(integratorcm_state), | |
537 | .qdev.props = (Property[]) { | |
bb36f66a GH |
538 | DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0), |
539 | DEFINE_PROP_END_OF_LIST(), | |
ee6847d1 GH |
540 | } |
541 | }; | |
542 | ||
a7086888 PB |
543 | static void integratorcp_register_devices(void) |
544 | { | |
545 | sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init); | |
ee6847d1 | 546 | sysbus_register_withprop(&core_info); |
a7086888 PB |
547 | } |
548 | ||
549 | device_init(integratorcp_register_devices) |