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[qemu.git] / hw / intel-hda.c
CommitLineData
d61a4ce8
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "hw.h"
21#include "pci.h"
17786d52 22#include "msi.h"
d61a4ce8
GH		 23#include "qemu-timer.h"
24#include "audiodev.h"
25#include "intel-hda.h"
26#include "intel-hda-defs.h"
fa0ce55c 27#include "dma.h"
d61a4ce8
GH		 28
29/* --------------------------------------------------------------------- */
30/* hda bus */
31
3cb75a7c
PB		 32static Property hda_props[] = {
33 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
34 DEFINE_PROP_END_OF_LIST()
35};
36
0d936928
AL		 37static const TypeInfo hda_codec_bus_info = {
38 .name = TYPE_HDA_BUS,
39 .parent = TYPE_BUS,
40 .instance_size = sizeof(HDACodecBus),
d61a4ce8
GH		 41};
42
43void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
44 hda_codec_response_func response,
45 hda_codec_xfer_func xfer)
46{
0d936928 47 qbus_create_inplace(&bus->qbus, TYPE_HDA_BUS, dev, NULL);
d61a4ce8
GH		 48 bus->response = response;
49 bus->xfer = xfer;
50}
51
d307af79 52static int hda_codec_dev_init(DeviceState *qdev)
d61a4ce8
GH		 53{
54 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
55 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 56 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
d61a4ce8 57
d61a4ce8
GH		 58 if (dev->cad == -1) {
59 dev->cad = bus->next_cad;
60 }
df0db221 61 if (dev->cad >= 15) {
d61a4ce8 62 return -1;
df0db221 63 }
d61a4ce8 64 bus->next_cad = dev->cad + 1;
dbaa7904 65 return cdc->init(dev);
d61a4ce8
GH		 66}
67
dc4b9240
GH		 68static int hda_codec_dev_exit(DeviceState *qdev)
69{
70 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 71 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
dc4b9240 72
dbaa7904
AL		 73 if (cdc->exit) {
74 cdc->exit(dev);
dc4b9240
GH		 75 }
76 return 0;
77}
78
d61a4ce8
GH		 79HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
80{
0866aca1 81 BusChild *kid;
d61a4ce8
GH		 82 HDACodecDevice *cdev;
83
0866aca1
AL		 84 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
85 DeviceState *qdev = kid->child;
d61a4ce8
GH		 86 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
87 if (cdev->cad == cad) {
88 return cdev;
89 }
90 }
91 return NULL;
92}
93
94void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
95{
96 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
97 bus->response(dev, solicited, response);
98}
99
100bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
101 uint8_t *buf, uint32_t len)
102{
103 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
104 return bus->xfer(dev, stnr, output, buf, len);
105}
106
107/* --------------------------------------------------------------------- */
108/* intel hda emulation */
109
110typedef struct IntelHDAStream IntelHDAStream;
111typedef struct IntelHDAState IntelHDAState;
112typedef struct IntelHDAReg IntelHDAReg;
113
114typedef struct bpl {
115 uint64_t addr;
116 uint32_t len;
117 uint32_t flags;
118} bpl;
119
120struct IntelHDAStream {
121 /* registers */
122 uint32_t ctl;
123 uint32_t lpib;
124 uint32_t cbl;
125 uint32_t lvi;
126 uint32_t fmt;
127 uint32_t bdlp_lbase;
128 uint32_t bdlp_ubase;
129
130 /* state */
131 bpl *bpl;
132 uint32_t bentries;
133 uint32_t bsize, be, bp;
134};
135
136struct IntelHDAState {
137 PCIDevice pci;
138 const char *name;
139 HDACodecBus codecs;
140
141 /* registers */
142 uint32_t g_ctl;
143 uint32_t wake_en;
144 uint32_t state_sts;
145 uint32_t int_ctl;
146 uint32_t int_sts;
147 uint32_t wall_clk;
148
149 uint32_t corb_lbase;
150 uint32_t corb_ubase;
151 uint32_t corb_rp;
152 uint32_t corb_wp;
153 uint32_t corb_ctl;
154 uint32_t corb_sts;
155 uint32_t corb_size;
156
157 uint32_t rirb_lbase;
158 uint32_t rirb_ubase;
159 uint32_t rirb_wp;
160 uint32_t rirb_cnt;
161 uint32_t rirb_ctl;
162 uint32_t rirb_sts;
163 uint32_t rirb_size;
164
165 uint32_t dp_lbase;
166 uint32_t dp_ubase;
167
168 uint32_t icw;
169 uint32_t irr;
170 uint32_t ics;
171
172 /* streams */
173 IntelHDAStream st[8];
174
175 /* state */
234bbdf1 176 MemoryRegion mmio;
d61a4ce8
GH		 177 uint32_t rirb_count;
178 int64_t wall_base_ns;
179
180 /* debug logging */
181 const IntelHDAReg *last_reg;
182 uint32_t last_val;
183 uint32_t last_write;
184 uint32_t last_sec;
185 uint32_t repeat_count;
186
187 /* properties */
188 uint32_t debug;
17786d52 189 uint32_t msi;
d61a4ce8
GH		 190};
191
192struct IntelHDAReg {
193 const char *name; /* register name */
194 uint32_t size; /* size in bytes */
195 uint32_t reset; /* reset value */
196 uint32_t wmask; /* write mask */
197 uint32_t wclear; /* write 1 to clear bits */
198 uint32_t offset; /* location in IntelHDAState */
199 uint32_t shift; /* byte access entries for dwords */
200 uint32_t stream;
201 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
202 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
203};
204
205static void intel_hda_reset(DeviceState *dev);
206
207/* --------------------------------------------------------------------- */
208
209static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
210{
211 target_phys_addr_t addr;
212
213#if TARGET_PHYS_ADDR_BITS == 32
214 addr = lbase;
215#else
216 addr = ubase;
217 addr <<= 32;
218 addr |= lbase;
219#endif
220 return addr;
221}
222
d61a4ce8
GH		 223static void intel_hda_update_int_sts(IntelHDAState *d)
224{
225 uint32_t sts = 0;
226 uint32_t i;
227
228 /* update controller status */
229 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
230 sts |= (1 << 30);
231 }
232 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
233 sts |= (1 << 30);
234 }
af93485c 235 if (d->state_sts & d->wake_en) {
d61a4ce8
GH		 236 sts |= (1 << 30);
237 }
238
239 /* update stream status */
240 for (i = 0; i < 8; i++) {
241 /* buffer completion interrupt */
242 if (d->st[i].ctl & (1 << 26)) {
243 sts |= (1 << i);
244 }
245 }
246
247 /* update global status */
248 if (sts & d->int_ctl) {
249 sts |= (1 << 31);
250 }
251
252 d->int_sts = sts;
253}
254
255static void intel_hda_update_irq(IntelHDAState *d)
256{
17786d52 257 int msi = d->msi && msi_enabled(&d->pci);
d61a4ce8
GH		 258 int level;
259
260 intel_hda_update_int_sts(d);
261 if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
262 level = 1;
263 } else {
264 level = 0;
265 }
17786d52
GH		 266 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
267 level, msi ? "msi" : "intx");
268 if (msi) {
269 if (level) {
270 msi_notify(&d->pci, 0);
271 }
272 } else {
273 qemu_set_irq(d->pci.irq[0], level);
274 }
d61a4ce8
GH		 275}
276
277static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
278{
279 uint32_t cad, nid, data;
280 HDACodecDevice *codec;
dbaa7904 281 HDACodecDeviceClass *cdc;
d61a4ce8
GH		 282
283 cad = (verb >> 28) & 0x0f;
284 if (verb & (1 << 27)) {
285 /* indirect node addressing, not specified in HDA 1.0 */
286 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
287 return -1;
288 }
289 nid = (verb >> 20) & 0x7f;
290 data = verb & 0xfffff;
291
292 codec = hda_codec_find(&d->codecs, cad);
293 if (codec == NULL) {
294 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
295 return -1;
296 }
dbaa7904
AL		 297 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
298 cdc->command(codec, nid, data);
d61a4ce8
GH		 299 return 0;
300}
301
302static void intel_hda_corb_run(IntelHDAState *d)
303{
304 target_phys_addr_t addr;
305 uint32_t rp, verb;
306
307 if (d->ics & ICH6_IRS_BUSY) {
308 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
309 intel_hda_send_command(d, d->icw);
310 return;
311 }
312
313 for (;;) {
314 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
315 dprint(d, 2, "%s: !run\n", __FUNCTION__);
316 return;
317 }
318 if ((d->corb_rp & 0xff) == d->corb_wp) {
319 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
320 return;
321 }
322 if (d->rirb_count == d->rirb_cnt) {
323 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
324 return;
325 }
326
327 rp = (d->corb_rp + 1) & 0xff;
328 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
fa0ce55c 329 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
d61a4ce8
GH		 330 d->corb_rp = rp;
331
332 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
333 intel_hda_send_command(d, verb);
334 }
335}
336
337static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
338{
339 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
340 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
341 target_phys_addr_t addr;
342 uint32_t wp, ex;
343
344 if (d->ics & ICH6_IRS_BUSY) {
345 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
346 __FUNCTION__, response, dev->cad);
347 d->irr = response;
348 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
349 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
350 return;
351 }
352
353 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
354 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
355 return;
356 }
357
358 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
359 wp = (d->rirb_wp + 1) & 0xff;
360 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
fa0ce55c
DG		 361 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
362 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
d61a4ce8
GH		 363 d->rirb_wp = wp;
364
365 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
366 __FUNCTION__, wp, response, ex);
367
368 d->rirb_count++;
369 if (d->rirb_count == d->rirb_cnt) {
370 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
371 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
372 d->rirb_sts |= ICH6_RBSTS_IRQ;
373 intel_hda_update_irq(d);
374 }
375 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
376 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
377 d->rirb_count, d->rirb_cnt);
378 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
379 d->rirb_sts |= ICH6_RBSTS_IRQ;
380 intel_hda_update_irq(d);
381 }
382 }
383}
384
385static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
386 uint8_t *buf, uint32_t len)
387{
388 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
389 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
d61a4ce8
GH		 390 target_phys_addr_t addr;
391 uint32_t s, copy, left;
36ac4ad3 392 IntelHDAStream *st;
d61a4ce8
GH		 393 bool irq = false;
394
36ac4ad3
MAL		 395 st = output ? d->st + 4 : d->st;
396 for (s = 0; s < 4; s++) {
397 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
398 st = st + s;
d61a4ce8
GH		 399 break;
400 }
401 }
18ebcc86 402 if (s == 4) {
d61a4ce8
GH		 403 return false;
404 }
405 if (st->bpl == NULL) {
406 return false;
407 }
408 if (st->ctl & (1 << 26)) {
409 /*
410 * Wait with the next DMA xfer until the guest
411 * has acked the buffer completion interrupt
412 */
413 return false;
414 }
415
416 left = len;
417 while (left > 0) {
418 copy = left;
419 if (copy > st->bsize - st->lpib)
420 copy = st->bsize - st->lpib;
421 if (copy > st->bpl[st->be].len - st->bp)
422 copy = st->bpl[st->be].len - st->bp;
423
424 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
425 st->be, st->bp, st->bpl[st->be].len, copy);
426
fa0ce55c 427 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
d61a4ce8
GH		 428 st->lpib += copy;
429 st->bp += copy;
430 buf += copy;
431 left -= copy;
432
433 if (st->bpl[st->be].len == st->bp) {
434 /* bpl entry filled */
435 if (st->bpl[st->be].flags & 0x01) {
436 irq = true;
437 }
438 st->bp = 0;
439 st->be++;
440 if (st->be == st->bentries) {
441 /* bpl wrap around */
442 st->be = 0;
443 st->lpib = 0;
444 }
445 }
446 }
447 if (d->dp_lbase & 0x01) {
448 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
fa0ce55c 449 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
d61a4ce8
GH		 450 }
451 dprint(d, 3, "dma: --\n");
452
453 if (irq) {
454 st->ctl |= (1 << 26); /* buffer completion interrupt */
455 intel_hda_update_irq(d);
456 }
457 return true;
458}
459
460static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
461{
462 target_phys_addr_t addr;
463 uint8_t buf[16];
464 uint32_t i;
465
466 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
467 st->bentries = st->lvi +1;
7267c094
AL		 468 g_free(st->bpl);
469 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
d61a4ce8 470 for (i = 0; i < st->bentries; i++, addr += 16) {
fa0ce55c 471 pci_dma_read(&d->pci, addr, buf, 16);
d61a4ce8
GH		 472 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
473 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
474 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
475 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
476 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
477 }
478
479 st->bsize = st->cbl;
480 st->lpib = 0;
481 st->be = 0;
482 st->bp = 0;
483}
484
ba43d289 485static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
d61a4ce8 486{
0866aca1 487 BusChild *kid;
d61a4ce8
GH		 488 HDACodecDevice *cdev;
489
0866aca1
AL		 490 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
491 DeviceState *qdev = kid->child;
dbaa7904
AL		 492 HDACodecDeviceClass *cdc;
493
d61a4ce8 494 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904
AL		 495 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
496 if (cdc->stream) {
497 cdc->stream(cdev, stream, running, output);
d61a4ce8
GH		 498 }
499 }
500}
501
502/* --------------------------------------------------------------------- */
503
504static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
505{
506 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
507 intel_hda_reset(&d->pci.qdev);
508 }
509}
510
6a0d02f5
GH		 511static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
512{
513 intel_hda_update_irq(d);
514}
515
d61a4ce8
GH		 516static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
517{
518 intel_hda_update_irq(d);
519}
520
521static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
522{
523 intel_hda_update_irq(d);
524}
525
526static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
527{
528 int64_t ns;
529
530 ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
531 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
532}
533
534static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
535{
536 intel_hda_corb_run(d);
537}
538
539static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
540{
541 intel_hda_corb_run(d);
542}
543
544static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
545{
546 if (d->rirb_wp & ICH6_RIRBWP_RST) {
547 d->rirb_wp = 0;
548 }
549}
550
551static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
552{
553 intel_hda_update_irq(d);
554
555 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
556 /* cleared ICH6_RBSTS_IRQ */
557 d->rirb_count = 0;
558 intel_hda_corb_run(d);
559 }
560}
561
562static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
563{
564 if (d->ics & ICH6_IRS_BUSY) {
565 intel_hda_corb_run(d);
566 }
567}
568
569static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
570{
ba43d289 571 bool output = reg->stream >= 4;
d61a4ce8
GH		 572 IntelHDAStream *st = d->st + reg->stream;
573
574 if (st->ctl & 0x01) {
575 /* reset */
576 dprint(d, 1, "st #%d: reset\n", reg->stream);
577 st->ctl = 0;
578 }
579 if ((st->ctl & 0x02) != (old & 0x02)) {
580 uint32_t stnr = (st->ctl >> 20) & 0x0f;
581 /* run bit flipped */
582 if (st->ctl & 0x02) {
583 /* start */
584 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
585 reg->stream, stnr, st->cbl);
586 intel_hda_parse_bdl(d, st);
ba43d289 587 intel_hda_notify_codecs(d, stnr, true, output);
d61a4ce8
GH		 588 } else {
589 /* stop */
590 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
ba43d289 591 intel_hda_notify_codecs(d, stnr, false, output);
d61a4ce8
GH		 592 }
593 }
594 intel_hda_update_irq(d);
595}
596
597/* --------------------------------------------------------------------- */
598
599#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
600
601static const struct IntelHDAReg regtab[] = {
602 /* global */
603 [ ICH6_REG_GCAP ] = {
604 .name = "GCAP",
605 .size = 2,
606 .reset = 0x4401,
607 },
608 [ ICH6_REG_VMIN ] = {
609 .name = "VMIN",
610 .size = 1,
611 },
612 [ ICH6_REG_VMAJ ] = {
613 .name = "VMAJ",
614 .size = 1,
615 .reset = 1,
616 },
617 [ ICH6_REG_OUTPAY ] = {
618 .name = "OUTPAY",
619 .size = 2,
620 .reset = 0x3c,
621 },
622 [ ICH6_REG_INPAY ] = {
623 .name = "INPAY",
624 .size = 2,
625 .reset = 0x1d,
626 },
627 [ ICH6_REG_GCTL ] = {
628 .name = "GCTL",
629 .size = 4,
630 .wmask = 0x0103,
631 .offset = offsetof(IntelHDAState, g_ctl),
632 .whandler = intel_hda_set_g_ctl,
633 },
634 [ ICH6_REG_WAKEEN ] = {
635 .name = "WAKEEN",
636 .size = 2,
df0db221 637 .wmask = 0x7fff,
d61a4ce8 638 .offset = offsetof(IntelHDAState, wake_en),
6a0d02f5 639 .whandler = intel_hda_set_wake_en,
d61a4ce8
GH		 640 },
641 [ ICH6_REG_STATESTS ] = {
642 .name = "STATESTS",
643 .size = 2,
df0db221
GH		 644 .wmask = 0x7fff,
645 .wclear = 0x7fff,
d61a4ce8
GH		 646 .offset = offsetof(IntelHDAState, state_sts),
647 .whandler = intel_hda_set_state_sts,
648 },
649
650 /* interrupts */
651 [ ICH6_REG_INTCTL ] = {
652 .name = "INTCTL",
653 .size = 4,
654 .wmask = 0xc00000ff,
655 .offset = offsetof(IntelHDAState, int_ctl),
656 .whandler = intel_hda_set_int_ctl,
657 },
658 [ ICH6_REG_INTSTS ] = {
659 .name = "INTSTS",
660 .size = 4,
661 .wmask = 0xc00000ff,
662 .wclear = 0xc00000ff,
663 .offset = offsetof(IntelHDAState, int_sts),
664 },
665
666 /* misc */
667 [ ICH6_REG_WALLCLK ] = {
668 .name = "WALLCLK",
669 .size = 4,
670 .offset = offsetof(IntelHDAState, wall_clk),
671 .rhandler = intel_hda_get_wall_clk,
672 },
673 [ ICH6_REG_WALLCLK + 0x2000 ] = {
674 .name = "WALLCLK(alias)",
675 .size = 4,
676 .offset = offsetof(IntelHDAState, wall_clk),
677 .rhandler = intel_hda_get_wall_clk,
678 },
679
680 /* dma engine */
681 [ ICH6_REG_CORBLBASE ] = {
682 .name = "CORBLBASE",
683 .size = 4,
684 .wmask = 0xffffff80,
685 .offset = offsetof(IntelHDAState, corb_lbase),
686 },
687 [ ICH6_REG_CORBUBASE ] = {
688 .name = "CORBUBASE",
689 .size = 4,
690 .wmask = 0xffffffff,
691 .offset = offsetof(IntelHDAState, corb_ubase),
692 },
693 [ ICH6_REG_CORBWP ] = {
694 .name = "CORBWP",
695 .size = 2,
696 .wmask = 0xff,
697 .offset = offsetof(IntelHDAState, corb_wp),
698 .whandler = intel_hda_set_corb_wp,
699 },
700 [ ICH6_REG_CORBRP ] = {
701 .name = "CORBRP",
702 .size = 2,
703 .wmask = 0x80ff,
704 .offset = offsetof(IntelHDAState, corb_rp),
705 },
706 [ ICH6_REG_CORBCTL ] = {
707 .name = "CORBCTL",
708 .size = 1,
709 .wmask = 0x03,
710 .offset = offsetof(IntelHDAState, corb_ctl),
711 .whandler = intel_hda_set_corb_ctl,
712 },
713 [ ICH6_REG_CORBSTS ] = {
714 .name = "CORBSTS",
715 .size = 1,
716 .wmask = 0x01,
717 .wclear = 0x01,
718 .offset = offsetof(IntelHDAState, corb_sts),
719 },
720 [ ICH6_REG_CORBSIZE ] = {
721 .name = "CORBSIZE",
722 .size = 1,
723 .reset = 0x42,
724 .offset = offsetof(IntelHDAState, corb_size),
725 },
726 [ ICH6_REG_RIRBLBASE ] = {
727 .name = "RIRBLBASE",
728 .size = 4,
729 .wmask = 0xffffff80,
730 .offset = offsetof(IntelHDAState, rirb_lbase),
731 },
732 [ ICH6_REG_RIRBUBASE ] = {
733 .name = "RIRBUBASE",
734 .size = 4,
735 .wmask = 0xffffffff,
736 .offset = offsetof(IntelHDAState, rirb_ubase),
737 },
738 [ ICH6_REG_RIRBWP ] = {
739 .name = "RIRBWP",
740 .size = 2,
741 .wmask = 0x8000,
742 .offset = offsetof(IntelHDAState, rirb_wp),
743 .whandler = intel_hda_set_rirb_wp,
744 },
745 [ ICH6_REG_RINTCNT ] = {
746 .name = "RINTCNT",
747 .size = 2,
748 .wmask = 0xff,
749 .offset = offsetof(IntelHDAState, rirb_cnt),
750 },
751 [ ICH6_REG_RIRBCTL ] = {
752 .name = "RIRBCTL",
753 .size = 1,
754 .wmask = 0x07,
755 .offset = offsetof(IntelHDAState, rirb_ctl),
756 },
757 [ ICH6_REG_RIRBSTS ] = {
758 .name = "RIRBSTS",
759 .size = 1,
760 .wmask = 0x05,
761 .wclear = 0x05,
762 .offset = offsetof(IntelHDAState, rirb_sts),
763 .whandler = intel_hda_set_rirb_sts,
764 },
765 [ ICH6_REG_RIRBSIZE ] = {
766 .name = "RIRBSIZE",
767 .size = 1,
768 .reset = 0x42,
769 .offset = offsetof(IntelHDAState, rirb_size),
770 },
771
772 [ ICH6_REG_DPLBASE ] = {
773 .name = "DPLBASE",
774 .size = 4,
775 .wmask = 0xffffff81,
776 .offset = offsetof(IntelHDAState, dp_lbase),
777 },
778 [ ICH6_REG_DPUBASE ] = {
779 .name = "DPUBASE",
780 .size = 4,
781 .wmask = 0xffffffff,
782 .offset = offsetof(IntelHDAState, dp_ubase),
783 },
784
785 [ ICH6_REG_IC ] = {
786 .name = "ICW",
787 .size = 4,
788 .wmask = 0xffffffff,
789 .offset = offsetof(IntelHDAState, icw),
790 },
791 [ ICH6_REG_IR ] = {
792 .name = "IRR",
793 .size = 4,
794 .offset = offsetof(IntelHDAState, irr),
795 },
796 [ ICH6_REG_IRS ] = {
797 .name = "ICS",
798 .size = 2,
799 .wmask = 0x0003,
800 .wclear = 0x0002,
801 .offset = offsetof(IntelHDAState, ics),
802 .whandler = intel_hda_set_ics,
803 },
804
805#define HDA_STREAM(_t, _i) \
806 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
807 .stream = _i, \
808 .name = _t stringify(_i) " CTL", \
809 .size = 4, \
810 .wmask = 0x1cff001f, \
811 .offset = offsetof(IntelHDAState, st[_i].ctl), \
812 .whandler = intel_hda_set_st_ctl, \
813 }, \
814 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
815 .stream = _i, \
816 .name = _t stringify(_i) " CTL(stnr)", \
817 .size = 1, \
818 .shift = 16, \
819 .wmask = 0x00ff0000, \
820 .offset = offsetof(IntelHDAState, st[_i].ctl), \
821 .whandler = intel_hda_set_st_ctl, \
822 }, \
823 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
824 .stream = _i, \
825 .name = _t stringify(_i) " CTL(sts)", \
826 .size = 1, \
827 .shift = 24, \
828 .wmask = 0x1c000000, \
829 .wclear = 0x1c000000, \
830 .offset = offsetof(IntelHDAState, st[_i].ctl), \
831 .whandler = intel_hda_set_st_ctl, \
832 }, \
833 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
834 .stream = _i, \
835 .name = _t stringify(_i) " LPIB", \
836 .size = 4, \
837 .offset = offsetof(IntelHDAState, st[_i].lpib), \
838 }, \
839 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
840 .stream = _i, \
841 .name = _t stringify(_i) " LPIB(alias)", \
842 .size = 4, \
843 .offset = offsetof(IntelHDAState, st[_i].lpib), \
844 }, \
845 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
846 .stream = _i, \
847 .name = _t stringify(_i) " CBL", \
848 .size = 4, \
849 .wmask = 0xffffffff, \
850 .offset = offsetof(IntelHDAState, st[_i].cbl), \
851 }, \
852 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
853 .stream = _i, \
854 .name = _t stringify(_i) " LVI", \
855 .size = 2, \
856 .wmask = 0x00ff, \
857 .offset = offsetof(IntelHDAState, st[_i].lvi), \
858 }, \
859 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
860 .stream = _i, \
861 .name = _t stringify(_i) " FIFOS", \
862 .size = 2, \
863 .reset = HDA_BUFFER_SIZE, \
864 }, \
865 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
866 .stream = _i, \
867 .name = _t stringify(_i) " FMT", \
868 .size = 2, \
869 .wmask = 0x7f7f, \
870 .offset = offsetof(IntelHDAState, st[_i].fmt), \
871 }, \
872 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
873 .stream = _i, \
874 .name = _t stringify(_i) " BDLPL", \
875 .size = 4, \
876 .wmask = 0xffffff80, \
877 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
878 }, \
879 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
880 .stream = _i, \
881 .name = _t stringify(_i) " BDLPU", \
882 .size = 4, \
883 .wmask = 0xffffffff, \
884 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
885 }, \
886
887 HDA_STREAM("IN", 0)
888 HDA_STREAM("IN", 1)
889 HDA_STREAM("IN", 2)
890 HDA_STREAM("IN", 3)
891
892 HDA_STREAM("OUT", 4)
893 HDA_STREAM("OUT", 5)
894 HDA_STREAM("OUT", 6)
895 HDA_STREAM("OUT", 7)
896
897};
898
899static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
900{
901 const IntelHDAReg *reg;
902
903 if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
904 goto noreg;
905 }
906 reg = regtab+addr;
907 if (reg->name == NULL) {
908 goto noreg;
909 }
910 return reg;
911
912noreg:
913 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
914 return NULL;
915}
916
917static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
918{
919 uint8_t *addr = (void*)d;
920
921 addr += reg->offset;
922 return (uint32_t*)addr;
923}
924
925static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
926 uint32_t wmask)
927{
928 uint32_t *addr;
929 uint32_t old;
930
931 if (!reg) {
932 return;
933 }
934
935 if (d->debug) {
936 time_t now = time(NULL);
937 if (d->last_write && d->last_reg == reg && d->last_val == val) {
938 d->repeat_count++;
939 if (d->last_sec != now) {
940 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
941 d->last_sec = now;
942 d->repeat_count = 0;
943 }
944 } else {
945 if (d->repeat_count) {
946 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
947 }
948 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
949 d->last_write = 1;
950 d->last_reg = reg;
951 d->last_val = val;
952 d->last_sec = now;
953 d->repeat_count = 0;
954 }
955 }
956 assert(reg->offset != 0);
957
958 addr = intel_hda_reg_addr(d, reg);
959 old = *addr;
960
961 if (reg->shift) {
962 val <<= reg->shift;
963 wmask <<= reg->shift;
964 }
965 wmask &= reg->wmask;
966 *addr &= ~wmask;
967 *addr |= wmask & val;
968 *addr &= ~(val & reg->wclear);
969
970 if (reg->whandler) {
971 reg->whandler(d, reg, old);
972 }
973}
974
975static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
976 uint32_t rmask)
977{
978 uint32_t *addr, ret;
979
980 if (!reg) {
981 return 0;
982 }
983
984 if (reg->rhandler) {
985 reg->rhandler(d, reg);
986 }
987
988 if (reg->offset == 0) {
989 /* constant read-only register */
990 ret = reg->reset;
991 } else {
992 addr = intel_hda_reg_addr(d, reg);
993 ret = *addr;
994 if (reg->shift) {
995 ret >>= reg->shift;
996 }
997 ret &= rmask;
998 }
999 if (d->debug) {
1000 time_t now = time(NULL);
1001 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1002 d->repeat_count++;
1003 if (d->last_sec != now) {
1004 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1005 d->last_sec = now;
1006 d->repeat_count = 0;
1007 }
1008 } else {
1009 if (d->repeat_count) {
1010 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1011 }
1012 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1013 d->last_write = 0;
1014 d->last_reg = reg;
1015 d->last_val = ret;
1016 d->last_sec = now;
1017 d->repeat_count = 0;
1018 }
1019 }
1020 return ret;
1021}
1022
1023static void intel_hda_regs_reset(IntelHDAState *d)
1024{
1025 uint32_t *addr;
1026 int i;
1027
1028 for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1029 if (regtab[i].name == NULL) {
1030 continue;
1031 }
1032 if (regtab[i].offset == 0) {
1033 continue;
1034 }
1035 addr = intel_hda_reg_addr(d, regtab + i);
1036 *addr = regtab[i].reset;
1037 }
1038}
1039
1040/* --------------------------------------------------------------------- */
1041
1042static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1043{
1044 IntelHDAState *d = opaque;
1045 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1046
1047 intel_hda_reg_write(d, reg, val, 0xff);
1048}
1049
1050static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1051{
1052 IntelHDAState *d = opaque;
1053 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1054
1055 intel_hda_reg_write(d, reg, val, 0xffff);
1056}
1057
1058static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1059{
1060 IntelHDAState *d = opaque;
1061 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1062
1063 intel_hda_reg_write(d, reg, val, 0xffffffff);
1064}
1065
1066static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1067{
1068 IntelHDAState *d = opaque;
1069 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1070
1071 return intel_hda_reg_read(d, reg, 0xff);
1072}
1073
1074static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1075{
1076 IntelHDAState *d = opaque;
1077 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1078
1079 return intel_hda_reg_read(d, reg, 0xffff);
1080}
1081
1082static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1083{
1084 IntelHDAState *d = opaque;
1085 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1086
1087 return intel_hda_reg_read(d, reg, 0xffffffff);
1088}
1089
234bbdf1
AK		 1090static const MemoryRegionOps intel_hda_mmio_ops = {
1091 .old_mmio = {
1092 .read = {
1093 intel_hda_mmio_readb,
1094 intel_hda_mmio_readw,
1095 intel_hda_mmio_readl,
1096 },
1097 .write = {
1098 intel_hda_mmio_writeb,
1099 intel_hda_mmio_writew,
1100 intel_hda_mmio_writel,
1101 },
1102 },
1103 .endianness = DEVICE_NATIVE_ENDIAN,
d61a4ce8
GH		 1104};
1105
d61a4ce8
GH		 1106/* --------------------------------------------------------------------- */
1107
1108static void intel_hda_reset(DeviceState *dev)
1109{
0866aca1 1110 BusChild *kid;
d61a4ce8 1111 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
d61a4ce8
GH		 1112 HDACodecDevice *cdev;
1113
1114 intel_hda_regs_reset(d);
74475455 1115 d->wall_base_ns = qemu_get_clock_ns(vm_clock);
d61a4ce8
GH		 1116
1117 /* reset codecs */
0866aca1
AL		 1118 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1119 DeviceState *qdev = kid->child;
d61a4ce8 1120 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
94afdadc 1121 device_reset(DEVICE(cdev));
d61a4ce8
GH		 1122 d->state_sts |= (1 << cdev->cad);
1123 }
1124 intel_hda_update_irq(d);
1125}
1126
1127static int intel_hda_init(PCIDevice *pci)
1128{
1129 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1130 uint8_t *conf = d->pci.config;
1131
f79f2bfc 1132 d->name = object_get_typename(OBJECT(d));
d61a4ce8 1133
d61a4ce8
GH		 1134 pci_config_set_interrupt_pin(conf, 1);
1135
1136 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1137 conf[0x40] = 0x01;
1138
234bbdf1
AK		 1139 memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
1140 "intel-hda", 0x4000);
e824b2cc 1141 pci_register_bar(&d->pci, 0, 0, &d->mmio);
17786d52
GH		 1142 if (d->msi) {
1143 msi_init(&d->pci, 0x50, 1, true, false);
1144 }
d61a4ce8
GH		 1145
1146 hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1147 intel_hda_response, intel_hda_xfer);
1148
1149 return 0;
1150}
1151
f90c2bcd 1152static void intel_hda_exit(PCIDevice *pci)
dc4b9240
GH		 1153{
1154 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1155
45fe15c2 1156 msi_uninit(&d->pci);
234bbdf1 1157 memory_region_destroy(&d->mmio);
dc4b9240
GH		 1158}
1159
d61a4ce8
GH		 1160static int intel_hda_post_load(void *opaque, int version)
1161{
1162 IntelHDAState* d = opaque;
1163 int i;
1164
1165 dprint(d, 1, "%s\n", __FUNCTION__);
1166 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1167 if (d->st[i].ctl & 0x02) {
1168 intel_hda_parse_bdl(d, &d->st[i]);
1169 }
1170 }
1171 intel_hda_update_irq(d);
1172 return 0;
1173}
1174
1175static const VMStateDescription vmstate_intel_hda_stream = {
1176 .name = "intel-hda-stream",
1177 .version_id = 1,
1178 .fields = (VMStateField []) {
1179 VMSTATE_UINT32(ctl, IntelHDAStream),
1180 VMSTATE_UINT32(lpib, IntelHDAStream),
1181 VMSTATE_UINT32(cbl, IntelHDAStream),
1182 VMSTATE_UINT32(lvi, IntelHDAStream),
1183 VMSTATE_UINT32(fmt, IntelHDAStream),
1184 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1185 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1186 VMSTATE_END_OF_LIST()
1187 }
1188};
1189
1190static const VMStateDescription vmstate_intel_hda = {
1191 .name = "intel-hda",
1192 .version_id = 1,
1193 .post_load = intel_hda_post_load,
1194 .fields = (VMStateField []) {
1195 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1196
1197 /* registers */
1198 VMSTATE_UINT32(g_ctl, IntelHDAState),
1199 VMSTATE_UINT32(wake_en, IntelHDAState),
1200 VMSTATE_UINT32(state_sts, IntelHDAState),
1201 VMSTATE_UINT32(int_ctl, IntelHDAState),
1202 VMSTATE_UINT32(int_sts, IntelHDAState),
1203 VMSTATE_UINT32(wall_clk, IntelHDAState),
1204 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1205 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1206 VMSTATE_UINT32(corb_rp, IntelHDAState),
1207 VMSTATE_UINT32(corb_wp, IntelHDAState),
1208 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1209 VMSTATE_UINT32(corb_sts, IntelHDAState),
1210 VMSTATE_UINT32(corb_size, IntelHDAState),
1211 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1212 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1213 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1214 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1215 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1216 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1217 VMSTATE_UINT32(rirb_size, IntelHDAState),
1218 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1219 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1220 VMSTATE_UINT32(icw, IntelHDAState),
1221 VMSTATE_UINT32(irr, IntelHDAState),
1222 VMSTATE_UINT32(ics, IntelHDAState),
1223 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1224 vmstate_intel_hda_stream,
1225 IntelHDAStream),
1226
1227 /* additional state info */
1228 VMSTATE_UINT32(rirb_count, IntelHDAState),
1229 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1230
1231 VMSTATE_END_OF_LIST()
1232 }
1233};
1234
40021f08
AL		 1235static Property intel_hda_properties[] = {
1236 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1237 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1238 DEFINE_PROP_END_OF_LIST(),
1239};
1240
1241static void intel_hda_class_init(ObjectClass *klass, void *data)
1242{
39bffca2 1243 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1244 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1245
1246 k->init = intel_hda_init;
1247 k->exit = intel_hda_exit;
40021f08
AL		 1248 k->vendor_id = PCI_VENDOR_ID_INTEL;
1249 k->device_id = 0x2668;
1250 k->revision = 1;
1251 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
39bffca2
AL		 1252 dc->desc = "Intel HD Audio Controller";
1253 dc->reset = intel_hda_reset;
1254 dc->vmsd = &vmstate_intel_hda;
1255 dc->props = intel_hda_properties;
40021f08
AL		 1256}
1257
39bffca2
AL		 1258static TypeInfo intel_hda_info = {
1259 .name = "intel-hda",
1260 .parent = TYPE_PCI_DEVICE,
1261 .instance_size = sizeof(IntelHDAState),
1262 .class_init = intel_hda_class_init,
40021f08
AL		 1263};
1264
39bffca2
AL		 1265static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1266{
1267 DeviceClass *k = DEVICE_CLASS(klass);
1268 k->init = hda_codec_dev_init;
1269 k->exit = hda_codec_dev_exit;
0d936928 1270 k->bus_type = TYPE_HDA_BUS;
bce54474 1271 k->props = hda_props;
39bffca2
AL		 1272}
1273
40021f08
AL		 1274static TypeInfo hda_codec_device_type_info = {
1275 .name = TYPE_HDA_CODEC_DEVICE,
1276 .parent = TYPE_DEVICE,
1277 .instance_size = sizeof(HDACodecDevice),
1278 .abstract = true,
1279 .class_size = sizeof(HDACodecDeviceClass),
39bffca2 1280 .class_init = hda_codec_device_class_init,
d61a4ce8
GH		 1281};
1282
83f7d43a 1283static void intel_hda_register_types(void)
d61a4ce8 1284{
0d936928 1285 type_register_static(&hda_codec_bus_info);
39bffca2 1286 type_register_static(&intel_hda_info);
40021f08 1287 type_register_static(&hda_codec_device_type_info);
d61a4ce8 1288}
83f7d43a
AF		 1289
1290type_init(intel_hda_register_types)
d61a4ce8
GH		 1291
1292/*
1293 * create intel hda controller with codec attached to it,
1294 * so '-soundhw hda' works.
1295 */
1296int intel_hda_and_codec_init(PCIBus *bus)
1297{
1298 PCIDevice *controller;
1299 BusState *hdabus;
1300 DeviceState *codec;
1301
1302 controller = pci_create_simple(bus, -1, "intel-hda");
1303 hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1304 codec = qdev_create(hdabus, "hda-duplex");
1305 qdev_init_nofail(codec);
1306 return 0;
1307}
1308
Qemu copy for testing