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d61a4ce8 GH |
1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Gerd Hoffmann <kraxel@redhat.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 or | |
9 | * (at your option) version 3 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "hw.h" | |
21 | #include "pci.h" | |
17786d52 | 22 | #include "msi.h" |
d61a4ce8 GH |
23 | #include "qemu-timer.h" |
24 | #include "audiodev.h" | |
25 | #include "intel-hda.h" | |
26 | #include "intel-hda-defs.h" | |
fa0ce55c | 27 | #include "dma.h" |
d61a4ce8 GH |
28 | |
29 | /* --------------------------------------------------------------------- */ | |
30 | /* hda bus */ | |
31 | ||
32 | static struct BusInfo hda_codec_bus_info = { | |
33 | .name = "HDA", | |
34 | .size = sizeof(HDACodecBus), | |
35 | .props = (Property[]) { | |
36 | DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), | |
37 | DEFINE_PROP_END_OF_LIST() | |
38 | } | |
39 | }; | |
40 | ||
41 | void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, | |
42 | hda_codec_response_func response, | |
43 | hda_codec_xfer_func xfer) | |
44 | { | |
45 | qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL); | |
46 | bus->response = response; | |
47 | bus->xfer = xfer; | |
48 | } | |
49 | ||
50 | static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base) | |
51 | { | |
52 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); | |
53 | HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); | |
dbaa7904 | 54 | HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); |
d61a4ce8 | 55 | |
d61a4ce8 GH |
56 | if (dev->cad == -1) { |
57 | dev->cad = bus->next_cad; | |
58 | } | |
df0db221 | 59 | if (dev->cad >= 15) { |
d61a4ce8 | 60 | return -1; |
df0db221 | 61 | } |
d61a4ce8 | 62 | bus->next_cad = dev->cad + 1; |
dbaa7904 | 63 | return cdc->init(dev); |
d61a4ce8 GH |
64 | } |
65 | ||
dc4b9240 GH |
66 | static int hda_codec_dev_exit(DeviceState *qdev) |
67 | { | |
68 | HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); | |
dbaa7904 | 69 | HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); |
dc4b9240 | 70 | |
dbaa7904 AL |
71 | if (cdc->exit) { |
72 | cdc->exit(dev); | |
dc4b9240 GH |
73 | } |
74 | return 0; | |
75 | } | |
76 | ||
dbaa7904 | 77 | void hda_codec_register(DeviceInfo *info) |
d61a4ce8 | 78 | { |
dbaa7904 AL |
79 | info->init = hda_codec_dev_init; |
80 | info->exit = hda_codec_dev_exit; | |
81 | info->bus_info = &hda_codec_bus_info; | |
82 | qdev_register(info); | |
d61a4ce8 GH |
83 | } |
84 | ||
85 | HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) | |
86 | { | |
87 | DeviceState *qdev; | |
88 | HDACodecDevice *cdev; | |
89 | ||
d8bb00d6 | 90 | QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) { |
d61a4ce8 GH |
91 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
92 | if (cdev->cad == cad) { | |
93 | return cdev; | |
94 | } | |
95 | } | |
96 | return NULL; | |
97 | } | |
98 | ||
99 | void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) | |
100 | { | |
101 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
102 | bus->response(dev, solicited, response); | |
103 | } | |
104 | ||
105 | bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, | |
106 | uint8_t *buf, uint32_t len) | |
107 | { | |
108 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
109 | return bus->xfer(dev, stnr, output, buf, len); | |
110 | } | |
111 | ||
112 | /* --------------------------------------------------------------------- */ | |
113 | /* intel hda emulation */ | |
114 | ||
115 | typedef struct IntelHDAStream IntelHDAStream; | |
116 | typedef struct IntelHDAState IntelHDAState; | |
117 | typedef struct IntelHDAReg IntelHDAReg; | |
118 | ||
119 | typedef struct bpl { | |
120 | uint64_t addr; | |
121 | uint32_t len; | |
122 | uint32_t flags; | |
123 | } bpl; | |
124 | ||
125 | struct IntelHDAStream { | |
126 | /* registers */ | |
127 | uint32_t ctl; | |
128 | uint32_t lpib; | |
129 | uint32_t cbl; | |
130 | uint32_t lvi; | |
131 | uint32_t fmt; | |
132 | uint32_t bdlp_lbase; | |
133 | uint32_t bdlp_ubase; | |
134 | ||
135 | /* state */ | |
136 | bpl *bpl; | |
137 | uint32_t bentries; | |
138 | uint32_t bsize, be, bp; | |
139 | }; | |
140 | ||
141 | struct IntelHDAState { | |
142 | PCIDevice pci; | |
143 | const char *name; | |
144 | HDACodecBus codecs; | |
145 | ||
146 | /* registers */ | |
147 | uint32_t g_ctl; | |
148 | uint32_t wake_en; | |
149 | uint32_t state_sts; | |
150 | uint32_t int_ctl; | |
151 | uint32_t int_sts; | |
152 | uint32_t wall_clk; | |
153 | ||
154 | uint32_t corb_lbase; | |
155 | uint32_t corb_ubase; | |
156 | uint32_t corb_rp; | |
157 | uint32_t corb_wp; | |
158 | uint32_t corb_ctl; | |
159 | uint32_t corb_sts; | |
160 | uint32_t corb_size; | |
161 | ||
162 | uint32_t rirb_lbase; | |
163 | uint32_t rirb_ubase; | |
164 | uint32_t rirb_wp; | |
165 | uint32_t rirb_cnt; | |
166 | uint32_t rirb_ctl; | |
167 | uint32_t rirb_sts; | |
168 | uint32_t rirb_size; | |
169 | ||
170 | uint32_t dp_lbase; | |
171 | uint32_t dp_ubase; | |
172 | ||
173 | uint32_t icw; | |
174 | uint32_t irr; | |
175 | uint32_t ics; | |
176 | ||
177 | /* streams */ | |
178 | IntelHDAStream st[8]; | |
179 | ||
180 | /* state */ | |
234bbdf1 | 181 | MemoryRegion mmio; |
d61a4ce8 GH |
182 | uint32_t rirb_count; |
183 | int64_t wall_base_ns; | |
184 | ||
185 | /* debug logging */ | |
186 | const IntelHDAReg *last_reg; | |
187 | uint32_t last_val; | |
188 | uint32_t last_write; | |
189 | uint32_t last_sec; | |
190 | uint32_t repeat_count; | |
191 | ||
192 | /* properties */ | |
193 | uint32_t debug; | |
17786d52 | 194 | uint32_t msi; |
d61a4ce8 GH |
195 | }; |
196 | ||
197 | struct IntelHDAReg { | |
198 | const char *name; /* register name */ | |
199 | uint32_t size; /* size in bytes */ | |
200 | uint32_t reset; /* reset value */ | |
201 | uint32_t wmask; /* write mask */ | |
202 | uint32_t wclear; /* write 1 to clear bits */ | |
203 | uint32_t offset; /* location in IntelHDAState */ | |
204 | uint32_t shift; /* byte access entries for dwords */ | |
205 | uint32_t stream; | |
206 | void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); | |
207 | void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); | |
208 | }; | |
209 | ||
210 | static void intel_hda_reset(DeviceState *dev); | |
211 | ||
212 | /* --------------------------------------------------------------------- */ | |
213 | ||
214 | static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase) | |
215 | { | |
216 | target_phys_addr_t addr; | |
217 | ||
218 | #if TARGET_PHYS_ADDR_BITS == 32 | |
219 | addr = lbase; | |
220 | #else | |
221 | addr = ubase; | |
222 | addr <<= 32; | |
223 | addr |= lbase; | |
224 | #endif | |
225 | return addr; | |
226 | } | |
227 | ||
d61a4ce8 GH |
228 | static void intel_hda_update_int_sts(IntelHDAState *d) |
229 | { | |
230 | uint32_t sts = 0; | |
231 | uint32_t i; | |
232 | ||
233 | /* update controller status */ | |
234 | if (d->rirb_sts & ICH6_RBSTS_IRQ) { | |
235 | sts |= (1 << 30); | |
236 | } | |
237 | if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { | |
238 | sts |= (1 << 30); | |
239 | } | |
af93485c | 240 | if (d->state_sts & d->wake_en) { |
d61a4ce8 GH |
241 | sts |= (1 << 30); |
242 | } | |
243 | ||
244 | /* update stream status */ | |
245 | for (i = 0; i < 8; i++) { | |
246 | /* buffer completion interrupt */ | |
247 | if (d->st[i].ctl & (1 << 26)) { | |
248 | sts |= (1 << i); | |
249 | } | |
250 | } | |
251 | ||
252 | /* update global status */ | |
253 | if (sts & d->int_ctl) { | |
254 | sts |= (1 << 31); | |
255 | } | |
256 | ||
257 | d->int_sts = sts; | |
258 | } | |
259 | ||
260 | static void intel_hda_update_irq(IntelHDAState *d) | |
261 | { | |
17786d52 | 262 | int msi = d->msi && msi_enabled(&d->pci); |
d61a4ce8 GH |
263 | int level; |
264 | ||
265 | intel_hda_update_int_sts(d); | |
266 | if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) { | |
267 | level = 1; | |
268 | } else { | |
269 | level = 0; | |
270 | } | |
17786d52 GH |
271 | dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__, |
272 | level, msi ? "msi" : "intx"); | |
273 | if (msi) { | |
274 | if (level) { | |
275 | msi_notify(&d->pci, 0); | |
276 | } | |
277 | } else { | |
278 | qemu_set_irq(d->pci.irq[0], level); | |
279 | } | |
d61a4ce8 GH |
280 | } |
281 | ||
282 | static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) | |
283 | { | |
284 | uint32_t cad, nid, data; | |
285 | HDACodecDevice *codec; | |
dbaa7904 | 286 | HDACodecDeviceClass *cdc; |
d61a4ce8 GH |
287 | |
288 | cad = (verb >> 28) & 0x0f; | |
289 | if (verb & (1 << 27)) { | |
290 | /* indirect node addressing, not specified in HDA 1.0 */ | |
291 | dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); | |
292 | return -1; | |
293 | } | |
294 | nid = (verb >> 20) & 0x7f; | |
295 | data = verb & 0xfffff; | |
296 | ||
297 | codec = hda_codec_find(&d->codecs, cad); | |
298 | if (codec == NULL) { | |
299 | dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); | |
300 | return -1; | |
301 | } | |
dbaa7904 AL |
302 | cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); |
303 | cdc->command(codec, nid, data); | |
d61a4ce8 GH |
304 | return 0; |
305 | } | |
306 | ||
307 | static void intel_hda_corb_run(IntelHDAState *d) | |
308 | { | |
309 | target_phys_addr_t addr; | |
310 | uint32_t rp, verb; | |
311 | ||
312 | if (d->ics & ICH6_IRS_BUSY) { | |
313 | dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); | |
314 | intel_hda_send_command(d, d->icw); | |
315 | return; | |
316 | } | |
317 | ||
318 | for (;;) { | |
319 | if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { | |
320 | dprint(d, 2, "%s: !run\n", __FUNCTION__); | |
321 | return; | |
322 | } | |
323 | if ((d->corb_rp & 0xff) == d->corb_wp) { | |
324 | dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); | |
325 | return; | |
326 | } | |
327 | if (d->rirb_count == d->rirb_cnt) { | |
328 | dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); | |
329 | return; | |
330 | } | |
331 | ||
332 | rp = (d->corb_rp + 1) & 0xff; | |
333 | addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); | |
fa0ce55c | 334 | verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); |
d61a4ce8 GH |
335 | d->corb_rp = rp; |
336 | ||
337 | dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); | |
338 | intel_hda_send_command(d, verb); | |
339 | } | |
340 | } | |
341 | ||
342 | static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) | |
343 | { | |
344 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
345 | IntelHDAState *d = container_of(bus, IntelHDAState, codecs); | |
346 | target_phys_addr_t addr; | |
347 | uint32_t wp, ex; | |
348 | ||
349 | if (d->ics & ICH6_IRS_BUSY) { | |
350 | dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", | |
351 | __FUNCTION__, response, dev->cad); | |
352 | d->irr = response; | |
353 | d->ics &= ~(ICH6_IRS_BUSY | 0xf0); | |
354 | d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); | |
355 | return; | |
356 | } | |
357 | ||
358 | if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { | |
359 | dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); | |
360 | return; | |
361 | } | |
362 | ||
363 | ex = (solicited ? 0 : (1 << 4)) | dev->cad; | |
364 | wp = (d->rirb_wp + 1) & 0xff; | |
365 | addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); | |
fa0ce55c DG |
366 | stl_le_pci_dma(&d->pci, addr + 8*wp, response); |
367 | stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); | |
d61a4ce8 GH |
368 | d->rirb_wp = wp; |
369 | ||
370 | dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", | |
371 | __FUNCTION__, wp, response, ex); | |
372 | ||
373 | d->rirb_count++; | |
374 | if (d->rirb_count == d->rirb_cnt) { | |
375 | dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); | |
376 | if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { | |
377 | d->rirb_sts |= ICH6_RBSTS_IRQ; | |
378 | intel_hda_update_irq(d); | |
379 | } | |
380 | } else if ((d->corb_rp & 0xff) == d->corb_wp) { | |
381 | dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, | |
382 | d->rirb_count, d->rirb_cnt); | |
383 | if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { | |
384 | d->rirb_sts |= ICH6_RBSTS_IRQ; | |
385 | intel_hda_update_irq(d); | |
386 | } | |
387 | } | |
388 | } | |
389 | ||
390 | static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, | |
391 | uint8_t *buf, uint32_t len) | |
392 | { | |
393 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
394 | IntelHDAState *d = container_of(bus, IntelHDAState, codecs); | |
d61a4ce8 GH |
395 | target_phys_addr_t addr; |
396 | uint32_t s, copy, left; | |
36ac4ad3 | 397 | IntelHDAStream *st; |
d61a4ce8 GH |
398 | bool irq = false; |
399 | ||
36ac4ad3 MAL |
400 | st = output ? d->st + 4 : d->st; |
401 | for (s = 0; s < 4; s++) { | |
402 | if (stnr == ((st[s].ctl >> 20) & 0x0f)) { | |
403 | st = st + s; | |
d61a4ce8 GH |
404 | break; |
405 | } | |
406 | } | |
18ebcc86 | 407 | if (s == 4) { |
d61a4ce8 GH |
408 | return false; |
409 | } | |
410 | if (st->bpl == NULL) { | |
411 | return false; | |
412 | } | |
413 | if (st->ctl & (1 << 26)) { | |
414 | /* | |
415 | * Wait with the next DMA xfer until the guest | |
416 | * has acked the buffer completion interrupt | |
417 | */ | |
418 | return false; | |
419 | } | |
420 | ||
421 | left = len; | |
422 | while (left > 0) { | |
423 | copy = left; | |
424 | if (copy > st->bsize - st->lpib) | |
425 | copy = st->bsize - st->lpib; | |
426 | if (copy > st->bpl[st->be].len - st->bp) | |
427 | copy = st->bpl[st->be].len - st->bp; | |
428 | ||
429 | dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", | |
430 | st->be, st->bp, st->bpl[st->be].len, copy); | |
431 | ||
fa0ce55c | 432 | pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output); |
d61a4ce8 GH |
433 | st->lpib += copy; |
434 | st->bp += copy; | |
435 | buf += copy; | |
436 | left -= copy; | |
437 | ||
438 | if (st->bpl[st->be].len == st->bp) { | |
439 | /* bpl entry filled */ | |
440 | if (st->bpl[st->be].flags & 0x01) { | |
441 | irq = true; | |
442 | } | |
443 | st->bp = 0; | |
444 | st->be++; | |
445 | if (st->be == st->bentries) { | |
446 | /* bpl wrap around */ | |
447 | st->be = 0; | |
448 | st->lpib = 0; | |
449 | } | |
450 | } | |
451 | } | |
452 | if (d->dp_lbase & 0x01) { | |
453 | addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); | |
fa0ce55c | 454 | stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); |
d61a4ce8 GH |
455 | } |
456 | dprint(d, 3, "dma: --\n"); | |
457 | ||
458 | if (irq) { | |
459 | st->ctl |= (1 << 26); /* buffer completion interrupt */ | |
460 | intel_hda_update_irq(d); | |
461 | } | |
462 | return true; | |
463 | } | |
464 | ||
465 | static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) | |
466 | { | |
467 | target_phys_addr_t addr; | |
468 | uint8_t buf[16]; | |
469 | uint32_t i; | |
470 | ||
471 | addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); | |
472 | st->bentries = st->lvi +1; | |
7267c094 AL |
473 | g_free(st->bpl); |
474 | st->bpl = g_malloc(sizeof(bpl) * st->bentries); | |
d61a4ce8 | 475 | for (i = 0; i < st->bentries; i++, addr += 16) { |
fa0ce55c | 476 | pci_dma_read(&d->pci, addr, buf, 16); |
d61a4ce8 GH |
477 | st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); |
478 | st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); | |
479 | st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); | |
480 | dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", | |
481 | i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); | |
482 | } | |
483 | ||
484 | st->bsize = st->cbl; | |
485 | st->lpib = 0; | |
486 | st->be = 0; | |
487 | st->bp = 0; | |
488 | } | |
489 | ||
ba43d289 | 490 | static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) |
d61a4ce8 GH |
491 | { |
492 | DeviceState *qdev; | |
493 | HDACodecDevice *cdev; | |
494 | ||
d8bb00d6 | 495 | QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
dbaa7904 AL |
496 | HDACodecDeviceClass *cdc; |
497 | ||
d61a4ce8 | 498 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
dbaa7904 AL |
499 | cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); |
500 | if (cdc->stream) { | |
501 | cdc->stream(cdev, stream, running, output); | |
d61a4ce8 GH |
502 | } |
503 | } | |
504 | } | |
505 | ||
506 | /* --------------------------------------------------------------------- */ | |
507 | ||
508 | static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
509 | { | |
510 | if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { | |
511 | intel_hda_reset(&d->pci.qdev); | |
512 | } | |
513 | } | |
514 | ||
6a0d02f5 GH |
515 | static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
516 | { | |
517 | intel_hda_update_irq(d); | |
518 | } | |
519 | ||
d61a4ce8 GH |
520 | static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
521 | { | |
522 | intel_hda_update_irq(d); | |
523 | } | |
524 | ||
525 | static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
526 | { | |
527 | intel_hda_update_irq(d); | |
528 | } | |
529 | ||
530 | static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) | |
531 | { | |
532 | int64_t ns; | |
533 | ||
534 | ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns; | |
535 | d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ | |
536 | } | |
537 | ||
538 | static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
539 | { | |
540 | intel_hda_corb_run(d); | |
541 | } | |
542 | ||
543 | static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
544 | { | |
545 | intel_hda_corb_run(d); | |
546 | } | |
547 | ||
548 | static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
549 | { | |
550 | if (d->rirb_wp & ICH6_RIRBWP_RST) { | |
551 | d->rirb_wp = 0; | |
552 | } | |
553 | } | |
554 | ||
555 | static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
556 | { | |
557 | intel_hda_update_irq(d); | |
558 | ||
559 | if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { | |
560 | /* cleared ICH6_RBSTS_IRQ */ | |
561 | d->rirb_count = 0; | |
562 | intel_hda_corb_run(d); | |
563 | } | |
564 | } | |
565 | ||
566 | static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
567 | { | |
568 | if (d->ics & ICH6_IRS_BUSY) { | |
569 | intel_hda_corb_run(d); | |
570 | } | |
571 | } | |
572 | ||
573 | static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
574 | { | |
ba43d289 | 575 | bool output = reg->stream >= 4; |
d61a4ce8 GH |
576 | IntelHDAStream *st = d->st + reg->stream; |
577 | ||
578 | if (st->ctl & 0x01) { | |
579 | /* reset */ | |
580 | dprint(d, 1, "st #%d: reset\n", reg->stream); | |
581 | st->ctl = 0; | |
582 | } | |
583 | if ((st->ctl & 0x02) != (old & 0x02)) { | |
584 | uint32_t stnr = (st->ctl >> 20) & 0x0f; | |
585 | /* run bit flipped */ | |
586 | if (st->ctl & 0x02) { | |
587 | /* start */ | |
588 | dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", | |
589 | reg->stream, stnr, st->cbl); | |
590 | intel_hda_parse_bdl(d, st); | |
ba43d289 | 591 | intel_hda_notify_codecs(d, stnr, true, output); |
d61a4ce8 GH |
592 | } else { |
593 | /* stop */ | |
594 | dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); | |
ba43d289 | 595 | intel_hda_notify_codecs(d, stnr, false, output); |
d61a4ce8 GH |
596 | } |
597 | } | |
598 | intel_hda_update_irq(d); | |
599 | } | |
600 | ||
601 | /* --------------------------------------------------------------------- */ | |
602 | ||
603 | #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) | |
604 | ||
605 | static const struct IntelHDAReg regtab[] = { | |
606 | /* global */ | |
607 | [ ICH6_REG_GCAP ] = { | |
608 | .name = "GCAP", | |
609 | .size = 2, | |
610 | .reset = 0x4401, | |
611 | }, | |
612 | [ ICH6_REG_VMIN ] = { | |
613 | .name = "VMIN", | |
614 | .size = 1, | |
615 | }, | |
616 | [ ICH6_REG_VMAJ ] = { | |
617 | .name = "VMAJ", | |
618 | .size = 1, | |
619 | .reset = 1, | |
620 | }, | |
621 | [ ICH6_REG_OUTPAY ] = { | |
622 | .name = "OUTPAY", | |
623 | .size = 2, | |
624 | .reset = 0x3c, | |
625 | }, | |
626 | [ ICH6_REG_INPAY ] = { | |
627 | .name = "INPAY", | |
628 | .size = 2, | |
629 | .reset = 0x1d, | |
630 | }, | |
631 | [ ICH6_REG_GCTL ] = { | |
632 | .name = "GCTL", | |
633 | .size = 4, | |
634 | .wmask = 0x0103, | |
635 | .offset = offsetof(IntelHDAState, g_ctl), | |
636 | .whandler = intel_hda_set_g_ctl, | |
637 | }, | |
638 | [ ICH6_REG_WAKEEN ] = { | |
639 | .name = "WAKEEN", | |
640 | .size = 2, | |
df0db221 | 641 | .wmask = 0x7fff, |
d61a4ce8 | 642 | .offset = offsetof(IntelHDAState, wake_en), |
6a0d02f5 | 643 | .whandler = intel_hda_set_wake_en, |
d61a4ce8 GH |
644 | }, |
645 | [ ICH6_REG_STATESTS ] = { | |
646 | .name = "STATESTS", | |
647 | .size = 2, | |
df0db221 GH |
648 | .wmask = 0x7fff, |
649 | .wclear = 0x7fff, | |
d61a4ce8 GH |
650 | .offset = offsetof(IntelHDAState, state_sts), |
651 | .whandler = intel_hda_set_state_sts, | |
652 | }, | |
653 | ||
654 | /* interrupts */ | |
655 | [ ICH6_REG_INTCTL ] = { | |
656 | .name = "INTCTL", | |
657 | .size = 4, | |
658 | .wmask = 0xc00000ff, | |
659 | .offset = offsetof(IntelHDAState, int_ctl), | |
660 | .whandler = intel_hda_set_int_ctl, | |
661 | }, | |
662 | [ ICH6_REG_INTSTS ] = { | |
663 | .name = "INTSTS", | |
664 | .size = 4, | |
665 | .wmask = 0xc00000ff, | |
666 | .wclear = 0xc00000ff, | |
667 | .offset = offsetof(IntelHDAState, int_sts), | |
668 | }, | |
669 | ||
670 | /* misc */ | |
671 | [ ICH6_REG_WALLCLK ] = { | |
672 | .name = "WALLCLK", | |
673 | .size = 4, | |
674 | .offset = offsetof(IntelHDAState, wall_clk), | |
675 | .rhandler = intel_hda_get_wall_clk, | |
676 | }, | |
677 | [ ICH6_REG_WALLCLK + 0x2000 ] = { | |
678 | .name = "WALLCLK(alias)", | |
679 | .size = 4, | |
680 | .offset = offsetof(IntelHDAState, wall_clk), | |
681 | .rhandler = intel_hda_get_wall_clk, | |
682 | }, | |
683 | ||
684 | /* dma engine */ | |
685 | [ ICH6_REG_CORBLBASE ] = { | |
686 | .name = "CORBLBASE", | |
687 | .size = 4, | |
688 | .wmask = 0xffffff80, | |
689 | .offset = offsetof(IntelHDAState, corb_lbase), | |
690 | }, | |
691 | [ ICH6_REG_CORBUBASE ] = { | |
692 | .name = "CORBUBASE", | |
693 | .size = 4, | |
694 | .wmask = 0xffffffff, | |
695 | .offset = offsetof(IntelHDAState, corb_ubase), | |
696 | }, | |
697 | [ ICH6_REG_CORBWP ] = { | |
698 | .name = "CORBWP", | |
699 | .size = 2, | |
700 | .wmask = 0xff, | |
701 | .offset = offsetof(IntelHDAState, corb_wp), | |
702 | .whandler = intel_hda_set_corb_wp, | |
703 | }, | |
704 | [ ICH6_REG_CORBRP ] = { | |
705 | .name = "CORBRP", | |
706 | .size = 2, | |
707 | .wmask = 0x80ff, | |
708 | .offset = offsetof(IntelHDAState, corb_rp), | |
709 | }, | |
710 | [ ICH6_REG_CORBCTL ] = { | |
711 | .name = "CORBCTL", | |
712 | .size = 1, | |
713 | .wmask = 0x03, | |
714 | .offset = offsetof(IntelHDAState, corb_ctl), | |
715 | .whandler = intel_hda_set_corb_ctl, | |
716 | }, | |
717 | [ ICH6_REG_CORBSTS ] = { | |
718 | .name = "CORBSTS", | |
719 | .size = 1, | |
720 | .wmask = 0x01, | |
721 | .wclear = 0x01, | |
722 | .offset = offsetof(IntelHDAState, corb_sts), | |
723 | }, | |
724 | [ ICH6_REG_CORBSIZE ] = { | |
725 | .name = "CORBSIZE", | |
726 | .size = 1, | |
727 | .reset = 0x42, | |
728 | .offset = offsetof(IntelHDAState, corb_size), | |
729 | }, | |
730 | [ ICH6_REG_RIRBLBASE ] = { | |
731 | .name = "RIRBLBASE", | |
732 | .size = 4, | |
733 | .wmask = 0xffffff80, | |
734 | .offset = offsetof(IntelHDAState, rirb_lbase), | |
735 | }, | |
736 | [ ICH6_REG_RIRBUBASE ] = { | |
737 | .name = "RIRBUBASE", | |
738 | .size = 4, | |
739 | .wmask = 0xffffffff, | |
740 | .offset = offsetof(IntelHDAState, rirb_ubase), | |
741 | }, | |
742 | [ ICH6_REG_RIRBWP ] = { | |
743 | .name = "RIRBWP", | |
744 | .size = 2, | |
745 | .wmask = 0x8000, | |
746 | .offset = offsetof(IntelHDAState, rirb_wp), | |
747 | .whandler = intel_hda_set_rirb_wp, | |
748 | }, | |
749 | [ ICH6_REG_RINTCNT ] = { | |
750 | .name = "RINTCNT", | |
751 | .size = 2, | |
752 | .wmask = 0xff, | |
753 | .offset = offsetof(IntelHDAState, rirb_cnt), | |
754 | }, | |
755 | [ ICH6_REG_RIRBCTL ] = { | |
756 | .name = "RIRBCTL", | |
757 | .size = 1, | |
758 | .wmask = 0x07, | |
759 | .offset = offsetof(IntelHDAState, rirb_ctl), | |
760 | }, | |
761 | [ ICH6_REG_RIRBSTS ] = { | |
762 | .name = "RIRBSTS", | |
763 | .size = 1, | |
764 | .wmask = 0x05, | |
765 | .wclear = 0x05, | |
766 | .offset = offsetof(IntelHDAState, rirb_sts), | |
767 | .whandler = intel_hda_set_rirb_sts, | |
768 | }, | |
769 | [ ICH6_REG_RIRBSIZE ] = { | |
770 | .name = "RIRBSIZE", | |
771 | .size = 1, | |
772 | .reset = 0x42, | |
773 | .offset = offsetof(IntelHDAState, rirb_size), | |
774 | }, | |
775 | ||
776 | [ ICH6_REG_DPLBASE ] = { | |
777 | .name = "DPLBASE", | |
778 | .size = 4, | |
779 | .wmask = 0xffffff81, | |
780 | .offset = offsetof(IntelHDAState, dp_lbase), | |
781 | }, | |
782 | [ ICH6_REG_DPUBASE ] = { | |
783 | .name = "DPUBASE", | |
784 | .size = 4, | |
785 | .wmask = 0xffffffff, | |
786 | .offset = offsetof(IntelHDAState, dp_ubase), | |
787 | }, | |
788 | ||
789 | [ ICH6_REG_IC ] = { | |
790 | .name = "ICW", | |
791 | .size = 4, | |
792 | .wmask = 0xffffffff, | |
793 | .offset = offsetof(IntelHDAState, icw), | |
794 | }, | |
795 | [ ICH6_REG_IR ] = { | |
796 | .name = "IRR", | |
797 | .size = 4, | |
798 | .offset = offsetof(IntelHDAState, irr), | |
799 | }, | |
800 | [ ICH6_REG_IRS ] = { | |
801 | .name = "ICS", | |
802 | .size = 2, | |
803 | .wmask = 0x0003, | |
804 | .wclear = 0x0002, | |
805 | .offset = offsetof(IntelHDAState, ics), | |
806 | .whandler = intel_hda_set_ics, | |
807 | }, | |
808 | ||
809 | #define HDA_STREAM(_t, _i) \ | |
810 | [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ | |
811 | .stream = _i, \ | |
812 | .name = _t stringify(_i) " CTL", \ | |
813 | .size = 4, \ | |
814 | .wmask = 0x1cff001f, \ | |
815 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ | |
816 | .whandler = intel_hda_set_st_ctl, \ | |
817 | }, \ | |
818 | [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ | |
819 | .stream = _i, \ | |
820 | .name = _t stringify(_i) " CTL(stnr)", \ | |
821 | .size = 1, \ | |
822 | .shift = 16, \ | |
823 | .wmask = 0x00ff0000, \ | |
824 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ | |
825 | .whandler = intel_hda_set_st_ctl, \ | |
826 | }, \ | |
827 | [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ | |
828 | .stream = _i, \ | |
829 | .name = _t stringify(_i) " CTL(sts)", \ | |
830 | .size = 1, \ | |
831 | .shift = 24, \ | |
832 | .wmask = 0x1c000000, \ | |
833 | .wclear = 0x1c000000, \ | |
834 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ | |
835 | .whandler = intel_hda_set_st_ctl, \ | |
836 | }, \ | |
837 | [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ | |
838 | .stream = _i, \ | |
839 | .name = _t stringify(_i) " LPIB", \ | |
840 | .size = 4, \ | |
841 | .offset = offsetof(IntelHDAState, st[_i].lpib), \ | |
842 | }, \ | |
843 | [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \ | |
844 | .stream = _i, \ | |
845 | .name = _t stringify(_i) " LPIB(alias)", \ | |
846 | .size = 4, \ | |
847 | .offset = offsetof(IntelHDAState, st[_i].lpib), \ | |
848 | }, \ | |
849 | [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ | |
850 | .stream = _i, \ | |
851 | .name = _t stringify(_i) " CBL", \ | |
852 | .size = 4, \ | |
853 | .wmask = 0xffffffff, \ | |
854 | .offset = offsetof(IntelHDAState, st[_i].cbl), \ | |
855 | }, \ | |
856 | [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ | |
857 | .stream = _i, \ | |
858 | .name = _t stringify(_i) " LVI", \ | |
859 | .size = 2, \ | |
860 | .wmask = 0x00ff, \ | |
861 | .offset = offsetof(IntelHDAState, st[_i].lvi), \ | |
862 | }, \ | |
863 | [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ | |
864 | .stream = _i, \ | |
865 | .name = _t stringify(_i) " FIFOS", \ | |
866 | .size = 2, \ | |
867 | .reset = HDA_BUFFER_SIZE, \ | |
868 | }, \ | |
869 | [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ | |
870 | .stream = _i, \ | |
871 | .name = _t stringify(_i) " FMT", \ | |
872 | .size = 2, \ | |
873 | .wmask = 0x7f7f, \ | |
874 | .offset = offsetof(IntelHDAState, st[_i].fmt), \ | |
875 | }, \ | |
876 | [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ | |
877 | .stream = _i, \ | |
878 | .name = _t stringify(_i) " BDLPL", \ | |
879 | .size = 4, \ | |
880 | .wmask = 0xffffff80, \ | |
881 | .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ | |
882 | }, \ | |
883 | [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ | |
884 | .stream = _i, \ | |
885 | .name = _t stringify(_i) " BDLPU", \ | |
886 | .size = 4, \ | |
887 | .wmask = 0xffffffff, \ | |
888 | .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ | |
889 | }, \ | |
890 | ||
891 | HDA_STREAM("IN", 0) | |
892 | HDA_STREAM("IN", 1) | |
893 | HDA_STREAM("IN", 2) | |
894 | HDA_STREAM("IN", 3) | |
895 | ||
896 | HDA_STREAM("OUT", 4) | |
897 | HDA_STREAM("OUT", 5) | |
898 | HDA_STREAM("OUT", 6) | |
899 | HDA_STREAM("OUT", 7) | |
900 | ||
901 | }; | |
902 | ||
903 | static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr) | |
904 | { | |
905 | const IntelHDAReg *reg; | |
906 | ||
907 | if (addr >= sizeof(regtab)/sizeof(regtab[0])) { | |
908 | goto noreg; | |
909 | } | |
910 | reg = regtab+addr; | |
911 | if (reg->name == NULL) { | |
912 | goto noreg; | |
913 | } | |
914 | return reg; | |
915 | ||
916 | noreg: | |
917 | dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); | |
918 | return NULL; | |
919 | } | |
920 | ||
921 | static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) | |
922 | { | |
923 | uint8_t *addr = (void*)d; | |
924 | ||
925 | addr += reg->offset; | |
926 | return (uint32_t*)addr; | |
927 | } | |
928 | ||
929 | static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, | |
930 | uint32_t wmask) | |
931 | { | |
932 | uint32_t *addr; | |
933 | uint32_t old; | |
934 | ||
935 | if (!reg) { | |
936 | return; | |
937 | } | |
938 | ||
939 | if (d->debug) { | |
940 | time_t now = time(NULL); | |
941 | if (d->last_write && d->last_reg == reg && d->last_val == val) { | |
942 | d->repeat_count++; | |
943 | if (d->last_sec != now) { | |
944 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
945 | d->last_sec = now; | |
946 | d->repeat_count = 0; | |
947 | } | |
948 | } else { | |
949 | if (d->repeat_count) { | |
950 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
951 | } | |
952 | dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); | |
953 | d->last_write = 1; | |
954 | d->last_reg = reg; | |
955 | d->last_val = val; | |
956 | d->last_sec = now; | |
957 | d->repeat_count = 0; | |
958 | } | |
959 | } | |
960 | assert(reg->offset != 0); | |
961 | ||
962 | addr = intel_hda_reg_addr(d, reg); | |
963 | old = *addr; | |
964 | ||
965 | if (reg->shift) { | |
966 | val <<= reg->shift; | |
967 | wmask <<= reg->shift; | |
968 | } | |
969 | wmask &= reg->wmask; | |
970 | *addr &= ~wmask; | |
971 | *addr |= wmask & val; | |
972 | *addr &= ~(val & reg->wclear); | |
973 | ||
974 | if (reg->whandler) { | |
975 | reg->whandler(d, reg, old); | |
976 | } | |
977 | } | |
978 | ||
979 | static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, | |
980 | uint32_t rmask) | |
981 | { | |
982 | uint32_t *addr, ret; | |
983 | ||
984 | if (!reg) { | |
985 | return 0; | |
986 | } | |
987 | ||
988 | if (reg->rhandler) { | |
989 | reg->rhandler(d, reg); | |
990 | } | |
991 | ||
992 | if (reg->offset == 0) { | |
993 | /* constant read-only register */ | |
994 | ret = reg->reset; | |
995 | } else { | |
996 | addr = intel_hda_reg_addr(d, reg); | |
997 | ret = *addr; | |
998 | if (reg->shift) { | |
999 | ret >>= reg->shift; | |
1000 | } | |
1001 | ret &= rmask; | |
1002 | } | |
1003 | if (d->debug) { | |
1004 | time_t now = time(NULL); | |
1005 | if (!d->last_write && d->last_reg == reg && d->last_val == ret) { | |
1006 | d->repeat_count++; | |
1007 | if (d->last_sec != now) { | |
1008 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
1009 | d->last_sec = now; | |
1010 | d->repeat_count = 0; | |
1011 | } | |
1012 | } else { | |
1013 | if (d->repeat_count) { | |
1014 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
1015 | } | |
1016 | dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); | |
1017 | d->last_write = 0; | |
1018 | d->last_reg = reg; | |
1019 | d->last_val = ret; | |
1020 | d->last_sec = now; | |
1021 | d->repeat_count = 0; | |
1022 | } | |
1023 | } | |
1024 | return ret; | |
1025 | } | |
1026 | ||
1027 | static void intel_hda_regs_reset(IntelHDAState *d) | |
1028 | { | |
1029 | uint32_t *addr; | |
1030 | int i; | |
1031 | ||
1032 | for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) { | |
1033 | if (regtab[i].name == NULL) { | |
1034 | continue; | |
1035 | } | |
1036 | if (regtab[i].offset == 0) { | |
1037 | continue; | |
1038 | } | |
1039 | addr = intel_hda_reg_addr(d, regtab + i); | |
1040 | *addr = regtab[i].reset; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | /* --------------------------------------------------------------------- */ | |
1045 | ||
1046 | static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | |
1047 | { | |
1048 | IntelHDAState *d = opaque; | |
1049 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1050 | ||
1051 | intel_hda_reg_write(d, reg, val, 0xff); | |
1052 | } | |
1053 | ||
1054 | static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
1055 | { | |
1056 | IntelHDAState *d = opaque; | |
1057 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1058 | ||
1059 | intel_hda_reg_write(d, reg, val, 0xffff); | |
1060 | } | |
1061 | ||
1062 | static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
1063 | { | |
1064 | IntelHDAState *d = opaque; | |
1065 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1066 | ||
1067 | intel_hda_reg_write(d, reg, val, 0xffffffff); | |
1068 | } | |
1069 | ||
1070 | static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr) | |
1071 | { | |
1072 | IntelHDAState *d = opaque; | |
1073 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1074 | ||
1075 | return intel_hda_reg_read(d, reg, 0xff); | |
1076 | } | |
1077 | ||
1078 | static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr) | |
1079 | { | |
1080 | IntelHDAState *d = opaque; | |
1081 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1082 | ||
1083 | return intel_hda_reg_read(d, reg, 0xffff); | |
1084 | } | |
1085 | ||
1086 | static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr) | |
1087 | { | |
1088 | IntelHDAState *d = opaque; | |
1089 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1090 | ||
1091 | return intel_hda_reg_read(d, reg, 0xffffffff); | |
1092 | } | |
1093 | ||
234bbdf1 AK |
1094 | static const MemoryRegionOps intel_hda_mmio_ops = { |
1095 | .old_mmio = { | |
1096 | .read = { | |
1097 | intel_hda_mmio_readb, | |
1098 | intel_hda_mmio_readw, | |
1099 | intel_hda_mmio_readl, | |
1100 | }, | |
1101 | .write = { | |
1102 | intel_hda_mmio_writeb, | |
1103 | intel_hda_mmio_writew, | |
1104 | intel_hda_mmio_writel, | |
1105 | }, | |
1106 | }, | |
1107 | .endianness = DEVICE_NATIVE_ENDIAN, | |
d61a4ce8 GH |
1108 | }; |
1109 | ||
d61a4ce8 GH |
1110 | /* --------------------------------------------------------------------- */ |
1111 | ||
1112 | static void intel_hda_reset(DeviceState *dev) | |
1113 | { | |
1114 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev); | |
1115 | DeviceState *qdev; | |
1116 | HDACodecDevice *cdev; | |
1117 | ||
1118 | intel_hda_regs_reset(d); | |
74475455 | 1119 | d->wall_base_ns = qemu_get_clock_ns(vm_clock); |
d61a4ce8 GH |
1120 | |
1121 | /* reset codecs */ | |
d8bb00d6 | 1122 | QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
d61a4ce8 | 1123 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
94afdadc | 1124 | device_reset(DEVICE(cdev)); |
d61a4ce8 GH |
1125 | d->state_sts |= (1 << cdev->cad); |
1126 | } | |
1127 | intel_hda_update_irq(d); | |
1128 | } | |
1129 | ||
1130 | static int intel_hda_init(PCIDevice *pci) | |
1131 | { | |
1132 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); | |
1133 | uint8_t *conf = d->pci.config; | |
1134 | ||
f79f2bfc | 1135 | d->name = object_get_typename(OBJECT(d)); |
d61a4ce8 | 1136 | |
d61a4ce8 GH |
1137 | pci_config_set_interrupt_pin(conf, 1); |
1138 | ||
1139 | /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ | |
1140 | conf[0x40] = 0x01; | |
1141 | ||
234bbdf1 AK |
1142 | memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d, |
1143 | "intel-hda", 0x4000); | |
e824b2cc | 1144 | pci_register_bar(&d->pci, 0, 0, &d->mmio); |
17786d52 GH |
1145 | if (d->msi) { |
1146 | msi_init(&d->pci, 0x50, 1, true, false); | |
1147 | } | |
d61a4ce8 GH |
1148 | |
1149 | hda_codec_bus_init(&d->pci.qdev, &d->codecs, | |
1150 | intel_hda_response, intel_hda_xfer); | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
dc4b9240 GH |
1155 | static int intel_hda_exit(PCIDevice *pci) |
1156 | { | |
1157 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); | |
1158 | ||
45fe15c2 | 1159 | msi_uninit(&d->pci); |
234bbdf1 | 1160 | memory_region_destroy(&d->mmio); |
dc4b9240 GH |
1161 | return 0; |
1162 | } | |
1163 | ||
17786d52 GH |
1164 | static void intel_hda_write_config(PCIDevice *pci, uint32_t addr, |
1165 | uint32_t val, int len) | |
1166 | { | |
1167 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); | |
1168 | ||
1169 | pci_default_write_config(pci, addr, val, len); | |
1170 | if (d->msi) { | |
1171 | msi_write_config(pci, addr, val, len); | |
1172 | } | |
1173 | } | |
1174 | ||
d61a4ce8 GH |
1175 | static int intel_hda_post_load(void *opaque, int version) |
1176 | { | |
1177 | IntelHDAState* d = opaque; | |
1178 | int i; | |
1179 | ||
1180 | dprint(d, 1, "%s\n", __FUNCTION__); | |
1181 | for (i = 0; i < ARRAY_SIZE(d->st); i++) { | |
1182 | if (d->st[i].ctl & 0x02) { | |
1183 | intel_hda_parse_bdl(d, &d->st[i]); | |
1184 | } | |
1185 | } | |
1186 | intel_hda_update_irq(d); | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | static const VMStateDescription vmstate_intel_hda_stream = { | |
1191 | .name = "intel-hda-stream", | |
1192 | .version_id = 1, | |
1193 | .fields = (VMStateField []) { | |
1194 | VMSTATE_UINT32(ctl, IntelHDAStream), | |
1195 | VMSTATE_UINT32(lpib, IntelHDAStream), | |
1196 | VMSTATE_UINT32(cbl, IntelHDAStream), | |
1197 | VMSTATE_UINT32(lvi, IntelHDAStream), | |
1198 | VMSTATE_UINT32(fmt, IntelHDAStream), | |
1199 | VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), | |
1200 | VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), | |
1201 | VMSTATE_END_OF_LIST() | |
1202 | } | |
1203 | }; | |
1204 | ||
1205 | static const VMStateDescription vmstate_intel_hda = { | |
1206 | .name = "intel-hda", | |
1207 | .version_id = 1, | |
1208 | .post_load = intel_hda_post_load, | |
1209 | .fields = (VMStateField []) { | |
1210 | VMSTATE_PCI_DEVICE(pci, IntelHDAState), | |
1211 | ||
1212 | /* registers */ | |
1213 | VMSTATE_UINT32(g_ctl, IntelHDAState), | |
1214 | VMSTATE_UINT32(wake_en, IntelHDAState), | |
1215 | VMSTATE_UINT32(state_sts, IntelHDAState), | |
1216 | VMSTATE_UINT32(int_ctl, IntelHDAState), | |
1217 | VMSTATE_UINT32(int_sts, IntelHDAState), | |
1218 | VMSTATE_UINT32(wall_clk, IntelHDAState), | |
1219 | VMSTATE_UINT32(corb_lbase, IntelHDAState), | |
1220 | VMSTATE_UINT32(corb_ubase, IntelHDAState), | |
1221 | VMSTATE_UINT32(corb_rp, IntelHDAState), | |
1222 | VMSTATE_UINT32(corb_wp, IntelHDAState), | |
1223 | VMSTATE_UINT32(corb_ctl, IntelHDAState), | |
1224 | VMSTATE_UINT32(corb_sts, IntelHDAState), | |
1225 | VMSTATE_UINT32(corb_size, IntelHDAState), | |
1226 | VMSTATE_UINT32(rirb_lbase, IntelHDAState), | |
1227 | VMSTATE_UINT32(rirb_ubase, IntelHDAState), | |
1228 | VMSTATE_UINT32(rirb_wp, IntelHDAState), | |
1229 | VMSTATE_UINT32(rirb_cnt, IntelHDAState), | |
1230 | VMSTATE_UINT32(rirb_ctl, IntelHDAState), | |
1231 | VMSTATE_UINT32(rirb_sts, IntelHDAState), | |
1232 | VMSTATE_UINT32(rirb_size, IntelHDAState), | |
1233 | VMSTATE_UINT32(dp_lbase, IntelHDAState), | |
1234 | VMSTATE_UINT32(dp_ubase, IntelHDAState), | |
1235 | VMSTATE_UINT32(icw, IntelHDAState), | |
1236 | VMSTATE_UINT32(irr, IntelHDAState), | |
1237 | VMSTATE_UINT32(ics, IntelHDAState), | |
1238 | VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, | |
1239 | vmstate_intel_hda_stream, | |
1240 | IntelHDAStream), | |
1241 | ||
1242 | /* additional state info */ | |
1243 | VMSTATE_UINT32(rirb_count, IntelHDAState), | |
1244 | VMSTATE_INT64(wall_base_ns, IntelHDAState), | |
1245 | ||
1246 | VMSTATE_END_OF_LIST() | |
1247 | } | |
1248 | }; | |
1249 | ||
1250 | static PCIDeviceInfo intel_hda_info = { | |
1251 | .qdev.name = "intel-hda", | |
1252 | .qdev.desc = "Intel HD Audio Controller", | |
1253 | .qdev.size = sizeof(IntelHDAState), | |
1254 | .qdev.vmsd = &vmstate_intel_hda, | |
1255 | .qdev.reset = intel_hda_reset, | |
1256 | .init = intel_hda_init, | |
dc4b9240 | 1257 | .exit = intel_hda_exit, |
17786d52 | 1258 | .config_write = intel_hda_write_config, |
d15fda63 IY |
1259 | .vendor_id = PCI_VENDOR_ID_INTEL, |
1260 | .device_id = 0x2668, | |
1261 | .revision = 1, | |
1262 | .class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO, | |
d61a4ce8 GH |
1263 | .qdev.props = (Property[]) { |
1264 | DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), | |
17786d52 | 1265 | DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1), |
d61a4ce8 GH |
1266 | DEFINE_PROP_END_OF_LIST(), |
1267 | } | |
1268 | }; | |
1269 | ||
1270 | static void intel_hda_register(void) | |
1271 | { | |
1272 | pci_qdev_register(&intel_hda_info); | |
1273 | } | |
1274 | device_init(intel_hda_register); | |
1275 | ||
1276 | /* | |
1277 | * create intel hda controller with codec attached to it, | |
1278 | * so '-soundhw hda' works. | |
1279 | */ | |
1280 | int intel_hda_and_codec_init(PCIBus *bus) | |
1281 | { | |
1282 | PCIDevice *controller; | |
1283 | BusState *hdabus; | |
1284 | DeviceState *codec; | |
1285 | ||
1286 | controller = pci_create_simple(bus, -1, "intel-hda"); | |
1287 | hdabus = QLIST_FIRST(&controller->qdev.child_bus); | |
1288 | codec = qdev_create(hdabus, "hda-duplex"); | |
1289 | qdev_init_nofail(codec); | |
1290 | return 0; | |
1291 | } | |
1292 |